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r600g: add initial evergreen support
[mesa.git] / src / gallium / drivers / r600 / r600_asm.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_asm.h"
24 #include "r600_context.h"
25 #include "util/u_memory.h"
26 #include "r600_sq.h"
27 #include "r600_opcodes.h"
28 #include <stdio.h>
29 #include <errno.h>
30
31 static inline unsigned int r600_bc_get_num_operands(struct r600_bc_alu *alu)
32 {
33 if(alu->is_op3)
34 return 3;
35
36 switch (alu->inst) {
37 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
38 return 0;
39 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
40 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
41 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
42 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
43 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
44 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
45 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
46 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
47 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
48 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
49 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
50 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
51 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
52 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
53 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
54 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
55 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
56 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
57 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
58 return 2;
59
60 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
61 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR:
62 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
63 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
64 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
65 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
66 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
67 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
68 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
69 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
70 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
71 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
72 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
73 return 1;
74
75 default: R600_ERR(
76 "Need instruction operand number for 0x%x.\n", alu->inst);
77 };
78
79 return 3;
80 }
81
82 int r700_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id);
83
84 static struct r600_bc_cf *r600_bc_cf(void)
85 {
86 struct r600_bc_cf *cf = CALLOC_STRUCT(r600_bc_cf);
87
88 if (cf == NULL)
89 return NULL;
90 LIST_INITHEAD(&cf->list);
91 LIST_INITHEAD(&cf->alu);
92 LIST_INITHEAD(&cf->vtx);
93 LIST_INITHEAD(&cf->tex);
94 return cf;
95 }
96
97 static struct r600_bc_alu *r600_bc_alu(void)
98 {
99 struct r600_bc_alu *alu = CALLOC_STRUCT(r600_bc_alu);
100
101 if (alu == NULL)
102 return NULL;
103 LIST_INITHEAD(&alu->list);
104 LIST_INITHEAD(&alu->bs_list);
105 return alu;
106 }
107
108 static struct r600_bc_vtx *r600_bc_vtx(void)
109 {
110 struct r600_bc_vtx *vtx = CALLOC_STRUCT(r600_bc_vtx);
111
112 if (vtx == NULL)
113 return NULL;
114 LIST_INITHEAD(&vtx->list);
115 return vtx;
116 }
117
118 static struct r600_bc_tex *r600_bc_tex(void)
119 {
120 struct r600_bc_tex *tex = CALLOC_STRUCT(r600_bc_tex);
121
122 if (tex == NULL)
123 return NULL;
124 LIST_INITHEAD(&tex->list);
125 return tex;
126 }
127
128 int r600_bc_init(struct r600_bc *bc, enum radeon_family family)
129 {
130 LIST_INITHEAD(&bc->cf);
131 bc->family = family;
132 switch (bc->family) {
133 case CHIP_R600:
134 case CHIP_RV610:
135 case CHIP_RV630:
136 case CHIP_RV670:
137 case CHIP_RV620:
138 case CHIP_RV635:
139 case CHIP_RS780:
140 case CHIP_RS880:
141 bc->chiprev = 0;
142 break;
143 case CHIP_RV770:
144 case CHIP_RV730:
145 case CHIP_RV710:
146 case CHIP_RV740:
147 bc->chiprev = 1;
148 break;
149 case CHIP_CEDAR:
150 case CHIP_REDWOOD:
151 case CHIP_JUNIPER:
152 case CHIP_CYPRESS:
153 case CHIP_HEMLOCK:
154 bc->chiprev = 2;
155 break;
156 default:
157 R600_ERR("unknown family %d\n", bc->family);
158 return -EINVAL;
159 }
160 return 0;
161 }
162
163 static int r600_bc_add_cf(struct r600_bc *bc)
164 {
165 struct r600_bc_cf *cf = r600_bc_cf();
166
167 if (cf == NULL)
168 return -ENOMEM;
169 LIST_ADDTAIL(&cf->list, &bc->cf);
170 if (bc->cf_last)
171 cf->id = bc->cf_last->id + 2;
172 bc->cf_last = cf;
173 bc->ncf++;
174 bc->ndw += 2;
175 bc->force_add_cf = 0;
176 return 0;
177 }
178
179 int r600_bc_add_output(struct r600_bc *bc, const struct r600_bc_output *output)
180 {
181 int r;
182
183 r = r600_bc_add_cf(bc);
184 if (r)
185 return r;
186 bc->cf_last->inst = output->inst;
187 memcpy(&bc->cf_last->output, output, sizeof(struct r600_bc_output));
188 return 0;
189 }
190
191 const unsigned bank_swizzle_vec[8] = {SQ_ALU_VEC_210, //000
192 SQ_ALU_VEC_120, //001
193 SQ_ALU_VEC_102, //010
194
195 SQ_ALU_VEC_201, //011
196 SQ_ALU_VEC_012, //100
197 SQ_ALU_VEC_021, //101
198
199 SQ_ALU_VEC_012, //110
200 SQ_ALU_VEC_012}; //111
201
202 const unsigned bank_swizzle_scl[8] = {SQ_ALU_SCL_210, //000
203 SQ_ALU_SCL_122, //001
204 SQ_ALU_SCL_122, //010
205
206 SQ_ALU_SCL_221, //011
207 SQ_ALU_SCL_212, //100
208 SQ_ALU_SCL_122, //101
209
210 SQ_ALU_SCL_122, //110
211 SQ_ALU_SCL_122}; //111
212
213 static int init_gpr(struct r600_bc_alu *alu)
214 {
215 int cycle, component;
216 /* set up gpr use */
217 for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
218 for (component = 0; component < NUM_OF_COMPONENTS; component++)
219 alu->hw_gpr[cycle][component] = -1;
220 return 0;
221 }
222
223 static int reserve_gpr(struct r600_bc_alu *alu, unsigned sel, unsigned chan, unsigned cycle)
224 {
225 if (alu->hw_gpr[cycle][chan] < 0)
226 alu->hw_gpr[cycle][chan] = sel;
227 else if (alu->hw_gpr[cycle][chan] != (int)sel) {
228 R600_ERR("Another scalar operation has already used GPR read port for channel\n");
229 return -1;
230 }
231 return 0;
232 }
233
234 static int cycle_for_scalar_bank_swizzle(const int swiz, const int sel, unsigned *p_cycle)
235 {
236 int table[3];
237 int ret = 0;
238 switch (swiz) {
239 case SQ_ALU_SCL_210:
240 table[0] = 2; table[1] = 1; table[2] = 0;
241 *p_cycle = table[sel];
242 break;
243 case SQ_ALU_SCL_122:
244 table[0] = 1; table[1] = 2; table[2] = 2;
245 *p_cycle = table[sel];
246 break;
247 case SQ_ALU_SCL_212:
248 table[0] = 2; table[1] = 1; table[2] = 2;
249 *p_cycle = table[sel];
250 break;
251 case SQ_ALU_SCL_221:
252 table[0] = 2; table[1] = 2; table[2] = 1;
253 *p_cycle = table[sel];
254 break;
255 break;
256 default:
257 R600_ERR("bad scalar bank swizzle value\n");
258 ret = -1;
259 break;
260 }
261 return ret;
262 }
263
264 static int cycle_for_vector_bank_swizzle(const int swiz, const int sel, unsigned *p_cycle)
265 {
266 int table[3];
267 int ret;
268
269 switch (swiz) {
270 case SQ_ALU_VEC_012:
271 table[0] = 0; table[1] = 1; table[2] = 2;
272 *p_cycle = table[sel];
273 break;
274 case SQ_ALU_VEC_021:
275 table[0] = 0; table[1] = 2; table[2] = 1;
276 *p_cycle = table[sel];
277 break;
278 case SQ_ALU_VEC_120:
279 table[0] = 1; table[1] = 2; table[2] = 0;
280 *p_cycle = table[sel];
281 break;
282 case SQ_ALU_VEC_102:
283 table[0] = 1; table[1] = 0; table[2] = 2;
284 *p_cycle = table[sel];
285 break;
286 case SQ_ALU_VEC_201:
287 table[0] = 2; table[1] = 0; table[2] = 1;
288 *p_cycle = table[sel];
289 break;
290 case SQ_ALU_VEC_210:
291 table[0] = 2; table[1] = 1; table[2] = 0;
292 *p_cycle = table[sel];
293 break;
294 default:
295 R600_ERR("bad vector bank swizzle value\n");
296 ret = -1;
297 break;
298 }
299 return ret;
300 }
301
302 static int is_const(int sel)
303 {
304 if (sel > 255 && sel < 512)
305 return 1;
306 if (sel >= V_SQ_ALU_SRC_0 && sel <= V_SQ_ALU_SRC_LITERAL)
307 return 1;
308 return 0;
309 }
310
311 static void update_chan_counter(struct r600_bc_alu *alu, int *chan_counter)
312 {
313 int num_src;
314 int i;
315 int channel_swizzle;
316
317 num_src = r600_bc_get_num_operands(alu);
318
319 for (i = 0; i < num_src; i++) {
320 channel_swizzle = alu->src[i].chan;
321 if ((alu->src[i].sel > 0 && alu->src[i].sel < 128) && channel_swizzle <= 3)
322 chan_counter[channel_swizzle]++;
323 }
324 }
325
326 #if 0
327 /* we need something like this I think - but this is bogus */
328 int check_read_slots(struct r600_bc *bc, struct r600_bc_alu *alu_first)
329 {
330 struct r600_bc_alu *alu;
331 int chan_counter[4] = { 0 };
332
333 update_chan_counter(alu_first, chan_counter);
334
335 LIST_FOR_EACH_ENTRY(alu, &alu_first->bs_list, bs_list) {
336 update_chan_counter(alu, chan_counter);
337 }
338
339 if (chan_counter[0] > 3 ||
340 chan_counter[1] > 3 ||
341 chan_counter[2] > 3 ||
342 chan_counter[3] > 3) {
343 R600_ERR("needed to split instruction for input ran out of banks %x %d %d %d %d\n",
344 alu_first->inst, chan_counter[0], chan_counter[1], chan_counter[2], chan_counter[3]);
345 return -1;
346 }
347 return 0;
348 }
349 #endif
350
351 static int check_scalar(struct r600_bc *bc, struct r600_bc_alu *alu)
352 {
353 unsigned swizzle_key;
354
355 if (alu->bank_swizzle_force) {
356 alu->bank_swizzle = alu->bank_swizzle_force;
357 return;
358 }
359 swizzle_key = (is_const(alu->src[0].sel) ? 4 : 0 ) +
360 (is_const(alu->src[1].sel) ? 2 : 0 ) +
361 (is_const(alu->src[2].sel) ? 1 : 0 );
362
363 alu->bank_swizzle = bank_swizzle_scl[swizzle_key];
364 return 0;
365 }
366
367 static int check_vector(struct r600_bc *bc, struct r600_bc_alu *alu)
368 {
369 unsigned swizzle_key;
370
371 if (alu->bank_swizzle_force) {
372 alu->bank_swizzle = alu->bank_swizzle_force;
373 return;
374 }
375 swizzle_key = (is_const(alu->src[0].sel) ? 4 : 0 ) +
376 (is_const(alu->src[1].sel) ? 2 : 0 ) +
377 (is_const(alu->src[2].sel) ? 1 : 0 );
378
379 alu->bank_swizzle = bank_swizzle_vec[swizzle_key];
380 return 0;
381 }
382
383 static int check_and_set_bank_swizzle(struct r600_bc *bc, struct r600_bc_alu *alu_first)
384 {
385 struct r600_bc_alu *alu;
386 int num_instr = 1;
387
388 init_gpr(alu_first);
389
390 LIST_FOR_EACH_ENTRY(alu, &alu_first->bs_list, bs_list) {
391 num_instr++;
392 }
393
394 if (num_instr == 1) {
395 check_scalar(bc, alu_first);
396
397 } else {
398 /* check_read_slots(bc, bc->cf_last->curr_bs_head);*/
399 check_vector(bc, alu_first);
400 LIST_FOR_EACH_ENTRY(alu, &alu_first->bs_list, bs_list) {
401 check_vector(bc, alu);
402 }
403 }
404 return 0;
405 }
406
407 int r600_bc_add_alu_type(struct r600_bc *bc, const struct r600_bc_alu *alu, int type)
408 {
409 struct r600_bc_alu *nalu = r600_bc_alu();
410 struct r600_bc_alu *lalu;
411 struct r600_bc_alu *curr_bs_head;
412 int i, r;
413
414 if (nalu == NULL)
415 return -ENOMEM;
416 memcpy(nalu, alu, sizeof(struct r600_bc_alu));
417 nalu->nliteral = 0;
418
419 /* cf can contains only alu or only vtx or only tex */
420 if (bc->cf_last == NULL || bc->cf_last->inst != (type << 3) ||
421 bc->force_add_cf) {
422 /* at most 128 slots, one add alu can add 4 slots + 4 constant worst case */
423 r = r600_bc_add_cf(bc);
424 if (r) {
425 free(nalu);
426 return r;
427 }
428 bc->cf_last->inst = (type << 3);
429 }
430 if (!bc->cf_last->curr_bs_head) {
431 bc->cf_last->curr_bs_head = nalu;
432 LIST_INITHEAD(&nalu->bs_list);
433 } else {
434 LIST_ADDTAIL(&nalu->bs_list, &bc->cf_last->curr_bs_head->bs_list);
435 }
436 if (alu->last && (bc->cf_last->ndw >> 1) >= 124) {
437 bc->force_add_cf = 1;
438 }
439 /* number of gpr == the last gpr used in any alu */
440 for (i = 0; i < 3; i++) {
441 if (alu->src[i].sel >= bc->ngpr && alu->src[i].sel < 128) {
442 bc->ngpr = alu->src[i].sel + 1;
443 }
444 /* compute how many literal are needed
445 * either 2 or 4 literals
446 */
447 if (alu->src[i].sel == 253) {
448 if (((alu->src[i].chan + 2) & 0x6) > nalu->nliteral) {
449 nalu->nliteral = (alu->src[i].chan + 2) & 0x6;
450 }
451 }
452 }
453 if (!LIST_IS_EMPTY(&bc->cf_last->alu)) {
454 lalu = LIST_ENTRY(struct r600_bc_alu, bc->cf_last->alu.prev, list);
455 if (!lalu->last && lalu->nliteral > nalu->nliteral) {
456 nalu->nliteral = lalu->nliteral;
457 }
458 }
459 if (alu->dst.sel >= bc->ngpr) {
460 bc->ngpr = alu->dst.sel + 1;
461 }
462 LIST_ADDTAIL(&nalu->list, &bc->cf_last->alu);
463 /* each alu use 2 dwords */
464 bc->cf_last->ndw += 2;
465 bc->ndw += 2;
466
467 if (bc->use_mem_constant)
468 bc->cf_last->kcache0_mode = 2;
469
470 /* process cur ALU instructions for bank swizzle */
471 if (alu->last) {
472 check_and_set_bank_swizzle(bc, bc->cf_last->curr_bs_head);
473 bc->cf_last->curr_bs_head = NULL;
474 }
475 return 0;
476 }
477
478 int r600_bc_add_alu(struct r600_bc *bc, const struct r600_bc_alu *alu)
479 {
480 return r600_bc_add_alu_type(bc, alu, BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
481 }
482
483 int r600_bc_add_literal(struct r600_bc *bc, const u32 *value)
484 {
485 struct r600_bc_alu *alu;
486
487 if (bc->cf_last == NULL) {
488 return 0;
489 }
490 if (bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_TEX) {
491 return 0;
492 }
493 /* all same on EG */
494 if (bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_JUMP ||
495 bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_ELSE ||
496 bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL ||
497 bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK ||
498 bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE ||
499 bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END ||
500 bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_POP) {
501 return 0;
502 }
503 /* same on EG */
504 if (((bc->cf_last->inst != (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3)) &&
505 (bc->cf_last->inst != (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3))) ||
506 LIST_IS_EMPTY(&bc->cf_last->alu)) {
507 R600_ERR("last CF is not ALU (%p)\n", bc->cf_last);
508 return -EINVAL;
509 }
510 alu = LIST_ENTRY(struct r600_bc_alu, bc->cf_last->alu.prev, list);
511 if (!alu->last || !alu->nliteral || alu->literal_added) {
512 return 0;
513 }
514 memcpy(alu->value, value, 4 * 4);
515 bc->cf_last->ndw += alu->nliteral;
516 bc->ndw += alu->nliteral;
517 alu->literal_added = 1;
518 return 0;
519 }
520
521 int r600_bc_add_vtx(struct r600_bc *bc, const struct r600_bc_vtx *vtx)
522 {
523 struct r600_bc_vtx *nvtx = r600_bc_vtx();
524 int r;
525
526 if (nvtx == NULL)
527 return -ENOMEM;
528 memcpy(nvtx, vtx, sizeof(struct r600_bc_vtx));
529
530 /* cf can contains only alu or only vtx or only tex */
531 if (bc->cf_last == NULL ||
532 (bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX &&
533 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC)) {
534 r = r600_bc_add_cf(bc);
535 if (r) {
536 free(nvtx);
537 return r;
538 }
539 bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_VTX;
540 }
541 LIST_ADDTAIL(&nvtx->list, &bc->cf_last->vtx);
542 /* each fetch use 4 dwords */
543 bc->cf_last->ndw += 4;
544 bc->ndw += 4;
545 return 0;
546 }
547
548 int r600_bc_add_tex(struct r600_bc *bc, const struct r600_bc_tex *tex)
549 {
550 struct r600_bc_tex *ntex = r600_bc_tex();
551 int r;
552
553 if (ntex == NULL)
554 return -ENOMEM;
555 memcpy(ntex, tex, sizeof(struct r600_bc_tex));
556
557 /* cf can contains only alu or only vtx or only tex */
558 if (bc->cf_last == NULL ||
559 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_TEX) {
560 r = r600_bc_add_cf(bc);
561 if (r) {
562 free(ntex);
563 return r;
564 }
565 bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_TEX;
566 }
567 LIST_ADDTAIL(&ntex->list, &bc->cf_last->tex);
568 /* each texture fetch use 4 dwords */
569 bc->cf_last->ndw += 4;
570 bc->ndw += 4;
571 return 0;
572 }
573
574 int r600_bc_add_cfinst(struct r600_bc *bc, int inst)
575 {
576 int r;
577 r = r600_bc_add_cf(bc);
578 if (r)
579 return r;
580
581 bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
582 bc->cf_last->inst = inst;
583 return 0;
584 }
585
586 /* common to all 3 families */
587 static int r600_bc_vtx_build(struct r600_bc *bc, struct r600_bc_vtx *vtx, unsigned id)
588 {
589 bc->bytecode[id++] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) |
590 S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
591 S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x) |
592 S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
593 bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
594 S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
595 S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
596 S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
597 S_SQ_VTX_WORD1_USE_CONST_FIELDS(1) |
598 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
599 bc->bytecode[id++] = S_SQ_VTX_WORD2_MEGA_FETCH(1);
600 bc->bytecode[id++] = 0;
601 return 0;
602 }
603
604 /* common to all 3 families */
605 static int r600_bc_tex_build(struct r600_bc *bc, struct r600_bc_tex *tex, unsigned id)
606 {
607 bc->bytecode[id++] = S_SQ_TEX_WORD0_TEX_INST(tex->inst) |
608 S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
609 S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
610 S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
611 bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
612 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
613 S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
614 S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
615 S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
616 S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
617 S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
618 S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
619 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
620 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
621 S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
622 bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
623 S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
624 S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
625 S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
626 S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
627 S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
628 S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
629 S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
630 bc->bytecode[id++] = 0;
631 return 0;
632 }
633
634 /* r600 only, r700/eg bits in r700_asm.c */
635 static int r600_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id)
636 {
637 unsigned i;
638
639 /* don't replace gpr by pv or ps for destination register */
640 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
641 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
642 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
643 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
644 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
645 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
646 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
647 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
648 S_SQ_ALU_WORD0_LAST(alu->last);
649
650 if (alu->is_op3) {
651 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
652 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
653 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
654 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
655 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
656 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
657 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
658 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
659 S_SQ_ALU_WORD1_OP3_ALU_INST(alu->inst) |
660 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
661 } else {
662 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
663 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
664 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
665 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
666 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
667 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
668 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
669 S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
670 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
671 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->predicate) |
672 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->predicate);
673 }
674 if (alu->last) {
675 if (alu->nliteral && !alu->literal_added) {
676 R600_ERR("Bug in ALU processing for instruction 0x%08x, literal not added correctly\n", alu->inst);
677 }
678 for (i = 0; i < alu->nliteral; i++) {
679 bc->bytecode[id++] = alu->value[i];
680 }
681 }
682 return 0;
683 }
684
685 /* common for r600/r700 - eg in eg_asm.c */
686 static int r600_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf)
687 {
688 unsigned id = cf->id;
689
690 switch (cf->inst) {
691 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
692 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
693 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
694 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache0_mode);
695
696 bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(cf->inst >> 3) |
697 S_SQ_CF_ALU_WORD1_BARRIER(1) |
698 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
699 break;
700 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
701 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
702 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
703 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
704 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) |
705 S_SQ_CF_WORD1_BARRIER(1) |
706 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
707 break;
708 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
709 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
710 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
711 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
712 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
713 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
714 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
715 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
716 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
717 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
718 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
719 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst) |
720 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program);
721 break;
722 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
723 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
724 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
725 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
726 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
727 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
728 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
729 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
730 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) |
731 S_SQ_CF_WORD1_BARRIER(1) |
732 S_SQ_CF_WORD1_COND(cf->cond) |
733 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count);
734
735 break;
736 default:
737 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
738 return -EINVAL;
739 }
740 return 0;
741 }
742
743 int r600_bc_build(struct r600_bc *bc)
744 {
745 struct r600_bc_cf *cf;
746 struct r600_bc_alu *alu;
747 struct r600_bc_vtx *vtx;
748 struct r600_bc_tex *tex;
749 unsigned addr;
750 int r;
751
752 if (bc->callstack[0].max > 0)
753 bc->nstack = ((bc->callstack[0].max + 3) >> 2) + 2;
754
755 /* first path compute addr of each CF block */
756 /* addr start after all the CF instructions */
757 addr = bc->cf_last->id + 2;
758 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
759 switch (cf->inst) {
760 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
761 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
762 break;
763 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
764 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
765 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
766 /* fetch node need to be 16 bytes aligned*/
767 addr += 3;
768 addr &= 0xFFFFFFFCUL;
769 break;
770 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
771 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
772 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
773 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
774 break;
775 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
776 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
777 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
778 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
779 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
780 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
781 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
782 break;
783 default:
784 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
785 return -EINVAL;
786 }
787 cf->addr = addr;
788 addr += cf->ndw;
789 bc->ndw = cf->addr + cf->ndw;
790 }
791 free(bc->bytecode);
792 bc->bytecode = calloc(1, bc->ndw * 4);
793 if (bc->bytecode == NULL)
794 return -ENOMEM;
795 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
796 addr = cf->addr;
797 if (bc->chiprev == 2)
798 r = eg_bc_cf_build(bc, cf);
799 else
800 r = r600_bc_cf_build(bc, cf);
801 if (r)
802 return r;
803 switch (cf->inst) {
804 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
805 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
806 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
807 switch(bc->chiprev) {
808 case 0:
809 r = r600_bc_alu_build(bc, alu, addr);
810 break;
811 case 1:
812 case 2: /* eg alu is same encoding as r700 */
813 r = r700_bc_alu_build(bc, alu, addr);
814 break;
815 default:
816 R600_ERR("unknown family %d\n", bc->family);
817 return -EINVAL;
818 }
819 if (r)
820 return r;
821 addr += 2;
822 if (alu->last) {
823 addr += alu->nliteral;
824 }
825 }
826 break;
827 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
828 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
829 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
830 r = r600_bc_vtx_build(bc, vtx, addr);
831 if (r)
832 return r;
833 addr += 4;
834 }
835 break;
836 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
837 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
838 r = r600_bc_tex_build(bc, tex, addr);
839 if (r)
840 return r;
841 addr += 4;
842 }
843 break;
844 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
845 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
846 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
847 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
848 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
849 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
850 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
851 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
852 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
853 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
854 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
855 break;
856 default:
857 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
858 return -EINVAL;
859 }
860 }
861 return 0;
862 }