2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 #include "r600_opcodes.h"
25 #include "r600_formats.h"
26 #include "r600_shader.h"
31 #include "util/u_memory.h"
32 #include "pipe/p_shader_tokens.h"
34 #define NUM_OF_CYCLES 3
35 #define NUM_OF_COMPONENTS 4
37 static inline unsigned int r600_bytecode_get_num_operands(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
42 switch (bc
->chip_class
) {
46 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
:
48 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
:
49 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT
:
50 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
:
51 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT
:
52 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT
:
53 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE
:
54 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
:
55 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE
:
56 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE
:
57 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
:
58 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE
:
59 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT
:
60 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT
:
61 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT
:
62 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT
:
63 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
:
64 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN
:
65 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT
:
66 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT
:
67 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT
:
68 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT
:
69 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE
:
70 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT
:
71 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE
:
72 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT
:
73 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
:
74 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT
:
75 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT
:
76 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
:
77 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT
:
78 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT
:
79 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE
:
80 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT
:
81 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE
:
82 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE
:
83 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT
:
84 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT
:
85 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
:
86 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE
:
87 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE
:
88 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT
:
89 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT
:
90 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT
:
91 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT
:
94 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
:
95 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA
:
96 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR
:
97 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT
:
98 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT
:
99 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
:
100 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL
:
101 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
:
102 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC
:
103 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
:
104 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED
:
105 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
:
106 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED
:
107 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
:
108 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT
:
109 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT
:
110 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED
:
111 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE
:
112 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT
:
113 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT
:
114 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT
:
115 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT
:
116 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
:
117 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
:
118 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE
:
119 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT
:
122 "Need instruction operand number for 0x%x.\n", alu
->inst
);
128 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
:
130 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
:
131 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT
:
132 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
:
133 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT
:
134 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT
:
135 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE
:
136 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
:
137 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE
:
138 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE
:
139 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
:
140 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE
:
141 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT
:
142 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT
:
143 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT
:
144 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT
:
145 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
:
146 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN
:
147 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT
:
148 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT
:
149 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT
:
150 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT
:
151 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE
:
152 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT
:
153 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE
:
154 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT
:
155 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
:
156 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT
:
157 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT
:
158 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
:
159 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT
:
160 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT
:
161 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE
:
162 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT
:
163 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT
:
164 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE
:
165 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE
:
166 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT
:
167 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
:
168 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE
:
169 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE
:
170 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_XY
:
171 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_ZW
:
172 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT
:
173 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT
:
174 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT
:
175 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT
:
178 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
:
179 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT
:
180 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
:
181 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL
:
182 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
:
183 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC
:
184 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
:
185 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED
:
186 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
:
187 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED
:
188 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
:
189 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED
:
190 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE
:
191 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT
:
192 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR
:
193 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT
:
194 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT
:
195 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT
:
196 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
:
197 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
:
198 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE
:
199 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT
:
200 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_LOAD_P0
:
201 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT
:
202 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT
:
205 "Need instruction operand number for 0x%x.\n", alu
->inst
);
213 int r700_bytecode_alu_build(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
, unsigned id
);
215 static struct r600_bytecode_cf
*r600_bytecode_cf(void)
217 struct r600_bytecode_cf
*cf
= CALLOC_STRUCT(r600_bytecode_cf
);
221 LIST_INITHEAD(&cf
->list
);
222 LIST_INITHEAD(&cf
->alu
);
223 LIST_INITHEAD(&cf
->vtx
);
224 LIST_INITHEAD(&cf
->tex
);
228 static struct r600_bytecode_alu
*r600_bytecode_alu(void)
230 struct r600_bytecode_alu
*alu
= CALLOC_STRUCT(r600_bytecode_alu
);
234 LIST_INITHEAD(&alu
->list
);
238 static struct r600_bytecode_vtx
*r600_bytecode_vtx(void)
240 struct r600_bytecode_vtx
*vtx
= CALLOC_STRUCT(r600_bytecode_vtx
);
244 LIST_INITHEAD(&vtx
->list
);
248 static struct r600_bytecode_tex
*r600_bytecode_tex(void)
250 struct r600_bytecode_tex
*tex
= CALLOC_STRUCT(r600_bytecode_tex
);
254 LIST_INITHEAD(&tex
->list
);
258 void r600_bytecode_init(struct r600_bytecode
*bc
, enum chip_class chip_class
, enum radeon_family family
)
260 if ((chip_class
== R600
) &&
261 (family
!= CHIP_RV670
&& family
!= CHIP_RS780
&& family
!= CHIP_RS880
)) {
262 bc
->ar_handling
= AR_HANDLE_RV6XX
;
263 bc
->r6xx_nop_after_rel_dst
= 1;
265 bc
->ar_handling
= AR_HANDLE_NORMAL
;
266 bc
->r6xx_nop_after_rel_dst
= 0;
269 LIST_INITHEAD(&bc
->cf
);
270 bc
->chip_class
= chip_class
;
273 static int r600_bytecode_add_cf(struct r600_bytecode
*bc
)
275 struct r600_bytecode_cf
*cf
= r600_bytecode_cf();
279 LIST_ADDTAIL(&cf
->list
, &bc
->cf
);
281 cf
->id
= bc
->cf_last
->id
+ 2;
282 if (bc
->cf_last
->eg_alu_extended
) {
283 /* take into account extended alu size */
291 bc
->force_add_cf
= 0;
296 int r600_bytecode_add_output(struct r600_bytecode
*bc
, const struct r600_bytecode_output
*output
)
300 if (output
->gpr
>= bc
->ngpr
)
301 bc
->ngpr
= output
->gpr
+ 1;
303 if (bc
->cf_last
&& (bc
->cf_last
->inst
== output
->inst
||
304 (bc
->cf_last
->inst
== BC_INST(bc
, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
) &&
305 output
->inst
== BC_INST(bc
, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
))) &&
306 output
->type
== bc
->cf_last
->output
.type
&&
307 output
->elem_size
== bc
->cf_last
->output
.elem_size
&&
308 output
->swizzle_x
== bc
->cf_last
->output
.swizzle_x
&&
309 output
->swizzle_y
== bc
->cf_last
->output
.swizzle_y
&&
310 output
->swizzle_z
== bc
->cf_last
->output
.swizzle_z
&&
311 output
->swizzle_w
== bc
->cf_last
->output
.swizzle_w
&&
312 (output
->burst_count
+ bc
->cf_last
->output
.burst_count
) <= 16) {
314 if ((output
->gpr
+ output
->burst_count
) == bc
->cf_last
->output
.gpr
&&
315 (output
->array_base
+ output
->burst_count
) == bc
->cf_last
->output
.array_base
) {
317 bc
->cf_last
->output
.end_of_program
|= output
->end_of_program
;
318 bc
->cf_last
->output
.inst
= output
->inst
;
319 bc
->cf_last
->output
.gpr
= output
->gpr
;
320 bc
->cf_last
->output
.array_base
= output
->array_base
;
321 bc
->cf_last
->output
.burst_count
+= output
->burst_count
;
324 } else if (output
->gpr
== (bc
->cf_last
->output
.gpr
+ bc
->cf_last
->output
.burst_count
) &&
325 output
->array_base
== (bc
->cf_last
->output
.array_base
+ bc
->cf_last
->output
.burst_count
)) {
327 bc
->cf_last
->output
.end_of_program
|= output
->end_of_program
;
328 bc
->cf_last
->output
.inst
= output
->inst
;
329 bc
->cf_last
->output
.burst_count
+= output
->burst_count
;
334 r
= r600_bytecode_add_cf(bc
);
337 bc
->cf_last
->inst
= output
->inst
;
338 memcpy(&bc
->cf_last
->output
, output
, sizeof(struct r600_bytecode_output
));
342 /* alu instructions that can ony exits once per group */
343 static int is_alu_once_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
345 switch (bc
->chip_class
) {
348 return !alu
->is_op3
&& (
349 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE
||
350 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
||
351 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE
||
352 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE
||
353 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT
||
354 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT
||
355 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT
||
356 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT
||
357 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT
||
358 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT
||
359 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT
||
360 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT
||
361 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE
||
362 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT
||
363 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE
||
364 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE
||
365 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV
||
366 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP
||
367 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR
||
368 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE
||
369 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH
||
370 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH
||
371 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH
||
372 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH
||
373 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT
||
374 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT
||
375 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT
||
376 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT
||
377 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT
||
378 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT
||
379 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT
||
380 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT
||
381 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT
||
382 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT
);
386 return !alu
->is_op3
&& (
387 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE
||
388 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
||
389 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE
||
390 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE
||
391 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT
||
392 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT
||
393 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT
||
394 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT
||
395 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT
||
396 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT
||
397 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT
||
398 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT
||
399 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE
||
400 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT
||
401 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE
||
402 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE
||
403 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV
||
404 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP
||
405 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR
||
406 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE
||
407 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH
||
408 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH
||
409 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH
||
410 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH
||
411 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT
||
412 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT
||
413 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT
||
414 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT
||
415 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT
||
416 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT
||
417 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT
||
418 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT
||
419 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT
||
420 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT
);
424 static int is_alu_reduction_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
426 switch (bc
->chip_class
) {
429 return !alu
->is_op3
&& (
430 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE
||
431 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
||
432 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE
||
433 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4
);
437 return !alu
->is_op3
&& (
438 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE
||
439 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
||
440 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE
||
441 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4
);
445 static int is_alu_cube_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
447 switch (bc
->chip_class
) {
450 return !alu
->is_op3
&&
451 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE
;
455 return !alu
->is_op3
&&
456 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE
;
460 static int is_alu_mova_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
462 switch (bc
->chip_class
) {
465 return !alu
->is_op3
&& (
466 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA
||
467 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR
||
468 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT
||
469 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT
);
473 return !alu
->is_op3
&& (
474 alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT
);
478 static int is_opcode_in_range(unsigned opcode
, unsigned min
, unsigned max
)
480 return min
<= opcode
&& opcode
<= max
;
483 /* ALU instructions that can only execute on the vector unit:
487 * op3 : [0x08 - 0x0B]
488 * op2 : 0x07, [0x15 - 0x18], [0x1B - 0x1D], [0x50 - 0x53], [0x7A - 0x7E]
494 static int is_alu_vec_unit_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
496 switch (bc
->chip_class
) {
500 return is_opcode_in_range(alu
->inst
,
501 V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_64
,
502 V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_64_D2
);
504 return (alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FREXP_64
) ||
505 is_opcode_in_range(alu
->inst
,
506 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA
,
507 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT
) ||
508 is_opcode_in_range(alu
->inst
,
509 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_64
,
510 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT32_TO_FLT64
) ||
511 is_opcode_in_range(alu
->inst
,
512 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
,
513 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4
) ||
514 is_opcode_in_range(alu
->inst
,
515 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LDEXP_64
,
516 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_64
);
520 return is_opcode_in_range(alu
->inst
,
521 EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_BFE_UINT
,
522 EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_LDS_IDX_OP
);
524 return is_opcode_in_range(alu
->inst
,
525 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_BFM_INT
,
526 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_LOAD_P20
);
534 /* ALU instructions that can only execute on the trans unit:
543 * op2: [0x60 - 0x6F], [0x73 - 0x79]
549 static int is_alu_trans_unit_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
552 switch (bc
->chip_class
) {
555 return alu
->inst
== V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT
;
557 return is_opcode_in_range(alu
->inst
,
558 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT
,
559 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT
);
562 return alu
->inst
== V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT
;
564 return is_opcode_in_range(alu
->inst
,
565 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT
,
566 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
) ||
567 is_opcode_in_range(alu
->inst
,
568 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT
,
569 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT
);
572 return alu
->inst
== EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT
;
574 return is_opcode_in_range(alu
->inst
,
575 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
,
576 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT
);
584 /* alu instructions that can execute on any unit */
585 static int is_alu_any_unit_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
587 return !is_alu_vec_unit_inst(bc
, alu
) &&
588 !is_alu_trans_unit_inst(bc
, alu
);
591 static int is_nop_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
593 switch (bc
->chip_class
) {
596 return (!alu
->is_op3
&& alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
);
600 return (!alu
->is_op3
&& alu
->inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
);
604 static int assign_alu_units(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu_first
,
605 struct r600_bytecode_alu
*assignment
[5])
607 struct r600_bytecode_alu
*alu
;
608 unsigned i
, chan
, trans
;
609 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
611 for (i
= 0; i
< max_slots
; i
++)
612 assignment
[i
] = NULL
;
614 for (alu
= alu_first
; alu
; alu
= LIST_ENTRY(struct r600_bytecode_alu
, alu
->list
.next
, list
)) {
615 chan
= alu
->dst
.chan
;
618 else if (is_alu_trans_unit_inst(bc
, alu
))
620 else if (is_alu_vec_unit_inst(bc
, alu
))
622 else if (assignment
[chan
])
623 trans
= 1; /* Assume ALU_INST_PREFER_VECTOR. */
629 assert(0); /* ALU.Trans has already been allocated. */
634 if (assignment
[chan
]) {
635 assert(0); /* ALU.chan has already been allocated. */
638 assignment
[chan
] = alu
;
647 struct alu_bank_swizzle
{
648 int hw_gpr
[NUM_OF_CYCLES
][NUM_OF_COMPONENTS
];
649 int hw_cfile_addr
[4];
650 int hw_cfile_elem
[4];
653 static const unsigned cycle_for_bank_swizzle_vec
[][3] = {
654 [SQ_ALU_VEC_012
] = { 0, 1, 2 },
655 [SQ_ALU_VEC_021
] = { 0, 2, 1 },
656 [SQ_ALU_VEC_120
] = { 1, 2, 0 },
657 [SQ_ALU_VEC_102
] = { 1, 0, 2 },
658 [SQ_ALU_VEC_201
] = { 2, 0, 1 },
659 [SQ_ALU_VEC_210
] = { 2, 1, 0 }
662 static const unsigned cycle_for_bank_swizzle_scl
[][3] = {
663 [SQ_ALU_SCL_210
] = { 2, 1, 0 },
664 [SQ_ALU_SCL_122
] = { 1, 2, 2 },
665 [SQ_ALU_SCL_212
] = { 2, 1, 2 },
666 [SQ_ALU_SCL_221
] = { 2, 2, 1 }
669 static void init_bank_swizzle(struct alu_bank_swizzle
*bs
)
671 int i
, cycle
, component
;
673 for (cycle
= 0; cycle
< NUM_OF_CYCLES
; cycle
++)
674 for (component
= 0; component
< NUM_OF_COMPONENTS
; component
++)
675 bs
->hw_gpr
[cycle
][component
] = -1;
676 for (i
= 0; i
< 4; i
++)
677 bs
->hw_cfile_addr
[i
] = -1;
678 for (i
= 0; i
< 4; i
++)
679 bs
->hw_cfile_elem
[i
] = -1;
682 static int reserve_gpr(struct alu_bank_swizzle
*bs
, unsigned sel
, unsigned chan
, unsigned cycle
)
684 if (bs
->hw_gpr
[cycle
][chan
] == -1)
685 bs
->hw_gpr
[cycle
][chan
] = sel
;
686 else if (bs
->hw_gpr
[cycle
][chan
] != (int)sel
) {
687 /* Another scalar operation has already used the GPR read port for the channel. */
693 static int reserve_cfile(struct r600_bytecode
*bc
, struct alu_bank_swizzle
*bs
, unsigned sel
, unsigned chan
)
695 int res
, num_res
= 4;
696 if (bc
->chip_class
>= R700
) {
700 for (res
= 0; res
< num_res
; ++res
) {
701 if (bs
->hw_cfile_addr
[res
] == -1) {
702 bs
->hw_cfile_addr
[res
] = sel
;
703 bs
->hw_cfile_elem
[res
] = chan
;
705 } else if (bs
->hw_cfile_addr
[res
] == sel
&&
706 bs
->hw_cfile_elem
[res
] == chan
)
707 return 0; /* Read for this scalar element already reserved, nothing to do here. */
709 /* All cfile read ports are used, cannot reference vector element. */
713 static int is_gpr(unsigned sel
)
715 return (sel
>= 0 && sel
<= 127);
718 /* CB constants start at 512, and get translated to a kcache index when ALU
719 * clauses are constructed. Note that we handle kcache constants the same way
720 * as (the now gone) cfile constants, is that really required? */
721 static int is_cfile(unsigned sel
)
723 return (sel
> 255 && sel
< 512) ||
724 (sel
> 511 && sel
< 4607) || /* Kcache before translation. */
725 (sel
> 127 && sel
< 192); /* Kcache after translation. */
728 static int is_const(int sel
)
730 return is_cfile(sel
) ||
731 (sel
>= V_SQ_ALU_SRC_0
&&
732 sel
<= V_SQ_ALU_SRC_LITERAL
);
735 static int check_vector(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
,
736 struct alu_bank_swizzle
*bs
, int bank_swizzle
)
738 int r
, src
, num_src
, sel
, elem
, cycle
;
740 num_src
= r600_bytecode_get_num_operands(bc
, alu
);
741 for (src
= 0; src
< num_src
; src
++) {
742 sel
= alu
->src
[src
].sel
;
743 elem
= alu
->src
[src
].chan
;
745 cycle
= cycle_for_bank_swizzle_vec
[bank_swizzle
][src
];
746 if (src
== 1 && sel
== alu
->src
[0].sel
&& elem
== alu
->src
[0].chan
)
747 /* Nothing to do; special-case optimization,
748 * second source uses first source’s reservation. */
751 r
= reserve_gpr(bs
, sel
, elem
, cycle
);
755 } else if (is_cfile(sel
)) {
756 r
= reserve_cfile(bc
, bs
, (alu
->src
[src
].kc_bank
<<16) + sel
, elem
);
760 /* No restrictions on PV, PS, literal or special constants. */
765 static int check_scalar(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
,
766 struct alu_bank_swizzle
*bs
, int bank_swizzle
)
768 int r
, src
, num_src
, const_count
, sel
, elem
, cycle
;
770 num_src
= r600_bytecode_get_num_operands(bc
, alu
);
771 for (const_count
= 0, src
= 0; src
< num_src
; ++src
) {
772 sel
= alu
->src
[src
].sel
;
773 elem
= alu
->src
[src
].chan
;
774 if (is_const(sel
)) { /* Any constant, including literal and inline constants. */
775 if (const_count
>= 2)
776 /* More than two references to a constant in
777 * transcendental operation. */
783 r
= reserve_cfile(bc
, bs
, (alu
->src
[src
].kc_bank
<<16) + sel
, elem
);
788 for (src
= 0; src
< num_src
; ++src
) {
789 sel
= alu
->src
[src
].sel
;
790 elem
= alu
->src
[src
].chan
;
792 cycle
= cycle_for_bank_swizzle_scl
[bank_swizzle
][src
];
793 if (cycle
< const_count
)
794 /* Cycle for GPR load conflicts with
795 * constant load in transcendental operation. */
797 r
= reserve_gpr(bs
, sel
, elem
, cycle
);
801 /* PV PS restrictions */
802 if (const_count
&& (sel
== 254 || sel
== 255)) {
803 cycle
= cycle_for_bank_swizzle_scl
[bank_swizzle
][src
];
804 if (cycle
< const_count
)
811 static int check_and_set_bank_swizzle(struct r600_bytecode
*bc
,
812 struct r600_bytecode_alu
*slots
[5])
814 struct alu_bank_swizzle bs
;
816 int i
, r
= 0, forced
= 1;
817 boolean scalar_only
= bc
->chip_class
== CAYMAN
? false : true;
818 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
820 for (i
= 0; i
< max_slots
; i
++) {
822 if (slots
[i
]->bank_swizzle_force
) {
823 slots
[i
]->bank_swizzle
= slots
[i
]->bank_swizzle_force
;
829 if (i
< 4 && slots
[i
])
835 /* Just check every possible combination of bank swizzle.
836 * Not very efficent, but works on the first try in most of the cases. */
837 for (i
= 0; i
< 4; i
++)
838 if (!slots
[i
] || !slots
[i
]->bank_swizzle_force
)
839 bank_swizzle
[i
] = SQ_ALU_VEC_012
;
841 bank_swizzle
[i
] = slots
[i
]->bank_swizzle
;
843 bank_swizzle
[4] = SQ_ALU_SCL_210
;
844 while(bank_swizzle
[4] <= SQ_ALU_SCL_221
) {
846 if (max_slots
== 4) {
847 for (i
= 0; i
< max_slots
; i
++) {
848 if (bank_swizzle
[i
] == SQ_ALU_VEC_210
)
852 init_bank_swizzle(&bs
);
853 if (scalar_only
== false) {
854 for (i
= 0; i
< 4; i
++) {
856 r
= check_vector(bc
, slots
[i
], &bs
, bank_swizzle
[i
]);
864 if (!r
&& slots
[4] && max_slots
== 5) {
865 r
= check_scalar(bc
, slots
[4], &bs
, bank_swizzle
[4]);
868 for (i
= 0; i
< max_slots
; i
++) {
870 slots
[i
]->bank_swizzle
= bank_swizzle
[i
];
878 for (i
= 0; i
< max_slots
; i
++) {
879 if (!slots
[i
] || !slots
[i
]->bank_swizzle_force
) {
881 if (bank_swizzle
[i
] <= SQ_ALU_VEC_210
)
884 bank_swizzle
[i
] = SQ_ALU_VEC_012
;
890 /* Couldn't find a working swizzle. */
894 static int replace_gpr_with_pv_ps(struct r600_bytecode
*bc
,
895 struct r600_bytecode_alu
*slots
[5], struct r600_bytecode_alu
*alu_prev
)
897 struct r600_bytecode_alu
*prev
[5];
899 int i
, j
, r
, src
, num_src
;
900 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
902 r
= assign_alu_units(bc
, alu_prev
, prev
);
906 for (i
= 0; i
< max_slots
; ++i
) {
907 if (prev
[i
] && (prev
[i
]->dst
.write
|| prev
[i
]->is_op3
) && !prev
[i
]->dst
.rel
) {
908 gpr
[i
] = prev
[i
]->dst
.sel
;
909 /* cube writes more than PV.X */
910 if (!is_alu_cube_inst(bc
, prev
[i
]) && is_alu_reduction_inst(bc
, prev
[i
]))
913 chan
[i
] = prev
[i
]->dst
.chan
;
918 for (i
= 0; i
< max_slots
; ++i
) {
919 struct r600_bytecode_alu
*alu
= slots
[i
];
923 num_src
= r600_bytecode_get_num_operands(bc
, alu
);
924 for (src
= 0; src
< num_src
; ++src
) {
925 if (!is_gpr(alu
->src
[src
].sel
) || alu
->src
[src
].rel
)
928 if (bc
->chip_class
< CAYMAN
) {
929 if (alu
->src
[src
].sel
== gpr
[4] &&
930 alu
->src
[src
].chan
== chan
[4] &&
931 alu_prev
->pred_sel
== alu
->pred_sel
) {
932 alu
->src
[src
].sel
= V_SQ_ALU_SRC_PS
;
933 alu
->src
[src
].chan
= 0;
938 for (j
= 0; j
< 4; ++j
) {
939 if (alu
->src
[src
].sel
== gpr
[j
] &&
940 alu
->src
[src
].chan
== j
&&
941 alu_prev
->pred_sel
== alu
->pred_sel
) {
942 alu
->src
[src
].sel
= V_SQ_ALU_SRC_PV
;
943 alu
->src
[src
].chan
= chan
[j
];
953 void r600_bytecode_special_constants(uint32_t value
, unsigned *sel
, unsigned *neg
)
957 *sel
= V_SQ_ALU_SRC_0
;
960 *sel
= V_SQ_ALU_SRC_1_INT
;
963 *sel
= V_SQ_ALU_SRC_M_1_INT
;
965 case 0x3F800000: /* 1.0f */
966 *sel
= V_SQ_ALU_SRC_1
;
968 case 0x3F000000: /* 0.5f */
969 *sel
= V_SQ_ALU_SRC_0_5
;
971 case 0xBF800000: /* -1.0f */
972 *sel
= V_SQ_ALU_SRC_1
;
975 case 0xBF000000: /* -0.5f */
976 *sel
= V_SQ_ALU_SRC_0_5
;
980 *sel
= V_SQ_ALU_SRC_LITERAL
;
985 /* compute how many literal are needed */
986 static int r600_bytecode_alu_nliterals(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
,
987 uint32_t literal
[4], unsigned *nliteral
)
989 unsigned num_src
= r600_bytecode_get_num_operands(bc
, alu
);
992 for (i
= 0; i
< num_src
; ++i
) {
993 if (alu
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
994 uint32_t value
= alu
->src
[i
].value
;
996 for (j
= 0; j
< *nliteral
; ++j
) {
997 if (literal
[j
] == value
) {
1005 literal
[(*nliteral
)++] = value
;
1012 static void r600_bytecode_alu_adjust_literals(struct r600_bytecode
*bc
,
1013 struct r600_bytecode_alu
*alu
,
1014 uint32_t literal
[4], unsigned nliteral
)
1016 unsigned num_src
= r600_bytecode_get_num_operands(bc
, alu
);
1019 for (i
= 0; i
< num_src
; ++i
) {
1020 if (alu
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
1021 uint32_t value
= alu
->src
[i
].value
;
1022 for (j
= 0; j
< nliteral
; ++j
) {
1023 if (literal
[j
] == value
) {
1024 alu
->src
[i
].chan
= j
;
1032 static int merge_inst_groups(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*slots
[5],
1033 struct r600_bytecode_alu
*alu_prev
)
1035 struct r600_bytecode_alu
*prev
[5];
1036 struct r600_bytecode_alu
*result
[5] = { NULL
};
1038 uint32_t literal
[4], prev_literal
[4];
1039 unsigned nliteral
= 0, prev_nliteral
= 0;
1041 int i
, j
, r
, src
, num_src
;
1042 int num_once_inst
= 0;
1043 int have_mova
= 0, have_rel
= 0;
1044 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
1046 r
= assign_alu_units(bc
, alu_prev
, prev
);
1050 for (i
= 0; i
< max_slots
; ++i
) {
1052 if (prev
[i
]->pred_sel
)
1054 if (is_alu_once_inst(bc
, prev
[i
]))
1058 if (slots
[i
]->pred_sel
)
1060 if (is_alu_once_inst(bc
, slots
[i
]))
1065 for (i
= 0; i
< max_slots
; ++i
) {
1066 struct r600_bytecode_alu
*alu
;
1068 if (num_once_inst
> 0)
1071 /* check number of literals */
1073 if (r600_bytecode_alu_nliterals(bc
, prev
[i
], literal
, &nliteral
))
1075 if (r600_bytecode_alu_nliterals(bc
, prev
[i
], prev_literal
, &prev_nliteral
))
1077 if (is_alu_mova_inst(bc
, prev
[i
])) {
1082 num_once_inst
+= is_alu_once_inst(bc
, prev
[i
]);
1084 if (slots
[i
] && r600_bytecode_alu_nliterals(bc
, slots
[i
], literal
, &nliteral
))
1087 /* Let's check used slots. */
1088 if (prev
[i
] && !slots
[i
]) {
1089 result
[i
] = prev
[i
];
1091 } else if (prev
[i
] && slots
[i
]) {
1092 if (max_slots
== 5 && result
[4] == NULL
&& prev
[4] == NULL
&& slots
[4] == NULL
) {
1093 /* Trans unit is still free try to use it. */
1094 if (is_alu_any_unit_inst(bc
, slots
[i
])) {
1095 result
[i
] = prev
[i
];
1096 result
[4] = slots
[i
];
1097 } else if (is_alu_any_unit_inst(bc
, prev
[i
])) {
1098 if (slots
[i
]->dst
.sel
== prev
[i
]->dst
.sel
&&
1099 (slots
[i
]->dst
.write
== 1 || slots
[i
]->is_op3
) &&
1100 (prev
[i
]->dst
.write
== 1 || prev
[i
]->is_op3
))
1103 result
[i
] = slots
[i
];
1104 result
[4] = prev
[i
];
1109 } else if(!slots
[i
]) {
1112 if (max_slots
== 5 && slots
[i
] && prev
[4] &&
1113 slots
[i
]->dst
.sel
== prev
[4]->dst
.sel
&&
1114 slots
[i
]->dst
.chan
== prev
[4]->dst
.chan
&&
1115 (slots
[i
]->dst
.write
== 1 || slots
[i
]->is_op3
) &&
1116 (prev
[4]->dst
.write
== 1 || prev
[4]->is_op3
))
1119 result
[i
] = slots
[i
];
1123 num_once_inst
+= is_alu_once_inst(bc
, alu
);
1125 /* don't reschedule NOPs */
1126 if (is_nop_inst(bc
, alu
))
1129 /* Let's check dst gpr. */
1136 /* Let's check source gprs */
1137 num_src
= r600_bytecode_get_num_operands(bc
, alu
);
1138 for (src
= 0; src
< num_src
; ++src
) {
1139 if (alu
->src
[src
].rel
) {
1145 /* Constants don't matter. */
1146 if (!is_gpr(alu
->src
[src
].sel
))
1149 for (j
= 0; j
< max_slots
; ++j
) {
1150 if (!prev
[j
] || !(prev
[j
]->dst
.write
|| prev
[j
]->is_op3
))
1153 /* If it's relative then we can't determin which gpr is really used. */
1154 if (prev
[j
]->dst
.chan
== alu
->src
[src
].chan
&&
1155 (prev
[j
]->dst
.sel
== alu
->src
[src
].sel
||
1156 prev
[j
]->dst
.rel
|| alu
->src
[src
].rel
))
1162 /* more than one PRED_ or KILL_ ? */
1163 if (num_once_inst
> 1)
1166 /* check if the result can still be swizzlet */
1167 r
= check_and_set_bank_swizzle(bc
, result
);
1171 /* looks like everything worked out right, apply the changes */
1173 /* undo adding previus literals */
1174 bc
->cf_last
->ndw
-= align(prev_nliteral
, 2);
1176 /* sort instructions */
1177 for (i
= 0; i
< max_slots
; ++i
) {
1178 slots
[i
] = result
[i
];
1180 LIST_DEL(&result
[i
]->list
);
1181 result
[i
]->last
= 0;
1182 LIST_ADDTAIL(&result
[i
]->list
, &bc
->cf_last
->alu
);
1186 /* determine new last instruction */
1187 LIST_ENTRY(struct r600_bytecode_alu
, bc
->cf_last
->alu
.prev
, list
)->last
= 1;
1189 /* determine new first instruction */
1190 for (i
= 0; i
< max_slots
; ++i
) {
1192 bc
->cf_last
->curr_bs_head
= result
[i
];
1197 bc
->cf_last
->prev_bs_head
= bc
->cf_last
->prev2_bs_head
;
1198 bc
->cf_last
->prev2_bs_head
= NULL
;
1203 /* we'll keep kcache sets sorted by bank & addr */
1204 static int r600_bytecode_alloc_kcache_line(struct r600_bytecode
*bc
,
1205 struct r600_bytecode_kcache
*kcache
,
1206 unsigned bank
, unsigned line
)
1208 int i
, kcache_banks
= bc
->chip_class
>= EVERGREEN
? 4 : 2;
1210 for (i
= 0; i
< kcache_banks
; i
++) {
1211 if (kcache
[i
].mode
) {
1214 if (kcache
[i
].bank
< bank
)
1217 if ((kcache
[i
].bank
== bank
&& kcache
[i
].addr
> line
+1) ||
1218 kcache
[i
].bank
> bank
) {
1219 /* try to insert new line */
1220 if (kcache
[kcache_banks
-1].mode
) {
1221 /* all sets are in use */
1225 memmove(&kcache
[i
+1],&kcache
[i
], (kcache_banks
-i
-1)*sizeof(struct r600_bytecode_kcache
));
1226 kcache
[i
].mode
= V_SQ_CF_KCACHE_LOCK_1
;
1227 kcache
[i
].bank
= bank
;
1228 kcache
[i
].addr
= line
;
1232 d
= line
- kcache
[i
].addr
;
1236 if (kcache
[i
].mode
== V_SQ_CF_KCACHE_LOCK_2
) {
1237 /* we are prepending the line to the current set,
1238 * discarding the existing second line,
1239 * so we'll have to insert line+2 after it */
1242 } else if (kcache
[i
].mode
== V_SQ_CF_KCACHE_LOCK_1
) {
1243 kcache
[i
].mode
= V_SQ_CF_KCACHE_LOCK_2
;
1246 /* V_SQ_CF_KCACHE_LOCK_LOOP_INDEX is not supported */
1249 } else if (d
== 1) {
1250 kcache
[i
].mode
= V_SQ_CF_KCACHE_LOCK_2
;
1254 } else { /* free kcache set - use it */
1255 kcache
[i
].mode
= V_SQ_CF_KCACHE_LOCK_1
;
1256 kcache
[i
].bank
= bank
;
1257 kcache
[i
].addr
= line
;
1264 static int r600_bytecode_alloc_inst_kcache_lines(struct r600_bytecode
*bc
,
1265 struct r600_bytecode_kcache
*kcache
,
1266 struct r600_bytecode_alu
*alu
)
1270 for (i
= 0; i
< 3; i
++) {
1271 unsigned bank
, line
, sel
= alu
->src
[i
].sel
;
1276 bank
= alu
->src
[i
].kc_bank
;
1277 line
= (sel
-512)>>4;
1279 if ((r
= r600_bytecode_alloc_kcache_line(bc
, kcache
, bank
, line
)))
1285 static int r600_bytecode_assign_kcache_banks(struct r600_bytecode
*bc
,
1286 struct r600_bytecode_alu
*alu
,
1287 struct r600_bytecode_kcache
* kcache
)
1291 /* Alter the src operands to refer to the kcache. */
1292 for (i
= 0; i
< 3; ++i
) {
1293 static const unsigned int base
[] = {128, 160, 256, 288};
1294 unsigned int line
, sel
= alu
->src
[i
].sel
, found
= 0;
1302 for (j
= 0; j
< 4 && !found
; ++j
) {
1303 switch (kcache
[j
].mode
) {
1304 case V_SQ_CF_KCACHE_NOP
:
1305 case V_SQ_CF_KCACHE_LOCK_LOOP_INDEX
:
1306 R600_ERR("unexpected kcache line mode\n");
1309 if (kcache
[j
].bank
== alu
->src
[i
].kc_bank
&&
1310 kcache
[j
].addr
<= line
&&
1311 line
< kcache
[j
].addr
+ kcache
[j
].mode
) {
1312 alu
->src
[i
].sel
= sel
- (kcache
[j
].addr
<<4);
1313 alu
->src
[i
].sel
+= base
[j
];
1322 static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
, int type
)
1324 struct r600_bytecode_kcache kcache_sets
[4];
1325 struct r600_bytecode_kcache
*kcache
= kcache_sets
;
1328 memcpy(kcache
, bc
->cf_last
->kcache
, 4 * sizeof(struct r600_bytecode_kcache
));
1330 if ((r
= r600_bytecode_alloc_inst_kcache_lines(bc
, kcache
, alu
))) {
1331 /* can't alloc, need to start new clause */
1332 if ((r
= r600_bytecode_add_cf(bc
))) {
1335 bc
->cf_last
->inst
= type
;
1337 /* retry with the new clause */
1338 kcache
= bc
->cf_last
->kcache
;
1339 if ((r
= r600_bytecode_alloc_inst_kcache_lines(bc
, kcache
, alu
))) {
1340 /* can't alloc again- should never happen */
1344 /* update kcache sets */
1345 memcpy(bc
->cf_last
->kcache
, kcache
, 4 * sizeof(struct r600_bytecode_kcache
));
1348 /* if we actually used more than 2 kcache sets - use ALU_EXTENDED on eg+ */
1349 if (kcache
[2].mode
!= V_SQ_CF_KCACHE_NOP
) {
1350 if (bc
->chip_class
< EVERGREEN
)
1352 bc
->cf_last
->eg_alu_extended
= 1;
1358 static int insert_nop_r6xx(struct r600_bytecode
*bc
)
1360 struct r600_bytecode_alu alu
;
1363 for (i
= 0; i
< 4; i
++) {
1364 memset(&alu
, 0, sizeof(alu
));
1365 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
;
1366 alu
.src
[0].chan
= i
;
1368 alu
.last
= (i
== 3);
1369 r
= r600_bytecode_add_alu(bc
, &alu
);
1376 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1377 static int load_ar_r6xx(struct r600_bytecode
*bc
)
1379 struct r600_bytecode_alu alu
;
1385 /* hack to avoid making MOVA the last instruction in the clause */
1386 if ((bc
->cf_last
->ndw
>>1) >= 110)
1387 bc
->force_add_cf
= 1;
1389 memset(&alu
, 0, sizeof(alu
));
1390 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT
;
1391 alu
.src
[0].sel
= bc
->ar_reg
;
1393 alu
.index_mode
= INDEX_MODE_LOOP
;
1394 r
= r600_bytecode_add_alu(bc
, &alu
);
1398 /* no requirement to set uses waterfall on MOVA_GPR_INT */
1403 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1404 static int load_ar(struct r600_bytecode
*bc
)
1406 struct r600_bytecode_alu alu
;
1409 if (bc
->ar_handling
)
1410 return load_ar_r6xx(bc
);
1415 /* hack to avoid making MOVA the last instruction in the clause */
1416 if ((bc
->cf_last
->ndw
>>1) >= 110)
1417 bc
->force_add_cf
= 1;
1419 memset(&alu
, 0, sizeof(alu
));
1420 alu
.inst
= BC_INST(bc
, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT
);
1421 alu
.src
[0].sel
= bc
->ar_reg
;
1423 r
= r600_bytecode_add_alu(bc
, &alu
);
1427 bc
->cf_last
->r6xx_uses_waterfall
= 1;
1432 int r600_bytecode_add_alu_type(struct r600_bytecode
*bc
, const struct r600_bytecode_alu
*alu
, int type
)
1434 struct r600_bytecode_alu
*nalu
= r600_bytecode_alu();
1435 struct r600_bytecode_alu
*lalu
;
1440 memcpy(nalu
, alu
, sizeof(struct r600_bytecode_alu
));
1442 if (bc
->cf_last
!= NULL
&& bc
->cf_last
->inst
!= type
) {
1443 /* check if we could add it anyway */
1444 if (bc
->cf_last
->inst
== BC_INST(bc
, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
) &&
1445 type
== BC_INST(bc
, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
)) {
1446 LIST_FOR_EACH_ENTRY(lalu
, &bc
->cf_last
->alu
, list
) {
1447 if (lalu
->execute_mask
) {
1448 bc
->force_add_cf
= 1;
1453 bc
->force_add_cf
= 1;
1456 /* cf can contains only alu or only vtx or only tex */
1457 if (bc
->cf_last
== NULL
|| bc
->force_add_cf
) {
1458 r
= r600_bytecode_add_cf(bc
);
1464 bc
->cf_last
->inst
= type
;
1466 /* Check AR usage and load it if required */
1467 for (i
= 0; i
< 3; i
++)
1468 if (nalu
->src
[i
].rel
&& !bc
->ar_loaded
)
1471 if (nalu
->dst
.rel
&& !bc
->ar_loaded
)
1474 /* Setup the kcache for this ALU instruction. This will start a new
1475 * ALU clause if needed. */
1476 if ((r
= r600_bytecode_alloc_kcache_lines(bc
, nalu
, type
))) {
1481 if (!bc
->cf_last
->curr_bs_head
) {
1482 bc
->cf_last
->curr_bs_head
= nalu
;
1484 /* number of gpr == the last gpr used in any alu */
1485 for (i
= 0; i
< 3; i
++) {
1486 if (nalu
->src
[i
].sel
>= bc
->ngpr
&& nalu
->src
[i
].sel
< 128) {
1487 bc
->ngpr
= nalu
->src
[i
].sel
+ 1;
1489 if (nalu
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
)
1490 r600_bytecode_special_constants(nalu
->src
[i
].value
,
1491 &nalu
->src
[i
].sel
, &nalu
->src
[i
].neg
);
1493 if (nalu
->dst
.sel
>= bc
->ngpr
) {
1494 bc
->ngpr
= nalu
->dst
.sel
+ 1;
1496 LIST_ADDTAIL(&nalu
->list
, &bc
->cf_last
->alu
);
1497 /* each alu use 2 dwords */
1498 bc
->cf_last
->ndw
+= 2;
1501 /* process cur ALU instructions for bank swizzle */
1503 uint32_t literal
[4];
1505 struct r600_bytecode_alu
*slots
[5];
1506 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
1507 r
= assign_alu_units(bc
, bc
->cf_last
->curr_bs_head
, slots
);
1511 if (bc
->cf_last
->prev_bs_head
) {
1512 r
= merge_inst_groups(bc
, slots
, bc
->cf_last
->prev_bs_head
);
1517 if (bc
->cf_last
->prev_bs_head
) {
1518 r
= replace_gpr_with_pv_ps(bc
, slots
, bc
->cf_last
->prev_bs_head
);
1523 r
= check_and_set_bank_swizzle(bc
, slots
);
1527 for (i
= 0, nliteral
= 0; i
< max_slots
; i
++) {
1529 r
= r600_bytecode_alu_nliterals(bc
, slots
[i
], literal
, &nliteral
);
1534 bc
->cf_last
->ndw
+= align(nliteral
, 2);
1536 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1538 if ((bc
->cf_last
->ndw
>> 1) >= 120) {
1539 bc
->force_add_cf
= 1;
1542 bc
->cf_last
->prev2_bs_head
= bc
->cf_last
->prev_bs_head
;
1543 bc
->cf_last
->prev_bs_head
= bc
->cf_last
->curr_bs_head
;
1544 bc
->cf_last
->curr_bs_head
= NULL
;
1547 if (nalu
->dst
.rel
&& bc
->r6xx_nop_after_rel_dst
)
1548 insert_nop_r6xx(bc
);
1553 int r600_bytecode_add_alu(struct r600_bytecode
*bc
, const struct r600_bytecode_alu
*alu
)
1555 return r600_bytecode_add_alu_type(bc
, alu
, BC_INST(bc
, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
));
1558 static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode
*bc
)
1560 switch (bc
->chip_class
) {
1570 R600_ERR("Unknown chip class %d.\n", bc
->chip_class
);
1575 static inline boolean
last_inst_was_not_vtx_fetch(struct r600_bytecode
*bc
)
1577 switch (bc
->chip_class
) {
1580 return bc
->cf_last
->inst
!= V_SQ_CF_WORD1_SQ_CF_INST_VTX
&&
1581 bc
->cf_last
->inst
!= V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC
;
1583 return bc
->cf_last
->inst
!= EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX
;
1585 return bc
->cf_last
->inst
!= CM_V_SQ_CF_WORD1_SQ_CF_INST_TC
;
1587 R600_ERR("Unknown chip class %d.\n", bc
->chip_class
);
1592 int r600_bytecode_add_vtx(struct r600_bytecode
*bc
, const struct r600_bytecode_vtx
*vtx
)
1594 struct r600_bytecode_vtx
*nvtx
= r600_bytecode_vtx();
1599 memcpy(nvtx
, vtx
, sizeof(struct r600_bytecode_vtx
));
1601 /* cf can contains only alu or only vtx or only tex */
1602 if (bc
->cf_last
== NULL
||
1603 last_inst_was_not_vtx_fetch(bc
) ||
1605 r
= r600_bytecode_add_cf(bc
);
1610 switch (bc
->chip_class
) {
1613 bc
->cf_last
->inst
= V_SQ_CF_WORD1_SQ_CF_INST_VTX
;
1616 bc
->cf_last
->inst
= EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX
;
1619 bc
->cf_last
->inst
= CM_V_SQ_CF_WORD1_SQ_CF_INST_TC
;
1622 R600_ERR("Unknown chip class %d.\n", bc
->chip_class
);
1626 LIST_ADDTAIL(&nvtx
->list
, &bc
->cf_last
->vtx
);
1627 /* each fetch use 4 dwords */
1628 bc
->cf_last
->ndw
+= 4;
1630 if ((bc
->cf_last
->ndw
/ 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc
))
1631 bc
->force_add_cf
= 1;
1633 bc
->ngpr
= MAX2(bc
->ngpr
, vtx
->src_gpr
+ 1);
1634 bc
->ngpr
= MAX2(bc
->ngpr
, vtx
->dst_gpr
+ 1);
1639 int r600_bytecode_add_tex(struct r600_bytecode
*bc
, const struct r600_bytecode_tex
*tex
)
1641 struct r600_bytecode_tex
*ntex
= r600_bytecode_tex();
1646 memcpy(ntex
, tex
, sizeof(struct r600_bytecode_tex
));
1648 /* we can't fetch data und use it as texture lookup address in the same TEX clause */
1649 if (bc
->cf_last
!= NULL
&&
1650 bc
->cf_last
->inst
== BC_INST(bc
, V_SQ_CF_WORD1_SQ_CF_INST_TEX
)) {
1651 struct r600_bytecode_tex
*ttex
;
1652 LIST_FOR_EACH_ENTRY(ttex
, &bc
->cf_last
->tex
, list
) {
1653 if (ttex
->dst_gpr
== ntex
->src_gpr
) {
1654 bc
->force_add_cf
= 1;
1658 /* slight hack to make gradients always go into same cf */
1659 if (ntex
->inst
== SQ_TEX_INST_SET_GRADIENTS_H
)
1660 bc
->force_add_cf
= 1;
1663 /* cf can contains only alu or only vtx or only tex */
1664 if (bc
->cf_last
== NULL
||
1665 bc
->cf_last
->inst
!= BC_INST(bc
, V_SQ_CF_WORD1_SQ_CF_INST_TEX
) ||
1667 r
= r600_bytecode_add_cf(bc
);
1672 bc
->cf_last
->inst
= BC_INST(bc
, V_SQ_CF_WORD1_SQ_CF_INST_TEX
);
1674 if (ntex
->src_gpr
>= bc
->ngpr
) {
1675 bc
->ngpr
= ntex
->src_gpr
+ 1;
1677 if (ntex
->dst_gpr
>= bc
->ngpr
) {
1678 bc
->ngpr
= ntex
->dst_gpr
+ 1;
1680 LIST_ADDTAIL(&ntex
->list
, &bc
->cf_last
->tex
);
1681 /* each texture fetch use 4 dwords */
1682 bc
->cf_last
->ndw
+= 4;
1684 if ((bc
->cf_last
->ndw
/ 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc
))
1685 bc
->force_add_cf
= 1;
1689 int r600_bytecode_add_cfinst(struct r600_bytecode
*bc
, int inst
)
1692 r
= r600_bytecode_add_cf(bc
);
1696 bc
->cf_last
->cond
= V_SQ_CF_COND_ACTIVE
;
1697 bc
->cf_last
->inst
= inst
;
1701 int cm_bytecode_add_cf_end(struct r600_bytecode
*bc
)
1703 return r600_bytecode_add_cfinst(bc
, CM_V_SQ_CF_WORD1_SQ_CF_INST_END
);
1706 /* common to all 3 families */
1707 static int r600_bytecode_vtx_build(struct r600_bytecode
*bc
, struct r600_bytecode_vtx
*vtx
, unsigned id
)
1709 bc
->bytecode
[id
] = S_SQ_VTX_WORD0_BUFFER_ID(vtx
->buffer_id
) |
1710 S_SQ_VTX_WORD0_FETCH_TYPE(vtx
->fetch_type
) |
1711 S_SQ_VTX_WORD0_SRC_GPR(vtx
->src_gpr
) |
1712 S_SQ_VTX_WORD0_SRC_SEL_X(vtx
->src_sel_x
);
1713 if (bc
->chip_class
< CAYMAN
)
1714 bc
->bytecode
[id
] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx
->mega_fetch_count
);
1716 bc
->bytecode
[id
++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx
->dst_sel_x
) |
1717 S_SQ_VTX_WORD1_DST_SEL_Y(vtx
->dst_sel_y
) |
1718 S_SQ_VTX_WORD1_DST_SEL_Z(vtx
->dst_sel_z
) |
1719 S_SQ_VTX_WORD1_DST_SEL_W(vtx
->dst_sel_w
) |
1720 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx
->use_const_fields
) |
1721 S_SQ_VTX_WORD1_DATA_FORMAT(vtx
->data_format
) |
1722 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx
->num_format_all
) |
1723 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx
->format_comp_all
) |
1724 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx
->srf_mode_all
) |
1725 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx
->dst_gpr
);
1726 bc
->bytecode
[id
] = S_SQ_VTX_WORD2_OFFSET(vtx
->offset
)|
1727 S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx
->endian
);
1728 if (bc
->chip_class
< CAYMAN
)
1729 bc
->bytecode
[id
] |= S_SQ_VTX_WORD2_MEGA_FETCH(1);
1731 bc
->bytecode
[id
++] = 0;
1735 /* common to all 3 families */
1736 static int r600_bytecode_tex_build(struct r600_bytecode
*bc
, struct r600_bytecode_tex
*tex
, unsigned id
)
1738 bc
->bytecode
[id
++] = S_SQ_TEX_WORD0_TEX_INST(tex
->inst
) |
1739 S_SQ_TEX_WORD0_RESOURCE_ID(tex
->resource_id
) |
1740 S_SQ_TEX_WORD0_SRC_GPR(tex
->src_gpr
) |
1741 S_SQ_TEX_WORD0_SRC_REL(tex
->src_rel
);
1742 bc
->bytecode
[id
++] = S_SQ_TEX_WORD1_DST_GPR(tex
->dst_gpr
) |
1743 S_SQ_TEX_WORD1_DST_REL(tex
->dst_rel
) |
1744 S_SQ_TEX_WORD1_DST_SEL_X(tex
->dst_sel_x
) |
1745 S_SQ_TEX_WORD1_DST_SEL_Y(tex
->dst_sel_y
) |
1746 S_SQ_TEX_WORD1_DST_SEL_Z(tex
->dst_sel_z
) |
1747 S_SQ_TEX_WORD1_DST_SEL_W(tex
->dst_sel_w
) |
1748 S_SQ_TEX_WORD1_LOD_BIAS(tex
->lod_bias
) |
1749 S_SQ_TEX_WORD1_COORD_TYPE_X(tex
->coord_type_x
) |
1750 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex
->coord_type_y
) |
1751 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex
->coord_type_z
) |
1752 S_SQ_TEX_WORD1_COORD_TYPE_W(tex
->coord_type_w
);
1753 bc
->bytecode
[id
++] = S_SQ_TEX_WORD2_OFFSET_X(tex
->offset_x
) |
1754 S_SQ_TEX_WORD2_OFFSET_Y(tex
->offset_y
) |
1755 S_SQ_TEX_WORD2_OFFSET_Z(tex
->offset_z
) |
1756 S_SQ_TEX_WORD2_SAMPLER_ID(tex
->sampler_id
) |
1757 S_SQ_TEX_WORD2_SRC_SEL_X(tex
->src_sel_x
) |
1758 S_SQ_TEX_WORD2_SRC_SEL_Y(tex
->src_sel_y
) |
1759 S_SQ_TEX_WORD2_SRC_SEL_Z(tex
->src_sel_z
) |
1760 S_SQ_TEX_WORD2_SRC_SEL_W(tex
->src_sel_w
);
1761 bc
->bytecode
[id
++] = 0;
1765 /* r600 only, r700/eg bits in r700_asm.c */
1766 static int r600_bytecode_alu_build(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
, unsigned id
)
1768 /* don't replace gpr by pv or ps for destination register */
1769 bc
->bytecode
[id
++] = S_SQ_ALU_WORD0_SRC0_SEL(alu
->src
[0].sel
) |
1770 S_SQ_ALU_WORD0_SRC0_REL(alu
->src
[0].rel
) |
1771 S_SQ_ALU_WORD0_SRC0_CHAN(alu
->src
[0].chan
) |
1772 S_SQ_ALU_WORD0_SRC0_NEG(alu
->src
[0].neg
) |
1773 S_SQ_ALU_WORD0_SRC1_SEL(alu
->src
[1].sel
) |
1774 S_SQ_ALU_WORD0_SRC1_REL(alu
->src
[1].rel
) |
1775 S_SQ_ALU_WORD0_SRC1_CHAN(alu
->src
[1].chan
) |
1776 S_SQ_ALU_WORD0_SRC1_NEG(alu
->src
[1].neg
) |
1777 S_SQ_ALU_WORD0_INDEX_MODE(alu
->index_mode
) |
1778 S_SQ_ALU_WORD0_PRED_SEL(alu
->pred_sel
) |
1779 S_SQ_ALU_WORD0_LAST(alu
->last
);
1782 bc
->bytecode
[id
++] = S_SQ_ALU_WORD1_DST_GPR(alu
->dst
.sel
) |
1783 S_SQ_ALU_WORD1_DST_CHAN(alu
->dst
.chan
) |
1784 S_SQ_ALU_WORD1_DST_REL(alu
->dst
.rel
) |
1785 S_SQ_ALU_WORD1_CLAMP(alu
->dst
.clamp
) |
1786 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu
->src
[2].sel
) |
1787 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu
->src
[2].rel
) |
1788 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu
->src
[2].chan
) |
1789 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu
->src
[2].neg
) |
1790 S_SQ_ALU_WORD1_OP3_ALU_INST(alu
->inst
) |
1791 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu
->bank_swizzle
);
1793 bc
->bytecode
[id
++] = S_SQ_ALU_WORD1_DST_GPR(alu
->dst
.sel
) |
1794 S_SQ_ALU_WORD1_DST_CHAN(alu
->dst
.chan
) |
1795 S_SQ_ALU_WORD1_DST_REL(alu
->dst
.rel
) |
1796 S_SQ_ALU_WORD1_CLAMP(alu
->dst
.clamp
) |
1797 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu
->src
[0].abs
) |
1798 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu
->src
[1].abs
) |
1799 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu
->dst
.write
) |
1800 S_SQ_ALU_WORD1_OP2_OMOD(alu
->omod
) |
1801 S_SQ_ALU_WORD1_OP2_ALU_INST(alu
->inst
) |
1802 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu
->bank_swizzle
) |
1803 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu
->execute_mask
) |
1804 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu
->update_pred
);
1809 static void r600_bytecode_cf_vtx_build(uint32_t *bytecode
, const struct r600_bytecode_cf
*cf
)
1811 *bytecode
++ = S_SQ_CF_WORD0_ADDR(cf
->addr
>> 1);
1812 *bytecode
++ = cf
->inst
|
1813 S_SQ_CF_WORD1_BARRIER(1) |
1814 S_SQ_CF_WORD1_COUNT((cf
->ndw
/ 4) - 1);
1817 /* common for r600/r700 - eg in eg_asm.c */
1818 static int r600_bytecode_cf_build(struct r600_bytecode
*bc
, struct r600_bytecode_cf
*cf
)
1820 unsigned id
= cf
->id
;
1823 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
:
1824 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
:
1825 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
:
1826 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER
:
1827 bc
->bytecode
[id
++] = S_SQ_CF_ALU_WORD0_ADDR(cf
->addr
>> 1) |
1828 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf
->kcache
[0].mode
) |
1829 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf
->kcache
[0].bank
) |
1830 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf
->kcache
[1].bank
);
1832 bc
->bytecode
[id
++] = cf
->inst
|
1833 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf
->kcache
[1].mode
) |
1834 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf
->kcache
[0].addr
) |
1835 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf
->kcache
[1].addr
) |
1836 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1837 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc
->chip_class
== R600
? cf
->r6xx_uses_waterfall
: 0) |
1838 S_SQ_CF_ALU_WORD1_COUNT((cf
->ndw
/ 2) - 1);
1840 case V_SQ_CF_WORD1_SQ_CF_INST_TEX
:
1841 case V_SQ_CF_WORD1_SQ_CF_INST_VTX
:
1842 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC
:
1843 if (bc
->chip_class
== R700
)
1844 r700_bytecode_cf_vtx_build(&bc
->bytecode
[id
], cf
);
1846 r600_bytecode_cf_vtx_build(&bc
->bytecode
[id
], cf
);
1848 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
:
1849 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
:
1850 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf
->output
.gpr
) |
1851 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf
->output
.elem_size
) |
1852 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf
->output
.array_base
) |
1853 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf
->output
.type
);
1854 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf
->output
.burst_count
- 1) |
1855 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf
->output
.swizzle_x
) |
1856 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf
->output
.swizzle_y
) |
1857 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf
->output
.swizzle_z
) |
1858 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf
->output
.swizzle_w
) |
1859 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf
->output
.barrier
) |
1861 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf
->output
.end_of_program
);
1863 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0
:
1864 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1
:
1865 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2
:
1866 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3
:
1867 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf
->output
.gpr
) |
1868 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf
->output
.elem_size
) |
1869 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf
->output
.array_base
) |
1870 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf
->output
.type
);
1871 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf
->output
.burst_count
- 1) |
1872 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf
->output
.barrier
) |
1874 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf
->output
.end_of_program
) |
1875 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf
->output
.array_size
) |
1876 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf
->output
.comp_mask
);
1878 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP
:
1879 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE
:
1880 case V_SQ_CF_WORD1_SQ_CF_INST_POP
:
1881 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL
:
1882 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10
:
1883 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
:
1884 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
:
1885 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
:
1886 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
:
1887 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN
:
1888 bc
->bytecode
[id
++] = S_SQ_CF_WORD0_ADDR(cf
->cf_addr
>> 1);
1889 bc
->bytecode
[id
++] = cf
->inst
|
1890 S_SQ_CF_WORD1_BARRIER(1) |
1891 S_SQ_CF_WORD1_COND(cf
->cond
) |
1892 S_SQ_CF_WORD1_POP_COUNT(cf
->pop_count
);
1896 R600_ERR("unsupported CF instruction (0x%X)\n", cf
->inst
);
1902 int r600_bytecode_build(struct r600_bytecode
*bc
)
1904 struct r600_bytecode_cf
*cf
;
1905 struct r600_bytecode_alu
*alu
;
1906 struct r600_bytecode_vtx
*vtx
;
1907 struct r600_bytecode_tex
*tex
;
1908 uint32_t literal
[4];
1913 if (bc
->callstack
[0].max
> 0)
1914 bc
->nstack
= ((bc
->callstack
[0].max
+ 3) >> 2) + 2;
1915 if (bc
->type
== TGSI_PROCESSOR_VERTEX
&& !bc
->nstack
) {
1919 /* first path compute addr of each CF block */
1920 /* addr start after all the CF instructions */
1921 addr
= bc
->cf_last
->id
+ 2;
1922 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
1923 if (bc
->chip_class
>= EVERGREEN
) {
1925 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX
:
1926 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX
:
1927 /* fetch node need to be 16 bytes aligned*/
1929 addr
&= 0xFFFFFFFCUL
;
1931 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
:
1932 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
:
1933 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER
:
1934 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
:
1935 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
:
1936 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
:
1937 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0
:
1938 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1
:
1939 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2
:
1940 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3
:
1941 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0
:
1942 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1
:
1943 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2
:
1944 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3
:
1945 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0
:
1946 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1
:
1947 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2
:
1948 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3
:
1949 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0
:
1950 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1
:
1951 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2
:
1952 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3
:
1953 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP
:
1954 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE
:
1955 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP
:
1956 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL
:
1957 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10
:
1958 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
:
1959 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
:
1960 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
:
1961 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
:
1962 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN
:
1963 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END
:
1967 R600_ERR("unsupported CF instruction (0x%X)\n", cf
->inst
);
1972 case V_SQ_CF_WORD1_SQ_CF_INST_TEX
:
1973 case V_SQ_CF_WORD1_SQ_CF_INST_VTX
:
1974 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC
:
1975 /* fetch node need to be 16 bytes aligned*/
1977 addr
&= 0xFFFFFFFCUL
;
1979 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
:
1980 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
:
1981 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER
:
1982 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
:
1983 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
:
1984 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
:
1985 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0
:
1986 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1
:
1987 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2
:
1988 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3
:
1989 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP
:
1990 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE
:
1991 case V_SQ_CF_WORD1_SQ_CF_INST_POP
:
1992 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10
:
1993 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
:
1994 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
:
1995 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
:
1996 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
:
1997 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN
:
2000 R600_ERR("unsupported CF instruction (0x%X)\n", cf
->inst
);
2006 bc
->ndw
= cf
->addr
+ cf
->ndw
;
2009 bc
->bytecode
= calloc(1, bc
->ndw
* 4);
2010 if (bc
->bytecode
== NULL
)
2012 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
2014 if (bc
->chip_class
>= EVERGREEN
) {
2015 r
= eg_bytecode_cf_build(bc
, cf
);
2020 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
:
2021 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
:
2022 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER
:
2023 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
:
2025 memset(literal
, 0, sizeof(literal
));
2026 LIST_FOR_EACH_ENTRY(alu
, &cf
->alu
, list
) {
2027 r
= r600_bytecode_alu_nliterals(bc
, alu
, literal
, &nliteral
);
2030 r600_bytecode_alu_adjust_literals(bc
, alu
, literal
, nliteral
);
2031 r600_bytecode_assign_kcache_banks(bc
, alu
, cf
->kcache
);
2033 switch(bc
->chip_class
) {
2034 case EVERGREEN
: /* eg alu is same encoding as r700 */
2036 r
= r700_bytecode_alu_build(bc
, alu
, addr
);
2039 R600_ERR("unknown chip class %d.\n", bc
->chip_class
);
2046 for (i
= 0; i
< align(nliteral
, 2); ++i
) {
2047 bc
->bytecode
[addr
++] = literal
[i
];
2050 memset(literal
, 0, sizeof(literal
));
2054 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX
:
2055 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
2056 r
= r600_bytecode_vtx_build(bc
, vtx
, addr
);
2062 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX
:
2063 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
2064 assert(bc
->chip_class
>= EVERGREEN
);
2065 r
= r600_bytecode_vtx_build(bc
, vtx
, addr
);
2070 LIST_FOR_EACH_ENTRY(tex
, &cf
->tex
, list
) {
2071 r
= r600_bytecode_tex_build(bc
, tex
, addr
);
2077 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
:
2078 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
:
2079 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0
:
2080 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1
:
2081 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2
:
2082 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3
:
2083 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0
:
2084 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1
:
2085 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2
:
2086 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3
:
2087 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0
:
2088 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1
:
2089 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2
:
2090 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3
:
2091 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0
:
2092 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1
:
2093 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2
:
2094 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3
:
2095 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10
:
2096 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL
:
2097 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
:
2098 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
:
2099 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
:
2100 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP
:
2101 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE
:
2102 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP
:
2103 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
:
2104 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN
:
2105 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END
:
2110 R600_ERR("unsupported CF instruction (0x%X)\n", cf
->inst
);
2114 r
= r600_bytecode_cf_build(bc
, cf
);
2119 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
:
2120 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
:
2121 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER
:
2122 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
:
2124 memset(literal
, 0, sizeof(literal
));
2125 LIST_FOR_EACH_ENTRY(alu
, &cf
->alu
, list
) {
2126 r
= r600_bytecode_alu_nliterals(bc
, alu
, literal
, &nliteral
);
2129 r600_bytecode_alu_adjust_literals(bc
, alu
, literal
, nliteral
);
2130 r600_bytecode_assign_kcache_banks(bc
, alu
, cf
->kcache
);
2132 switch(bc
->chip_class
) {
2134 r
= r600_bytecode_alu_build(bc
, alu
, addr
);
2137 r
= r700_bytecode_alu_build(bc
, alu
, addr
);
2140 R600_ERR("unknown chip class %d.\n", bc
->chip_class
);
2147 for (i
= 0; i
< align(nliteral
, 2); ++i
) {
2148 bc
->bytecode
[addr
++] = literal
[i
];
2151 memset(literal
, 0, sizeof(literal
));
2155 case V_SQ_CF_WORD1_SQ_CF_INST_VTX
:
2156 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC
:
2157 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
2158 r
= r600_bytecode_vtx_build(bc
, vtx
, addr
);
2164 case V_SQ_CF_WORD1_SQ_CF_INST_TEX
:
2165 LIST_FOR_EACH_ENTRY(tex
, &cf
->tex
, list
) {
2166 r
= r600_bytecode_tex_build(bc
, tex
, addr
);
2172 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
:
2173 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
:
2174 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0
:
2175 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1
:
2176 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2
:
2177 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3
:
2178 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL
:
2179 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10
:
2180 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
:
2181 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
:
2182 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
:
2183 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP
:
2184 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE
:
2185 case V_SQ_CF_WORD1_SQ_CF_INST_POP
:
2186 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
:
2187 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN
:
2190 R600_ERR("unsupported CF instruction (0x%X)\n", cf
->inst
);
2198 void r600_bytecode_clear(struct r600_bytecode
*bc
)
2200 struct r600_bytecode_cf
*cf
= NULL
, *next_cf
;
2203 bc
->bytecode
= NULL
;
2205 LIST_FOR_EACH_ENTRY_SAFE(cf
, next_cf
, &bc
->cf
, list
) {
2206 struct r600_bytecode_alu
*alu
= NULL
, *next_alu
;
2207 struct r600_bytecode_tex
*tex
= NULL
, *next_tex
;
2208 struct r600_bytecode_tex
*vtx
= NULL
, *next_vtx
;
2210 LIST_FOR_EACH_ENTRY_SAFE(alu
, next_alu
, &cf
->alu
, list
) {
2214 LIST_INITHEAD(&cf
->alu
);
2216 LIST_FOR_EACH_ENTRY_SAFE(tex
, next_tex
, &cf
->tex
, list
) {
2220 LIST_INITHEAD(&cf
->tex
);
2222 LIST_FOR_EACH_ENTRY_SAFE(vtx
, next_vtx
, &cf
->vtx
, list
) {
2226 LIST_INITHEAD(&cf
->vtx
);
2231 LIST_INITHEAD(&cf
->list
);
2234 void r600_bytecode_dump(struct r600_bytecode
*bc
)
2236 struct r600_bytecode_cf
*cf
= NULL
;
2237 struct r600_bytecode_alu
*alu
= NULL
;
2238 struct r600_bytecode_vtx
*vtx
= NULL
;
2239 struct r600_bytecode_tex
*tex
= NULL
;
2242 uint32_t literal
[4];
2246 switch (bc
->chip_class
) {
2261 fprintf(stderr
, "bytecode %d dw -- %d gprs ---------------------\n", bc
->ndw
, bc
->ngpr
);
2262 fprintf(stderr
, " %c\n", chip
);
2264 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
2267 if (bc
->chip_class
>= EVERGREEN
) {
2269 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
:
2270 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
:
2271 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER
:
2272 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
:
2273 if (cf
->eg_alu_extended
) {
2274 fprintf(stderr
, "%04d %08X ALU_EXT0 ", id
, bc
->bytecode
[id
]);
2275 fprintf(stderr
, "KCACHE_BANK2:%X ", cf
->kcache
[2].bank
);
2276 fprintf(stderr
, "KCACHE_BANK3:%X ", cf
->kcache
[3].bank
);
2277 fprintf(stderr
, "KCACHE_MODE2:%X\n", cf
->kcache
[2].mode
);
2279 fprintf(stderr
, "%04d %08X ALU_EXT1 ", id
, bc
->bytecode
[id
]);
2280 fprintf(stderr
, "KCACHE_MODE3:%X ", cf
->kcache
[3].mode
);
2281 fprintf(stderr
, "KCACHE_ADDR2:%X ", cf
->kcache
[2].addr
);
2282 fprintf(stderr
, "KCACHE_ADDR3:%X\n", cf
->kcache
[3].addr
);
2286 fprintf(stderr
, "%04d %08X ALU ", id
, bc
->bytecode
[id
]);
2287 fprintf(stderr
, "ADDR:%d ", cf
->addr
);
2288 fprintf(stderr
, "KCACHE_MODE0:%X ", cf
->kcache
[0].mode
);
2289 fprintf(stderr
, "KCACHE_BANK0:%X ", cf
->kcache
[0].bank
);
2290 fprintf(stderr
, "KCACHE_BANK1:%X\n", cf
->kcache
[1].bank
);
2292 fprintf(stderr
, "%04d %08X ALU ", id
, bc
->bytecode
[id
]);
2293 fprintf(stderr
, "INST:0x%x ", EG_G_SQ_CF_ALU_WORD1_CF_INST(cf
->inst
));
2294 fprintf(stderr
, "KCACHE_MODE1:%X ", cf
->kcache
[1].mode
);
2295 fprintf(stderr
, "KCACHE_ADDR0:%X ", cf
->kcache
[0].addr
);
2296 fprintf(stderr
, "KCACHE_ADDR1:%X ", cf
->kcache
[1].addr
);
2297 fprintf(stderr
, "COUNT:%d\n", cf
->ndw
/ 2);
2299 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX
:
2300 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX
:
2301 fprintf(stderr
, "%04d %08X TEX/VTX ", id
, bc
->bytecode
[id
]);
2302 fprintf(stderr
, "ADDR:%d\n", cf
->addr
);
2304 fprintf(stderr
, "%04d %08X TEX/VTX ", id
, bc
->bytecode
[id
]);
2305 fprintf(stderr
, "INST:0x%x ", EG_G_SQ_CF_WORD1_CF_INST(cf
->inst
));
2306 fprintf(stderr
, "COUNT:%d\n", cf
->ndw
/ 4);
2308 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
:
2309 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
:
2310 fprintf(stderr
, "%04d %08X EXPORT ", id
, bc
->bytecode
[id
]);
2311 fprintf(stderr
, "GPR:%X ", cf
->output
.gpr
);
2312 fprintf(stderr
, "ELEM_SIZE:%X ", cf
->output
.elem_size
);
2313 fprintf(stderr
, "ARRAY_BASE:%X ", cf
->output
.array_base
);
2314 fprintf(stderr
, "TYPE:%X\n", cf
->output
.type
);
2316 fprintf(stderr
, "%04d %08X EXPORT ", id
, bc
->bytecode
[id
]);
2317 fprintf(stderr
, "SWIZ_X:%X ", cf
->output
.swizzle_x
);
2318 fprintf(stderr
, "SWIZ_Y:%X ", cf
->output
.swizzle_y
);
2319 fprintf(stderr
, "SWIZ_Z:%X ", cf
->output
.swizzle_z
);
2320 fprintf(stderr
, "SWIZ_W:%X ", cf
->output
.swizzle_w
);
2321 fprintf(stderr
, "BARRIER:%X ", cf
->output
.barrier
);
2322 fprintf(stderr
, "INST:0x%x ", EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf
->output
.inst
));
2323 fprintf(stderr
, "BURST_COUNT:%d ", cf
->output
.burst_count
);
2324 fprintf(stderr
, "EOP:%X\n", cf
->output
.end_of_program
);
2326 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0
:
2327 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1
:
2328 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2
:
2329 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3
:
2330 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0
:
2331 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1
:
2332 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2
:
2333 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3
:
2334 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0
:
2335 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1
:
2336 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2
:
2337 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3
:
2338 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0
:
2339 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1
:
2340 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2
:
2341 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3
:
2342 fprintf(stderr
, "%04d %08X EXPORT MEM_STREAM%i_BUF%i ", id
, bc
->bytecode
[id
],
2343 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf
->inst
) -
2344 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0
)) / 4,
2345 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf
->inst
) -
2346 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0
)) % 4);
2347 fprintf(stderr
, "GPR:%X ", cf
->output
.gpr
);
2348 fprintf(stderr
, "ELEM_SIZE:%i ", cf
->output
.elem_size
);
2349 fprintf(stderr
, "ARRAY_BASE:%i ", cf
->output
.array_base
);
2350 fprintf(stderr
, "TYPE:%X\n", cf
->output
.type
);
2352 fprintf(stderr
, "%04d %08X EXPORT MEM_STREAM%i_BUF%i ", id
, bc
->bytecode
[id
],
2353 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf
->inst
) -
2354 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0
)) / 4,
2355 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf
->inst
) -
2356 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0
)) % 4);
2357 fprintf(stderr
, "ARRAY_SIZE:%i ", cf
->output
.array_size
);
2358 fprintf(stderr
, "COMP_MASK:%X ", cf
->output
.comp_mask
);
2359 fprintf(stderr
, "BARRIER:%X ", cf
->output
.barrier
);
2360 fprintf(stderr
, "INST:%d ", cf
->output
.inst
);
2361 fprintf(stderr
, "BURST_COUNT:%d ", cf
->output
.burst_count
);
2362 fprintf(stderr
, "EOP:%X\n", cf
->output
.end_of_program
);
2364 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP
:
2365 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE
:
2366 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP
:
2367 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL
:
2368 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10
:
2369 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
:
2370 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
:
2371 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
:
2372 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
:
2373 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN
:
2374 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END
:
2375 fprintf(stderr
, "%04d %08X CF ", id
, bc
->bytecode
[id
]);
2376 fprintf(stderr
, "ADDR:%d\n", cf
->cf_addr
);
2378 fprintf(stderr
, "%04d %08X CF ", id
, bc
->bytecode
[id
]);
2379 fprintf(stderr
, "INST:0x%x ", EG_G_SQ_CF_WORD1_CF_INST(cf
->inst
));
2380 fprintf(stderr
, "COND:%X ", cf
->cond
);
2381 fprintf(stderr
, "POP_COUNT:%X\n", cf
->pop_count
);
2384 fprintf(stderr
, "%04d %08X CF NATIVE\n", id
, bc
->bytecode
[id
]);
2385 fprintf(stderr
, "%04d %08X CF NATIVE\n", id
+ 1, bc
->bytecode
[id
+ 1]);
2388 R600_ERR("Unknown instruction %0x\n", cf
->inst
);
2392 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
:
2393 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
:
2394 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER
:
2395 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
:
2396 fprintf(stderr
, "%04d %08X ALU ", id
, bc
->bytecode
[id
]);
2397 fprintf(stderr
, "ADDR:%d ", cf
->addr
);
2398 fprintf(stderr
, "KCACHE_MODE0:%X ", cf
->kcache
[0].mode
);
2399 fprintf(stderr
, "KCACHE_BANK0:%X ", cf
->kcache
[0].bank
);
2400 fprintf(stderr
, "KCACHE_BANK1:%X\n", cf
->kcache
[1].bank
);
2402 fprintf(stderr
, "%04d %08X ALU ", id
, bc
->bytecode
[id
]);
2403 fprintf(stderr
, "INST:0x%x ", R600_G_SQ_CF_ALU_WORD1_CF_INST(cf
->inst
));
2404 fprintf(stderr
, "KCACHE_MODE1:%X ", cf
->kcache
[1].mode
);
2405 fprintf(stderr
, "KCACHE_ADDR0:%X ", cf
->kcache
[0].addr
);
2406 fprintf(stderr
, "KCACHE_ADDR1:%X ", cf
->kcache
[1].addr
);
2407 fprintf(stderr
, "COUNT:%d\n", cf
->ndw
/ 2);
2409 case V_SQ_CF_WORD1_SQ_CF_INST_TEX
:
2410 case V_SQ_CF_WORD1_SQ_CF_INST_VTX
:
2411 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC
:
2412 fprintf(stderr
, "%04d %08X TEX/VTX ", id
, bc
->bytecode
[id
]);
2413 fprintf(stderr
, "ADDR:%d\n", cf
->addr
);
2415 fprintf(stderr
, "%04d %08X TEX/VTX ", id
, bc
->bytecode
[id
]);
2416 fprintf(stderr
, "INST:0x%x ", R600_G_SQ_CF_WORD1_CF_INST(cf
->inst
));
2417 fprintf(stderr
, "COUNT:%d\n", cf
->ndw
/ 4);
2419 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
:
2420 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
:
2421 fprintf(stderr
, "%04d %08X EXPORT ", id
, bc
->bytecode
[id
]);
2422 fprintf(stderr
, "GPR:%X ", cf
->output
.gpr
);
2423 fprintf(stderr
, "ELEM_SIZE:%X ", cf
->output
.elem_size
);
2424 fprintf(stderr
, "ARRAY_BASE:%X ", cf
->output
.array_base
);
2425 fprintf(stderr
, "TYPE:%X\n", cf
->output
.type
);
2427 fprintf(stderr
, "%04d %08X EXPORT ", id
, bc
->bytecode
[id
]);
2428 fprintf(stderr
, "SWIZ_X:%X ", cf
->output
.swizzle_x
);
2429 fprintf(stderr
, "SWIZ_Y:%X ", cf
->output
.swizzle_y
);
2430 fprintf(stderr
, "SWIZ_Z:%X ", cf
->output
.swizzle_z
);
2431 fprintf(stderr
, "SWIZ_W:%X ", cf
->output
.swizzle_w
);
2432 fprintf(stderr
, "BARRIER:%X ", cf
->output
.barrier
);
2433 fprintf(stderr
, "INST:0x%x ", R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf
->output
.inst
));
2434 fprintf(stderr
, "BURST_COUNT:%d ", cf
->output
.burst_count
);
2435 fprintf(stderr
, "EOP:%X\n", cf
->output
.end_of_program
);
2437 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0
:
2438 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1
:
2439 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2
:
2440 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3
:
2441 fprintf(stderr
, "%04d %08X EXPORT MEM_STREAM%i ", id
, bc
->bytecode
[id
],
2442 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf
->inst
) -
2443 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0
));
2444 fprintf(stderr
, "GPR:%X ", cf
->output
.gpr
);
2445 fprintf(stderr
, "ELEM_SIZE:%i ", cf
->output
.elem_size
);
2446 fprintf(stderr
, "ARRAY_BASE:%i ", cf
->output
.array_base
);
2447 fprintf(stderr
, "TYPE:%X\n", cf
->output
.type
);
2449 fprintf(stderr
, "%04d %08X EXPORT MEM_STREAM%i ", id
, bc
->bytecode
[id
],
2450 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf
->inst
) -
2451 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0
));
2452 fprintf(stderr
, "ARRAY_SIZE:%i ", cf
->output
.array_size
);
2453 fprintf(stderr
, "COMP_MASK:%X ", cf
->output
.comp_mask
);
2454 fprintf(stderr
, "BARRIER:%X ", cf
->output
.barrier
);
2455 fprintf(stderr
, "INST:%d ", cf
->output
.inst
);
2456 fprintf(stderr
, "BURST_COUNT:%d ", cf
->output
.burst_count
);
2457 fprintf(stderr
, "EOP:%X\n", cf
->output
.end_of_program
);
2459 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP
:
2460 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE
:
2461 case V_SQ_CF_WORD1_SQ_CF_INST_POP
:
2462 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL
:
2463 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10
:
2464 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
:
2465 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
:
2466 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
:
2467 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
:
2468 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN
:
2469 fprintf(stderr
, "%04d %08X CF ", id
, bc
->bytecode
[id
]);
2470 fprintf(stderr
, "ADDR:%d\n", cf
->cf_addr
);
2472 fprintf(stderr
, "%04d %08X CF ", id
, bc
->bytecode
[id
]);
2473 fprintf(stderr
, "INST:0x%x ", R600_G_SQ_CF_WORD1_CF_INST(cf
->inst
));
2474 fprintf(stderr
, "COND:%X ", cf
->cond
);
2475 fprintf(stderr
, "POP_COUNT:%X\n", cf
->pop_count
);
2478 R600_ERR("Unknown instruction %0x\n", cf
->inst
);
2484 LIST_FOR_EACH_ENTRY(alu
, &cf
->alu
, list
) {
2485 r600_bytecode_alu_nliterals(bc
, alu
, literal
, &nliteral
);
2487 fprintf(stderr
, "%04d %08X ", id
, bc
->bytecode
[id
]);
2488 fprintf(stderr
, "SRC0(SEL:%d ", alu
->src
[0].sel
);
2489 fprintf(stderr
, "REL:%d ", alu
->src
[0].rel
);
2490 fprintf(stderr
, "CHAN:%d ", alu
->src
[0].chan
);
2491 fprintf(stderr
, "NEG:%d) ", alu
->src
[0].neg
);
2492 fprintf(stderr
, "SRC1(SEL:%d ", alu
->src
[1].sel
);
2493 fprintf(stderr
, "REL:%d ", alu
->src
[1].rel
);
2494 fprintf(stderr
, "CHAN:%d ", alu
->src
[1].chan
);
2495 fprintf(stderr
, "NEG:%d ", alu
->src
[1].neg
);
2496 fprintf(stderr
, "IM:%d) ", alu
->index_mode
);
2497 fprintf(stderr
, "PRED_SEL:%d ", alu
->pred_sel
);
2498 fprintf(stderr
, "LAST:%d)\n", alu
->last
);
2500 fprintf(stderr
, "%04d %08X %c ", id
, bc
->bytecode
[id
], alu
->last
? '*' : ' ');
2501 fprintf(stderr
, "INST:0x%x ", alu
->inst
);
2502 fprintf(stderr
, "DST(SEL:%d ", alu
->dst
.sel
);
2503 fprintf(stderr
, "CHAN:%d ", alu
->dst
.chan
);
2504 fprintf(stderr
, "REL:%d ", alu
->dst
.rel
);
2505 fprintf(stderr
, "CLAMP:%d) ", alu
->dst
.clamp
);
2506 fprintf(stderr
, "BANK_SWIZZLE:%d ", alu
->bank_swizzle
);
2508 fprintf(stderr
, "SRC2(SEL:%d ", alu
->src
[2].sel
);
2509 fprintf(stderr
, "REL:%d ", alu
->src
[2].rel
);
2510 fprintf(stderr
, "CHAN:%d ", alu
->src
[2].chan
);
2511 fprintf(stderr
, "NEG:%d)\n", alu
->src
[2].neg
);
2513 fprintf(stderr
, "SRC0_ABS:%d ", alu
->src
[0].abs
);
2514 fprintf(stderr
, "SRC1_ABS:%d ", alu
->src
[1].abs
);
2515 fprintf(stderr
, "WRITE_MASK:%d ", alu
->dst
.write
);
2516 fprintf(stderr
, "OMOD:%d ", alu
->omod
);
2517 fprintf(stderr
, "EXECUTE_MASK:%d ", alu
->execute_mask
);
2518 fprintf(stderr
, "UPDATE_PRED:%d\n", alu
->update_pred
);
2523 for (i
= 0; i
< nliteral
; i
++, id
++) {
2524 float *f
= (float*)(bc
->bytecode
+ id
);
2525 fprintf(stderr
, "%04d %08X\t%f (%d)\n", id
, bc
->bytecode
[id
], *f
,
2526 *(bc
->bytecode
+ id
));
2533 LIST_FOR_EACH_ENTRY(tex
, &cf
->tex
, list
) {
2534 fprintf(stderr
, "%04d %08X ", id
, bc
->bytecode
[id
]);
2535 fprintf(stderr
, "INST:0x%x ", tex
->inst
);
2536 fprintf(stderr
, "RESOURCE_ID:%d ", tex
->resource_id
);
2537 fprintf(stderr
, "SRC(GPR:%d ", tex
->src_gpr
);
2538 fprintf(stderr
, "REL:%d)\n", tex
->src_rel
);
2540 fprintf(stderr
, "%04d %08X ", id
, bc
->bytecode
[id
]);
2541 fprintf(stderr
, "DST(GPR:%d ", tex
->dst_gpr
);
2542 fprintf(stderr
, "REL:%d ", tex
->dst_rel
);
2543 fprintf(stderr
, "SEL_X:%d ", tex
->dst_sel_x
);
2544 fprintf(stderr
, "SEL_Y:%d ", tex
->dst_sel_y
);
2545 fprintf(stderr
, "SEL_Z:%d ", tex
->dst_sel_z
);
2546 fprintf(stderr
, "SEL_W:%d) ", tex
->dst_sel_w
);
2547 fprintf(stderr
, "LOD_BIAS:%d ", tex
->lod_bias
);
2548 fprintf(stderr
, "COORD_TYPE_X:%d ", tex
->coord_type_x
);
2549 fprintf(stderr
, "COORD_TYPE_Y:%d ", tex
->coord_type_y
);
2550 fprintf(stderr
, "COORD_TYPE_Z:%d ", tex
->coord_type_z
);
2551 fprintf(stderr
, "COORD_TYPE_W:%d\n", tex
->coord_type_w
);
2553 fprintf(stderr
, "%04d %08X ", id
, bc
->bytecode
[id
]);
2554 fprintf(stderr
, "OFFSET_X:%d ", tex
->offset_x
);
2555 fprintf(stderr
, "OFFSET_Y:%d ", tex
->offset_y
);
2556 fprintf(stderr
, "OFFSET_Z:%d ", tex
->offset_z
);
2557 fprintf(stderr
, "SAMPLER_ID:%d ", tex
->sampler_id
);
2558 fprintf(stderr
, "SRC(SEL_X:%d ", tex
->src_sel_x
);
2559 fprintf(stderr
, "SEL_Y:%d ", tex
->src_sel_y
);
2560 fprintf(stderr
, "SEL_Z:%d ", tex
->src_sel_z
);
2561 fprintf(stderr
, "SEL_W:%d)\n", tex
->src_sel_w
);
2563 fprintf(stderr
, "%04d %08X \n", id
, bc
->bytecode
[id
]);
2567 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
2568 fprintf(stderr
, "%04d %08X ", id
, bc
->bytecode
[id
]);
2569 fprintf(stderr
, "INST:%d ", vtx
->inst
);
2570 fprintf(stderr
, "FETCH_TYPE:%d ", vtx
->fetch_type
);
2571 fprintf(stderr
, "BUFFER_ID:%d\n", vtx
->buffer_id
);
2573 /* This assumes that no semantic fetches exist */
2574 fprintf(stderr
, "%04d %08X ", id
, bc
->bytecode
[id
]);
2575 fprintf(stderr
, "SRC(GPR:%d ", vtx
->src_gpr
);
2576 fprintf(stderr
, "SEL_X:%d) ", vtx
->src_sel_x
);
2577 if (bc
->chip_class
< CAYMAN
)
2578 fprintf(stderr
, "MEGA_FETCH_COUNT:%d ", vtx
->mega_fetch_count
);
2580 fprintf(stderr
, "SEL_Y:%d) ", 0);
2581 fprintf(stderr
, "DST(GPR:%d ", vtx
->dst_gpr
);
2582 fprintf(stderr
, "SEL_X:%d ", vtx
->dst_sel_x
);
2583 fprintf(stderr
, "SEL_Y:%d ", vtx
->dst_sel_y
);
2584 fprintf(stderr
, "SEL_Z:%d ", vtx
->dst_sel_z
);
2585 fprintf(stderr
, "SEL_W:%d) ", vtx
->dst_sel_w
);
2586 fprintf(stderr
, "USE_CONST_FIELDS:%d ", vtx
->use_const_fields
);
2587 fprintf(stderr
, "FORMAT(DATA:%d ", vtx
->data_format
);
2588 fprintf(stderr
, "NUM:%d ", vtx
->num_format_all
);
2589 fprintf(stderr
, "COMP:%d ", vtx
->format_comp_all
);
2590 fprintf(stderr
, "MODE:%d)\n", vtx
->srf_mode_all
);
2592 fprintf(stderr
, "%04d %08X ", id
, bc
->bytecode
[id
]);
2593 fprintf(stderr
, "ENDIAN:%d ", vtx
->endian
);
2594 fprintf(stderr
, "OFFSET:%d\n", vtx
->offset
);
2597 fprintf(stderr
, "%04d %08X \n", id
, bc
->bytecode
[id
]);
2602 fprintf(stderr
, "--------------------------------------\n");
2605 static void r600_vertex_data_type(enum pipe_format pformat
,
2607 unsigned *num_format
, unsigned *format_comp
, unsigned *endian
)
2609 const struct util_format_description
*desc
;
2615 *endian
= ENDIAN_NONE
;
2617 desc
= util_format_description(pformat
);
2618 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
) {
2622 /* Find the first non-VOID channel. */
2623 for (i
= 0; i
< 4; i
++) {
2624 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2629 *endian
= r600_endian_swap(desc
->channel
[i
].size
);
2631 switch (desc
->channel
[i
].type
) {
2632 /* Half-floats, floats, ints */
2633 case UTIL_FORMAT_TYPE_FLOAT
:
2634 switch (desc
->channel
[i
].size
) {
2636 switch (desc
->nr_channels
) {
2638 *format
= FMT_16_FLOAT
;
2641 *format
= FMT_16_16_FLOAT
;
2645 *format
= FMT_16_16_16_16_FLOAT
;
2650 switch (desc
->nr_channels
) {
2652 *format
= FMT_32_FLOAT
;
2655 *format
= FMT_32_32_FLOAT
;
2658 *format
= FMT_32_32_32_FLOAT
;
2661 *format
= FMT_32_32_32_32_FLOAT
;
2670 case UTIL_FORMAT_TYPE_UNSIGNED
:
2672 case UTIL_FORMAT_TYPE_SIGNED
:
2673 switch (desc
->channel
[i
].size
) {
2675 switch (desc
->nr_channels
) {
2684 *format
= FMT_8_8_8_8
;
2689 if (desc
->nr_channels
!= 4)
2692 *format
= FMT_2_10_10_10
;
2695 switch (desc
->nr_channels
) {
2700 *format
= FMT_16_16
;
2704 *format
= FMT_16_16_16_16
;
2709 switch (desc
->nr_channels
) {
2714 *format
= FMT_32_32
;
2717 *format
= FMT_32_32_32
;
2720 *format
= FMT_32_32_32_32
;
2732 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2737 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
||
2738 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2739 if (!desc
->channel
[i
].normalized
) {
2740 if (desc
->channel
[i
].pure_integer
)
2748 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat
));
2751 void *r600_create_vertex_fetch_shader(struct pipe_context
*ctx
,
2753 const struct pipe_vertex_element
*elements
)
2755 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2756 static int dump_shaders
= -1;
2757 struct r600_bytecode bc
;
2758 struct r600_bytecode_vtx vtx
;
2759 const struct util_format_description
*desc
;
2760 unsigned fetch_resource_start
= rctx
->chip_class
>= EVERGREEN
? 0 : 160;
2761 unsigned format
, num_format
, format_comp
, endian
;
2763 int i
, j
, r
, fs_size
;
2764 struct r600_resource
*fetch_shader
;
2768 memset(&bc
, 0, sizeof(bc
));
2769 r600_bytecode_init(&bc
, rctx
->chip_class
, rctx
->family
);
2771 for (i
= 0; i
< count
; i
++) {
2772 if (elements
[i
].instance_divisor
> 1) {
2773 if (rctx
->chip_class
== CAYMAN
) {
2774 for (j
= 0; j
< 4; j
++) {
2775 struct r600_bytecode_alu alu
;
2776 memset(&alu
, 0, sizeof(alu
));
2777 alu
.inst
= BC_INST(&bc
, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT
);
2779 alu
.src
[0].chan
= 3;
2780 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2781 alu
.src
[1].value
= (1ll << 32) / elements
[i
].instance_divisor
+ 1;
2782 alu
.dst
.sel
= i
+ 1;
2784 alu
.dst
.write
= j
== 3;
2786 if ((r
= r600_bytecode_add_alu(&bc
, &alu
))) {
2787 r600_bytecode_clear(&bc
);
2792 struct r600_bytecode_alu alu
;
2793 memset(&alu
, 0, sizeof(alu
));
2794 alu
.inst
= BC_INST(&bc
, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT
);
2796 alu
.src
[0].chan
= 3;
2797 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2798 alu
.src
[1].value
= (1ll << 32) / elements
[i
].instance_divisor
+ 1;
2799 alu
.dst
.sel
= i
+ 1;
2803 if ((r
= r600_bytecode_add_alu(&bc
, &alu
))) {
2804 r600_bytecode_clear(&bc
);
2811 for (i
= 0; i
< count
; i
++) {
2812 r600_vertex_data_type(elements
[i
].src_format
,
2813 &format
, &num_format
, &format_comp
, &endian
);
2815 desc
= util_format_description(elements
[i
].src_format
);
2817 r600_bytecode_clear(&bc
);
2818 R600_ERR("unknown format %d\n", elements
[i
].src_format
);
2822 if (elements
[i
].src_offset
> 65535) {
2823 r600_bytecode_clear(&bc
);
2824 R600_ERR("too big src_offset: %u\n", elements
[i
].src_offset
);
2828 memset(&vtx
, 0, sizeof(vtx
));
2829 vtx
.buffer_id
= elements
[i
].vertex_buffer_index
+ fetch_resource_start
;
2830 vtx
.fetch_type
= elements
[i
].instance_divisor
? 1 : 0;
2831 vtx
.src_gpr
= elements
[i
].instance_divisor
> 1 ? i
+ 1 : 0;
2832 vtx
.src_sel_x
= elements
[i
].instance_divisor
? 3 : 0;
2833 vtx
.mega_fetch_count
= 0x1F;
2834 vtx
.dst_gpr
= i
+ 1;
2835 vtx
.dst_sel_x
= desc
->swizzle
[0];
2836 vtx
.dst_sel_y
= desc
->swizzle
[1];
2837 vtx
.dst_sel_z
= desc
->swizzle
[2];
2838 vtx
.dst_sel_w
= desc
->swizzle
[3];
2839 vtx
.data_format
= format
;
2840 vtx
.num_format_all
= num_format
;
2841 vtx
.format_comp_all
= format_comp
;
2842 vtx
.srf_mode_all
= 1;
2843 vtx
.offset
= elements
[i
].src_offset
;
2844 vtx
.endian
= endian
;
2846 if ((r
= r600_bytecode_add_vtx(&bc
, &vtx
))) {
2847 r600_bytecode_clear(&bc
);
2852 r600_bytecode_add_cfinst(&bc
, BC_INST(&bc
, V_SQ_CF_WORD1_SQ_CF_INST_RETURN
));
2854 if ((r
= r600_bytecode_build(&bc
))) {
2855 r600_bytecode_clear(&bc
);
2859 if (dump_shaders
== -1)
2860 dump_shaders
= debug_get_bool_option("R600_DUMP_SHADERS", FALSE
);
2863 fprintf(stderr
, "--------------------------------------------------------------\n");
2864 r600_bytecode_dump(&bc
);
2865 fprintf(stderr
, "______________________________________________________________\n");
2870 fetch_shader
= (struct r600_resource
*)
2871 pipe_buffer_create(rctx
->context
.screen
,
2873 PIPE_USAGE_IMMUTABLE
, fs_size
);
2874 if (fetch_shader
== NULL
) {
2875 r600_bytecode_clear(&bc
);
2879 bytecode
= rctx
->ws
->buffer_map(fetch_shader
->cs_buf
, rctx
->cs
, PIPE_TRANSFER_WRITE
);
2880 if (bytecode
== NULL
) {
2881 r600_bytecode_clear(&bc
);
2882 pipe_resource_reference((struct pipe_resource
**)&fetch_shader
, NULL
);
2886 if (R600_BIG_ENDIAN
) {
2887 for (i
= 0; i
< fs_size
/ 4; ++i
) {
2888 bytecode
[i
] = bswap_32(bc
.bytecode
[i
]);
2891 memcpy(bytecode
, bc
.bytecode
, fs_size
);
2894 rctx
->ws
->buffer_unmap(fetch_shader
->cs_buf
);
2895 r600_bytecode_clear(&bc
);
2897 return fetch_shader
;
2900 void r600_bytecode_alu_read(struct r600_bytecode_alu
*alu
, uint32_t word0
, uint32_t word1
)
2903 alu
->src
[0].sel
= G_SQ_ALU_WORD0_SRC0_SEL(word0
);
2904 alu
->src
[0].rel
= G_SQ_ALU_WORD0_SRC0_REL(word0
);
2905 alu
->src
[0].chan
= G_SQ_ALU_WORD0_SRC0_CHAN(word0
);
2906 alu
->src
[0].neg
= G_SQ_ALU_WORD0_SRC0_NEG(word0
);
2907 alu
->src
[1].sel
= G_SQ_ALU_WORD0_SRC1_SEL(word0
);
2908 alu
->src
[1].rel
= G_SQ_ALU_WORD0_SRC1_REL(word0
);
2909 alu
->src
[1].chan
= G_SQ_ALU_WORD0_SRC1_CHAN(word0
);
2910 alu
->src
[1].neg
= G_SQ_ALU_WORD0_SRC1_NEG(word0
);
2911 alu
->index_mode
= G_SQ_ALU_WORD0_INDEX_MODE(word0
);
2912 alu
->pred_sel
= G_SQ_ALU_WORD0_PRED_SEL(word0
);
2913 alu
->last
= G_SQ_ALU_WORD0_LAST(word0
);
2916 alu
->bank_swizzle
= G_SQ_ALU_WORD1_BANK_SWIZZLE(word1
);
2917 alu
->dst
.sel
= G_SQ_ALU_WORD1_DST_GPR(word1
);
2918 alu
->dst
.rel
= G_SQ_ALU_WORD1_DST_REL(word1
);
2919 alu
->dst
.chan
= G_SQ_ALU_WORD1_DST_CHAN(word1
);
2920 alu
->dst
.clamp
= G_SQ_ALU_WORD1_CLAMP(word1
);
2921 if (G_SQ_ALU_WORD1_ENCODING(word1
)) /*ALU_DWORD1_OP3*/
2924 alu
->src
[2].sel
= G_SQ_ALU_WORD1_OP3_SRC2_SEL(word1
);
2925 alu
->src
[2].rel
= G_SQ_ALU_WORD1_OP3_SRC2_REL(word1
);
2926 alu
->src
[2].chan
= G_SQ_ALU_WORD1_OP3_SRC2_CHAN(word1
);
2927 alu
->src
[2].neg
= G_SQ_ALU_WORD1_OP3_SRC2_NEG(word1
);
2928 alu
->inst
= G_SQ_ALU_WORD1_OP3_ALU_INST(word1
);
2930 else /*ALU_DWORD1_OP2*/
2932 alu
->src
[0].abs
= G_SQ_ALU_WORD1_OP2_SRC0_ABS(word1
);
2933 alu
->src
[1].abs
= G_SQ_ALU_WORD1_OP2_SRC1_ABS(word1
);
2934 alu
->inst
= G_SQ_ALU_WORD1_OP2_ALU_INST(word1
);
2935 alu
->omod
= G_SQ_ALU_WORD1_OP2_OMOD(word1
);
2936 alu
->dst
.write
= G_SQ_ALU_WORD1_OP2_WRITE_MASK(word1
);
2937 alu
->update_pred
= G_SQ_ALU_WORD1_OP2_UPDATE_PRED(word1
);
2939 G_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(word1
);