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r600g: fix inconsistency with INTERP* opcode definitions
[mesa.git] / src / gallium / drivers / r600 / r600_asm.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include <stdio.h>
24 #include <errno.h>
25 #include <byteswap.h>
26 #include "util/u_format.h"
27 #include "util/u_memory.h"
28 #include "pipe/p_shader_tokens.h"
29 #include "r600_pipe.h"
30 #include "r600_sq.h"
31 #include "r600_opcodes.h"
32 #include "r600_asm.h"
33 #include "r600_formats.h"
34 #include "r600d.h"
35
36 #define NUM_OF_CYCLES 3
37 #define NUM_OF_COMPONENTS 4
38
39 static inline unsigned int r600_bytecode_get_num_operands(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
40 {
41 if(alu->is_op3)
42 return 3;
43
44 switch (bc->chip_class) {
45 case R600:
46 case R700:
47 switch (alu->inst) {
48 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
49 return 0;
50 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
51 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT:
52 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT:
53 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT:
54 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT:
55 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
56 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
57 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
58 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
59 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
60 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT:
61 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT:
62 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT:
63 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT:
64 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
65 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
66 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT:
67 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT:
68 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT:
69 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT:
70 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
71 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT:
72 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
73 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT:
74 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
75 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT:
76 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT:
77 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
78 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT:
79 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT:
80 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
81 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
82 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
83 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
84 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT:
85 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
86 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
87 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
88 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT:
89 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT:
90 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT:
91 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT:
92 return 2;
93
94 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
95 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA:
96 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR:
97 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT:
98 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
99 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
100 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
101 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
102 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
103 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
104 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
105 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
106 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
107 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT:
108 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
109 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
110 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
111 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT:
112 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT:
113 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT:
114 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
115 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
116 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE:
117 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT:
118 return 1;
119 default: R600_ERR(
120 "Need instruction operand number for 0x%x.\n", alu->inst);
121 }
122 break;
123 case EVERGREEN:
124 case CAYMAN:
125 switch (alu->inst) {
126 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
127 return 0;
128 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
129 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT:
130 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT:
131 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT:
132 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT:
133 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
134 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
135 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
136 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
137 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
138 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT:
139 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT:
140 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT:
141 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT:
142 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
143 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
144 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT:
145 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT:
146 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT:
147 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT:
148 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
149 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT:
150 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
151 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT:
152 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
153 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT:
154 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT:
155 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
156 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT:
157 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT:
158 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
159 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
160 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
161 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
162 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT:
163 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
164 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
165 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
166 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_XY:
167 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_ZW:
168 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT:
169 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT:
170 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT:
171 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT:
172 return 2;
173
174 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
175 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
176 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
177 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
178 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
179 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
180 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
181 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
182 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
183 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
184 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
185 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
186 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
187 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR:
188 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT:
189 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT:
190 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT:
191 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
192 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
193 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE:
194 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT:
195 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_LOAD_P0:
196 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT:
197 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT:
198 return 1;
199 default: R600_ERR(
200 "Need instruction operand number for 0x%x.\n", alu->inst);
201 }
202 break;
203 }
204
205 return 3;
206 }
207
208 int r700_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id);
209
210 static struct r600_bytecode_cf *r600_bytecode_cf(void)
211 {
212 struct r600_bytecode_cf *cf = CALLOC_STRUCT(r600_bytecode_cf);
213
214 if (cf == NULL)
215 return NULL;
216 LIST_INITHEAD(&cf->list);
217 LIST_INITHEAD(&cf->alu);
218 LIST_INITHEAD(&cf->vtx);
219 LIST_INITHEAD(&cf->tex);
220 return cf;
221 }
222
223 static struct r600_bytecode_alu *r600_bytecode_alu(void)
224 {
225 struct r600_bytecode_alu *alu = CALLOC_STRUCT(r600_bytecode_alu);
226
227 if (alu == NULL)
228 return NULL;
229 LIST_INITHEAD(&alu->list);
230 return alu;
231 }
232
233 static struct r600_bytecode_vtx *r600_bytecode_vtx(void)
234 {
235 struct r600_bytecode_vtx *vtx = CALLOC_STRUCT(r600_bytecode_vtx);
236
237 if (vtx == NULL)
238 return NULL;
239 LIST_INITHEAD(&vtx->list);
240 return vtx;
241 }
242
243 static struct r600_bytecode_tex *r600_bytecode_tex(void)
244 {
245 struct r600_bytecode_tex *tex = CALLOC_STRUCT(r600_bytecode_tex);
246
247 if (tex == NULL)
248 return NULL;
249 LIST_INITHEAD(&tex->list);
250 return tex;
251 }
252
253 void r600_bytecode_init(struct r600_bytecode *bc, enum chip_class chip_class, enum radeon_family family)
254 {
255 if ((chip_class == R600) && (family != CHIP_RV670))
256 bc->ar_handling = AR_HANDLE_RV6XX;
257 else
258 bc->ar_handling = AR_HANDLE_NORMAL;
259
260 if ((chip_class == R600) && (family != CHIP_RV670 && family != CHIP_RS780 &&
261 family != CHIP_RS880))
262 bc->r6xx_nop_after_rel_dst = 1;
263 else
264 bc->r6xx_nop_after_rel_dst = 0;
265 LIST_INITHEAD(&bc->cf);
266 bc->chip_class = chip_class;
267 }
268
269 static int r600_bytecode_add_cf(struct r600_bytecode *bc)
270 {
271 struct r600_bytecode_cf *cf = r600_bytecode_cf();
272
273 if (cf == NULL)
274 return -ENOMEM;
275 LIST_ADDTAIL(&cf->list, &bc->cf);
276 if (bc->cf_last) {
277 cf->id = bc->cf_last->id + 2;
278 if (bc->cf_last->eg_alu_extended) {
279 /* take into account extended alu size */
280 cf->id += 2;
281 bc->ndw += 2;
282 }
283 }
284 bc->cf_last = cf;
285 bc->ncf++;
286 bc->ndw += 2;
287 bc->force_add_cf = 0;
288 bc->ar_loaded = 0;
289 return 0;
290 }
291
292 int r600_bytecode_add_output(struct r600_bytecode *bc, const struct r600_bytecode_output *output)
293 {
294 int r;
295
296 if (bc->cf_last && (bc->cf_last->inst == output->inst ||
297 (bc->cf_last->inst == BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT) &&
298 output->inst == BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE))) &&
299 output->type == bc->cf_last->output.type &&
300 output->elem_size == bc->cf_last->output.elem_size &&
301 output->swizzle_x == bc->cf_last->output.swizzle_x &&
302 output->swizzle_y == bc->cf_last->output.swizzle_y &&
303 output->swizzle_z == bc->cf_last->output.swizzle_z &&
304 output->swizzle_w == bc->cf_last->output.swizzle_w &&
305 (output->burst_count + bc->cf_last->output.burst_count) <= 16) {
306
307 if ((output->gpr + output->burst_count) == bc->cf_last->output.gpr &&
308 (output->array_base + output->burst_count) == bc->cf_last->output.array_base) {
309
310 bc->cf_last->output.end_of_program |= output->end_of_program;
311 bc->cf_last->output.inst = output->inst;
312 bc->cf_last->output.gpr = output->gpr;
313 bc->cf_last->output.array_base = output->array_base;
314 bc->cf_last->output.burst_count += output->burst_count;
315 return 0;
316
317 } else if (output->gpr == (bc->cf_last->output.gpr + bc->cf_last->output.burst_count) &&
318 output->array_base == (bc->cf_last->output.array_base + bc->cf_last->output.burst_count)) {
319
320 bc->cf_last->output.end_of_program |= output->end_of_program;
321 bc->cf_last->output.inst = output->inst;
322 bc->cf_last->output.burst_count += output->burst_count;
323 return 0;
324 }
325 }
326
327 r = r600_bytecode_add_cf(bc);
328 if (r)
329 return r;
330 bc->cf_last->inst = output->inst;
331 memcpy(&bc->cf_last->output, output, sizeof(struct r600_bytecode_output));
332 return 0;
333 }
334
335 /* alu instructions that can ony exits once per group */
336 static int is_alu_once_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
337 {
338 switch (bc->chip_class) {
339 case R600:
340 case R700:
341 return !alu->is_op3 && (
342 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
343 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
344 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
345 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
346 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
347 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
348 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
349 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
350 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
351 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
352 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
353 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
354 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
355 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
356 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
357 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
358 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
359 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
360 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
361 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
362 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
363 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
364 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
365 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
366 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
367 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
368 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
369 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
370 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
371 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
372 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
373 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
374 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
375 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
376 case EVERGREEN:
377 case CAYMAN:
378 default:
379 return !alu->is_op3 && (
380 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
381 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
382 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
383 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
384 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
385 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
386 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
387 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
388 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
389 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
390 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
391 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
392 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
393 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
394 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
395 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
396 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
397 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
398 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
399 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
400 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
401 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
402 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
403 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
404 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
405 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
406 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
407 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
408 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
409 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
410 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
411 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
412 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
413 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
414 }
415 }
416
417 static int is_alu_reduction_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
418 {
419 switch (bc->chip_class) {
420 case R600:
421 case R700:
422 return !alu->is_op3 && (
423 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
424 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
425 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
426 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
427 case EVERGREEN:
428 case CAYMAN:
429 default:
430 return !alu->is_op3 && (
431 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
432 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
433 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
434 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
435 }
436 }
437
438 static int is_alu_cube_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
439 {
440 switch (bc->chip_class) {
441 case R600:
442 case R700:
443 return !alu->is_op3 &&
444 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
445 case EVERGREEN:
446 case CAYMAN:
447 default:
448 return !alu->is_op3 &&
449 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
450 }
451 }
452
453 static int is_alu_mova_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
454 {
455 switch (bc->chip_class) {
456 case R600:
457 case R700:
458 return !alu->is_op3 && (
459 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA ||
460 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR ||
461 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT ||
462 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT);
463 case EVERGREEN:
464 case CAYMAN:
465 default:
466 return !alu->is_op3 && (
467 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
468 }
469 }
470
471 static int is_opcode_in_range(unsigned opcode, unsigned min, unsigned max)
472 {
473 return min <= opcode && opcode <= max;
474 }
475
476 /* ALU instructions that can only execute on the vector unit:
477 *
478 * opcode ranges:
479 * R6xx/R7xx:
480 * op3 : [0x08 - 0x0B]
481 * op2 : 0x07, [0x15 - 0x18], [0x1B - 0x1D], [0x50 - 0x53], [0x7A - 0x7E]
482 *
483 * EVERGREEN:
484 * op3: [0x04 - 0x11]
485 * op2: [0xA0 - 0xE2]
486 */
487 static int is_alu_vec_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
488 {
489 switch (bc->chip_class) {
490 case R600:
491 case R700:
492 if (alu->is_op3)
493 return is_opcode_in_range(alu->inst,
494 V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_64,
495 V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_64_D2);
496 else
497 return (alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FREXP_64) ||
498 is_opcode_in_range(alu->inst,
499 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA,
500 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT) ||
501 is_opcode_in_range(alu->inst,
502 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_64,
503 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT32_TO_FLT64) ||
504 is_opcode_in_range(alu->inst,
505 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4,
506 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4) ||
507 is_opcode_in_range(alu->inst,
508 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LDEXP_64,
509 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_64);
510
511 case EVERGREEN:
512 if (alu->is_op3)
513 return is_opcode_in_range(alu->inst,
514 EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_BFE_UINT,
515 EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_LDS_IDX_OP);
516 else
517 return is_opcode_in_range(alu->inst,
518 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_BFM_INT,
519 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_LOAD_P20);
520 case CAYMAN:
521 default:
522 assert(0);
523 return 0;
524 }
525 }
526
527 /* ALU instructions that can only execute on the trans unit:
528 *
529 * opcode ranges:
530 * R600:
531 * op3: 0x0C
532 * op2: [0x60 - 0x79]
533 *
534 * R700:
535 * op3: 0x0C
536 * op2: [0x60 - 0x6F], [0x73 - 0x79]
537 *
538 * EVERGREEN:
539 * op3: 0x1F
540 * op2: [0x81 - 0x9C]
541 */
542 static int is_alu_trans_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
543 {
544
545 switch (bc->chip_class) {
546 case R600:
547 if (alu->is_op3)
548 return alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
549 else
550 return is_opcode_in_range(alu->inst,
551 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT,
552 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT);
553 case R700:
554 if (alu->is_op3)
555 return alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
556 else
557 return is_opcode_in_range(alu->inst,
558 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT,
559 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS) ||
560 is_opcode_in_range(alu->inst,
561 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT,
562 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT);
563 case EVERGREEN:
564 if (alu->is_op3)
565 return alu->inst == EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
566 else
567 return is_opcode_in_range(alu->inst,
568 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE,
569 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT);
570 case CAYMAN:
571 default:
572 assert(0);
573 return 0;
574 }
575 }
576
577 /* alu instructions that can execute on any unit */
578 static int is_alu_any_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
579 {
580 return !is_alu_vec_unit_inst(bc, alu) &&
581 !is_alu_trans_unit_inst(bc, alu);
582 }
583
584 static int is_nop_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
585 {
586 switch (bc->chip_class) {
587 case R600:
588 case R700:
589 return (!alu->is_op3 && alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
590 case EVERGREEN:
591 case CAYMAN:
592 default:
593 return (!alu->is_op3 && alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
594 }
595 }
596
597 static int assign_alu_units(struct r600_bytecode *bc, struct r600_bytecode_alu *alu_first,
598 struct r600_bytecode_alu *assignment[5])
599 {
600 struct r600_bytecode_alu *alu;
601 unsigned i, chan, trans;
602 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
603
604 for (i = 0; i < max_slots; i++)
605 assignment[i] = NULL;
606
607 for (alu = alu_first; alu; alu = LIST_ENTRY(struct r600_bytecode_alu, alu->list.next, list)) {
608 chan = alu->dst.chan;
609 if (max_slots == 4)
610 trans = 0;
611 else if (is_alu_trans_unit_inst(bc, alu))
612 trans = 1;
613 else if (is_alu_vec_unit_inst(bc, alu))
614 trans = 0;
615 else if (assignment[chan])
616 trans = 1; /* Assume ALU_INST_PREFER_VECTOR. */
617 else
618 trans = 0;
619
620 if (trans) {
621 if (assignment[4]) {
622 assert(0); /* ALU.Trans has already been allocated. */
623 return -1;
624 }
625 assignment[4] = alu;
626 } else {
627 if (assignment[chan]) {
628 assert(0); /* ALU.chan has already been allocated. */
629 return -1;
630 }
631 assignment[chan] = alu;
632 }
633
634 if (alu->last)
635 break;
636 }
637 return 0;
638 }
639
640 struct alu_bank_swizzle {
641 int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
642 int hw_cfile_addr[4];
643 int hw_cfile_elem[4];
644 };
645
646 static const unsigned cycle_for_bank_swizzle_vec[][3] = {
647 [SQ_ALU_VEC_012] = { 0, 1, 2 },
648 [SQ_ALU_VEC_021] = { 0, 2, 1 },
649 [SQ_ALU_VEC_120] = { 1, 2, 0 },
650 [SQ_ALU_VEC_102] = { 1, 0, 2 },
651 [SQ_ALU_VEC_201] = { 2, 0, 1 },
652 [SQ_ALU_VEC_210] = { 2, 1, 0 }
653 };
654
655 static const unsigned cycle_for_bank_swizzle_scl[][3] = {
656 [SQ_ALU_SCL_210] = { 2, 1, 0 },
657 [SQ_ALU_SCL_122] = { 1, 2, 2 },
658 [SQ_ALU_SCL_212] = { 2, 1, 2 },
659 [SQ_ALU_SCL_221] = { 2, 2, 1 }
660 };
661
662 static void init_bank_swizzle(struct alu_bank_swizzle *bs)
663 {
664 int i, cycle, component;
665 /* set up gpr use */
666 for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
667 for (component = 0; component < NUM_OF_COMPONENTS; component++)
668 bs->hw_gpr[cycle][component] = -1;
669 for (i = 0; i < 4; i++)
670 bs->hw_cfile_addr[i] = -1;
671 for (i = 0; i < 4; i++)
672 bs->hw_cfile_elem[i] = -1;
673 }
674
675 static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan, unsigned cycle)
676 {
677 if (bs->hw_gpr[cycle][chan] == -1)
678 bs->hw_gpr[cycle][chan] = sel;
679 else if (bs->hw_gpr[cycle][chan] != (int)sel) {
680 /* Another scalar operation has already used the GPR read port for the channel. */
681 return -1;
682 }
683 return 0;
684 }
685
686 static int reserve_cfile(struct r600_bytecode *bc, struct alu_bank_swizzle *bs, unsigned sel, unsigned chan)
687 {
688 int res, num_res = 4;
689 if (bc->chip_class >= R700) {
690 num_res = 2;
691 chan /= 2;
692 }
693 for (res = 0; res < num_res; ++res) {
694 if (bs->hw_cfile_addr[res] == -1) {
695 bs->hw_cfile_addr[res] = sel;
696 bs->hw_cfile_elem[res] = chan;
697 return 0;
698 } else if (bs->hw_cfile_addr[res] == sel &&
699 bs->hw_cfile_elem[res] == chan)
700 return 0; /* Read for this scalar element already reserved, nothing to do here. */
701 }
702 /* All cfile read ports are used, cannot reference vector element. */
703 return -1;
704 }
705
706 static int is_gpr(unsigned sel)
707 {
708 return (sel >= 0 && sel <= 127);
709 }
710
711 /* CB constants start at 512, and get translated to a kcache index when ALU
712 * clauses are constructed. Note that we handle kcache constants the same way
713 * as (the now gone) cfile constants, is that really required? */
714 static int is_cfile(unsigned sel)
715 {
716 return (sel > 255 && sel < 512) ||
717 (sel > 511 && sel < 4607) || /* Kcache before translation. */
718 (sel > 127 && sel < 192); /* Kcache after translation. */
719 }
720
721 static int is_const(int sel)
722 {
723 return is_cfile(sel) ||
724 (sel >= V_SQ_ALU_SRC_0 &&
725 sel <= V_SQ_ALU_SRC_LITERAL);
726 }
727
728 static int check_vector(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
729 struct alu_bank_swizzle *bs, int bank_swizzle)
730 {
731 int r, src, num_src, sel, elem, cycle;
732
733 num_src = r600_bytecode_get_num_operands(bc, alu);
734 for (src = 0; src < num_src; src++) {
735 sel = alu->src[src].sel;
736 elem = alu->src[src].chan;
737 if (is_gpr(sel)) {
738 cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src];
739 if (src == 1 && sel == alu->src[0].sel && elem == alu->src[0].chan)
740 /* Nothing to do; special-case optimization,
741 * second source uses first source’s reservation. */
742 continue;
743 else {
744 r = reserve_gpr(bs, sel, elem, cycle);
745 if (r)
746 return r;
747 }
748 } else if (is_cfile(sel)) {
749 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
750 if (r)
751 return r;
752 }
753 /* No restrictions on PV, PS, literal or special constants. */
754 }
755 return 0;
756 }
757
758 static int check_scalar(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
759 struct alu_bank_swizzle *bs, int bank_swizzle)
760 {
761 int r, src, num_src, const_count, sel, elem, cycle;
762
763 num_src = r600_bytecode_get_num_operands(bc, alu);
764 for (const_count = 0, src = 0; src < num_src; ++src) {
765 sel = alu->src[src].sel;
766 elem = alu->src[src].chan;
767 if (is_const(sel)) { /* Any constant, including literal and inline constants. */
768 if (const_count >= 2)
769 /* More than two references to a constant in
770 * transcendental operation. */
771 return -1;
772 else
773 const_count++;
774 }
775 if (is_cfile(sel)) {
776 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
777 if (r)
778 return r;
779 }
780 }
781 for (src = 0; src < num_src; ++src) {
782 sel = alu->src[src].sel;
783 elem = alu->src[src].chan;
784 if (is_gpr(sel)) {
785 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
786 if (cycle < const_count)
787 /* Cycle for GPR load conflicts with
788 * constant load in transcendental operation. */
789 return -1;
790 r = reserve_gpr(bs, sel, elem, cycle);
791 if (r)
792 return r;
793 }
794 /* PV PS restrictions */
795 if (const_count && (sel == 254 || sel == 255)) {
796 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
797 if (cycle < const_count)
798 return -1;
799 }
800 }
801 return 0;
802 }
803
804 static int check_and_set_bank_swizzle(struct r600_bytecode *bc,
805 struct r600_bytecode_alu *slots[5])
806 {
807 struct alu_bank_swizzle bs;
808 int bank_swizzle[5];
809 int i, r = 0, forced = 1;
810 boolean scalar_only = bc->chip_class == CAYMAN ? false : true;
811 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
812
813 for (i = 0; i < max_slots; i++) {
814 if (slots[i]) {
815 if (slots[i]->bank_swizzle_force) {
816 slots[i]->bank_swizzle = slots[i]->bank_swizzle_force;
817 } else {
818 forced = 0;
819 }
820 }
821
822 if (i < 4 && slots[i])
823 scalar_only = false;
824 }
825 if (forced)
826 return 0;
827
828 /* Just check every possible combination of bank swizzle.
829 * Not very efficent, but works on the first try in most of the cases. */
830 for (i = 0; i < 4; i++)
831 if (!slots[i] || !slots[i]->bank_swizzle_force)
832 bank_swizzle[i] = SQ_ALU_VEC_012;
833 else
834 bank_swizzle[i] = slots[i]->bank_swizzle;
835
836 bank_swizzle[4] = SQ_ALU_SCL_210;
837 while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
838
839 if (max_slots == 4) {
840 for (i = 0; i < max_slots; i++) {
841 if (bank_swizzle[i] == SQ_ALU_VEC_210)
842 return -1;
843 }
844 }
845 init_bank_swizzle(&bs);
846 if (scalar_only == false) {
847 for (i = 0; i < 4; i++) {
848 if (slots[i]) {
849 r = check_vector(bc, slots[i], &bs, bank_swizzle[i]);
850 if (r)
851 break;
852 }
853 }
854 } else
855 r = 0;
856
857 if (!r && slots[4] && max_slots == 5) {
858 r = check_scalar(bc, slots[4], &bs, bank_swizzle[4]);
859 }
860 if (!r) {
861 for (i = 0; i < max_slots; i++) {
862 if (slots[i])
863 slots[i]->bank_swizzle = bank_swizzle[i];
864 }
865 return 0;
866 }
867
868 if (scalar_only) {
869 bank_swizzle[4]++;
870 } else {
871 for (i = 0; i < max_slots; i++) {
872 if (!slots[i] || !slots[i]->bank_swizzle_force) {
873 bank_swizzle[i]++;
874 if (bank_swizzle[i] <= SQ_ALU_VEC_210)
875 break;
876 else
877 bank_swizzle[i] = SQ_ALU_VEC_012;
878 }
879 }
880 }
881 }
882
883 /* Couldn't find a working swizzle. */
884 return -1;
885 }
886
887 static int replace_gpr_with_pv_ps(struct r600_bytecode *bc,
888 struct r600_bytecode_alu *slots[5], struct r600_bytecode_alu *alu_prev)
889 {
890 struct r600_bytecode_alu *prev[5];
891 int gpr[5], chan[5];
892 int i, j, r, src, num_src;
893 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
894
895 r = assign_alu_units(bc, alu_prev, prev);
896 if (r)
897 return r;
898
899 for (i = 0; i < max_slots; ++i) {
900 if (prev[i] && (prev[i]->dst.write || prev[i]->is_op3) && !prev[i]->dst.rel) {
901 gpr[i] = prev[i]->dst.sel;
902 /* cube writes more than PV.X */
903 if (!is_alu_cube_inst(bc, prev[i]) && is_alu_reduction_inst(bc, prev[i]))
904 chan[i] = 0;
905 else
906 chan[i] = prev[i]->dst.chan;
907 } else
908 gpr[i] = -1;
909 }
910
911 for (i = 0; i < max_slots; ++i) {
912 struct r600_bytecode_alu *alu = slots[i];
913 if(!alu)
914 continue;
915
916 num_src = r600_bytecode_get_num_operands(bc, alu);
917 for (src = 0; src < num_src; ++src) {
918 if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
919 continue;
920
921 if (bc->chip_class < CAYMAN) {
922 if (alu->src[src].sel == gpr[4] &&
923 alu->src[src].chan == chan[4]) {
924 alu->src[src].sel = V_SQ_ALU_SRC_PS;
925 alu->src[src].chan = 0;
926 continue;
927 }
928 }
929
930 for (j = 0; j < 4; ++j) {
931 if (alu->src[src].sel == gpr[j] &&
932 alu->src[src].chan == j) {
933 alu->src[src].sel = V_SQ_ALU_SRC_PV;
934 alu->src[src].chan = chan[j];
935 break;
936 }
937 }
938 }
939 }
940
941 return 0;
942 }
943
944 void r600_bytecode_special_constants(u32 value, unsigned *sel, unsigned *neg)
945 {
946 switch(value) {
947 case 0:
948 *sel = V_SQ_ALU_SRC_0;
949 break;
950 case 1:
951 *sel = V_SQ_ALU_SRC_1_INT;
952 break;
953 case -1:
954 *sel = V_SQ_ALU_SRC_M_1_INT;
955 break;
956 case 0x3F800000: /* 1.0f */
957 *sel = V_SQ_ALU_SRC_1;
958 break;
959 case 0x3F000000: /* 0.5f */
960 *sel = V_SQ_ALU_SRC_0_5;
961 break;
962 case 0xBF800000: /* -1.0f */
963 *sel = V_SQ_ALU_SRC_1;
964 *neg ^= 1;
965 break;
966 case 0xBF000000: /* -0.5f */
967 *sel = V_SQ_ALU_SRC_0_5;
968 *neg ^= 1;
969 break;
970 default:
971 *sel = V_SQ_ALU_SRC_LITERAL;
972 break;
973 }
974 }
975
976 /* compute how many literal are needed */
977 static int r600_bytecode_alu_nliterals(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
978 uint32_t literal[4], unsigned *nliteral)
979 {
980 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
981 unsigned i, j;
982
983 for (i = 0; i < num_src; ++i) {
984 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
985 uint32_t value = alu->src[i].value;
986 unsigned found = 0;
987 for (j = 0; j < *nliteral; ++j) {
988 if (literal[j] == value) {
989 found = 1;
990 break;
991 }
992 }
993 if (!found) {
994 if (*nliteral >= 4)
995 return -EINVAL;
996 literal[(*nliteral)++] = value;
997 }
998 }
999 }
1000 return 0;
1001 }
1002
1003 static void r600_bytecode_alu_adjust_literals(struct r600_bytecode *bc,
1004 struct r600_bytecode_alu *alu,
1005 uint32_t literal[4], unsigned nliteral)
1006 {
1007 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
1008 unsigned i, j;
1009
1010 for (i = 0; i < num_src; ++i) {
1011 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1012 uint32_t value = alu->src[i].value;
1013 for (j = 0; j < nliteral; ++j) {
1014 if (literal[j] == value) {
1015 alu->src[i].chan = j;
1016 break;
1017 }
1018 }
1019 }
1020 }
1021 }
1022
1023 static int merge_inst_groups(struct r600_bytecode *bc, struct r600_bytecode_alu *slots[5],
1024 struct r600_bytecode_alu *alu_prev)
1025 {
1026 struct r600_bytecode_alu *prev[5];
1027 struct r600_bytecode_alu *result[5] = { NULL };
1028
1029 uint32_t literal[4], prev_literal[4];
1030 unsigned nliteral = 0, prev_nliteral = 0;
1031
1032 int i, j, r, src, num_src;
1033 int num_once_inst = 0;
1034 int have_mova = 0, have_rel = 0;
1035 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
1036
1037 r = assign_alu_units(bc, alu_prev, prev);
1038 if (r)
1039 return r;
1040
1041 for (i = 0; i < max_slots; ++i) {
1042 struct r600_bytecode_alu *alu;
1043
1044 /* check number of literals */
1045 if (prev[i]) {
1046 if (r600_bytecode_alu_nliterals(bc, prev[i], literal, &nliteral))
1047 return 0;
1048 if (r600_bytecode_alu_nliterals(bc, prev[i], prev_literal, &prev_nliteral))
1049 return 0;
1050 if (is_alu_mova_inst(bc, prev[i])) {
1051 if (have_rel)
1052 return 0;
1053 have_mova = 1;
1054 }
1055 num_once_inst += is_alu_once_inst(bc, prev[i]);
1056 }
1057 if (slots[i] && r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral))
1058 return 0;
1059
1060 /* Let's check used slots. */
1061 if (prev[i] && !slots[i]) {
1062 result[i] = prev[i];
1063 continue;
1064 } else if (prev[i] && slots[i]) {
1065 if (max_slots == 5 && result[4] == NULL && prev[4] == NULL && slots[4] == NULL) {
1066 /* Trans unit is still free try to use it. */
1067 if (is_alu_any_unit_inst(bc, slots[i])) {
1068 result[i] = prev[i];
1069 result[4] = slots[i];
1070 } else if (is_alu_any_unit_inst(bc, prev[i])) {
1071 if (slots[i]->dst.sel == prev[i]->dst.sel &&
1072 (slots[i]->dst.write == 1 || slots[i]->is_op3) &&
1073 (prev[i]->dst.write == 1 || prev[i]->is_op3))
1074 return 0;
1075
1076 result[i] = slots[i];
1077 result[4] = prev[i];
1078 } else
1079 return 0;
1080 } else
1081 return 0;
1082 } else if(!slots[i]) {
1083 continue;
1084 } else {
1085 if (max_slots == 5 && slots[i] && prev[4] &&
1086 slots[i]->dst.sel == prev[4]->dst.sel &&
1087 slots[i]->dst.chan == prev[4]->dst.chan &&
1088 (slots[i]->dst.write == 1 || slots[i]->is_op3) &&
1089 (prev[4]->dst.write == 1 || prev[4]->is_op3))
1090 return 0;
1091
1092 result[i] = slots[i];
1093 }
1094
1095 alu = slots[i];
1096 num_once_inst += is_alu_once_inst(bc, alu);
1097
1098 /* don't reschedule NOPs */
1099 if (is_nop_inst(bc, alu))
1100 return 0;
1101
1102 /* Let's check dst gpr. */
1103 if (alu->dst.rel) {
1104 if (have_mova)
1105 return 0;
1106 have_rel = 1;
1107 }
1108
1109 /* Let's check source gprs */
1110 num_src = r600_bytecode_get_num_operands(bc, alu);
1111 for (src = 0; src < num_src; ++src) {
1112 if (alu->src[src].rel) {
1113 if (have_mova)
1114 return 0;
1115 have_rel = 1;
1116 }
1117
1118 /* Constants don't matter. */
1119 if (!is_gpr(alu->src[src].sel))
1120 continue;
1121
1122 for (j = 0; j < max_slots; ++j) {
1123 if (!prev[j] || !(prev[j]->dst.write || prev[j]->is_op3))
1124 continue;
1125
1126 /* If it's relative then we can't determin which gpr is really used. */
1127 if (prev[j]->dst.chan == alu->src[src].chan &&
1128 (prev[j]->dst.sel == alu->src[src].sel ||
1129 prev[j]->dst.rel || alu->src[src].rel))
1130 return 0;
1131 }
1132 }
1133 }
1134
1135 /* more than one PRED_ or KILL_ ? */
1136 if (num_once_inst > 1)
1137 return 0;
1138
1139 /* check if the result can still be swizzlet */
1140 r = check_and_set_bank_swizzle(bc, result);
1141 if (r)
1142 return 0;
1143
1144 /* looks like everything worked out right, apply the changes */
1145
1146 /* undo adding previus literals */
1147 bc->cf_last->ndw -= align(prev_nliteral, 2);
1148
1149 /* sort instructions */
1150 for (i = 0; i < max_slots; ++i) {
1151 slots[i] = result[i];
1152 if (result[i]) {
1153 LIST_DEL(&result[i]->list);
1154 result[i]->last = 0;
1155 LIST_ADDTAIL(&result[i]->list, &bc->cf_last->alu);
1156 }
1157 }
1158
1159 /* determine new last instruction */
1160 LIST_ENTRY(struct r600_bytecode_alu, bc->cf_last->alu.prev, list)->last = 1;
1161
1162 /* determine new first instruction */
1163 for (i = 0; i < max_slots; ++i) {
1164 if (result[i]) {
1165 bc->cf_last->curr_bs_head = result[i];
1166 break;
1167 }
1168 }
1169
1170 bc->cf_last->prev_bs_head = bc->cf_last->prev2_bs_head;
1171 bc->cf_last->prev2_bs_head = NULL;
1172
1173 return 0;
1174 }
1175
1176 /* we'll keep kcache sets sorted by bank & addr */
1177 static int r600_bytecode_alloc_kcache_line(struct r600_bytecode *bc,
1178 struct r600_bytecode_kcache *kcache,
1179 unsigned bank, unsigned line)
1180 {
1181 int i, kcache_banks = bc->chip_class >= EVERGREEN ? 4 : 2;
1182
1183 for (i = 0; i < kcache_banks; i++) {
1184 if (kcache[i].mode) {
1185 int d;
1186
1187 if (kcache[i].bank < bank)
1188 continue;
1189
1190 if ((kcache[i].bank == bank && kcache[i].addr > line+1) ||
1191 kcache[i].bank > bank) {
1192 /* try to insert new line */
1193 if (kcache[kcache_banks-1].mode) {
1194 /* all sets are in use */
1195 return -ENOMEM;
1196 }
1197
1198 memmove(&kcache[i+1],&kcache[i], (kcache_banks-i-1)*sizeof(struct r600_bytecode_kcache));
1199 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
1200 kcache[i].bank = bank;
1201 kcache[i].addr = line;
1202 return 0;
1203 }
1204
1205 d = line - kcache[i].addr;
1206
1207 if (d == -1) {
1208 kcache[i].addr--;
1209 if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_2) {
1210 /* we are prepending the line to the current set,
1211 * discarding the existing second line,
1212 * so we'll have to insert line+2 after it */
1213 line += 2;
1214 continue;
1215 } else if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_1) {
1216 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
1217 return 0;
1218 } else {
1219 /* V_SQ_CF_KCACHE_LOCK_LOOP_INDEX is not supported */
1220 return -ENOMEM;
1221 }
1222 } else if (d == 1) {
1223 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
1224 return 0;
1225 } else if (d == 0)
1226 return 0;
1227 } else { /* free kcache set - use it */
1228 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
1229 kcache[i].bank = bank;
1230 kcache[i].addr = line;
1231 return 0;
1232 }
1233 }
1234 return -ENOMEM;
1235 }
1236
1237 static int r600_bytecode_alloc_inst_kcache_lines(struct r600_bytecode *bc,
1238 struct r600_bytecode_kcache *kcache,
1239 struct r600_bytecode_alu *alu)
1240 {
1241 int i, r;
1242
1243 for (i = 0; i < 3; i++) {
1244 unsigned bank, line, sel = alu->src[i].sel;
1245
1246 if (sel < 512)
1247 continue;
1248
1249 bank = alu->src[i].kc_bank;
1250 line = (sel-512)>>4;
1251
1252 if ((r = r600_bytecode_alloc_kcache_line(bc, kcache, bank, line)))
1253 return r;
1254 }
1255 return 0;
1256 }
1257
1258 static int r600_bytecode_assign_kcache_banks(struct r600_bytecode *bc,
1259 struct r600_bytecode_alu *alu,
1260 struct r600_bytecode_kcache * kcache)
1261 {
1262 int i, j;
1263
1264 /* Alter the src operands to refer to the kcache. */
1265 for (i = 0; i < 3; ++i) {
1266 static const unsigned int base[] = {128, 160, 256, 288};
1267 unsigned int line, sel = alu->src[i].sel, found = 0;
1268
1269 if (sel < 512)
1270 continue;
1271
1272 sel -= 512;
1273 line = sel>>4;
1274
1275 for (j = 0; j < 4 && !found; ++j) {
1276 switch (kcache[j].mode) {
1277 case V_SQ_CF_KCACHE_NOP:
1278 case V_SQ_CF_KCACHE_LOCK_LOOP_INDEX:
1279 R600_ERR("unexpected kcache line mode\n");
1280 return -ENOMEM;
1281 default:
1282 if (kcache[j].bank == alu->src[i].kc_bank &&
1283 kcache[j].addr <= line &&
1284 line < kcache[j].addr + kcache[j].mode) {
1285 alu->src[i].sel = sel - (kcache[j].addr<<4);
1286 alu->src[i].sel += base[j];
1287 found=1;
1288 }
1289 }
1290 }
1291 }
1292 return 0;
1293 }
1294
1295 static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, int type)
1296 {
1297 struct r600_bytecode_kcache kcache_sets[4];
1298 struct r600_bytecode_kcache *kcache = kcache_sets;
1299 int r;
1300
1301 memcpy(kcache, bc->cf_last->kcache, 4 * sizeof(struct r600_bytecode_kcache));
1302
1303 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1304 /* can't alloc, need to start new clause */
1305 if ((r = r600_bytecode_add_cf(bc))) {
1306 return r;
1307 }
1308 bc->cf_last->inst = type;
1309
1310 /* retry with the new clause */
1311 kcache = bc->cf_last->kcache;
1312 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1313 /* can't alloc again- should never happen */
1314 return r;
1315 }
1316 } else {
1317 /* update kcache sets */
1318 memcpy(bc->cf_last->kcache, kcache, 4 * sizeof(struct r600_bytecode_kcache));
1319 }
1320
1321 /* if we actually used more than 2 kcache sets - use ALU_EXTENDED on eg+ */
1322 if (kcache[2].mode != V_SQ_CF_KCACHE_NOP) {
1323 if (bc->chip_class < EVERGREEN)
1324 return -ENOMEM;
1325 bc->cf_last->eg_alu_extended = 1;
1326 }
1327
1328 return 0;
1329 }
1330
1331 static int insert_nop_r6xx(struct r600_bytecode *bc)
1332 {
1333 struct r600_bytecode_alu alu;
1334 int r, i;
1335
1336 for (i = 0; i < 4; i++) {
1337 memset(&alu, 0, sizeof(alu));
1338 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP;
1339 alu.src[0].chan = i;
1340 alu.dst.chan = i;
1341 alu.last = (i == 3);
1342 r = r600_bytecode_add_alu(bc, &alu);
1343 if (r)
1344 return r;
1345 }
1346 return 0;
1347 }
1348
1349 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1350 static int load_ar_r6xx(struct r600_bytecode *bc)
1351 {
1352 struct r600_bytecode_alu alu;
1353 int r;
1354
1355 if (bc->ar_loaded)
1356 return 0;
1357
1358 /* hack to avoid making MOVA the last instruction in the clause */
1359 if ((bc->cf_last->ndw>>1) >= 110)
1360 bc->force_add_cf = 1;
1361
1362 memset(&alu, 0, sizeof(alu));
1363 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT;
1364 alu.src[0].sel = bc->ar_reg;
1365 alu.last = 1;
1366 alu.index_mode = INDEX_MODE_LOOP;
1367 r = r600_bytecode_add_alu(bc, &alu);
1368 if (r)
1369 return r;
1370
1371 /* no requirement to set uses waterfall on MOVA_GPR_INT */
1372 bc->ar_loaded = 1;
1373 return 0;
1374 }
1375
1376 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1377 static int load_ar(struct r600_bytecode *bc)
1378 {
1379 struct r600_bytecode_alu alu;
1380 int r;
1381
1382 if (bc->ar_handling)
1383 return load_ar_r6xx(bc);
1384
1385 if (bc->ar_loaded)
1386 return 0;
1387
1388 /* hack to avoid making MOVA the last instruction in the clause */
1389 if ((bc->cf_last->ndw>>1) >= 110)
1390 bc->force_add_cf = 1;
1391
1392 memset(&alu, 0, sizeof(alu));
1393 alu.inst = BC_INST(bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
1394 alu.src[0].sel = bc->ar_reg;
1395 alu.last = 1;
1396 r = r600_bytecode_add_alu(bc, &alu);
1397 if (r)
1398 return r;
1399
1400 bc->cf_last->r6xx_uses_waterfall = 1;
1401 bc->ar_loaded = 1;
1402 return 0;
1403 }
1404
1405 int r600_bytecode_add_alu_type(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu, int type)
1406 {
1407 struct r600_bytecode_alu *nalu = r600_bytecode_alu();
1408 struct r600_bytecode_alu *lalu;
1409 int i, r;
1410
1411 if (nalu == NULL)
1412 return -ENOMEM;
1413 memcpy(nalu, alu, sizeof(struct r600_bytecode_alu));
1414
1415 if (bc->cf_last != NULL && bc->cf_last->inst != type) {
1416 /* check if we could add it anyway */
1417 if (bc->cf_last->inst == BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU) &&
1418 type == BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE)) {
1419 LIST_FOR_EACH_ENTRY(lalu, &bc->cf_last->alu, list) {
1420 if (lalu->predicate) {
1421 bc->force_add_cf = 1;
1422 break;
1423 }
1424 }
1425 } else
1426 bc->force_add_cf = 1;
1427 }
1428
1429 /* cf can contains only alu or only vtx or only tex */
1430 if (bc->cf_last == NULL || bc->force_add_cf) {
1431 r = r600_bytecode_add_cf(bc);
1432 if (r) {
1433 free(nalu);
1434 return r;
1435 }
1436 }
1437 bc->cf_last->inst = type;
1438
1439 /* Check AR usage and load it if required */
1440 for (i = 0; i < 3; i++)
1441 if (nalu->src[i].rel && !bc->ar_loaded)
1442 load_ar(bc);
1443
1444 if (nalu->dst.rel && !bc->ar_loaded)
1445 load_ar(bc);
1446
1447 /* Setup the kcache for this ALU instruction. This will start a new
1448 * ALU clause if needed. */
1449 if ((r = r600_bytecode_alloc_kcache_lines(bc, nalu, type))) {
1450 free(nalu);
1451 return r;
1452 }
1453
1454 if (!bc->cf_last->curr_bs_head) {
1455 bc->cf_last->curr_bs_head = nalu;
1456 }
1457 /* number of gpr == the last gpr used in any alu */
1458 for (i = 0; i < 3; i++) {
1459 if (nalu->src[i].sel >= bc->ngpr && nalu->src[i].sel < 128) {
1460 bc->ngpr = nalu->src[i].sel + 1;
1461 }
1462 if (nalu->src[i].sel == V_SQ_ALU_SRC_LITERAL)
1463 r600_bytecode_special_constants(nalu->src[i].value,
1464 &nalu->src[i].sel, &nalu->src[i].neg);
1465 }
1466 if (nalu->dst.sel >= bc->ngpr) {
1467 bc->ngpr = nalu->dst.sel + 1;
1468 }
1469 LIST_ADDTAIL(&nalu->list, &bc->cf_last->alu);
1470 /* each alu use 2 dwords */
1471 bc->cf_last->ndw += 2;
1472 bc->ndw += 2;
1473
1474 /* process cur ALU instructions for bank swizzle */
1475 if (nalu->last) {
1476 uint32_t literal[4];
1477 unsigned nliteral;
1478 struct r600_bytecode_alu *slots[5];
1479 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
1480 r = assign_alu_units(bc, bc->cf_last->curr_bs_head, slots);
1481 if (r)
1482 return r;
1483
1484 if (bc->cf_last->prev_bs_head) {
1485 r = merge_inst_groups(bc, slots, bc->cf_last->prev_bs_head);
1486 if (r)
1487 return r;
1488 }
1489
1490 if (bc->cf_last->prev_bs_head) {
1491 r = replace_gpr_with_pv_ps(bc, slots, bc->cf_last->prev_bs_head);
1492 if (r)
1493 return r;
1494 }
1495
1496 r = check_and_set_bank_swizzle(bc, slots);
1497 if (r)
1498 return r;
1499
1500 for (i = 0, nliteral = 0; i < max_slots; i++) {
1501 if (slots[i]) {
1502 r = r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral);
1503 if (r)
1504 return r;
1505 }
1506 }
1507 bc->cf_last->ndw += align(nliteral, 2);
1508
1509 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1510 * worst case */
1511 if ((bc->cf_last->ndw >> 1) >= 120) {
1512 bc->force_add_cf = 1;
1513 }
1514
1515 bc->cf_last->prev2_bs_head = bc->cf_last->prev_bs_head;
1516 bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head;
1517 bc->cf_last->curr_bs_head = NULL;
1518 }
1519
1520 if (nalu->dst.rel && bc->r6xx_nop_after_rel_dst)
1521 insert_nop_r6xx(bc);
1522
1523 return 0;
1524 }
1525
1526 int r600_bytecode_add_alu(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu)
1527 {
1528 return r600_bytecode_add_alu_type(bc, alu, BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
1529 }
1530
1531 static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode *bc)
1532 {
1533 switch (bc->chip_class) {
1534 case R600:
1535 return 8;
1536
1537 case R700:
1538 case EVERGREEN:
1539 case CAYMAN:
1540 return 16;
1541
1542 default:
1543 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1544 return 8;
1545 }
1546 }
1547
1548 static inline boolean last_inst_was_not_vtx_fetch(struct r600_bytecode *bc)
1549 {
1550 switch (bc->chip_class) {
1551 case R700:
1552 case R600:
1553 return bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX &&
1554 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC;
1555 case EVERGREEN:
1556 return bc->cf_last->inst != EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1557 case CAYMAN:
1558 return bc->cf_last->inst != CM_V_SQ_CF_WORD1_SQ_CF_INST_TC;
1559 default:
1560 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1561 return FALSE;
1562 }
1563 }
1564
1565 int r600_bytecode_add_vtx(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx)
1566 {
1567 struct r600_bytecode_vtx *nvtx = r600_bytecode_vtx();
1568 int r;
1569
1570 if (nvtx == NULL)
1571 return -ENOMEM;
1572 memcpy(nvtx, vtx, sizeof(struct r600_bytecode_vtx));
1573
1574 /* cf can contains only alu or only vtx or only tex */
1575 if (bc->cf_last == NULL ||
1576 last_inst_was_not_vtx_fetch(bc) ||
1577 bc->force_add_cf) {
1578 r = r600_bytecode_add_cf(bc);
1579 if (r) {
1580 free(nvtx);
1581 return r;
1582 }
1583 switch (bc->chip_class) {
1584 case R600:
1585 case R700:
1586 bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1587 break;
1588 case EVERGREEN:
1589 bc->cf_last->inst = EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1590 break;
1591 case CAYMAN:
1592 bc->cf_last->inst = CM_V_SQ_CF_WORD1_SQ_CF_INST_TC;
1593 break;
1594 default:
1595 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1596 return -EINVAL;
1597 }
1598 }
1599 LIST_ADDTAIL(&nvtx->list, &bc->cf_last->vtx);
1600 /* each fetch use 4 dwords */
1601 bc->cf_last->ndw += 4;
1602 bc->ndw += 4;
1603 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1604 bc->force_add_cf = 1;
1605 return 0;
1606 }
1607
1608 int r600_bytecode_add_tex(struct r600_bytecode *bc, const struct r600_bytecode_tex *tex)
1609 {
1610 struct r600_bytecode_tex *ntex = r600_bytecode_tex();
1611 int r;
1612
1613 if (ntex == NULL)
1614 return -ENOMEM;
1615 memcpy(ntex, tex, sizeof(struct r600_bytecode_tex));
1616
1617 /* we can't fetch data und use it as texture lookup address in the same TEX clause */
1618 if (bc->cf_last != NULL &&
1619 bc->cf_last->inst == BC_INST(bc, V_SQ_CF_WORD1_SQ_CF_INST_TEX)) {
1620 struct r600_bytecode_tex *ttex;
1621 LIST_FOR_EACH_ENTRY(ttex, &bc->cf_last->tex, list) {
1622 if (ttex->dst_gpr == ntex->src_gpr) {
1623 bc->force_add_cf = 1;
1624 break;
1625 }
1626 }
1627 /* slight hack to make gradients always go into same cf */
1628 if (ntex->inst == SQ_TEX_INST_SET_GRADIENTS_H)
1629 bc->force_add_cf = 1;
1630 }
1631
1632 /* cf can contains only alu or only vtx or only tex */
1633 if (bc->cf_last == NULL ||
1634 bc->cf_last->inst != BC_INST(bc, V_SQ_CF_WORD1_SQ_CF_INST_TEX) ||
1635 bc->force_add_cf) {
1636 r = r600_bytecode_add_cf(bc);
1637 if (r) {
1638 free(ntex);
1639 return r;
1640 }
1641 bc->cf_last->inst = BC_INST(bc, V_SQ_CF_WORD1_SQ_CF_INST_TEX);
1642 }
1643 if (ntex->src_gpr >= bc->ngpr) {
1644 bc->ngpr = ntex->src_gpr + 1;
1645 }
1646 if (ntex->dst_gpr >= bc->ngpr) {
1647 bc->ngpr = ntex->dst_gpr + 1;
1648 }
1649 LIST_ADDTAIL(&ntex->list, &bc->cf_last->tex);
1650 /* each texture fetch use 4 dwords */
1651 bc->cf_last->ndw += 4;
1652 bc->ndw += 4;
1653 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1654 bc->force_add_cf = 1;
1655 return 0;
1656 }
1657
1658 int r600_bytecode_add_cfinst(struct r600_bytecode *bc, int inst)
1659 {
1660 int r;
1661 r = r600_bytecode_add_cf(bc);
1662 if (r)
1663 return r;
1664
1665 bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
1666 bc->cf_last->inst = inst;
1667 return 0;
1668 }
1669
1670 int cm_bytecode_add_cf_end(struct r600_bytecode *bc)
1671 {
1672 return r600_bytecode_add_cfinst(bc, CM_V_SQ_CF_WORD1_SQ_CF_INST_END);
1673 }
1674
1675 /* common to all 3 families */
1676 static int r600_bytecode_vtx_build(struct r600_bytecode *bc, struct r600_bytecode_vtx *vtx, unsigned id)
1677 {
1678 bc->bytecode[id] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) |
1679 S_SQ_VTX_WORD0_FETCH_TYPE(vtx->fetch_type) |
1680 S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
1681 S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x);
1682 if (bc->chip_class < CAYMAN)
1683 bc->bytecode[id] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
1684 id++;
1685 bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
1686 S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
1687 S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
1688 S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
1689 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) |
1690 S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) |
1691 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) |
1692 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) |
1693 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
1694 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
1695 bc->bytecode[id] = S_SQ_VTX_WORD2_OFFSET(vtx->offset)|
1696 S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx->endian);
1697 if (bc->chip_class < CAYMAN)
1698 bc->bytecode[id] |= S_SQ_VTX_WORD2_MEGA_FETCH(1);
1699 id++;
1700 bc->bytecode[id++] = 0;
1701 return 0;
1702 }
1703
1704 /* common to all 3 families */
1705 static int r600_bytecode_tex_build(struct r600_bytecode *bc, struct r600_bytecode_tex *tex, unsigned id)
1706 {
1707 bc->bytecode[id++] = S_SQ_TEX_WORD0_TEX_INST(tex->inst) |
1708 S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
1709 S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
1710 S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
1711 bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
1712 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
1713 S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
1714 S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
1715 S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
1716 S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
1717 S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
1718 S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
1719 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
1720 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
1721 S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
1722 bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
1723 S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
1724 S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
1725 S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
1726 S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
1727 S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
1728 S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
1729 S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
1730 bc->bytecode[id++] = 0;
1731 return 0;
1732 }
1733
1734 /* r600 only, r700/eg bits in r700_asm.c */
1735 static int r600_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id)
1736 {
1737 /* don't replace gpr by pv or ps for destination register */
1738 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
1739 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
1740 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
1741 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
1742 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
1743 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
1744 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
1745 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
1746 S_SQ_ALU_WORD0_INDEX_MODE(alu->index_mode) |
1747 S_SQ_ALU_WORD0_LAST(alu->last);
1748
1749 if (alu->is_op3) {
1750 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1751 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1752 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1753 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1754 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
1755 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
1756 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
1757 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
1758 S_SQ_ALU_WORD1_OP3_ALU_INST(alu->inst) |
1759 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
1760 } else {
1761 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1762 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1763 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1764 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1765 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
1766 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
1767 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
1768 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
1769 S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
1770 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
1771 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->predicate) |
1772 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->predicate);
1773 }
1774 return 0;
1775 }
1776
1777 static void r600_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_cf *cf)
1778 {
1779 *bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
1780 *bytecode++ = cf->inst |
1781 S_SQ_CF_WORD1_BARRIER(1) |
1782 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
1783 }
1784
1785 /* common for r600/r700 - eg in eg_asm.c */
1786 static int r600_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf)
1787 {
1788 unsigned id = cf->id;
1789
1790 switch (cf->inst) {
1791 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
1792 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
1793 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
1794 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
1795 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
1796 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
1797 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
1798 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank);
1799
1800 bc->bytecode[id++] = cf->inst |
1801 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) |
1802 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
1803 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
1804 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1805 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chip_class == R600 ? cf->r6xx_uses_waterfall : 0) |
1806 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
1807 break;
1808 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1809 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1810 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1811 if (bc->chip_class == R700)
1812 r700_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1813 else
1814 r600_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1815 break;
1816 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1817 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1818 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1819 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1820 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1821 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
1822 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1823 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
1824 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
1825 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
1826 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
1827 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
1828 cf->output.inst |
1829 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program);
1830 break;
1831 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
1832 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
1833 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
1834 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
1835 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1836 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1837 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1838 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
1839 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1840 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
1841 cf->output.inst |
1842 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program) |
1843 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf->output.array_size) |
1844 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf->output.comp_mask);
1845 break;
1846 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1847 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1848 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1849 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1850 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1851 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1852 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1853 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1854 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1855 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
1856 bc->bytecode[id++] = cf->inst |
1857 S_SQ_CF_WORD1_BARRIER(1) |
1858 S_SQ_CF_WORD1_COND(cf->cond) |
1859 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count);
1860
1861 break;
1862 default:
1863 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1864 return -EINVAL;
1865 }
1866 return 0;
1867 }
1868
1869 int r600_bytecode_build(struct r600_bytecode *bc)
1870 {
1871 struct r600_bytecode_cf *cf;
1872 struct r600_bytecode_alu *alu;
1873 struct r600_bytecode_vtx *vtx;
1874 struct r600_bytecode_tex *tex;
1875 uint32_t literal[4];
1876 unsigned nliteral;
1877 unsigned addr;
1878 int i, r;
1879
1880 if (bc->callstack[0].max > 0)
1881 bc->nstack = ((bc->callstack[0].max + 3) >> 2) + 2;
1882 if (bc->type == TGSI_PROCESSOR_VERTEX && !bc->nstack) {
1883 bc->nstack = 1;
1884 }
1885
1886 /* first path compute addr of each CF block */
1887 /* addr start after all the CF instructions */
1888 addr = bc->cf_last->id + 2;
1889 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1890 if (bc->chip_class >= EVERGREEN) {
1891 switch (cf->inst) {
1892 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1893 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1894 /* fetch node need to be 16 bytes aligned*/
1895 addr += 3;
1896 addr &= 0xFFFFFFFCUL;
1897 break;
1898 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
1899 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
1900 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
1901 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
1902 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1903 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1904 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0:
1905 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1:
1906 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2:
1907 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3:
1908 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0:
1909 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1:
1910 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2:
1911 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3:
1912 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0:
1913 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1:
1914 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2:
1915 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3:
1916 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0:
1917 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1:
1918 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2:
1919 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3:
1920 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1921 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1922 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
1923 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1924 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1925 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1926 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1927 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1928 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1929 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
1930 break;
1931 default:
1932 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1933 return -EINVAL;
1934 }
1935 } else {
1936 switch (cf->inst) {
1937 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1938 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1939 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1940 /* fetch node need to be 16 bytes aligned*/
1941 addr += 3;
1942 addr &= 0xFFFFFFFCUL;
1943 break;
1944 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
1945 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
1946 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
1947 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
1948 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1949 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1950 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
1951 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
1952 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
1953 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
1954 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1955 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1956 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1957 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1958 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1959 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1960 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1961 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1962 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1963 break;
1964 default:
1965 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1966 return -EINVAL;
1967 }
1968 }
1969 cf->addr = addr;
1970 addr += cf->ndw;
1971 bc->ndw = cf->addr + cf->ndw;
1972 }
1973 free(bc->bytecode);
1974 bc->bytecode = calloc(1, bc->ndw * 4);
1975 if (bc->bytecode == NULL)
1976 return -ENOMEM;
1977 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1978 addr = cf->addr;
1979 if (bc->chip_class >= EVERGREEN) {
1980 r = eg_bytecode_cf_build(bc, cf);
1981 if (r)
1982 return r;
1983
1984 switch (cf->inst) {
1985 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
1986 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
1987 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
1988 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
1989 nliteral = 0;
1990 memset(literal, 0, sizeof(literal));
1991 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1992 r = r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
1993 if (r)
1994 return r;
1995 r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral);
1996 r600_bytecode_assign_kcache_banks(bc, alu, cf->kcache);
1997
1998 switch(bc->chip_class) {
1999 case EVERGREEN: /* eg alu is same encoding as r700 */
2000 case CAYMAN:
2001 r = r700_bytecode_alu_build(bc, alu, addr);
2002 break;
2003 default:
2004 R600_ERR("unknown chip class %d.\n", bc->chip_class);
2005 return -EINVAL;
2006 }
2007 if (r)
2008 return r;
2009 addr += 2;
2010 if (alu->last) {
2011 for (i = 0; i < align(nliteral, 2); ++i) {
2012 bc->bytecode[addr++] = literal[i];
2013 }
2014 nliteral = 0;
2015 memset(literal, 0, sizeof(literal));
2016 }
2017 }
2018 break;
2019 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2020 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2021 r = r600_bytecode_vtx_build(bc, vtx, addr);
2022 if (r)
2023 return r;
2024 addr += 4;
2025 }
2026 break;
2027 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2028 if (bc->chip_class == CAYMAN) {
2029 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2030 r = r600_bytecode_vtx_build(bc, vtx, addr);
2031 if (r)
2032 return r;
2033 addr += 4;
2034 }
2035 }
2036 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2037 r = r600_bytecode_tex_build(bc, tex, addr);
2038 if (r)
2039 return r;
2040 addr += 4;
2041 }
2042 break;
2043 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2044 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2045 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0:
2046 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1:
2047 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2:
2048 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3:
2049 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0:
2050 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1:
2051 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2:
2052 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3:
2053 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0:
2054 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1:
2055 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2:
2056 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3:
2057 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0:
2058 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1:
2059 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2:
2060 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3:
2061 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
2062 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2063 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2064 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2065 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2066 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2067 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
2068 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2069 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2070 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
2071 break;
2072 default:
2073 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
2074 return -EINVAL;
2075 }
2076 } else {
2077 r = r600_bytecode_cf_build(bc, cf);
2078 if (r)
2079 return r;
2080
2081 switch (cf->inst) {
2082 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
2083 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
2084 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
2085 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
2086 nliteral = 0;
2087 memset(literal, 0, sizeof(literal));
2088 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
2089 r = r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
2090 if (r)
2091 return r;
2092 r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral);
2093 r600_bytecode_assign_kcache_banks(bc, alu, cf->kcache);
2094
2095 switch(bc->chip_class) {
2096 case R600:
2097 r = r600_bytecode_alu_build(bc, alu, addr);
2098 break;
2099 case R700:
2100 r = r700_bytecode_alu_build(bc, alu, addr);
2101 break;
2102 default:
2103 R600_ERR("unknown chip class %d.\n", bc->chip_class);
2104 return -EINVAL;
2105 }
2106 if (r)
2107 return r;
2108 addr += 2;
2109 if (alu->last) {
2110 for (i = 0; i < align(nliteral, 2); ++i) {
2111 bc->bytecode[addr++] = literal[i];
2112 }
2113 nliteral = 0;
2114 memset(literal, 0, sizeof(literal));
2115 }
2116 }
2117 break;
2118 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2119 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
2120 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2121 r = r600_bytecode_vtx_build(bc, vtx, addr);
2122 if (r)
2123 return r;
2124 addr += 4;
2125 }
2126 break;
2127 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2128 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2129 r = r600_bytecode_tex_build(bc, tex, addr);
2130 if (r)
2131 return r;
2132 addr += 4;
2133 }
2134 break;
2135 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2136 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2137 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
2138 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
2139 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
2140 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
2141 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
2142 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2143 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2144 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2145 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2146 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2147 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
2148 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2149 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2150 break;
2151 default:
2152 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
2153 return -EINVAL;
2154 }
2155 }
2156 }
2157 return 0;
2158 }
2159
2160 void r600_bytecode_clear(struct r600_bytecode *bc)
2161 {
2162 struct r600_bytecode_cf *cf = NULL, *next_cf;
2163
2164 free(bc->bytecode);
2165 bc->bytecode = NULL;
2166
2167 LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
2168 struct r600_bytecode_alu *alu = NULL, *next_alu;
2169 struct r600_bytecode_tex *tex = NULL, *next_tex;
2170 struct r600_bytecode_tex *vtx = NULL, *next_vtx;
2171
2172 LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
2173 free(alu);
2174 }
2175
2176 LIST_INITHEAD(&cf->alu);
2177
2178 LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) {
2179 free(tex);
2180 }
2181
2182 LIST_INITHEAD(&cf->tex);
2183
2184 LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) {
2185 free(vtx);
2186 }
2187
2188 LIST_INITHEAD(&cf->vtx);
2189
2190 free(cf);
2191 }
2192
2193 LIST_INITHEAD(&cf->list);
2194 }
2195
2196 void r600_bytecode_dump(struct r600_bytecode *bc)
2197 {
2198 struct r600_bytecode_cf *cf = NULL;
2199 struct r600_bytecode_alu *alu = NULL;
2200 struct r600_bytecode_vtx *vtx = NULL;
2201 struct r600_bytecode_tex *tex = NULL;
2202
2203 unsigned i, id;
2204 uint32_t literal[4];
2205 unsigned nliteral;
2206 char chip = '6';
2207
2208 switch (bc->chip_class) {
2209 case R700:
2210 chip = '7';
2211 break;
2212 case EVERGREEN:
2213 chip = 'E';
2214 break;
2215 case CAYMAN:
2216 chip = 'C';
2217 break;
2218 case R600:
2219 default:
2220 chip = '6';
2221 break;
2222 }
2223 fprintf(stderr, "bytecode %d dw -- %d gprs ---------------------\n", bc->ndw, bc->ngpr);
2224 fprintf(stderr, " %c\n", chip);
2225
2226 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
2227 id = cf->id;
2228
2229 if (bc->chip_class >= EVERGREEN) {
2230 switch (cf->inst) {
2231 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
2232 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
2233 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
2234 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
2235 if (cf->eg_alu_extended) {
2236 fprintf(stderr, "%04d %08X ALU_EXT0 ", id, bc->bytecode[id]);
2237 fprintf(stderr, "KCACHE_BANK2:%X ", cf->kcache[2].bank);
2238 fprintf(stderr, "KCACHE_BANK3:%X ", cf->kcache[3].bank);
2239 fprintf(stderr, "KCACHE_MODE2:%X\n", cf->kcache[2].mode);
2240 id++;
2241 fprintf(stderr, "%04d %08X ALU_EXT1 ", id, bc->bytecode[id]);
2242 fprintf(stderr, "KCACHE_MODE3:%X ", cf->kcache[3].mode);
2243 fprintf(stderr, "KCACHE_ADDR2:%X ", cf->kcache[2].addr);
2244 fprintf(stderr, "KCACHE_ADDR3:%X\n", cf->kcache[3].addr);
2245 id++;
2246 }
2247
2248 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2249 fprintf(stderr, "ADDR:%d ", cf->addr);
2250 fprintf(stderr, "KCACHE_MODE0:%X ", cf->kcache[0].mode);
2251 fprintf(stderr, "KCACHE_BANK0:%X ", cf->kcache[0].bank);
2252 fprintf(stderr, "KCACHE_BANK1:%X\n", cf->kcache[1].bank);
2253 id++;
2254 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2255 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_ALU_WORD1_CF_INST(cf->inst));
2256 fprintf(stderr, "KCACHE_MODE1:%X ", cf->kcache[1].mode);
2257 fprintf(stderr, "KCACHE_ADDR0:%X ", cf->kcache[0].addr);
2258 fprintf(stderr, "KCACHE_ADDR1:%X ", cf->kcache[1].addr);
2259 fprintf(stderr, "COUNT:%d\n", cf->ndw / 2);
2260 break;
2261 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2262 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2263 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2264 fprintf(stderr, "ADDR:%d\n", cf->addr);
2265 id++;
2266 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2267 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_WORD1_CF_INST(cf->inst));
2268 fprintf(stderr, "COUNT:%d\n", cf->ndw / 4);
2269 break;
2270 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2271 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2272 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2273 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2274 fprintf(stderr, "ELEM_SIZE:%X ", cf->output.elem_size);
2275 fprintf(stderr, "ARRAY_BASE:%X ", cf->output.array_base);
2276 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2277 id++;
2278 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2279 fprintf(stderr, "SWIZ_X:%X ", cf->output.swizzle_x);
2280 fprintf(stderr, "SWIZ_Y:%X ", cf->output.swizzle_y);
2281 fprintf(stderr, "SWIZ_Z:%X ", cf->output.swizzle_z);
2282 fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
2283 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2284 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst));
2285 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2286 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2287 break;
2288 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0:
2289 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1:
2290 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2:
2291 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3:
2292 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0:
2293 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1:
2294 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2:
2295 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3:
2296 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0:
2297 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1:
2298 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2:
2299 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3:
2300 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0:
2301 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1:
2302 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2:
2303 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3:
2304 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i_BUF%i ", id, bc->bytecode[id],
2305 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2306 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) / 4,
2307 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2308 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) % 4);
2309 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2310 fprintf(stderr, "ELEM_SIZE:%i ", cf->output.elem_size);
2311 fprintf(stderr, "ARRAY_BASE:%i ", cf->output.array_base);
2312 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2313 id++;
2314 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i_BUF%i ", id, bc->bytecode[id],
2315 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2316 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) / 4,
2317 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2318 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) % 4);
2319 fprintf(stderr, "ARRAY_SIZE:%i ", cf->output.array_size);
2320 fprintf(stderr, "COMP_MASK:%X ", cf->output.comp_mask);
2321 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2322 fprintf(stderr, "INST:%d ", cf->output.inst);
2323 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2324 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2325 break;
2326 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2327 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2328 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
2329 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
2330 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2331 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2332 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2333 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2334 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2335 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
2336 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2337 fprintf(stderr, "ADDR:%d\n", cf->cf_addr);
2338 id++;
2339 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2340 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_WORD1_CF_INST(cf->inst));
2341 fprintf(stderr, "COND:%X ", cf->cond);
2342 fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
2343 break;
2344 default:
2345 R600_ERR("Unknown instruction %0x\n", cf->inst);
2346 }
2347 } else {
2348 switch (cf->inst) {
2349 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
2350 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
2351 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
2352 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
2353 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2354 fprintf(stderr, "ADDR:%d ", cf->addr);
2355 fprintf(stderr, "KCACHE_MODE0:%X ", cf->kcache[0].mode);
2356 fprintf(stderr, "KCACHE_BANK0:%X ", cf->kcache[0].bank);
2357 fprintf(stderr, "KCACHE_BANK1:%X\n", cf->kcache[1].bank);
2358 id++;
2359 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2360 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_ALU_WORD1_CF_INST(cf->inst));
2361 fprintf(stderr, "KCACHE_MODE1:%X ", cf->kcache[1].mode);
2362 fprintf(stderr, "KCACHE_ADDR0:%X ", cf->kcache[0].addr);
2363 fprintf(stderr, "KCACHE_ADDR1:%X ", cf->kcache[1].addr);
2364 fprintf(stderr, "COUNT:%d\n", cf->ndw / 2);
2365 break;
2366 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2367 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2368 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
2369 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2370 fprintf(stderr, "ADDR:%d\n", cf->addr);
2371 id++;
2372 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2373 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_WORD1_CF_INST(cf->inst));
2374 fprintf(stderr, "COUNT:%d\n", cf->ndw / 4);
2375 break;
2376 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2377 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2378 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2379 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2380 fprintf(stderr, "ELEM_SIZE:%X ", cf->output.elem_size);
2381 fprintf(stderr, "ARRAY_BASE:%X ", cf->output.array_base);
2382 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2383 id++;
2384 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2385 fprintf(stderr, "SWIZ_X:%X ", cf->output.swizzle_x);
2386 fprintf(stderr, "SWIZ_Y:%X ", cf->output.swizzle_y);
2387 fprintf(stderr, "SWIZ_Z:%X ", cf->output.swizzle_z);
2388 fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
2389 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2390 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst));
2391 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2392 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2393 break;
2394 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
2395 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
2396 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
2397 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
2398 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i ", id, bc->bytecode[id],
2399 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2400 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0));
2401 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2402 fprintf(stderr, "ELEM_SIZE:%i ", cf->output.elem_size);
2403 fprintf(stderr, "ARRAY_BASE:%i ", cf->output.array_base);
2404 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2405 id++;
2406 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i ", id, bc->bytecode[id],
2407 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2408 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0));
2409 fprintf(stderr, "ARRAY_SIZE:%i ", cf->output.array_size);
2410 fprintf(stderr, "COMP_MASK:%X ", cf->output.comp_mask);
2411 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2412 fprintf(stderr, "INST:%d ", cf->output.inst);
2413 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2414 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2415 break;
2416 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2417 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2418 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
2419 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
2420 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2421 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2422 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2423 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2424 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2425 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2426 fprintf(stderr, "ADDR:%d\n", cf->cf_addr);
2427 id++;
2428 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2429 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_WORD1_CF_INST(cf->inst));
2430 fprintf(stderr, "COND:%X ", cf->cond);
2431 fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
2432 break;
2433 default:
2434 R600_ERR("Unknown instruction %0x\n", cf->inst);
2435 }
2436 }
2437
2438 id = cf->addr;
2439 nliteral = 0;
2440 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
2441 r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
2442
2443 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2444 fprintf(stderr, "SRC0(SEL:%d ", alu->src[0].sel);
2445 fprintf(stderr, "REL:%d ", alu->src[0].rel);
2446 fprintf(stderr, "CHAN:%d ", alu->src[0].chan);
2447 fprintf(stderr, "NEG:%d) ", alu->src[0].neg);
2448 fprintf(stderr, "SRC1(SEL:%d ", alu->src[1].sel);
2449 fprintf(stderr, "REL:%d ", alu->src[1].rel);
2450 fprintf(stderr, "CHAN:%d ", alu->src[1].chan);
2451 fprintf(stderr, "NEG:%d ", alu->src[1].neg);
2452 fprintf(stderr, "IM:%d) ", alu->index_mode);
2453 fprintf(stderr, "LAST:%d)\n", alu->last);
2454 id++;
2455 fprintf(stderr, "%04d %08X %c ", id, bc->bytecode[id], alu->last ? '*' : ' ');
2456 fprintf(stderr, "INST:0x%x ", alu->inst);
2457 fprintf(stderr, "DST(SEL:%d ", alu->dst.sel);
2458 fprintf(stderr, "CHAN:%d ", alu->dst.chan);
2459 fprintf(stderr, "REL:%d ", alu->dst.rel);
2460 fprintf(stderr, "CLAMP:%d) ", alu->dst.clamp);
2461 fprintf(stderr, "BANK_SWIZZLE:%d ", alu->bank_swizzle);
2462 if (alu->is_op3) {
2463 fprintf(stderr, "SRC2(SEL:%d ", alu->src[2].sel);
2464 fprintf(stderr, "REL:%d ", alu->src[2].rel);
2465 fprintf(stderr, "CHAN:%d ", alu->src[2].chan);
2466 fprintf(stderr, "NEG:%d)\n", alu->src[2].neg);
2467 } else {
2468 fprintf(stderr, "SRC0_ABS:%d ", alu->src[0].abs);
2469 fprintf(stderr, "SRC1_ABS:%d ", alu->src[1].abs);
2470 fprintf(stderr, "WRITE_MASK:%d ", alu->dst.write);
2471 fprintf(stderr, "OMOD:%d ", alu->omod);
2472 fprintf(stderr, "EXECUTE_MASK:%d ", alu->predicate);
2473 fprintf(stderr, "UPDATE_PRED:%d\n", alu->predicate);
2474 }
2475
2476 id++;
2477 if (alu->last) {
2478 for (i = 0; i < nliteral; i++, id++) {
2479 float *f = (float*)(bc->bytecode + id);
2480 fprintf(stderr, "%04d %08X\t%f\n", id, bc->bytecode[id], *f);
2481 }
2482 id += nliteral & 1;
2483 nliteral = 0;
2484 }
2485 }
2486
2487 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2488 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2489 fprintf(stderr, "INST:0x%x ", tex->inst);
2490 fprintf(stderr, "RESOURCE_ID:%d ", tex->resource_id);
2491 fprintf(stderr, "SRC(GPR:%d ", tex->src_gpr);
2492 fprintf(stderr, "REL:%d)\n", tex->src_rel);
2493 id++;
2494 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2495 fprintf(stderr, "DST(GPR:%d ", tex->dst_gpr);
2496 fprintf(stderr, "REL:%d ", tex->dst_rel);
2497 fprintf(stderr, "SEL_X:%d ", tex->dst_sel_x);
2498 fprintf(stderr, "SEL_Y:%d ", tex->dst_sel_y);
2499 fprintf(stderr, "SEL_Z:%d ", tex->dst_sel_z);
2500 fprintf(stderr, "SEL_W:%d) ", tex->dst_sel_w);
2501 fprintf(stderr, "LOD_BIAS:%d ", tex->lod_bias);
2502 fprintf(stderr, "COORD_TYPE_X:%d ", tex->coord_type_x);
2503 fprintf(stderr, "COORD_TYPE_Y:%d ", tex->coord_type_y);
2504 fprintf(stderr, "COORD_TYPE_Z:%d ", tex->coord_type_z);
2505 fprintf(stderr, "COORD_TYPE_W:%d\n", tex->coord_type_w);
2506 id++;
2507 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2508 fprintf(stderr, "OFFSET_X:%d ", tex->offset_x);
2509 fprintf(stderr, "OFFSET_Y:%d ", tex->offset_y);
2510 fprintf(stderr, "OFFSET_Z:%d ", tex->offset_z);
2511 fprintf(stderr, "SAMPLER_ID:%d ", tex->sampler_id);
2512 fprintf(stderr, "SRC(SEL_X:%d ", tex->src_sel_x);
2513 fprintf(stderr, "SEL_Y:%d ", tex->src_sel_y);
2514 fprintf(stderr, "SEL_Z:%d ", tex->src_sel_z);
2515 fprintf(stderr, "SEL_W:%d)\n", tex->src_sel_w);
2516 id++;
2517 fprintf(stderr, "%04d %08X \n", id, bc->bytecode[id]);
2518 id++;
2519 }
2520
2521 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2522 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2523 fprintf(stderr, "INST:%d ", vtx->inst);
2524 fprintf(stderr, "FETCH_TYPE:%d ", vtx->fetch_type);
2525 fprintf(stderr, "BUFFER_ID:%d\n", vtx->buffer_id);
2526 id++;
2527 /* This assumes that no semantic fetches exist */
2528 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2529 fprintf(stderr, "SRC(GPR:%d ", vtx->src_gpr);
2530 fprintf(stderr, "SEL_X:%d) ", vtx->src_sel_x);
2531 if (bc->chip_class < CAYMAN)
2532 fprintf(stderr, "MEGA_FETCH_COUNT:%d ", vtx->mega_fetch_count);
2533 else
2534 fprintf(stderr, "SEL_Y:%d) ", 0);
2535 fprintf(stderr, "DST(GPR:%d ", vtx->dst_gpr);
2536 fprintf(stderr, "SEL_X:%d ", vtx->dst_sel_x);
2537 fprintf(stderr, "SEL_Y:%d ", vtx->dst_sel_y);
2538 fprintf(stderr, "SEL_Z:%d ", vtx->dst_sel_z);
2539 fprintf(stderr, "SEL_W:%d) ", vtx->dst_sel_w);
2540 fprintf(stderr, "USE_CONST_FIELDS:%d ", vtx->use_const_fields);
2541 fprintf(stderr, "FORMAT(DATA:%d ", vtx->data_format);
2542 fprintf(stderr, "NUM:%d ", vtx->num_format_all);
2543 fprintf(stderr, "COMP:%d ", vtx->format_comp_all);
2544 fprintf(stderr, "MODE:%d)\n", vtx->srf_mode_all);
2545 id++;
2546 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2547 fprintf(stderr, "ENDIAN:%d ", vtx->endian);
2548 fprintf(stderr, "OFFSET:%d\n", vtx->offset);
2549 /* TODO */
2550 id++;
2551 fprintf(stderr, "%04d %08X \n", id, bc->bytecode[id]);
2552 id++;
2553 }
2554 }
2555
2556 fprintf(stderr, "--------------------------------------\n");
2557 }
2558
2559 static void r600_vertex_data_type(enum pipe_format pformat,
2560 unsigned *format,
2561 unsigned *num_format, unsigned *format_comp, unsigned *endian)
2562 {
2563 const struct util_format_description *desc;
2564 unsigned i;
2565
2566 *format = 0;
2567 *num_format = 0;
2568 *format_comp = 0;
2569 *endian = ENDIAN_NONE;
2570
2571 desc = util_format_description(pformat);
2572 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
2573 goto out_unknown;
2574 }
2575
2576 /* Find the first non-VOID channel. */
2577 for (i = 0; i < 4; i++) {
2578 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2579 break;
2580 }
2581 }
2582
2583 *endian = r600_endian_swap(desc->channel[i].size);
2584
2585 switch (desc->channel[i].type) {
2586 /* Half-floats, floats, ints */
2587 case UTIL_FORMAT_TYPE_FLOAT:
2588 switch (desc->channel[i].size) {
2589 case 16:
2590 switch (desc->nr_channels) {
2591 case 1:
2592 *format = FMT_16_FLOAT;
2593 break;
2594 case 2:
2595 *format = FMT_16_16_FLOAT;
2596 break;
2597 case 3:
2598 case 4:
2599 *format = FMT_16_16_16_16_FLOAT;
2600 break;
2601 }
2602 break;
2603 case 32:
2604 switch (desc->nr_channels) {
2605 case 1:
2606 *format = FMT_32_FLOAT;
2607 break;
2608 case 2:
2609 *format = FMT_32_32_FLOAT;
2610 break;
2611 case 3:
2612 *format = FMT_32_32_32_FLOAT;
2613 break;
2614 case 4:
2615 *format = FMT_32_32_32_32_FLOAT;
2616 break;
2617 }
2618 break;
2619 default:
2620 goto out_unknown;
2621 }
2622 break;
2623 /* Unsigned ints */
2624 case UTIL_FORMAT_TYPE_UNSIGNED:
2625 /* Signed ints */
2626 case UTIL_FORMAT_TYPE_SIGNED:
2627 switch (desc->channel[i].size) {
2628 case 8:
2629 switch (desc->nr_channels) {
2630 case 1:
2631 *format = FMT_8;
2632 break;
2633 case 2:
2634 *format = FMT_8_8;
2635 break;
2636 case 3:
2637 case 4:
2638 *format = FMT_8_8_8_8;
2639 break;
2640 }
2641 break;
2642 case 10:
2643 if (desc->nr_channels != 4)
2644 goto out_unknown;
2645
2646 *format = FMT_2_10_10_10;
2647 break;
2648 case 16:
2649 switch (desc->nr_channels) {
2650 case 1:
2651 *format = FMT_16;
2652 break;
2653 case 2:
2654 *format = FMT_16_16;
2655 break;
2656 case 3:
2657 case 4:
2658 *format = FMT_16_16_16_16;
2659 break;
2660 }
2661 break;
2662 case 32:
2663 switch (desc->nr_channels) {
2664 case 1:
2665 *format = FMT_32;
2666 break;
2667 case 2:
2668 *format = FMT_32_32;
2669 break;
2670 case 3:
2671 *format = FMT_32_32_32;
2672 break;
2673 case 4:
2674 *format = FMT_32_32_32_32;
2675 break;
2676 }
2677 break;
2678 default:
2679 goto out_unknown;
2680 }
2681 break;
2682 default:
2683 goto out_unknown;
2684 }
2685
2686 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2687 *format_comp = 1;
2688 }
2689
2690 *num_format = 0;
2691 if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED ||
2692 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2693 if (!desc->channel[i].normalized) {
2694 if (desc->channel[i].pure_integer)
2695 *num_format = 1;
2696 else
2697 *num_format = 2;
2698 }
2699 }
2700 return;
2701 out_unknown:
2702 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
2703 }
2704
2705 int r600_vertex_elements_build_fetch_shader(struct r600_pipe_context *rctx, struct r600_vertex_element *ve)
2706 {
2707 static int dump_shaders = -1;
2708
2709 struct r600_bytecode bc;
2710 struct r600_bytecode_vtx vtx;
2711 struct pipe_vertex_element *elements = ve->elements;
2712 const struct util_format_description *desc;
2713 unsigned fetch_resource_start = rctx->chip_class >= EVERGREEN ? 0 : 160;
2714 unsigned format, num_format, format_comp, endian;
2715 u32 *bytecode;
2716 int i, r;
2717
2718 /* Vertex element offsets need special handling. If the offset is
2719 * bigger than what we can put in the fetch instruction we need to
2720 * alter the vertex resource offset. In order to simplify code we
2721 * will bind one resource per element in such cases. It's a worst
2722 * case scenario. */
2723 for (i = 0; i < ve->count; i++) {
2724 ve->vbuffer_offset[i] = C_SQ_VTX_WORD2_OFFSET & elements[i].src_offset;
2725 if (ve->vbuffer_offset[i]) {
2726 ve->vbuffer_need_offset = 1;
2727 }
2728 }
2729
2730 memset(&bc, 0, sizeof(bc));
2731 r600_bytecode_init(&bc, rctx->chip_class, rctx->family);
2732
2733 for (i = 0; i < ve->count; i++) {
2734 if (elements[i].instance_divisor > 1) {
2735 struct r600_bytecode_alu alu;
2736
2737 memset(&alu, 0, sizeof(alu));
2738 alu.inst = BC_INST(&bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
2739 alu.src[0].sel = 0;
2740 alu.src[0].chan = 3;
2741
2742 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2743 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2744
2745 alu.dst.sel = i + 1;
2746 alu.dst.chan = 3;
2747 alu.dst.write = 1;
2748 alu.last = 1;
2749
2750 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2751 r600_bytecode_clear(&bc);
2752 return r;
2753 }
2754 }
2755 }
2756
2757 for (i = 0; i < ve->count; i++) {
2758 unsigned vbuffer_index;
2759 r600_vertex_data_type(ve->elements[i].src_format,
2760 &format, &num_format, &format_comp, &endian);
2761 desc = util_format_description(ve->elements[i].src_format);
2762 if (desc == NULL) {
2763 r600_bytecode_clear(&bc);
2764 R600_ERR("unknown format %d\n", ve->elements[i].src_format);
2765 return -EINVAL;
2766 }
2767
2768 /* see above for vbuffer_need_offset explanation */
2769 vbuffer_index = elements[i].vertex_buffer_index;
2770 memset(&vtx, 0, sizeof(vtx));
2771 vtx.buffer_id = (ve->vbuffer_need_offset ? i : vbuffer_index) + fetch_resource_start;
2772 vtx.fetch_type = elements[i].instance_divisor ? 1 : 0;
2773 vtx.src_gpr = elements[i].instance_divisor > 1 ? i + 1 : 0;
2774 vtx.src_sel_x = elements[i].instance_divisor ? 3 : 0;
2775 vtx.mega_fetch_count = 0x1F;
2776 vtx.dst_gpr = i + 1;
2777 vtx.dst_sel_x = desc->swizzle[0];
2778 vtx.dst_sel_y = desc->swizzle[1];
2779 vtx.dst_sel_z = desc->swizzle[2];
2780 vtx.dst_sel_w = desc->swizzle[3];
2781 vtx.data_format = format;
2782 vtx.num_format_all = num_format;
2783 vtx.format_comp_all = format_comp;
2784 vtx.srf_mode_all = 1;
2785 vtx.offset = elements[i].src_offset;
2786 vtx.endian = endian;
2787
2788 if ((r = r600_bytecode_add_vtx(&bc, &vtx))) {
2789 r600_bytecode_clear(&bc);
2790 return r;
2791 }
2792 }
2793
2794 r600_bytecode_add_cfinst(&bc, BC_INST(&bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN));
2795
2796 if ((r = r600_bytecode_build(&bc))) {
2797 r600_bytecode_clear(&bc);
2798 return r;
2799 }
2800
2801 if (dump_shaders == -1)
2802 dump_shaders = debug_get_bool_option("R600_DUMP_SHADERS", FALSE);
2803
2804 if (dump_shaders) {
2805 fprintf(stderr, "--------------------------------------------------------------\n");
2806 r600_bytecode_dump(&bc);
2807 fprintf(stderr, "______________________________________________________________\n");
2808 }
2809
2810 ve->fs_size = bc.ndw*4;
2811
2812 ve->fetch_shader = (struct r600_resource*)
2813 pipe_buffer_create(rctx->context.screen,
2814 PIPE_BIND_CUSTOM,
2815 PIPE_USAGE_IMMUTABLE, ve->fs_size);
2816 if (ve->fetch_shader == NULL) {
2817 r600_bytecode_clear(&bc);
2818 return -ENOMEM;
2819 }
2820
2821 bytecode = rctx->ws->buffer_map(ve->fetch_shader->buf, rctx->ctx.cs, PIPE_TRANSFER_WRITE);
2822 if (bytecode == NULL) {
2823 r600_bytecode_clear(&bc);
2824 pipe_resource_reference((struct pipe_resource**)&ve->fetch_shader, NULL);
2825 return -ENOMEM;
2826 }
2827
2828 if (R600_BIG_ENDIAN) {
2829 for (i = 0; i < ve->fs_size / 4; ++i) {
2830 bytecode[i] = bswap_32(bc.bytecode[i]);
2831 }
2832 } else {
2833 memcpy(bytecode, bc.bytecode, ve->fs_size);
2834 }
2835
2836 rctx->ws->buffer_unmap(ve->fetch_shader->buf);
2837 r600_bytecode_clear(&bc);
2838
2839 if (rctx->chip_class >= EVERGREEN)
2840 evergreen_fetch_shader(&rctx->context, ve);
2841 else
2842 r600_fetch_shader(&rctx->context, ve);
2843
2844 return 0;
2845 }