2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "util/u_format.h"
26 #include "util/u_memory.h"
27 #include "pipe/p_shader_tokens.h"
28 #include "r600_pipe.h"
30 #include "r600_opcodes.h"
32 #include "r600_formats.h"
35 #define NUM_OF_CYCLES 3
36 #define NUM_OF_COMPONENTS 4
38 static inline unsigned int r600_bc_get_num_operands(struct r600_bc_alu
*alu
)
44 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
:
46 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
:
47 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE
:
48 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
:
49 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE
:
50 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE
:
51 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
:
52 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
:
53 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN
:
54 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE
:
55 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE
:
56 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
:
57 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
:
58 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE
:
59 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT
:
60 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE
:
61 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE
:
62 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
:
63 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE
:
64 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE
:
67 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
:
68 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR
:
69 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
:
70 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
:
71 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC
:
72 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
:
73 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED
:
74 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
:
75 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
:
76 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE
:
77 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT
:
78 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
:
79 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
:
82 "Need instruction operand number for 0x%x.\n", alu
->inst
);
88 int r700_bc_alu_build(struct r600_bc
*bc
, struct r600_bc_alu
*alu
, unsigned id
);
90 static struct r600_bc_cf
*r600_bc_cf(void)
92 struct r600_bc_cf
*cf
= CALLOC_STRUCT(r600_bc_cf
);
96 LIST_INITHEAD(&cf
->list
);
97 LIST_INITHEAD(&cf
->alu
);
98 LIST_INITHEAD(&cf
->vtx
);
99 LIST_INITHEAD(&cf
->tex
);
103 static struct r600_bc_alu
*r600_bc_alu(void)
105 struct r600_bc_alu
*alu
= CALLOC_STRUCT(r600_bc_alu
);
109 LIST_INITHEAD(&alu
->list
);
113 static struct r600_bc_vtx
*r600_bc_vtx(void)
115 struct r600_bc_vtx
*vtx
= CALLOC_STRUCT(r600_bc_vtx
);
119 LIST_INITHEAD(&vtx
->list
);
123 static struct r600_bc_tex
*r600_bc_tex(void)
125 struct r600_bc_tex
*tex
= CALLOC_STRUCT(r600_bc_tex
);
129 LIST_INITHEAD(&tex
->list
);
133 int r600_bc_init(struct r600_bc
*bc
, enum radeon_family family
)
135 LIST_INITHEAD(&bc
->cf
);
137 switch (bc
->family
) {
146 bc
->chiprev
= CHIPREV_R600
;
152 bc
->chiprev
= CHIPREV_R700
;
160 bc
->chiprev
= CHIPREV_EVERGREEN
;
163 R600_ERR("unknown family %d\n", bc
->family
);
169 static int r600_bc_add_cf(struct r600_bc
*bc
)
171 struct r600_bc_cf
*cf
= r600_bc_cf();
175 LIST_ADDTAIL(&cf
->list
, &bc
->cf
);
177 cf
->id
= bc
->cf_last
->id
+ 2;
181 bc
->force_add_cf
= 0;
185 int r600_bc_add_output(struct r600_bc
*bc
, const struct r600_bc_output
*output
)
189 r
= r600_bc_add_cf(bc
);
192 bc
->cf_last
->inst
= output
->inst
;
193 memcpy(&bc
->cf_last
->output
, output
, sizeof(struct r600_bc_output
));
197 /* alu instructions that can ony exits once per group */
198 static int is_alu_once_inst(struct r600_bc_alu
*alu
)
200 return !alu
->is_op3
&& (
201 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE
||
202 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
||
203 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE
||
204 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE
||
205 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT
||
206 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT
||
207 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT
||
208 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT
||
209 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT
||
210 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT
||
211 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT
||
212 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT
||
213 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE
||
214 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT
||
215 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE
||
216 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE
||
217 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV
||
218 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP
||
219 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR
||
220 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE
||
221 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH
||
222 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH
||
223 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH
||
224 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH
||
225 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT
||
226 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT
||
227 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT
||
228 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT
||
229 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT
||
230 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT
||
231 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT
||
232 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT
||
233 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT
||
234 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT
);
237 static int is_alu_reduction_inst(struct r600_bc_alu
*alu
)
239 return !alu
->is_op3
&& (
240 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE
||
241 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
||
242 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE
||
243 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4
);
246 static int is_alu_mova_inst(struct r600_bc_alu
*alu
)
248 return !alu
->is_op3
&& (
249 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA
||
250 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR
||
251 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT
);
254 /* alu instructions that can only execute on the vector unit */
255 static int is_alu_vec_unit_inst(struct r600_bc_alu
*alu
)
257 return is_alu_reduction_inst(alu
) ||
258 is_alu_mova_inst(alu
);
261 /* alu instructions that can only execute on the trans unit */
262 static int is_alu_trans_unit_inst(struct r600_bc_alu
*alu
)
265 return alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT
||
266 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT
||
267 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT
||
268 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT
||
269 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT
||
270 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT
||
271 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT
||
272 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT
||
273 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT
||
274 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT
||
275 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT
||
276 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT
||
277 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
||
278 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
||
279 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED
||
280 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
||
281 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED
||
282 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_FF
||
283 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
||
284 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED
||
285 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF
||
286 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE
||
287 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
||
288 alu
->inst
== V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_IEEE
;
290 return alu
->inst
== V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT
||
291 alu
->inst
== V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_D2
||
292 alu
->inst
== V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M2
||
293 alu
->inst
== V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M4
;
296 /* alu instructions that can execute on any unit */
297 static int is_alu_any_unit_inst(struct r600_bc_alu
*alu
)
299 return !is_alu_vec_unit_inst(alu
) &&
300 !is_alu_trans_unit_inst(alu
);
303 static int assign_alu_units(struct r600_bc_alu
*alu_first
, struct r600_bc_alu
*assignment
[5])
305 struct r600_bc_alu
*alu
;
306 unsigned i
, chan
, trans
;
308 for (i
= 0; i
< 5; i
++)
309 assignment
[i
] = NULL
;
311 for (alu
= alu_first
; alu
; alu
= container_of(alu
->list
.next
, alu
, list
)) {
312 chan
= alu
->dst
.chan
;
313 if (is_alu_trans_unit_inst(alu
))
315 else if (is_alu_vec_unit_inst(alu
))
317 else if (assignment
[chan
])
318 trans
= 1; // assume ALU_INST_PREFER_VECTOR
324 assert(0); //ALU.Trans has already been allocated
329 if (assignment
[chan
]) {
330 assert(0); //ALU.chan has already been allocated
333 assignment
[chan
] = alu
;
342 struct alu_bank_swizzle
{
343 int hw_gpr
[NUM_OF_CYCLES
][NUM_OF_COMPONENTS
];
344 int hw_cfile_addr
[4];
345 int hw_cfile_elem
[4];
348 const unsigned cycle_for_bank_swizzle_vec
[][3] = {
349 [SQ_ALU_VEC_012
] = { 0, 1, 2 },
350 [SQ_ALU_VEC_021
] = { 0, 2, 1 },
351 [SQ_ALU_VEC_120
] = { 1, 2, 0 },
352 [SQ_ALU_VEC_102
] = { 1, 0, 2 },
353 [SQ_ALU_VEC_201
] = { 2, 0, 1 },
354 [SQ_ALU_VEC_210
] = { 2, 1, 0 }
357 const unsigned cycle_for_bank_swizzle_scl
[][3] = {
358 [SQ_ALU_SCL_210
] = { 2, 1, 0 },
359 [SQ_ALU_SCL_122
] = { 1, 2, 2 },
360 [SQ_ALU_SCL_212
] = { 2, 1, 2 },
361 [SQ_ALU_SCL_221
] = { 2, 2, 1 }
364 static void init_bank_swizzle(struct alu_bank_swizzle
*bs
)
366 int i
, cycle
, component
;
368 for (cycle
= 0; cycle
< NUM_OF_CYCLES
; cycle
++)
369 for (component
= 0; component
< NUM_OF_COMPONENTS
; component
++)
370 bs
->hw_gpr
[cycle
][component
] = -1;
371 for (i
= 0; i
< 4; i
++)
372 bs
->hw_cfile_addr
[i
] = -1;
373 for (i
= 0; i
< 4; i
++)
374 bs
->hw_cfile_elem
[i
] = -1;
377 static int reserve_gpr(struct alu_bank_swizzle
*bs
, unsigned sel
, unsigned chan
, unsigned cycle
)
379 if (bs
->hw_gpr
[cycle
][chan
] == -1)
380 bs
->hw_gpr
[cycle
][chan
] = sel
;
381 else if (bs
->hw_gpr
[cycle
][chan
] != (int)sel
) {
382 // Another scalar operation has already used GPR read port for channel
388 static int reserve_cfile(struct alu_bank_swizzle
*bs
, unsigned sel
, unsigned chan
)
390 int res
, resmatch
= -1, resempty
= -1;
391 for (res
= 3; res
>= 0; --res
) {
392 if (bs
->hw_cfile_addr
[res
] == -1)
394 else if (bs
->hw_cfile_addr
[res
] == sel
&&
395 bs
->hw_cfile_elem
[res
] == chan
)
399 return 0; // Read for this scalar element already reserved, nothing to do here.
400 else if (resempty
!= -1) {
401 bs
->hw_cfile_addr
[resempty
] = sel
;
402 bs
->hw_cfile_elem
[resempty
] = chan
;
404 // All cfile read ports are used, cannot reference vector element
410 static int is_gpr(unsigned sel
)
412 return (sel
>= 0 && sel
<= 127);
415 static int is_cfile(unsigned sel
)
417 return (sel
> 255 && sel
< 512);
420 static int is_const(int sel
)
422 return is_cfile(sel
) ||
423 (sel
>= V_SQ_ALU_SRC_0
&&
424 sel
<= V_SQ_ALU_SRC_LITERAL
);
427 static int check_vector(struct r600_bc_alu
*alu
, struct alu_bank_swizzle
*bs
, int bank_swizzle
)
429 int r
, src
, num_src
, sel
, elem
, cycle
;
431 num_src
= r600_bc_get_num_operands(alu
);
432 for (src
= 0; src
< num_src
; src
++) {
433 sel
= alu
->src
[src
].sel
;
434 elem
= alu
->src
[src
].chan
;
436 cycle
= cycle_for_bank_swizzle_vec
[bank_swizzle
][src
];
437 if (src
== 1 && sel
== alu
->src
[0].sel
&& elem
== alu
->src
[0].chan
)
438 // Nothing to do; special-case optimization,
439 // second source uses first source’s reservation
442 r
= reserve_gpr(bs
, sel
, elem
, cycle
);
446 } else if (is_cfile(sel
)) {
447 r
= reserve_cfile(bs
, sel
, elem
);
451 // No restrictions on PV, PS, literal or special constants
456 static int check_scalar(struct r600_bc_alu
*alu
, struct alu_bank_swizzle
*bs
, int bank_swizzle
)
458 int r
, src
, num_src
, const_count
, sel
, elem
, cycle
;
460 num_src
= r600_bc_get_num_operands(alu
);
461 for (const_count
= 0, src
= 0; src
< num_src
; ++src
) {
462 sel
= alu
->src
[src
].sel
;
463 elem
= alu
->src
[src
].chan
;
464 if (is_const(sel
)) { // Any constant, including literal and inline constants
465 if (const_count
>= 2)
466 // More than two references to a constant in
467 // transcendental operation.
473 r
= reserve_cfile(bs
, sel
, elem
);
478 for (src
= 0; src
< num_src
; ++src
) {
479 sel
= alu
->src
[src
].sel
;
480 elem
= alu
->src
[src
].chan
;
482 cycle
= cycle_for_bank_swizzle_scl
[bank_swizzle
][src
];
483 if (cycle
< const_count
)
484 // Cycle for GPR load conflicts with
485 // constant load in transcendental operation.
487 r
= reserve_gpr(bs
, sel
, elem
, cycle
);
491 // Constants already processed
492 // No restrictions on PV, PS
497 static int check_and_set_bank_swizzle(struct r600_bc
*bc
, struct r600_bc_alu
*alu_first
)
499 struct r600_bc_alu
*assignment
[5];
500 struct alu_bank_swizzle bs
;
504 r
= assign_alu_units(alu_first
, assignment
);
508 if(alu_first
->bank_swizzle_force
) {
509 for (i
= 0; i
< 5; i
++)
511 assignment
[i
]->bank_swizzle
= assignment
[i
]->bank_swizzle_force
;
515 // just check every possible combination of bank swizzle
516 // not very efficent, but works on the first try in most of the cases
517 for (i
= 0; i
< 4; i
++)
518 bank_swizzle
[i
] = SQ_ALU_VEC_012
;
519 bank_swizzle
[4] = SQ_ALU_SCL_210
;
520 while(bank_swizzle
[4] <= SQ_ALU_SCL_221
) {
521 init_bank_swizzle(&bs
);
522 for (i
= 0; i
< 4; i
++) {
524 r
= check_vector(assignment
[i
], &bs
, bank_swizzle
[i
]);
529 if (!r
&& assignment
[4]) {
530 r
= check_scalar(assignment
[4], &bs
, bank_swizzle
[4]);
533 for (i
= 0; i
< 5; i
++) {
535 assignment
[i
]->bank_swizzle
= bank_swizzle
[i
];
540 for (i
= 0; i
< 5; i
++) {
542 if (bank_swizzle
[i
] <= SQ_ALU_VEC_210
)
545 bank_swizzle
[i
] = SQ_ALU_VEC_012
;
549 // couldn't find a working swizzle
553 static int replace_gpr_with_pv_ps(struct r600_bc_alu
*alu_first
, struct r600_bc_alu
*alu_prev
)
555 struct r600_bc_alu
*slots
[5];
557 int i
, j
, r
, src
, num_src
;
559 r
= assign_alu_units(alu_prev
, slots
);
563 for (i
= 0; i
< 5; ++i
) {
564 if(slots
[i
] && slots
[i
]->dst
.write
&& !slots
[i
]->dst
.rel
) {
565 gpr
[i
] = slots
[i
]->dst
.sel
;
566 if (is_alu_reduction_inst(slots
[i
]))
569 chan
[i
] = slots
[i
]->dst
.chan
;
575 r
= assign_alu_units(alu_first
, slots
);
579 for (i
= 0; i
< 5; ++i
) {
580 struct r600_bc_alu
*alu
= slots
[i
];
584 num_src
= r600_bc_get_num_operands(alu
);
585 for (src
= 0; src
< num_src
; ++src
) {
586 if (!is_gpr(alu
->src
[src
].sel
) || alu
->src
[src
].rel
)
589 if (alu
->src
[src
].sel
== gpr
[4] &&
590 alu
->src
[src
].chan
== chan
[4]) {
591 alu
->src
[src
].sel
= V_SQ_ALU_SRC_PS
;
592 alu
->src
[src
].chan
= 0;
596 for (j
= 0; j
< 4; ++j
) {
597 if (alu
->src
[src
].sel
== gpr
[j
] &&
598 alu
->src
[src
].chan
== j
) {
599 alu
->src
[src
].sel
= V_SQ_ALU_SRC_PV
;
600 alu
->src
[src
].chan
= chan
[j
];
610 int r600_bc_add_alu_type(struct r600_bc
*bc
, const struct r600_bc_alu
*alu
, int type
)
612 struct r600_bc_alu
*nalu
= r600_bc_alu();
613 struct r600_bc_alu
*lalu
;
618 memcpy(nalu
, alu
, sizeof(struct r600_bc_alu
));
621 if (bc
->cf_last
!= NULL
&& bc
->cf_last
->inst
!= (type
<< 3)) {
622 /* check if we could add it anyway */
623 if (bc
->cf_last
->inst
== (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
<< 3) &&
624 type
== V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
) {
625 LIST_FOR_EACH_ENTRY(alu
, &bc
->cf_last
->alu
, list
) {
626 if (alu
->predicate
) {
627 bc
->force_add_cf
= 1;
632 bc
->force_add_cf
= 1;
635 /* cf can contains only alu or only vtx or only tex */
636 if (bc
->cf_last
== NULL
|| bc
->force_add_cf
) {
637 r
= r600_bc_add_cf(bc
);
643 bc
->cf_last
->inst
= (type
<< 3);
644 if (!bc
->cf_last
->curr_bs_head
) {
645 bc
->cf_last
->curr_bs_head
= nalu
;
647 /* at most 128 slots, one add alu can add 4 slots + 4 constants(2 slots)
649 if (alu
->last
&& (bc
->cf_last
->ndw
>> 1) >= 120) {
650 bc
->force_add_cf
= 1;
652 /* number of gpr == the last gpr used in any alu */
653 for (i
= 0; i
< 3; i
++) {
654 if (alu
->src
[i
].sel
>= bc
->ngpr
&& alu
->src
[i
].sel
< 128) {
655 bc
->ngpr
= alu
->src
[i
].sel
+ 1;
657 /* compute how many literal are needed
658 * either 2 or 4 literals
660 if (alu
->src
[i
].sel
== 253) {
661 if (((alu
->src
[i
].chan
+ 2) & 0x6) > nalu
->nliteral
) {
662 nalu
->nliteral
= (alu
->src
[i
].chan
+ 2) & 0x6;
666 if (!LIST_IS_EMPTY(&bc
->cf_last
->alu
)) {
667 lalu
= LIST_ENTRY(struct r600_bc_alu
, bc
->cf_last
->alu
.prev
, list
);
668 if (!lalu
->last
&& lalu
->nliteral
> nalu
->nliteral
) {
669 nalu
->nliteral
= lalu
->nliteral
;
672 if (alu
->dst
.sel
>= bc
->ngpr
) {
673 bc
->ngpr
= alu
->dst
.sel
+ 1;
675 LIST_ADDTAIL(&nalu
->list
, &bc
->cf_last
->alu
);
676 /* each alu use 2 dwords */
677 bc
->cf_last
->ndw
+= 2;
680 bc
->cf_last
->kcache0_mode
= 2;
682 /* process cur ALU instructions for bank swizzle */
684 if (bc
->cf_last
->prev_bs_head
)
685 replace_gpr_with_pv_ps(bc
->cf_last
->curr_bs_head
, bc
->cf_last
->prev_bs_head
);
686 r
= check_and_set_bank_swizzle(bc
, bc
->cf_last
->curr_bs_head
);
689 bc
->cf_last
->prev_bs_head
= bc
->cf_last
->curr_bs_head
;
690 bc
->cf_last
->curr_bs_head
= NULL
;
695 int r600_bc_add_alu(struct r600_bc
*bc
, const struct r600_bc_alu
*alu
)
697 return r600_bc_add_alu_type(bc
, alu
, BC_INST(bc
, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
));
700 int r600_bc_add_literal(struct r600_bc
*bc
, const u32
*value
)
702 struct r600_bc_alu
*alu
;
704 if (bc
->cf_last
== NULL
) {
707 if (bc
->cf_last
->inst
== V_SQ_CF_WORD1_SQ_CF_INST_TEX
) {
711 if (bc
->cf_last
->inst
== V_SQ_CF_WORD1_SQ_CF_INST_JUMP
||
712 bc
->cf_last
->inst
== V_SQ_CF_WORD1_SQ_CF_INST_ELSE
||
713 bc
->cf_last
->inst
== V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL
||
714 bc
->cf_last
->inst
== V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
||
715 bc
->cf_last
->inst
== V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
||
716 bc
->cf_last
->inst
== V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
||
717 bc
->cf_last
->inst
== V_SQ_CF_WORD1_SQ_CF_INST_POP
) {
721 if (((bc
->cf_last
->inst
!= (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
<< 3)) &&
722 (bc
->cf_last
->inst
!= (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
<< 3)) &&
723 (bc
->cf_last
->inst
!= (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER
<< 3)) &&
724 (bc
->cf_last
->inst
!= (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
<< 3))) ||
725 LIST_IS_EMPTY(&bc
->cf_last
->alu
)) {
726 R600_ERR("last CF is not ALU (%p)\n", bc
->cf_last
);
729 alu
= LIST_ENTRY(struct r600_bc_alu
, bc
->cf_last
->alu
.prev
, list
);
730 if (!alu
->last
|| !alu
->nliteral
|| alu
->literal_added
) {
733 memcpy(alu
->value
, value
, 4 * 4);
734 bc
->cf_last
->ndw
+= alu
->nliteral
;
735 bc
->ndw
+= alu
->nliteral
;
736 alu
->literal_added
= 1;
740 int r600_bc_add_vtx(struct r600_bc
*bc
, const struct r600_bc_vtx
*vtx
)
742 struct r600_bc_vtx
*nvtx
= r600_bc_vtx();
747 memcpy(nvtx
, vtx
, sizeof(struct r600_bc_vtx
));
749 /* cf can contains only alu or only vtx or only tex */
750 if (bc
->cf_last
== NULL
||
751 (bc
->cf_last
->inst
!= V_SQ_CF_WORD1_SQ_CF_INST_VTX
&&
752 bc
->cf_last
->inst
!= V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC
) ||
754 r
= r600_bc_add_cf(bc
);
759 bc
->cf_last
->inst
= V_SQ_CF_WORD1_SQ_CF_INST_VTX
;
761 LIST_ADDTAIL(&nvtx
->list
, &bc
->cf_last
->vtx
);
762 /* each fetch use 4 dwords */
763 bc
->cf_last
->ndw
+= 4;
765 if ((bc
->cf_last
->ndw
/ 4) > 7)
766 bc
->force_add_cf
= 1;
770 int r600_bc_add_tex(struct r600_bc
*bc
, const struct r600_bc_tex
*tex
)
772 struct r600_bc_tex
*ntex
= r600_bc_tex();
777 memcpy(ntex
, tex
, sizeof(struct r600_bc_tex
));
779 /* cf can contains only alu or only vtx or only tex */
780 if (bc
->cf_last
== NULL
||
781 bc
->cf_last
->inst
!= V_SQ_CF_WORD1_SQ_CF_INST_TEX
||
783 r
= r600_bc_add_cf(bc
);
788 bc
->cf_last
->inst
= V_SQ_CF_WORD1_SQ_CF_INST_TEX
;
790 LIST_ADDTAIL(&ntex
->list
, &bc
->cf_last
->tex
);
791 /* each texture fetch use 4 dwords */
792 bc
->cf_last
->ndw
+= 4;
794 if ((bc
->cf_last
->ndw
/ 4) > 7)
795 bc
->force_add_cf
= 1;
799 int r600_bc_add_cfinst(struct r600_bc
*bc
, int inst
)
802 r
= r600_bc_add_cf(bc
);
806 bc
->cf_last
->cond
= V_SQ_CF_COND_ACTIVE
;
807 bc
->cf_last
->inst
= inst
;
811 /* common to all 3 families */
812 static int r600_bc_vtx_build(struct r600_bc
*bc
, struct r600_bc_vtx
*vtx
, unsigned id
)
814 unsigned fetch_resource_start
= 0;
816 /* check if we are fetch shader */
817 /* fetch shader can also access vertex resource,
818 * first fetch shader resource is at 160
820 if (bc
->type
== -1) {
821 switch (bc
->chiprev
) {
826 fetch_resource_start
= 160;
829 case CHIPREV_EVERGREEN
:
830 fetch_resource_start
= 0;
833 fprintf(stderr
, "%s:%s:%d unknown chiprev %d\n",
834 __FILE__
, __func__
, __LINE__
, bc
->chiprev
);
838 bc
->bytecode
[id
++] = S_SQ_VTX_WORD0_BUFFER_ID(vtx
->buffer_id
+ fetch_resource_start
) |
839 S_SQ_VTX_WORD0_SRC_GPR(vtx
->src_gpr
) |
840 S_SQ_VTX_WORD0_SRC_SEL_X(vtx
->src_sel_x
) |
841 S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx
->mega_fetch_count
);
842 bc
->bytecode
[id
++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx
->dst_sel_x
) |
843 S_SQ_VTX_WORD1_DST_SEL_Y(vtx
->dst_sel_y
) |
844 S_SQ_VTX_WORD1_DST_SEL_Z(vtx
->dst_sel_z
) |
845 S_SQ_VTX_WORD1_DST_SEL_W(vtx
->dst_sel_w
) |
846 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx
->use_const_fields
) |
847 S_SQ_VTX_WORD1_DATA_FORMAT(vtx
->data_format
) |
848 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx
->num_format_all
) |
849 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx
->format_comp_all
) |
850 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx
->srf_mode_all
) |
851 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx
->dst_gpr
);
852 bc
->bytecode
[id
++] = S_SQ_VTX_WORD2_MEGA_FETCH(1);
853 bc
->bytecode
[id
++] = 0;
857 /* common to all 3 families */
858 static int r600_bc_tex_build(struct r600_bc
*bc
, struct r600_bc_tex
*tex
, unsigned id
)
860 bc
->bytecode
[id
++] = S_SQ_TEX_WORD0_TEX_INST(tex
->inst
) |
861 S_SQ_TEX_WORD0_RESOURCE_ID(tex
->resource_id
) |
862 S_SQ_TEX_WORD0_SRC_GPR(tex
->src_gpr
) |
863 S_SQ_TEX_WORD0_SRC_REL(tex
->src_rel
);
864 bc
->bytecode
[id
++] = S_SQ_TEX_WORD1_DST_GPR(tex
->dst_gpr
) |
865 S_SQ_TEX_WORD1_DST_REL(tex
->dst_rel
) |
866 S_SQ_TEX_WORD1_DST_SEL_X(tex
->dst_sel_x
) |
867 S_SQ_TEX_WORD1_DST_SEL_Y(tex
->dst_sel_y
) |
868 S_SQ_TEX_WORD1_DST_SEL_Z(tex
->dst_sel_z
) |
869 S_SQ_TEX_WORD1_DST_SEL_W(tex
->dst_sel_w
) |
870 S_SQ_TEX_WORD1_LOD_BIAS(tex
->lod_bias
) |
871 S_SQ_TEX_WORD1_COORD_TYPE_X(tex
->coord_type_x
) |
872 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex
->coord_type_y
) |
873 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex
->coord_type_z
) |
874 S_SQ_TEX_WORD1_COORD_TYPE_W(tex
->coord_type_w
);
875 bc
->bytecode
[id
++] = S_SQ_TEX_WORD2_OFFSET_X(tex
->offset_x
) |
876 S_SQ_TEX_WORD2_OFFSET_Y(tex
->offset_y
) |
877 S_SQ_TEX_WORD2_OFFSET_Z(tex
->offset_z
) |
878 S_SQ_TEX_WORD2_SAMPLER_ID(tex
->sampler_id
) |
879 S_SQ_TEX_WORD2_SRC_SEL_X(tex
->src_sel_x
) |
880 S_SQ_TEX_WORD2_SRC_SEL_Y(tex
->src_sel_y
) |
881 S_SQ_TEX_WORD2_SRC_SEL_Z(tex
->src_sel_z
) |
882 S_SQ_TEX_WORD2_SRC_SEL_W(tex
->src_sel_w
);
883 bc
->bytecode
[id
++] = 0;
887 /* r600 only, r700/eg bits in r700_asm.c */
888 static int r600_bc_alu_build(struct r600_bc
*bc
, struct r600_bc_alu
*alu
, unsigned id
)
892 /* don't replace gpr by pv or ps for destination register */
893 bc
->bytecode
[id
++] = S_SQ_ALU_WORD0_SRC0_SEL(alu
->src
[0].sel
) |
894 S_SQ_ALU_WORD0_SRC0_REL(alu
->src
[0].rel
) |
895 S_SQ_ALU_WORD0_SRC0_CHAN(alu
->src
[0].chan
) |
896 S_SQ_ALU_WORD0_SRC0_NEG(alu
->src
[0].neg
) |
897 S_SQ_ALU_WORD0_SRC1_SEL(alu
->src
[1].sel
) |
898 S_SQ_ALU_WORD0_SRC1_REL(alu
->src
[1].rel
) |
899 S_SQ_ALU_WORD0_SRC1_CHAN(alu
->src
[1].chan
) |
900 S_SQ_ALU_WORD0_SRC1_NEG(alu
->src
[1].neg
) |
901 S_SQ_ALU_WORD0_LAST(alu
->last
);
904 bc
->bytecode
[id
++] = S_SQ_ALU_WORD1_DST_GPR(alu
->dst
.sel
) |
905 S_SQ_ALU_WORD1_DST_CHAN(alu
->dst
.chan
) |
906 S_SQ_ALU_WORD1_DST_REL(alu
->dst
.rel
) |
907 S_SQ_ALU_WORD1_CLAMP(alu
->dst
.clamp
) |
908 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu
->src
[2].sel
) |
909 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu
->src
[2].rel
) |
910 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu
->src
[2].chan
) |
911 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu
->src
[2].neg
) |
912 S_SQ_ALU_WORD1_OP3_ALU_INST(alu
->inst
) |
913 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu
->bank_swizzle
);
915 bc
->bytecode
[id
++] = S_SQ_ALU_WORD1_DST_GPR(alu
->dst
.sel
) |
916 S_SQ_ALU_WORD1_DST_CHAN(alu
->dst
.chan
) |
917 S_SQ_ALU_WORD1_DST_REL(alu
->dst
.rel
) |
918 S_SQ_ALU_WORD1_CLAMP(alu
->dst
.clamp
) |
919 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu
->src
[0].abs
) |
920 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu
->src
[1].abs
) |
921 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu
->dst
.write
) |
922 S_SQ_ALU_WORD1_OP2_OMOD(alu
->omod
) |
923 S_SQ_ALU_WORD1_OP2_ALU_INST(alu
->inst
) |
924 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu
->bank_swizzle
) |
925 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu
->predicate
) |
926 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu
->predicate
);
929 if (alu
->nliteral
&& !alu
->literal_added
) {
930 R600_ERR("Bug in ALU processing for instruction 0x%08x, literal not added correctly\n", alu
->inst
);
932 for (i
= 0; i
< alu
->nliteral
; i
++) {
933 bc
->bytecode
[id
++] = alu
->value
[i
];
939 /* common for r600/r700 - eg in eg_asm.c */
940 static int r600_bc_cf_build(struct r600_bc
*bc
, struct r600_bc_cf
*cf
)
942 unsigned id
= cf
->id
;
945 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
<< 3):
946 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
<< 3):
947 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER
<< 3):
948 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
<< 3):
949 bc
->bytecode
[id
++] = S_SQ_CF_ALU_WORD0_ADDR(cf
->addr
>> 1) |
950 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf
->kcache0_mode
) |
951 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf
->kcache0_bank
) |
952 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf
->kcache1_bank
);
954 bc
->bytecode
[id
++] = S_SQ_CF_ALU_WORD1_CF_INST(cf
->inst
>> 3) |
955 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf
->kcache1_mode
) |
956 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf
->kcache0_addr
) |
957 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf
->kcache1_addr
) |
958 S_SQ_CF_ALU_WORD1_BARRIER(1) |
959 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc
->chiprev
== CHIPREV_R600
? cf
->r6xx_uses_waterfall
: 0) |
960 S_SQ_CF_ALU_WORD1_COUNT((cf
->ndw
/ 2) - 1);
962 case V_SQ_CF_WORD1_SQ_CF_INST_TEX
:
963 case V_SQ_CF_WORD1_SQ_CF_INST_VTX
:
964 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC
:
965 bc
->bytecode
[id
++] = S_SQ_CF_WORD0_ADDR(cf
->addr
>> 1);
966 bc
->bytecode
[id
++] = S_SQ_CF_WORD1_CF_INST(cf
->inst
) |
967 S_SQ_CF_WORD1_BARRIER(1) |
968 S_SQ_CF_WORD1_COUNT((cf
->ndw
/ 4) - 1);
970 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
:
971 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
:
972 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf
->output
.gpr
) |
973 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf
->output
.elem_size
) |
974 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf
->output
.array_base
) |
975 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf
->output
.type
);
976 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf
->output
.swizzle_x
) |
977 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf
->output
.swizzle_y
) |
978 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf
->output
.swizzle_z
) |
979 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf
->output
.swizzle_w
) |
980 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf
->output
.barrier
) |
981 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf
->output
.inst
) |
982 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf
->output
.end_of_program
);
984 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP
:
985 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE
:
986 case V_SQ_CF_WORD1_SQ_CF_INST_POP
:
987 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL
:
988 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
:
989 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
:
990 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
:
991 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
:
992 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN
:
993 bc
->bytecode
[id
++] = S_SQ_CF_WORD0_ADDR(cf
->cf_addr
>> 1);
994 bc
->bytecode
[id
++] = S_SQ_CF_WORD1_CF_INST(cf
->inst
) |
995 S_SQ_CF_WORD1_BARRIER(1) |
996 S_SQ_CF_WORD1_COND(cf
->cond
) |
997 S_SQ_CF_WORD1_POP_COUNT(cf
->pop_count
);
1001 R600_ERR("unsupported CF instruction (0x%X)\n", cf
->inst
);
1007 int r600_bc_build(struct r600_bc
*bc
)
1009 struct r600_bc_cf
*cf
;
1010 struct r600_bc_alu
*alu
;
1011 struct r600_bc_vtx
*vtx
;
1012 struct r600_bc_tex
*tex
;
1016 if (bc
->callstack
[0].max
> 0)
1017 bc
->nstack
= ((bc
->callstack
[0].max
+ 3) >> 2) + 2;
1018 if (bc
->type
== TGSI_PROCESSOR_VERTEX
&& !bc
->nstack
) {
1022 /* first path compute addr of each CF block */
1023 /* addr start after all the CF instructions */
1024 addr
= bc
->cf_last
->id
+ 2;
1025 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
1027 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
<< 3):
1028 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
<< 3):
1029 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER
<< 3):
1030 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
<< 3):
1032 case V_SQ_CF_WORD1_SQ_CF_INST_TEX
:
1033 case V_SQ_CF_WORD1_SQ_CF_INST_VTX
:
1034 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC
:
1035 /* fetch node need to be 16 bytes aligned*/
1037 addr
&= 0xFFFFFFFCUL
;
1039 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
:
1040 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
:
1041 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
:
1042 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
:
1044 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP
:
1045 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE
:
1046 case V_SQ_CF_WORD1_SQ_CF_INST_POP
:
1047 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL
:
1048 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
:
1049 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
:
1050 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
:
1051 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
:
1052 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN
:
1055 R600_ERR("unsupported CF instruction (0x%X)\n", cf
->inst
);
1060 bc
->ndw
= cf
->addr
+ cf
->ndw
;
1063 bc
->bytecode
= calloc(1, bc
->ndw
* 4);
1064 if (bc
->bytecode
== NULL
)
1066 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
1068 if (bc
->chiprev
== CHIPREV_EVERGREEN
)
1069 r
= eg_bc_cf_build(bc
, cf
);
1071 r
= r600_bc_cf_build(bc
, cf
);
1075 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
<< 3):
1076 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
<< 3):
1077 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER
<< 3):
1078 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
<< 3):
1079 LIST_FOR_EACH_ENTRY(alu
, &cf
->alu
, list
) {
1080 switch(bc
->chiprev
) {
1082 r
= r600_bc_alu_build(bc
, alu
, addr
);
1085 case CHIPREV_EVERGREEN
: /* eg alu is same encoding as r700 */
1086 r
= r700_bc_alu_build(bc
, alu
, addr
);
1089 R600_ERR("unknown family %d\n", bc
->family
);
1096 addr
+= alu
->nliteral
;
1100 case V_SQ_CF_WORD1_SQ_CF_INST_VTX
:
1101 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC
:
1102 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
1103 r
= r600_bc_vtx_build(bc
, vtx
, addr
);
1109 case V_SQ_CF_WORD1_SQ_CF_INST_TEX
:
1110 LIST_FOR_EACH_ENTRY(tex
, &cf
->tex
, list
) {
1111 r
= r600_bc_tex_build(bc
, tex
, addr
);
1117 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
:
1118 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
:
1119 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
:
1120 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
:
1121 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL
:
1122 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
:
1123 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
:
1124 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
:
1125 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP
:
1126 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE
:
1127 case V_SQ_CF_WORD1_SQ_CF_INST_POP
:
1128 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
:
1129 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN
:
1132 R600_ERR("unsupported CF instruction (0x%X)\n", cf
->inst
);
1139 void r600_bc_clear(struct r600_bc
*bc
)
1141 struct r600_bc_cf
*cf
= NULL
, *next_cf
;
1144 bc
->bytecode
= NULL
;
1146 LIST_FOR_EACH_ENTRY_SAFE(cf
, next_cf
, &bc
->cf
, list
) {
1147 struct r600_bc_alu
*alu
= NULL
, *next_alu
;
1148 struct r600_bc_tex
*tex
= NULL
, *next_tex
;
1149 struct r600_bc_tex
*vtx
= NULL
, *next_vtx
;
1151 LIST_FOR_EACH_ENTRY_SAFE(alu
, next_alu
, &cf
->alu
, list
) {
1155 LIST_INITHEAD(&cf
->alu
);
1157 LIST_FOR_EACH_ENTRY_SAFE(tex
, next_tex
, &cf
->tex
, list
) {
1161 LIST_INITHEAD(&cf
->tex
);
1163 LIST_FOR_EACH_ENTRY_SAFE(vtx
, next_vtx
, &cf
->vtx
, list
) {
1167 LIST_INITHEAD(&cf
->vtx
);
1172 LIST_INITHEAD(&cf
->list
);
1175 void r600_bc_dump(struct r600_bc
*bc
)
1177 struct r600_bc_cf
*cf
;
1178 struct r600_bc_alu
*alu
;
1179 struct r600_bc_vtx
*vtx
;
1180 struct r600_bc_tex
*tex
;
1185 switch (bc
->chiprev
) {
1197 fprintf(stderr
, "bytecode %d dw -----------------------\n", bc
->ndw
);
1198 fprintf(stderr
, " %c\n", chip
);
1200 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
1204 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
<< 3):
1205 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
<< 3):
1206 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER
<< 3):
1207 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
<< 3):
1208 fprintf(stderr
, "%04d %08X ALU ", id
, bc
->bytecode
[id
]);
1209 fprintf(stderr
, "ADDR:%d ", cf
->addr
);
1210 fprintf(stderr
, "KCACHE_MODE0:%X ", cf
->kcache0_mode
);
1211 fprintf(stderr
, "KCACHE_BANK0:%X ", cf
->kcache0_bank
);
1212 fprintf(stderr
, "KCACHE_BANK1:%X\n", cf
->kcache1_bank
);
1214 fprintf(stderr
, "%04d %08X ALU ", id
, bc
->bytecode
[id
]);
1215 fprintf(stderr
, "INST:%d ", cf
->inst
);
1216 fprintf(stderr
, "KCACHE_MODE1:%X ", cf
->kcache1_mode
);
1217 fprintf(stderr
, "KCACHE_ADDR0:%X ", cf
->kcache0_addr
);
1218 fprintf(stderr
, "KCACHE_ADDR1:%X ", cf
->kcache1_addr
);
1219 fprintf(stderr
, "COUNT:%d\n", cf
->ndw
/ 2);
1221 case V_SQ_CF_WORD1_SQ_CF_INST_TEX
:
1222 case V_SQ_CF_WORD1_SQ_CF_INST_VTX
:
1223 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC
:
1224 fprintf(stderr
, "%04d %08X TEX/VTX ", id
, bc
->bytecode
[id
]);
1225 fprintf(stderr
, "ADDR:%d\n", cf
->addr
);
1227 fprintf(stderr
, "%04d %08X TEX/VTX ", id
, bc
->bytecode
[id
]);
1228 fprintf(stderr
, "INST:%d ", cf
->inst
);
1229 fprintf(stderr
, "COUNT:%d\n", cf
->ndw
/ 4);
1231 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
:
1232 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
:
1233 fprintf(stderr
, "%04d %08X EXPORT ", id
, bc
->bytecode
[id
]);
1234 fprintf(stderr
, "GPR:%X ", cf
->output
.gpr
);
1235 fprintf(stderr
, "ELEM_SIZE:%X ", cf
->output
.elem_size
);
1236 fprintf(stderr
, "ARRAY_BASE:%X ", cf
->output
.array_base
);
1237 fprintf(stderr
, "TYPE:%X\n", cf
->output
.type
);
1239 fprintf(stderr
, "%04d %08X EXPORT ", id
, bc
->bytecode
[id
]);
1240 fprintf(stderr
, "SWIZ_X:%X ", cf
->output
.swizzle_x
);
1241 fprintf(stderr
, "SWIZ_Y:%X ", cf
->output
.swizzle_y
);
1242 fprintf(stderr
, "SWIZ_Z:%X ", cf
->output
.swizzle_z
);
1243 fprintf(stderr
, "SWIZ_W:%X ", cf
->output
.swizzle_w
);
1244 fprintf(stderr
, "SWIZ_W:%X ", cf
->output
.swizzle_w
);
1245 fprintf(stderr
, "BARRIER:%X ", cf
->output
.barrier
);
1246 fprintf(stderr
, "INST:%d ", cf
->output
.inst
);
1247 fprintf(stderr
, "EOP:%X\n", cf
->output
.end_of_program
);
1249 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP
:
1250 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE
:
1251 case V_SQ_CF_WORD1_SQ_CF_INST_POP
:
1252 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL
:
1253 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
:
1254 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
:
1255 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
:
1256 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
:
1257 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN
:
1258 fprintf(stderr
, "%04d %08X CF ", id
, bc
->bytecode
[id
]);
1259 fprintf(stderr
, "ADDR:%d\n", cf
->cf_addr
);
1261 fprintf(stderr
, "%04d %08X CF ", id
, bc
->bytecode
[id
]);
1262 fprintf(stderr
, "INST:%d ", cf
->inst
);
1263 fprintf(stderr
, "COND:%X ", cf
->cond
);
1264 fprintf(stderr
, "POP_COUNT:%X\n", cf
->pop_count
);
1269 LIST_FOR_EACH_ENTRY(alu
, &cf
->alu
, list
) {
1270 fprintf(stderr
, "%04d %08X ", id
, bc
->bytecode
[id
]);
1271 fprintf(stderr
, "SRC0(SEL:%d ", alu
->src
[0].sel
);
1272 fprintf(stderr
, "REL:%d ", alu
->src
[0].rel
);
1273 fprintf(stderr
, "CHAN:%d ", alu
->src
[0].chan
);
1274 fprintf(stderr
, "NEG:%d) ", alu
->src
[0].neg
);
1275 fprintf(stderr
, "SRC1(SEL:%d ", alu
->src
[1].sel
);
1276 fprintf(stderr
, "REL:%d ", alu
->src
[1].rel
);
1277 fprintf(stderr
, "CHAN:%d ", alu
->src
[1].chan
);
1278 fprintf(stderr
, "NEG:%d) ", alu
->src
[1].neg
);
1279 fprintf(stderr
, "LAST:%d)\n", alu
->last
);
1281 fprintf(stderr
, "%04d %08X %c ", id
, bc
->bytecode
[id
], alu
->last
? '*' : ' ');
1282 fprintf(stderr
, "INST:%d ", alu
->inst
);
1283 fprintf(stderr
, "DST(SEL:%d ", alu
->dst
.sel
);
1284 fprintf(stderr
, "CHAN:%d ", alu
->dst
.chan
);
1285 fprintf(stderr
, "REL:%d ", alu
->dst
.rel
);
1286 fprintf(stderr
, "CLAMP:%d) ", alu
->dst
.clamp
);
1287 fprintf(stderr
, "BANK_SWIZZLE:%d ", alu
->bank_swizzle
);
1289 fprintf(stderr
, "SRC2(SEL:%d ", alu
->src
[2].sel
);
1290 fprintf(stderr
, "REL:%d ", alu
->src
[2].rel
);
1291 fprintf(stderr
, "CHAN:%d ", alu
->src
[2].chan
);
1292 fprintf(stderr
, "NEG:%d)\n", alu
->src
[2].neg
);
1294 fprintf(stderr
, "SRC0_ABS:%d ", alu
->src
[0].abs
);
1295 fprintf(stderr
, "SRC1_ABS:%d ", alu
->src
[1].abs
);
1296 fprintf(stderr
, "WRITE_MASK:%d ", alu
->dst
.write
);
1297 fprintf(stderr
, "OMOD:%d ", alu
->omod
);
1298 fprintf(stderr
, "EXECUTE_MASK:%d ", alu
->predicate
);
1299 fprintf(stderr
, "UPDATE_PRED:%d\n", alu
->predicate
);
1304 for (i
= 0; i
< alu
->nliteral
; i
++, id
++) {
1305 float *f
= (float*)(bc
->bytecode
+ id
);
1306 fprintf(stderr
, "%04d %08X %f\n", id
, bc
->bytecode
[id
], *f
);
1311 LIST_FOR_EACH_ENTRY(tex
, &cf
->tex
, list
) {
1315 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
1320 fprintf(stderr
, "--------------------------------------\n");
1323 void r600_cf_vtx(struct r600_vertex_element
*ve
, u32
*bytecode
, unsigned count
)
1325 struct r600_pipe_state
*rstate
;
1329 bytecode
[i
++] = S_SQ_CF_WORD0_ADDR(8 >> 1);
1330 bytecode
[i
++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX
) |
1331 S_SQ_CF_WORD1_BARRIER(1) |
1332 S_SQ_CF_WORD1_COUNT(8 - 1);
1333 bytecode
[i
++] = S_SQ_CF_WORD0_ADDR(40 >> 1);
1334 bytecode
[i
++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX
) |
1335 S_SQ_CF_WORD1_BARRIER(1) |
1336 S_SQ_CF_WORD1_COUNT(count
- 8 - 1);
1338 bytecode
[i
++] = S_SQ_CF_WORD0_ADDR(8 >> 1);
1339 bytecode
[i
++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX
) |
1340 S_SQ_CF_WORD1_BARRIER(1) |
1341 S_SQ_CF_WORD1_COUNT(count
- 1);
1343 bytecode
[i
++] = S_SQ_CF_WORD0_ADDR(0);
1344 bytecode
[i
++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_RETURN
) |
1345 S_SQ_CF_WORD1_BARRIER(1);
1347 rstate
= &ve
->rstate
;
1348 rstate
->id
= R600_PIPE_STATE_FETCH_SHADER
;
1350 r600_pipe_state_add_reg(rstate
, R_0288A4_SQ_PGM_RESOURCES_FS
,
1351 0x00000000, 0xFFFFFFFF, NULL
);
1352 r600_pipe_state_add_reg(rstate
, R_0288DC_SQ_PGM_CF_OFFSET_FS
,
1353 0x00000000, 0xFFFFFFFF, NULL
);
1354 r600_pipe_state_add_reg(rstate
, R_028894_SQ_PGM_START_FS
,
1355 r600_bo_offset(ve
->fetch_shader
) >> 8,
1356 0xFFFFFFFF, ve
->fetch_shader
);
1359 void r600_cf_vtx_tc(struct r600_vertex_element
*ve
, u32
*bytecode
, unsigned count
)
1361 struct r600_pipe_state
*rstate
;
1365 bytecode
[i
++] = S_SQ_CF_WORD0_ADDR(8 >> 1);
1366 bytecode
[i
++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC
) |
1367 S_SQ_CF_WORD1_BARRIER(1) |
1368 S_SQ_CF_WORD1_COUNT(8 - 1);
1369 bytecode
[i
++] = S_SQ_CF_WORD0_ADDR(40 >> 1);
1370 bytecode
[i
++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC
) |
1371 S_SQ_CF_WORD1_BARRIER(1) |
1372 S_SQ_CF_WORD1_COUNT((count
- 8) - 1);
1374 bytecode
[i
++] = S_SQ_CF_WORD0_ADDR(8 >> 1);
1375 bytecode
[i
++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC
) |
1376 S_SQ_CF_WORD1_BARRIER(1) |
1377 S_SQ_CF_WORD1_COUNT(count
- 1);
1379 bytecode
[i
++] = S_SQ_CF_WORD0_ADDR(0);
1380 bytecode
[i
++] = S_SQ_CF_WORD1_CF_INST(V_SQ_CF_WORD1_SQ_CF_INST_RETURN
) |
1381 S_SQ_CF_WORD1_BARRIER(1);
1383 rstate
= &ve
->rstate
;
1384 rstate
->id
= R600_PIPE_STATE_FETCH_SHADER
;
1386 r600_pipe_state_add_reg(rstate
, R_0288A4_SQ_PGM_RESOURCES_FS
,
1387 0x00000000, 0xFFFFFFFF, NULL
);
1388 r600_pipe_state_add_reg(rstate
, R_0288DC_SQ_PGM_CF_OFFSET_FS
,
1389 0x00000000, 0xFFFFFFFF, NULL
);
1390 r600_pipe_state_add_reg(rstate
, R_028894_SQ_PGM_START_FS
,
1391 r600_bo_offset(ve
->fetch_shader
) >> 8,
1392 0xFFFFFFFF, ve
->fetch_shader
);
1395 static void r600_vertex_data_type(enum pipe_format pformat
, unsigned *format
,
1396 unsigned *num_format
, unsigned *format_comp
)
1398 const struct util_format_description
*desc
;
1405 desc
= util_format_description(pformat
);
1406 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
) {
1410 /* Find the first non-VOID channel. */
1411 for (i
= 0; i
< 4; i
++) {
1412 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1417 switch (desc
->channel
[i
].type
) {
1418 /* Half-floats, floats, doubles */
1419 case UTIL_FORMAT_TYPE_FLOAT
:
1420 switch (desc
->channel
[i
].size
) {
1422 switch (desc
->nr_channels
) {
1424 *format
= FMT_16_FLOAT
;
1427 *format
= FMT_16_16_FLOAT
;
1430 *format
= FMT_16_16_16_FLOAT
;
1433 *format
= FMT_16_16_16_16_FLOAT
;
1438 switch (desc
->nr_channels
) {
1440 *format
= FMT_32_FLOAT
;
1443 *format
= FMT_32_32_FLOAT
;
1446 *format
= FMT_32_32_32_FLOAT
;
1449 *format
= FMT_32_32_32_32_FLOAT
;
1458 case UTIL_FORMAT_TYPE_UNSIGNED
:
1460 case UTIL_FORMAT_TYPE_SIGNED
:
1461 switch (desc
->channel
[i
].size
) {
1463 switch (desc
->nr_channels
) {
1471 // *format = FMT_8_8_8; /* fails piglit draw-vertices test */
1474 *format
= FMT_8_8_8_8
;
1479 switch (desc
->nr_channels
) {
1484 *format
= FMT_16_16
;
1487 // *format = FMT_16_16_16; /* fails piglit draw-vertices test */
1490 *format
= FMT_16_16_16_16
;
1495 switch (desc
->nr_channels
) {
1500 *format
= FMT_32_32
;
1503 *format
= FMT_32_32_32
;
1506 *format
= FMT_32_32_32_32
;
1518 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1521 if (desc
->channel
[i
].normalized
) {
1528 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat
));
1531 int r600_vertex_elements_build_fetch_shader(struct r600_pipe_context
*rctx
, struct r600_vertex_element
*ve
)
1535 unsigned fetch_resource_start
= 0, format
, num_format
, format_comp
;
1536 struct pipe_vertex_element
*elements
= ve
->elements
;
1537 const struct util_format_description
*desc
;
1539 /* 2 dwords for cf aligned to 4 + 4 dwords per input */
1540 ndw
= 8 + ve
->count
* 4;
1541 ve
->fs_size
= ndw
* 4;
1543 /* use PIPE_BIND_VERTEX_BUFFER so we use the cache buffer manager */
1544 ve
->fetch_shader
= r600_bo(rctx
->radeon
, ndw
*4, 256, PIPE_BIND_VERTEX_BUFFER
, 0);
1545 if (ve
->fetch_shader
== NULL
) {
1549 bytecode
= r600_bo_map(rctx
->radeon
, ve
->fetch_shader
, 0, NULL
);
1550 if (bytecode
== NULL
) {
1551 r600_bo_reference(rctx
->radeon
, &ve
->fetch_shader
, NULL
);
1555 if (rctx
->family
>= CHIP_CEDAR
) {
1556 eg_cf_vtx(ve
, &bytecode
[0], (ndw
- 8) / 4);
1558 r600_cf_vtx(ve
, &bytecode
[0], (ndw
- 8) / 4);
1559 fetch_resource_start
= 160;
1562 /* vertex elements offset need special handling, if offset is bigger
1563 * than what we can put in fetch instruction then we need to alterate
1564 * the vertex resource offset. In such case in order to simplify code
1565 * we will bound one resource per elements. It's a worst case scenario.
1567 for (i
= 0; i
< ve
->count
; i
++) {
1568 ve
->vbuffer_offset
[i
] = C_SQ_VTX_WORD2_OFFSET
& elements
[i
].src_offset
;
1569 if (ve
->vbuffer_offset
[i
]) {
1570 ve
->vbuffer_need_offset
= 1;
1574 for (i
= 0; i
< ve
->count
; i
++) {
1575 unsigned vbuffer_index
;
1576 r600_vertex_data_type(ve
->hw_format
[i
], &format
, &num_format
, &format_comp
);
1577 desc
= util_format_description(ve
->hw_format
[i
]);
1579 R600_ERR("unknown format %d\n", ve
->hw_format
[i
]);
1580 r600_bo_reference(rctx
->radeon
, &ve
->fetch_shader
, NULL
);
1584 /* see above for vbuffer_need_offset explanation */
1585 vbuffer_index
= elements
[i
].vertex_buffer_index
;
1586 if (ve
->vbuffer_need_offset
) {
1587 bytecode
[8 + i
* 4 + 0] = S_SQ_VTX_WORD0_BUFFER_ID(i
+ fetch_resource_start
);
1589 bytecode
[8 + i
* 4 + 0] = S_SQ_VTX_WORD0_BUFFER_ID(vbuffer_index
+ fetch_resource_start
);
1591 bytecode
[8 + i
* 4 + 0] |= S_SQ_VTX_WORD0_SRC_GPR(0) |
1592 S_SQ_VTX_WORD0_SRC_SEL_X(0) |
1593 S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(0x1F);
1594 bytecode
[8 + i
* 4 + 1] = S_SQ_VTX_WORD1_DST_SEL_X(desc
->swizzle
[0]) |
1595 S_SQ_VTX_WORD1_DST_SEL_Y(desc
->swizzle
[1]) |
1596 S_SQ_VTX_WORD1_DST_SEL_Z(desc
->swizzle
[2]) |
1597 S_SQ_VTX_WORD1_DST_SEL_W(desc
->swizzle
[3]) |
1598 S_SQ_VTX_WORD1_USE_CONST_FIELDS(0) |
1599 S_SQ_VTX_WORD1_DATA_FORMAT(format
) |
1600 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(num_format
) |
1601 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(format_comp
) |
1602 S_SQ_VTX_WORD1_SRF_MODE_ALL(1) |
1603 S_SQ_VTX_WORD1_GPR_DST_GPR(i
+ 1);
1604 bytecode
[8 + i
* 4 + 2] = S_SQ_VTX_WORD2_OFFSET(elements
[i
].src_offset
) |
1605 S_SQ_VTX_WORD2_MEGA_FETCH(1);
1606 bytecode
[8 + i
* 4 + 3] = 0;
1608 r600_bo_unmap(rctx
->radeon
, ve
->fetch_shader
);