2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 #include "r600_opcodes.h"
25 #include "r600_formats.h"
26 #include "r600_shader.h"
30 #include "util/u_dump.h"
31 #include "util/u_memory.h"
32 #include "util/u_math.h"
33 #include "pipe/p_shader_tokens.h"
35 #include "sb/sb_public.h"
37 #define NUM_OF_CYCLES 3
38 #define NUM_OF_COMPONENTS 4
40 static inline bool alu_writes(struct r600_bytecode_alu
*alu
)
42 return alu
->dst
.write
|| alu
->is_op3
;
45 static inline unsigned int r600_bytecode_get_num_operands(
46 struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
48 return r600_isa_alu(alu
->op
)->src_count
;
51 int r700_bytecode_alu_build(struct r600_bytecode
*bc
,
52 struct r600_bytecode_alu
*alu
, unsigned id
);
54 static struct r600_bytecode_cf
*r600_bytecode_cf(void)
56 struct r600_bytecode_cf
*cf
= CALLOC_STRUCT(r600_bytecode_cf
);
60 LIST_INITHEAD(&cf
->list
);
61 LIST_INITHEAD(&cf
->alu
);
62 LIST_INITHEAD(&cf
->vtx
);
63 LIST_INITHEAD(&cf
->tex
);
64 LIST_INITHEAD(&cf
->gds
);
68 static struct r600_bytecode_alu
*r600_bytecode_alu(void)
70 struct r600_bytecode_alu
*alu
= CALLOC_STRUCT(r600_bytecode_alu
);
74 LIST_INITHEAD(&alu
->list
);
78 static struct r600_bytecode_vtx
*r600_bytecode_vtx(void)
80 struct r600_bytecode_vtx
*vtx
= CALLOC_STRUCT(r600_bytecode_vtx
);
84 LIST_INITHEAD(&vtx
->list
);
88 static struct r600_bytecode_tex
*r600_bytecode_tex(void)
90 struct r600_bytecode_tex
*tex
= CALLOC_STRUCT(r600_bytecode_tex
);
94 LIST_INITHEAD(&tex
->list
);
98 static struct r600_bytecode_gds
*r600_bytecode_gds(void)
100 struct r600_bytecode_gds
*gds
= CALLOC_STRUCT(r600_bytecode_gds
);
104 LIST_INITHEAD(&gds
->list
);
108 static unsigned stack_entry_size(enum radeon_family chip
) {
110 * 64: R600/RV670/RV770/Cypress/R740/Barts/Turks/Caicos/
111 * Aruba/Sumo/Sumo2/redwood/juniper
112 * 32: R630/R730/R710/Palm/Cedar
116 * Wavefront Size 16 32 48 64
117 * Columns per Row (R6xx/R7xx/R8xx only) 8 8 4 4
118 * Columns per Row (R9xx+) 8 4 4 4 */
121 /* FIXME: are some chips missing here? */
122 /* wavefront size 16 */
127 /* wavefront size 32 */
136 /* wavefront size 64 */
142 void r600_bytecode_init(struct r600_bytecode
*bc
,
143 enum chip_class chip_class
,
144 enum radeon_family family
,
145 bool has_compressed_msaa_texturing
)
147 static unsigned next_shader_id
= 0;
149 bc
->debug_id
= ++next_shader_id
;
151 if ((chip_class
== R600
) &&
152 (family
!= CHIP_RV670
&& family
!= CHIP_RS780
&& family
!= CHIP_RS880
)) {
153 bc
->ar_handling
= AR_HANDLE_RV6XX
;
154 bc
->r6xx_nop_after_rel_dst
= 1;
156 bc
->ar_handling
= AR_HANDLE_NORMAL
;
157 bc
->r6xx_nop_after_rel_dst
= 0;
160 LIST_INITHEAD(&bc
->cf
);
161 bc
->chip_class
= chip_class
;
163 bc
->has_compressed_msaa_texturing
= has_compressed_msaa_texturing
;
164 bc
->stack
.entry_size
= stack_entry_size(family
);
167 int r600_bytecode_add_cf(struct r600_bytecode
*bc
)
169 struct r600_bytecode_cf
*cf
= r600_bytecode_cf();
173 LIST_ADDTAIL(&cf
->list
, &bc
->cf
);
175 cf
->id
= bc
->cf_last
->id
+ 2;
176 if (bc
->cf_last
->eg_alu_extended
) {
177 /* take into account extended alu size */
185 bc
->force_add_cf
= 0;
190 int r600_bytecode_add_output(struct r600_bytecode
*bc
,
191 const struct r600_bytecode_output
*output
)
195 if (output
->gpr
>= bc
->ngpr
)
196 bc
->ngpr
= output
->gpr
+ 1;
198 if (bc
->cf_last
&& (bc
->cf_last
->op
== output
->op
||
199 (bc
->cf_last
->op
== CF_OP_EXPORT
&&
200 output
->op
== CF_OP_EXPORT_DONE
)) &&
201 output
->type
== bc
->cf_last
->output
.type
&&
202 output
->elem_size
== bc
->cf_last
->output
.elem_size
&&
203 output
->swizzle_x
== bc
->cf_last
->output
.swizzle_x
&&
204 output
->swizzle_y
== bc
->cf_last
->output
.swizzle_y
&&
205 output
->swizzle_z
== bc
->cf_last
->output
.swizzle_z
&&
206 output
->swizzle_w
== bc
->cf_last
->output
.swizzle_w
&&
207 output
->comp_mask
== bc
->cf_last
->output
.comp_mask
&&
208 (output
->burst_count
+ bc
->cf_last
->output
.burst_count
) <= 16) {
210 if ((output
->gpr
+ output
->burst_count
) == bc
->cf_last
->output
.gpr
&&
211 (output
->array_base
+ output
->burst_count
) == bc
->cf_last
->output
.array_base
) {
213 bc
->cf_last
->op
= bc
->cf_last
->output
.op
= output
->op
;
214 bc
->cf_last
->output
.gpr
= output
->gpr
;
215 bc
->cf_last
->output
.array_base
= output
->array_base
;
216 bc
->cf_last
->output
.burst_count
+= output
->burst_count
;
219 } else if (output
->gpr
== (bc
->cf_last
->output
.gpr
+ bc
->cf_last
->output
.burst_count
) &&
220 output
->array_base
== (bc
->cf_last
->output
.array_base
+ bc
->cf_last
->output
.burst_count
)) {
222 bc
->cf_last
->op
= bc
->cf_last
->output
.op
= output
->op
;
223 bc
->cf_last
->output
.burst_count
+= output
->burst_count
;
228 r
= r600_bytecode_add_cf(bc
);
231 bc
->cf_last
->op
= output
->op
;
232 memcpy(&bc
->cf_last
->output
, output
, sizeof(struct r600_bytecode_output
));
233 bc
->cf_last
->barrier
= 1;
237 /* alu instructions that can ony exits once per group */
238 static int is_alu_once_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
240 return r600_isa_alu(alu
->op
)->flags
& (AF_KILL
| AF_PRED
);
243 static int is_alu_reduction_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
245 return (r600_isa_alu(alu
->op
)->flags
& AF_REPL
) &&
246 (r600_isa_alu_slots(bc
->isa
->hw_class
, alu
->op
) == AF_4V
);
249 static int is_alu_mova_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
251 return r600_isa_alu(alu
->op
)->flags
& AF_MOVA
;
254 static int alu_uses_rel(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
256 unsigned num_src
= r600_bytecode_get_num_operands(bc
, alu
);
263 for (src
= 0; src
< num_src
; ++src
) {
264 if (alu
->src
[src
].rel
) {
271 static int is_alu_64bit_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
273 const struct alu_op_info
*op
= r600_isa_alu(alu
->op
);
274 return (op
->flags
& AF_64
);
277 static int is_alu_vec_unit_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
279 unsigned slots
= r600_isa_alu_slots(bc
->isa
->hw_class
, alu
->op
);
280 return !(slots
& AF_S
);
283 static int is_alu_trans_unit_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
285 unsigned slots
= r600_isa_alu_slots(bc
->isa
->hw_class
, alu
->op
);
286 return !(slots
& AF_V
);
289 /* alu instructions that can execute on any unit */
290 static int is_alu_any_unit_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
292 unsigned slots
= r600_isa_alu_slots(bc
->isa
->hw_class
, alu
->op
);
293 return slots
== AF_VS
;
296 static int is_nop_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
298 return alu
->op
== ALU_OP0_NOP
;
301 static int assign_alu_units(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu_first
,
302 struct r600_bytecode_alu
*assignment
[5])
304 struct r600_bytecode_alu
*alu
;
305 unsigned i
, chan
, trans
;
306 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
308 for (i
= 0; i
< max_slots
; i
++)
309 assignment
[i
] = NULL
;
311 for (alu
= alu_first
; alu
; alu
= LIST_ENTRY(struct r600_bytecode_alu
, alu
->list
.next
, list
)) {
312 chan
= alu
->dst
.chan
;
315 else if (is_alu_trans_unit_inst(bc
, alu
))
317 else if (is_alu_vec_unit_inst(bc
, alu
))
319 else if (assignment
[chan
])
320 trans
= 1; /* Assume ALU_INST_PREFER_VECTOR. */
326 assert(0); /* ALU.Trans has already been allocated. */
331 if (assignment
[chan
]) {
332 assert(0); /* ALU.chan has already been allocated. */
335 assignment
[chan
] = alu
;
344 struct alu_bank_swizzle
{
345 int hw_gpr
[NUM_OF_CYCLES
][NUM_OF_COMPONENTS
];
346 int hw_cfile_addr
[4];
347 int hw_cfile_elem
[4];
350 static const unsigned cycle_for_bank_swizzle_vec
[][3] = {
351 [SQ_ALU_VEC_012
] = { 0, 1, 2 },
352 [SQ_ALU_VEC_021
] = { 0, 2, 1 },
353 [SQ_ALU_VEC_120
] = { 1, 2, 0 },
354 [SQ_ALU_VEC_102
] = { 1, 0, 2 },
355 [SQ_ALU_VEC_201
] = { 2, 0, 1 },
356 [SQ_ALU_VEC_210
] = { 2, 1, 0 }
359 static const unsigned cycle_for_bank_swizzle_scl
[][3] = {
360 [SQ_ALU_SCL_210
] = { 2, 1, 0 },
361 [SQ_ALU_SCL_122
] = { 1, 2, 2 },
362 [SQ_ALU_SCL_212
] = { 2, 1, 2 },
363 [SQ_ALU_SCL_221
] = { 2, 2, 1 }
366 static void init_bank_swizzle(struct alu_bank_swizzle
*bs
)
368 int i
, cycle
, component
;
370 for (cycle
= 0; cycle
< NUM_OF_CYCLES
; cycle
++)
371 for (component
= 0; component
< NUM_OF_COMPONENTS
; component
++)
372 bs
->hw_gpr
[cycle
][component
] = -1;
373 for (i
= 0; i
< 4; i
++)
374 bs
->hw_cfile_addr
[i
] = -1;
375 for (i
= 0; i
< 4; i
++)
376 bs
->hw_cfile_elem
[i
] = -1;
379 static int reserve_gpr(struct alu_bank_swizzle
*bs
, unsigned sel
, unsigned chan
, unsigned cycle
)
381 if (bs
->hw_gpr
[cycle
][chan
] == -1)
382 bs
->hw_gpr
[cycle
][chan
] = sel
;
383 else if (bs
->hw_gpr
[cycle
][chan
] != (int)sel
) {
384 /* Another scalar operation has already used the GPR read port for the channel. */
390 static int reserve_cfile(struct r600_bytecode
*bc
, struct alu_bank_swizzle
*bs
, unsigned sel
, unsigned chan
)
392 int res
, num_res
= 4;
393 if (bc
->chip_class
>= R700
) {
397 for (res
= 0; res
< num_res
; ++res
) {
398 if (bs
->hw_cfile_addr
[res
] == -1) {
399 bs
->hw_cfile_addr
[res
] = sel
;
400 bs
->hw_cfile_elem
[res
] = chan
;
402 } else if (bs
->hw_cfile_addr
[res
] == sel
&&
403 bs
->hw_cfile_elem
[res
] == chan
)
404 return 0; /* Read for this scalar element already reserved, nothing to do here. */
406 /* All cfile read ports are used, cannot reference vector element. */
410 static int is_gpr(unsigned sel
)
415 /* CB constants start at 512, and get translated to a kcache index when ALU
416 * clauses are constructed. Note that we handle kcache constants the same way
417 * as (the now gone) cfile constants, is that really required? */
418 static int is_cfile(unsigned sel
)
420 return (sel
> 255 && sel
< 512) ||
421 (sel
> 511 && sel
< 4607) || /* Kcache before translation. */
422 (sel
> 127 && sel
< 192); /* Kcache after translation. */
425 static int is_const(int sel
)
427 return is_cfile(sel
) ||
428 (sel
>= V_SQ_ALU_SRC_0
&&
429 sel
<= V_SQ_ALU_SRC_LITERAL
);
432 static int check_vector(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
,
433 struct alu_bank_swizzle
*bs
, int bank_swizzle
)
435 int r
, src
, num_src
, sel
, elem
, cycle
;
437 num_src
= r600_bytecode_get_num_operands(bc
, alu
);
438 for (src
= 0; src
< num_src
; src
++) {
439 sel
= alu
->src
[src
].sel
;
440 elem
= alu
->src
[src
].chan
;
442 cycle
= cycle_for_bank_swizzle_vec
[bank_swizzle
][src
];
443 if (src
== 1 && sel
== alu
->src
[0].sel
&& elem
== alu
->src
[0].chan
)
444 /* Nothing to do; special-case optimization,
445 * second source uses first source’s reservation. */
448 r
= reserve_gpr(bs
, sel
, elem
, cycle
);
452 } else if (is_cfile(sel
)) {
453 r
= reserve_cfile(bc
, bs
, (alu
->src
[src
].kc_bank
<<16) + sel
, elem
);
457 /* No restrictions on PV, PS, literal or special constants. */
462 static int check_scalar(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
,
463 struct alu_bank_swizzle
*bs
, int bank_swizzle
)
465 int r
, src
, num_src
, const_count
, sel
, elem
, cycle
;
467 num_src
= r600_bytecode_get_num_operands(bc
, alu
);
468 for (const_count
= 0, src
= 0; src
< num_src
; ++src
) {
469 sel
= alu
->src
[src
].sel
;
470 elem
= alu
->src
[src
].chan
;
471 if (is_const(sel
)) { /* Any constant, including literal and inline constants. */
472 if (const_count
>= 2)
473 /* More than two references to a constant in
474 * transcendental operation. */
480 r
= reserve_cfile(bc
, bs
, (alu
->src
[src
].kc_bank
<<16) + sel
, elem
);
485 for (src
= 0; src
< num_src
; ++src
) {
486 sel
= alu
->src
[src
].sel
;
487 elem
= alu
->src
[src
].chan
;
489 cycle
= cycle_for_bank_swizzle_scl
[bank_swizzle
][src
];
490 if (cycle
< const_count
)
491 /* Cycle for GPR load conflicts with
492 * constant load in transcendental operation. */
494 r
= reserve_gpr(bs
, sel
, elem
, cycle
);
498 /* PV PS restrictions */
499 if (const_count
&& (sel
== 254 || sel
== 255)) {
500 cycle
= cycle_for_bank_swizzle_scl
[bank_swizzle
][src
];
501 if (cycle
< const_count
)
508 static int check_and_set_bank_swizzle(struct r600_bytecode
*bc
,
509 struct r600_bytecode_alu
*slots
[5])
511 struct alu_bank_swizzle bs
;
513 int i
, r
= 0, forced
= 1;
514 boolean scalar_only
= bc
->chip_class
== CAYMAN
? false : true;
515 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
517 for (i
= 0; i
< max_slots
; i
++) {
519 if (slots
[i
]->bank_swizzle_force
) {
520 slots
[i
]->bank_swizzle
= slots
[i
]->bank_swizzle_force
;
526 if (i
< 4 && slots
[i
])
532 /* Just check every possible combination of bank swizzle.
533 * Not very efficent, but works on the first try in most of the cases. */
534 for (i
= 0; i
< 4; i
++)
535 if (!slots
[i
] || !slots
[i
]->bank_swizzle_force
)
536 bank_swizzle
[i
] = SQ_ALU_VEC_012
;
538 bank_swizzle
[i
] = slots
[i
]->bank_swizzle
;
540 bank_swizzle
[4] = SQ_ALU_SCL_210
;
541 while(bank_swizzle
[4] <= SQ_ALU_SCL_221
) {
543 init_bank_swizzle(&bs
);
544 if (scalar_only
== false) {
545 for (i
= 0; i
< 4; i
++) {
547 r
= check_vector(bc
, slots
[i
], &bs
, bank_swizzle
[i
]);
555 if (!r
&& max_slots
== 5 && slots
[4]) {
556 r
= check_scalar(bc
, slots
[4], &bs
, bank_swizzle
[4]);
559 for (i
= 0; i
< max_slots
; i
++) {
561 slots
[i
]->bank_swizzle
= bank_swizzle
[i
];
569 for (i
= 0; i
< max_slots
; i
++) {
570 if (!slots
[i
] || !slots
[i
]->bank_swizzle_force
) {
572 if (bank_swizzle
[i
] <= SQ_ALU_VEC_210
)
574 else if (i
< max_slots
- 1)
575 bank_swizzle
[i
] = SQ_ALU_VEC_012
;
583 /* Couldn't find a working swizzle. */
587 static int replace_gpr_with_pv_ps(struct r600_bytecode
*bc
,
588 struct r600_bytecode_alu
*slots
[5], struct r600_bytecode_alu
*alu_prev
)
590 struct r600_bytecode_alu
*prev
[5];
592 int i
, j
, r
, src
, num_src
;
593 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
595 r
= assign_alu_units(bc
, alu_prev
, prev
);
599 for (i
= 0; i
< max_slots
; ++i
) {
600 if (prev
[i
] && alu_writes(prev
[i
]) && !prev
[i
]->dst
.rel
) {
602 if (is_alu_64bit_inst(bc
, prev
[i
])) {
607 gpr
[i
] = prev
[i
]->dst
.sel
;
608 /* cube writes more than PV.X */
609 if (is_alu_reduction_inst(bc
, prev
[i
]))
612 chan
[i
] = prev
[i
]->dst
.chan
;
617 for (i
= 0; i
< max_slots
; ++i
) {
618 struct r600_bytecode_alu
*alu
= slots
[i
];
622 if (is_alu_64bit_inst(bc
, alu
))
624 num_src
= r600_bytecode_get_num_operands(bc
, alu
);
625 for (src
= 0; src
< num_src
; ++src
) {
626 if (!is_gpr(alu
->src
[src
].sel
) || alu
->src
[src
].rel
)
629 if (bc
->chip_class
< CAYMAN
) {
630 if (alu
->src
[src
].sel
== gpr
[4] &&
631 alu
->src
[src
].chan
== chan
[4] &&
632 alu_prev
->pred_sel
== alu
->pred_sel
) {
633 alu
->src
[src
].sel
= V_SQ_ALU_SRC_PS
;
634 alu
->src
[src
].chan
= 0;
639 for (j
= 0; j
< 4; ++j
) {
640 if (alu
->src
[src
].sel
== gpr
[j
] &&
641 alu
->src
[src
].chan
== j
&&
642 alu_prev
->pred_sel
== alu
->pred_sel
) {
643 alu
->src
[src
].sel
= V_SQ_ALU_SRC_PV
;
644 alu
->src
[src
].chan
= chan
[j
];
654 void r600_bytecode_special_constants(uint32_t value
, unsigned *sel
, unsigned *neg
, unsigned abs
)
658 *sel
= V_SQ_ALU_SRC_0
;
661 *sel
= V_SQ_ALU_SRC_1_INT
;
664 *sel
= V_SQ_ALU_SRC_M_1_INT
;
666 case 0x3F800000: /* 1.0f */
667 *sel
= V_SQ_ALU_SRC_1
;
669 case 0x3F000000: /* 0.5f */
670 *sel
= V_SQ_ALU_SRC_0_5
;
672 case 0xBF800000: /* -1.0f */
673 *sel
= V_SQ_ALU_SRC_1
;
676 case 0xBF000000: /* -0.5f */
677 *sel
= V_SQ_ALU_SRC_0_5
;
681 *sel
= V_SQ_ALU_SRC_LITERAL
;
686 /* compute how many literal are needed */
687 static int r600_bytecode_alu_nliterals(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
,
688 uint32_t literal
[4], unsigned *nliteral
)
690 unsigned num_src
= r600_bytecode_get_num_operands(bc
, alu
);
693 for (i
= 0; i
< num_src
; ++i
) {
694 if (alu
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
695 uint32_t value
= alu
->src
[i
].value
;
697 for (j
= 0; j
< *nliteral
; ++j
) {
698 if (literal
[j
] == value
) {
706 literal
[(*nliteral
)++] = value
;
713 static void r600_bytecode_alu_adjust_literals(struct r600_bytecode
*bc
,
714 struct r600_bytecode_alu
*alu
,
715 uint32_t literal
[4], unsigned nliteral
)
717 unsigned num_src
= r600_bytecode_get_num_operands(bc
, alu
);
720 for (i
= 0; i
< num_src
; ++i
) {
721 if (alu
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
722 uint32_t value
= alu
->src
[i
].value
;
723 for (j
= 0; j
< nliteral
; ++j
) {
724 if (literal
[j
] == value
) {
725 alu
->src
[i
].chan
= j
;
733 static int merge_inst_groups(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*slots
[5],
734 struct r600_bytecode_alu
*alu_prev
)
736 struct r600_bytecode_alu
*prev
[5];
737 struct r600_bytecode_alu
*result
[5] = { NULL
};
739 uint32_t literal
[4], prev_literal
[4];
740 unsigned nliteral
= 0, prev_nliteral
= 0;
742 int i
, j
, r
, src
, num_src
;
743 int num_once_inst
= 0;
744 int have_mova
= 0, have_rel
= 0;
745 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
747 r
= assign_alu_units(bc
, alu_prev
, prev
);
751 for (i
= 0; i
< max_slots
; ++i
) {
753 if (prev
[i
]->pred_sel
)
755 if (is_alu_once_inst(bc
, prev
[i
]))
759 if (slots
[i
]->pred_sel
)
761 if (is_alu_once_inst(bc
, slots
[i
]))
766 for (i
= 0; i
< max_slots
; ++i
) {
767 struct r600_bytecode_alu
*alu
;
769 if (num_once_inst
> 0)
772 /* check number of literals */
774 if (r600_bytecode_alu_nliterals(bc
, prev
[i
], literal
, &nliteral
))
776 if (r600_bytecode_alu_nliterals(bc
, prev
[i
], prev_literal
, &prev_nliteral
))
778 if (is_alu_mova_inst(bc
, prev
[i
])) {
784 if (alu_uses_rel(bc
, prev
[i
])) {
791 num_once_inst
+= is_alu_once_inst(bc
, prev
[i
]);
793 if (slots
[i
] && r600_bytecode_alu_nliterals(bc
, slots
[i
], literal
, &nliteral
))
796 /* Let's check used slots. */
797 if (prev
[i
] && !slots
[i
]) {
800 } else if (prev
[i
] && slots
[i
]) {
801 if (max_slots
== 5 && result
[4] == NULL
&& prev
[4] == NULL
&& slots
[4] == NULL
) {
802 /* Trans unit is still free try to use it. */
803 if (is_alu_any_unit_inst(bc
, slots
[i
])) {
805 result
[4] = slots
[i
];
806 } else if (is_alu_any_unit_inst(bc
, prev
[i
])) {
807 if (slots
[i
]->dst
.sel
== prev
[i
]->dst
.sel
&&
808 alu_writes(slots
[i
]) &&
812 result
[i
] = slots
[i
];
818 } else if(!slots
[i
]) {
821 if (max_slots
== 5 && slots
[i
] && prev
[4] &&
822 slots
[i
]->dst
.sel
== prev
[4]->dst
.sel
&&
823 slots
[i
]->dst
.chan
== prev
[4]->dst
.chan
&&
824 alu_writes(slots
[i
]) &&
828 result
[i
] = slots
[i
];
832 num_once_inst
+= is_alu_once_inst(bc
, alu
);
834 /* don't reschedule NOPs */
835 if (is_nop_inst(bc
, alu
))
838 if (is_alu_mova_inst(bc
, alu
)) {
845 if (alu_uses_rel(bc
, alu
)) {
852 if (alu
->op
== ALU_OP0_SET_CF_IDX0
||
853 alu
->op
== ALU_OP0_SET_CF_IDX1
)
854 return 0; /* data hazard with MOVA */
856 /* Let's check source gprs */
857 num_src
= r600_bytecode_get_num_operands(bc
, alu
);
858 for (src
= 0; src
< num_src
; ++src
) {
860 /* Constants don't matter. */
861 if (!is_gpr(alu
->src
[src
].sel
))
864 for (j
= 0; j
< max_slots
; ++j
) {
865 if (!prev
[j
] || !alu_writes(prev
[j
]))
868 /* If it's relative then we can't determin which gpr is really used. */
869 if (prev
[j
]->dst
.chan
== alu
->src
[src
].chan
&&
870 (prev
[j
]->dst
.sel
== alu
->src
[src
].sel
||
871 prev
[j
]->dst
.rel
|| alu
->src
[src
].rel
))
877 /* more than one PRED_ or KILL_ ? */
878 if (num_once_inst
> 1)
881 /* check if the result can still be swizzlet */
882 r
= check_and_set_bank_swizzle(bc
, result
);
886 /* looks like everything worked out right, apply the changes */
888 /* undo adding previus literals */
889 bc
->cf_last
->ndw
-= align(prev_nliteral
, 2);
891 /* sort instructions */
892 for (i
= 0; i
< max_slots
; ++i
) {
893 slots
[i
] = result
[i
];
895 LIST_DEL(&result
[i
]->list
);
897 LIST_ADDTAIL(&result
[i
]->list
, &bc
->cf_last
->alu
);
901 /* determine new last instruction */
902 LIST_ENTRY(struct r600_bytecode_alu
, bc
->cf_last
->alu
.prev
, list
)->last
= 1;
904 /* determine new first instruction */
905 for (i
= 0; i
< max_slots
; ++i
) {
907 bc
->cf_last
->curr_bs_head
= result
[i
];
912 bc
->cf_last
->prev_bs_head
= bc
->cf_last
->prev2_bs_head
;
913 bc
->cf_last
->prev2_bs_head
= NULL
;
918 /* we'll keep kcache sets sorted by bank & addr */
919 static int r600_bytecode_alloc_kcache_line(struct r600_bytecode
*bc
,
920 struct r600_bytecode_kcache
*kcache
,
921 unsigned bank
, unsigned line
, unsigned index_mode
)
923 int i
, kcache_banks
= bc
->chip_class
>= EVERGREEN
? 4 : 2;
925 for (i
= 0; i
< kcache_banks
; i
++) {
926 if (kcache
[i
].mode
) {
929 if (kcache
[i
].bank
< bank
)
932 if ((kcache
[i
].bank
== bank
&& kcache
[i
].addr
> line
+1) ||
933 kcache
[i
].bank
> bank
) {
934 /* try to insert new line */
935 if (kcache
[kcache_banks
-1].mode
) {
936 /* all sets are in use */
940 memmove(&kcache
[i
+1],&kcache
[i
], (kcache_banks
-i
-1)*sizeof(struct r600_bytecode_kcache
));
941 kcache
[i
].mode
= V_SQ_CF_KCACHE_LOCK_1
;
942 kcache
[i
].bank
= bank
;
943 kcache
[i
].addr
= line
;
944 kcache
[i
].index_mode
= index_mode
;
948 d
= line
- kcache
[i
].addr
;
952 if (kcache
[i
].mode
== V_SQ_CF_KCACHE_LOCK_2
) {
953 /* we are prepending the line to the current set,
954 * discarding the existing second line,
955 * so we'll have to insert line+2 after it */
958 } else if (kcache
[i
].mode
== V_SQ_CF_KCACHE_LOCK_1
) {
959 kcache
[i
].mode
= V_SQ_CF_KCACHE_LOCK_2
;
962 /* V_SQ_CF_KCACHE_LOCK_LOOP_INDEX is not supported */
966 kcache
[i
].mode
= V_SQ_CF_KCACHE_LOCK_2
;
970 } else { /* free kcache set - use it */
971 kcache
[i
].mode
= V_SQ_CF_KCACHE_LOCK_1
;
972 kcache
[i
].bank
= bank
;
973 kcache
[i
].addr
= line
;
974 kcache
[i
].index_mode
= index_mode
;
981 static int r600_bytecode_alloc_inst_kcache_lines(struct r600_bytecode
*bc
,
982 struct r600_bytecode_kcache
*kcache
,
983 struct r600_bytecode_alu
*alu
)
987 for (i
= 0; i
< 3; i
++) {
988 unsigned bank
, line
, sel
= alu
->src
[i
].sel
, index_mode
;
993 bank
= alu
->src
[i
].kc_bank
;
995 index_mode
= alu
->src
[i
].kc_rel
? 1 : 0; // V_SQ_CF_INDEX_0 / V_SQ_CF_INDEX_NONE
997 if ((r
= r600_bytecode_alloc_kcache_line(bc
, kcache
, bank
, line
, index_mode
)))
1003 static int r600_bytecode_assign_kcache_banks(struct r600_bytecode
*bc
,
1004 struct r600_bytecode_alu
*alu
,
1005 struct r600_bytecode_kcache
* kcache
)
1009 /* Alter the src operands to refer to the kcache. */
1010 for (i
= 0; i
< 3; ++i
) {
1011 static const unsigned int base
[] = {128, 160, 256, 288};
1012 unsigned int line
, sel
= alu
->src
[i
].sel
, found
= 0;
1020 for (j
= 0; j
< 4 && !found
; ++j
) {
1021 switch (kcache
[j
].mode
) {
1022 case V_SQ_CF_KCACHE_NOP
:
1023 case V_SQ_CF_KCACHE_LOCK_LOOP_INDEX
:
1024 R600_ERR("unexpected kcache line mode\n");
1027 if (kcache
[j
].bank
== alu
->src
[i
].kc_bank
&&
1028 kcache
[j
].addr
<= line
&&
1029 line
< kcache
[j
].addr
+ kcache
[j
].mode
) {
1030 alu
->src
[i
].sel
= sel
- (kcache
[j
].addr
<<4);
1031 alu
->src
[i
].sel
+= base
[j
];
1040 static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode
*bc
,
1041 struct r600_bytecode_alu
*alu
,
1044 struct r600_bytecode_kcache kcache_sets
[4];
1045 struct r600_bytecode_kcache
*kcache
= kcache_sets
;
1048 memcpy(kcache
, bc
->cf_last
->kcache
, 4 * sizeof(struct r600_bytecode_kcache
));
1050 if ((r
= r600_bytecode_alloc_inst_kcache_lines(bc
, kcache
, alu
))) {
1051 /* can't alloc, need to start new clause */
1052 if ((r
= r600_bytecode_add_cf(bc
))) {
1055 bc
->cf_last
->op
= type
;
1057 /* retry with the new clause */
1058 kcache
= bc
->cf_last
->kcache
;
1059 if ((r
= r600_bytecode_alloc_inst_kcache_lines(bc
, kcache
, alu
))) {
1060 /* can't alloc again- should never happen */
1064 /* update kcache sets */
1065 memcpy(bc
->cf_last
->kcache
, kcache
, 4 * sizeof(struct r600_bytecode_kcache
));
1068 /* if we actually used more than 2 kcache sets, or have relative indexing - use ALU_EXTENDED on eg+ */
1069 if (kcache
[2].mode
!= V_SQ_CF_KCACHE_NOP
||
1070 kcache
[0].index_mode
|| kcache
[1].index_mode
|| kcache
[2].index_mode
|| kcache
[3].index_mode
) {
1071 if (bc
->chip_class
< EVERGREEN
)
1073 bc
->cf_last
->eg_alu_extended
= 1;
1079 static int insert_nop_r6xx(struct r600_bytecode
*bc
)
1081 struct r600_bytecode_alu alu
;
1084 for (i
= 0; i
< 4; i
++) {
1085 memset(&alu
, 0, sizeof(alu
));
1086 alu
.op
= ALU_OP0_NOP
;
1087 alu
.src
[0].chan
= i
;
1089 alu
.last
= (i
== 3);
1090 r
= r600_bytecode_add_alu(bc
, &alu
);
1097 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1098 static int load_ar_r6xx(struct r600_bytecode
*bc
)
1100 struct r600_bytecode_alu alu
;
1106 /* hack to avoid making MOVA the last instruction in the clause */
1107 if ((bc
->cf_last
->ndw
>>1) >= 110)
1108 bc
->force_add_cf
= 1;
1110 memset(&alu
, 0, sizeof(alu
));
1111 alu
.op
= ALU_OP1_MOVA_GPR_INT
;
1112 alu
.src
[0].sel
= bc
->ar_reg
;
1113 alu
.src
[0].chan
= bc
->ar_chan
;
1115 alu
.index_mode
= INDEX_MODE_LOOP
;
1116 r
= r600_bytecode_add_alu(bc
, &alu
);
1120 /* no requirement to set uses waterfall on MOVA_GPR_INT */
1125 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1126 static int load_ar(struct r600_bytecode
*bc
)
1128 struct r600_bytecode_alu alu
;
1131 if (bc
->ar_handling
)
1132 return load_ar_r6xx(bc
);
1137 /* hack to avoid making MOVA the last instruction in the clause */
1138 if ((bc
->cf_last
->ndw
>>1) >= 110)
1139 bc
->force_add_cf
= 1;
1141 memset(&alu
, 0, sizeof(alu
));
1142 alu
.op
= ALU_OP1_MOVA_INT
;
1143 alu
.src
[0].sel
= bc
->ar_reg
;
1144 alu
.src
[0].chan
= bc
->ar_chan
;
1146 r
= r600_bytecode_add_alu(bc
, &alu
);
1150 bc
->cf_last
->r6xx_uses_waterfall
= 1;
1155 int r600_bytecode_add_alu_type(struct r600_bytecode
*bc
,
1156 const struct r600_bytecode_alu
*alu
, unsigned type
)
1158 struct r600_bytecode_alu
*nalu
= r600_bytecode_alu();
1159 struct r600_bytecode_alu
*lalu
;
1164 memcpy(nalu
, alu
, sizeof(struct r600_bytecode_alu
));
1167 /* will fail later since alu does not support it. */
1168 assert(!alu
->src
[0].abs
&& !alu
->src
[1].abs
&& !alu
->src
[2].abs
);
1171 if (bc
->cf_last
!= NULL
&& bc
->cf_last
->op
!= type
) {
1172 /* check if we could add it anyway */
1173 if (bc
->cf_last
->op
== CF_OP_ALU
&&
1174 type
== CF_OP_ALU_PUSH_BEFORE
) {
1175 LIST_FOR_EACH_ENTRY(lalu
, &bc
->cf_last
->alu
, list
) {
1176 if (lalu
->execute_mask
) {
1177 bc
->force_add_cf
= 1;
1182 bc
->force_add_cf
= 1;
1185 /* cf can contains only alu or only vtx or only tex */
1186 if (bc
->cf_last
== NULL
|| bc
->force_add_cf
) {
1187 r
= r600_bytecode_add_cf(bc
);
1193 bc
->cf_last
->op
= type
;
1195 /* Load index register if required */
1196 if (bc
->chip_class
>= EVERGREEN
) {
1197 for (i
= 0; i
< 3; i
++)
1198 if (nalu
->src
[i
].kc_bank
&& nalu
->src
[i
].kc_rel
)
1199 egcm_load_index_reg(bc
, 0, true);
1202 /* Check AR usage and load it if required */
1203 for (i
= 0; i
< 3; i
++)
1204 if (nalu
->src
[i
].rel
&& !bc
->ar_loaded
)
1207 if (nalu
->dst
.rel
&& !bc
->ar_loaded
)
1210 /* Setup the kcache for this ALU instruction. This will start a new
1211 * ALU clause if needed. */
1212 if ((r
= r600_bytecode_alloc_kcache_lines(bc
, nalu
, type
))) {
1217 if (!bc
->cf_last
->curr_bs_head
) {
1218 bc
->cf_last
->curr_bs_head
= nalu
;
1220 /* number of gpr == the last gpr used in any alu */
1221 for (i
= 0; i
< 3; i
++) {
1222 if (nalu
->src
[i
].sel
>= bc
->ngpr
&& nalu
->src
[i
].sel
< 128) {
1223 bc
->ngpr
= nalu
->src
[i
].sel
+ 1;
1225 if (nalu
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
)
1226 r600_bytecode_special_constants(nalu
->src
[i
].value
,
1227 &nalu
->src
[i
].sel
, &nalu
->src
[i
].neg
, nalu
->src
[i
].abs
);
1229 if (nalu
->dst
.sel
>= bc
->ngpr
) {
1230 bc
->ngpr
= nalu
->dst
.sel
+ 1;
1232 LIST_ADDTAIL(&nalu
->list
, &bc
->cf_last
->alu
);
1233 /* each alu use 2 dwords */
1234 bc
->cf_last
->ndw
+= 2;
1237 /* process cur ALU instructions for bank swizzle */
1239 uint32_t literal
[4];
1241 struct r600_bytecode_alu
*slots
[5];
1242 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
1243 r
= assign_alu_units(bc
, bc
->cf_last
->curr_bs_head
, slots
);
1247 if (bc
->cf_last
->prev_bs_head
) {
1248 r
= merge_inst_groups(bc
, slots
, bc
->cf_last
->prev_bs_head
);
1253 if (bc
->cf_last
->prev_bs_head
) {
1254 r
= replace_gpr_with_pv_ps(bc
, slots
, bc
->cf_last
->prev_bs_head
);
1259 r
= check_and_set_bank_swizzle(bc
, slots
);
1263 for (i
= 0, nliteral
= 0; i
< max_slots
; i
++) {
1265 r
= r600_bytecode_alu_nliterals(bc
, slots
[i
], literal
, &nliteral
);
1270 bc
->cf_last
->ndw
+= align(nliteral
, 2);
1272 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1274 if ((bc
->cf_last
->ndw
>> 1) >= 120) {
1275 bc
->force_add_cf
= 1;
1278 bc
->cf_last
->prev2_bs_head
= bc
->cf_last
->prev_bs_head
;
1279 bc
->cf_last
->prev_bs_head
= bc
->cf_last
->curr_bs_head
;
1280 bc
->cf_last
->curr_bs_head
= NULL
;
1283 if (nalu
->dst
.rel
&& bc
->r6xx_nop_after_rel_dst
)
1284 insert_nop_r6xx(bc
);
1289 int r600_bytecode_add_alu(struct r600_bytecode
*bc
, const struct r600_bytecode_alu
*alu
)
1291 return r600_bytecode_add_alu_type(bc
, alu
, CF_OP_ALU
);
1294 static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode
*bc
)
1296 switch (bc
->chip_class
) {
1306 R600_ERR("Unknown chip class %d.\n", bc
->chip_class
);
1311 static inline boolean
last_inst_was_not_vtx_fetch(struct r600_bytecode
*bc
)
1313 return !((r600_isa_cf(bc
->cf_last
->op
)->flags
& CF_FETCH
) &&
1314 (bc
->chip_class
== CAYMAN
||
1315 bc
->cf_last
->op
!= CF_OP_TEX
));
1318 int r600_bytecode_add_vtx(struct r600_bytecode
*bc
, const struct r600_bytecode_vtx
*vtx
)
1320 struct r600_bytecode_vtx
*nvtx
= r600_bytecode_vtx();
1325 memcpy(nvtx
, vtx
, sizeof(struct r600_bytecode_vtx
));
1327 /* Load index register if required */
1328 if (bc
->chip_class
>= EVERGREEN
) {
1329 if (vtx
->buffer_index_mode
)
1330 egcm_load_index_reg(bc
, 0, false);
1333 /* cf can contains only alu or only vtx or only tex */
1334 if (bc
->cf_last
== NULL
||
1335 last_inst_was_not_vtx_fetch(bc
) ||
1337 r
= r600_bytecode_add_cf(bc
);
1342 switch (bc
->chip_class
) {
1346 bc
->cf_last
->op
= CF_OP_VTX
;
1349 bc
->cf_last
->op
= CF_OP_TEX
;
1352 R600_ERR("Unknown chip class %d.\n", bc
->chip_class
);
1357 LIST_ADDTAIL(&nvtx
->list
, &bc
->cf_last
->vtx
);
1358 /* each fetch use 4 dwords */
1359 bc
->cf_last
->ndw
+= 4;
1361 if ((bc
->cf_last
->ndw
/ 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc
))
1362 bc
->force_add_cf
= 1;
1364 bc
->ngpr
= MAX2(bc
->ngpr
, vtx
->src_gpr
+ 1);
1365 bc
->ngpr
= MAX2(bc
->ngpr
, vtx
->dst_gpr
+ 1);
1370 int r600_bytecode_add_tex(struct r600_bytecode
*bc
, const struct r600_bytecode_tex
*tex
)
1372 struct r600_bytecode_tex
*ntex
= r600_bytecode_tex();
1377 memcpy(ntex
, tex
, sizeof(struct r600_bytecode_tex
));
1379 /* Load index register if required */
1380 if (bc
->chip_class
>= EVERGREEN
) {
1381 if (tex
->sampler_index_mode
|| tex
->resource_index_mode
)
1382 egcm_load_index_reg(bc
, 1, false);
1385 /* we can't fetch data und use it as texture lookup address in the same TEX clause */
1386 if (bc
->cf_last
!= NULL
&&
1387 bc
->cf_last
->op
== CF_OP_TEX
) {
1388 struct r600_bytecode_tex
*ttex
;
1389 LIST_FOR_EACH_ENTRY(ttex
, &bc
->cf_last
->tex
, list
) {
1390 if (ttex
->dst_gpr
== ntex
->src_gpr
) {
1391 bc
->force_add_cf
= 1;
1395 /* slight hack to make gradients always go into same cf */
1396 if (ntex
->op
== FETCH_OP_SET_GRADIENTS_H
)
1397 bc
->force_add_cf
= 1;
1400 /* cf can contains only alu or only vtx or only tex */
1401 if (bc
->cf_last
== NULL
||
1402 bc
->cf_last
->op
!= CF_OP_TEX
||
1404 r
= r600_bytecode_add_cf(bc
);
1409 bc
->cf_last
->op
= CF_OP_TEX
;
1411 if (ntex
->src_gpr
>= bc
->ngpr
) {
1412 bc
->ngpr
= ntex
->src_gpr
+ 1;
1414 if (ntex
->dst_gpr
>= bc
->ngpr
) {
1415 bc
->ngpr
= ntex
->dst_gpr
+ 1;
1417 LIST_ADDTAIL(&ntex
->list
, &bc
->cf_last
->tex
);
1418 /* each texture fetch use 4 dwords */
1419 bc
->cf_last
->ndw
+= 4;
1421 if ((bc
->cf_last
->ndw
/ 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc
))
1422 bc
->force_add_cf
= 1;
1426 int r600_bytecode_add_gds(struct r600_bytecode
*bc
, const struct r600_bytecode_gds
*gds
)
1428 struct r600_bytecode_gds
*ngds
= r600_bytecode_gds();
1433 memcpy(ngds
, gds
, sizeof(struct r600_bytecode_gds
));
1435 if (bc
->cf_last
== NULL
||
1436 bc
->cf_last
->op
!= CF_OP_GDS
||
1438 r
= r600_bytecode_add_cf(bc
);
1443 bc
->cf_last
->op
= CF_OP_GDS
;
1446 LIST_ADDTAIL(&ngds
->list
, &bc
->cf_last
->gds
);
1447 bc
->cf_last
->ndw
+= 4; /* each GDS uses 4 dwords */
1448 if ((bc
->cf_last
->ndw
/ 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc
))
1449 bc
->force_add_cf
= 1;
1453 int r600_bytecode_add_cfinst(struct r600_bytecode
*bc
, unsigned op
)
1456 r
= r600_bytecode_add_cf(bc
);
1460 bc
->cf_last
->cond
= V_SQ_CF_COND_ACTIVE
;
1461 bc
->cf_last
->op
= op
;
1465 int cm_bytecode_add_cf_end(struct r600_bytecode
*bc
)
1467 return r600_bytecode_add_cfinst(bc
, CF_OP_CF_END
);
1470 /* common to all 3 families */
1471 static int r600_bytecode_vtx_build(struct r600_bytecode
*bc
, struct r600_bytecode_vtx
*vtx
, unsigned id
)
1473 bc
->bytecode
[id
] = S_SQ_VTX_WORD0_BUFFER_ID(vtx
->buffer_id
) |
1474 S_SQ_VTX_WORD0_FETCH_TYPE(vtx
->fetch_type
) |
1475 S_SQ_VTX_WORD0_SRC_GPR(vtx
->src_gpr
) |
1476 S_SQ_VTX_WORD0_SRC_SEL_X(vtx
->src_sel_x
);
1477 if (bc
->chip_class
< CAYMAN
)
1478 bc
->bytecode
[id
] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx
->mega_fetch_count
);
1480 bc
->bytecode
[id
++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx
->dst_sel_x
) |
1481 S_SQ_VTX_WORD1_DST_SEL_Y(vtx
->dst_sel_y
) |
1482 S_SQ_VTX_WORD1_DST_SEL_Z(vtx
->dst_sel_z
) |
1483 S_SQ_VTX_WORD1_DST_SEL_W(vtx
->dst_sel_w
) |
1484 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx
->use_const_fields
) |
1485 S_SQ_VTX_WORD1_DATA_FORMAT(vtx
->data_format
) |
1486 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx
->num_format_all
) |
1487 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx
->format_comp_all
) |
1488 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx
->srf_mode_all
) |
1489 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx
->dst_gpr
);
1490 bc
->bytecode
[id
] = S_SQ_VTX_WORD2_OFFSET(vtx
->offset
)|
1491 S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx
->endian
);
1492 if (bc
->chip_class
>= EVERGREEN
)
1493 bc
->bytecode
[id
] |= ((vtx
->buffer_index_mode
& 0x3) << 21); // S_SQ_VTX_WORD2_BIM(vtx->buffer_index_mode);
1494 if (bc
->chip_class
< CAYMAN
)
1495 bc
->bytecode
[id
] |= S_SQ_VTX_WORD2_MEGA_FETCH(1);
1497 bc
->bytecode
[id
++] = 0;
1501 /* common to all 3 families */
1502 static int r600_bytecode_tex_build(struct r600_bytecode
*bc
, struct r600_bytecode_tex
*tex
, unsigned id
)
1504 bc
->bytecode
[id
] = S_SQ_TEX_WORD0_TEX_INST(
1505 r600_isa_fetch_opcode(bc
->isa
->hw_class
, tex
->op
)) |
1506 EG_S_SQ_TEX_WORD0_INST_MOD(tex
->inst_mod
) |
1507 S_SQ_TEX_WORD0_RESOURCE_ID(tex
->resource_id
) |
1508 S_SQ_TEX_WORD0_SRC_GPR(tex
->src_gpr
) |
1509 S_SQ_TEX_WORD0_SRC_REL(tex
->src_rel
);
1510 if (bc
->chip_class
>= EVERGREEN
)
1511 bc
->bytecode
[id
] |= ((tex
->sampler_index_mode
& 0x3) << 27) | // S_SQ_TEX_WORD0_SIM(tex->sampler_index_mode);
1512 ((tex
->resource_index_mode
& 0x3) << 25); // S_SQ_TEX_WORD0_RIM(tex->resource_index_mode)
1514 bc
->bytecode
[id
++] = S_SQ_TEX_WORD1_DST_GPR(tex
->dst_gpr
) |
1515 S_SQ_TEX_WORD1_DST_REL(tex
->dst_rel
) |
1516 S_SQ_TEX_WORD1_DST_SEL_X(tex
->dst_sel_x
) |
1517 S_SQ_TEX_WORD1_DST_SEL_Y(tex
->dst_sel_y
) |
1518 S_SQ_TEX_WORD1_DST_SEL_Z(tex
->dst_sel_z
) |
1519 S_SQ_TEX_WORD1_DST_SEL_W(tex
->dst_sel_w
) |
1520 S_SQ_TEX_WORD1_LOD_BIAS(tex
->lod_bias
) |
1521 S_SQ_TEX_WORD1_COORD_TYPE_X(tex
->coord_type_x
) |
1522 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex
->coord_type_y
) |
1523 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex
->coord_type_z
) |
1524 S_SQ_TEX_WORD1_COORD_TYPE_W(tex
->coord_type_w
);
1525 bc
->bytecode
[id
++] = S_SQ_TEX_WORD2_OFFSET_X(tex
->offset_x
) |
1526 S_SQ_TEX_WORD2_OFFSET_Y(tex
->offset_y
) |
1527 S_SQ_TEX_WORD2_OFFSET_Z(tex
->offset_z
) |
1528 S_SQ_TEX_WORD2_SAMPLER_ID(tex
->sampler_id
) |
1529 S_SQ_TEX_WORD2_SRC_SEL_X(tex
->src_sel_x
) |
1530 S_SQ_TEX_WORD2_SRC_SEL_Y(tex
->src_sel_y
) |
1531 S_SQ_TEX_WORD2_SRC_SEL_Z(tex
->src_sel_z
) |
1532 S_SQ_TEX_WORD2_SRC_SEL_W(tex
->src_sel_w
);
1533 bc
->bytecode
[id
++] = 0;
1537 /* r600 only, r700/eg bits in r700_asm.c */
1538 static int r600_bytecode_alu_build(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
, unsigned id
)
1540 unsigned opcode
= r600_isa_alu_opcode(bc
->isa
->hw_class
, alu
->op
);
1542 /* don't replace gpr by pv or ps for destination register */
1543 bc
->bytecode
[id
++] = S_SQ_ALU_WORD0_SRC0_SEL(alu
->src
[0].sel
) |
1544 S_SQ_ALU_WORD0_SRC0_REL(alu
->src
[0].rel
) |
1545 S_SQ_ALU_WORD0_SRC0_CHAN(alu
->src
[0].chan
) |
1546 S_SQ_ALU_WORD0_SRC0_NEG(alu
->src
[0].neg
) |
1547 S_SQ_ALU_WORD0_SRC1_SEL(alu
->src
[1].sel
) |
1548 S_SQ_ALU_WORD0_SRC1_REL(alu
->src
[1].rel
) |
1549 S_SQ_ALU_WORD0_SRC1_CHAN(alu
->src
[1].chan
) |
1550 S_SQ_ALU_WORD0_SRC1_NEG(alu
->src
[1].neg
) |
1551 S_SQ_ALU_WORD0_INDEX_MODE(alu
->index_mode
) |
1552 S_SQ_ALU_WORD0_PRED_SEL(alu
->pred_sel
) |
1553 S_SQ_ALU_WORD0_LAST(alu
->last
);
1556 assert(!alu
->src
[0].abs
&& !alu
->src
[1].abs
&& !alu
->src
[2].abs
);
1557 bc
->bytecode
[id
++] = S_SQ_ALU_WORD1_DST_GPR(alu
->dst
.sel
) |
1558 S_SQ_ALU_WORD1_DST_CHAN(alu
->dst
.chan
) |
1559 S_SQ_ALU_WORD1_DST_REL(alu
->dst
.rel
) |
1560 S_SQ_ALU_WORD1_CLAMP(alu
->dst
.clamp
) |
1561 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu
->src
[2].sel
) |
1562 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu
->src
[2].rel
) |
1563 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu
->src
[2].chan
) |
1564 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu
->src
[2].neg
) |
1565 S_SQ_ALU_WORD1_OP3_ALU_INST(opcode
) |
1566 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu
->bank_swizzle
);
1568 bc
->bytecode
[id
++] = S_SQ_ALU_WORD1_DST_GPR(alu
->dst
.sel
) |
1569 S_SQ_ALU_WORD1_DST_CHAN(alu
->dst
.chan
) |
1570 S_SQ_ALU_WORD1_DST_REL(alu
->dst
.rel
) |
1571 S_SQ_ALU_WORD1_CLAMP(alu
->dst
.clamp
) |
1572 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu
->src
[0].abs
) |
1573 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu
->src
[1].abs
) |
1574 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu
->dst
.write
) |
1575 S_SQ_ALU_WORD1_OP2_OMOD(alu
->omod
) |
1576 S_SQ_ALU_WORD1_OP2_ALU_INST(opcode
) |
1577 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu
->bank_swizzle
) |
1578 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu
->execute_mask
) |
1579 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu
->update_pred
);
1584 static void r600_bytecode_cf_vtx_build(uint32_t *bytecode
, const struct r600_bytecode_cf
*cf
)
1586 *bytecode
++ = S_SQ_CF_WORD0_ADDR(cf
->addr
>> 1);
1587 *bytecode
++ = S_SQ_CF_WORD1_CF_INST(r600_isa_cf_opcode(ISA_CC_R600
, cf
->op
)) |
1588 S_SQ_CF_WORD1_BARRIER(1) |
1589 S_SQ_CF_WORD1_COUNT((cf
->ndw
/ 4) - 1);
1592 /* common for r600/r700 - eg in eg_asm.c */
1593 static int r600_bytecode_cf_build(struct r600_bytecode
*bc
, struct r600_bytecode_cf
*cf
)
1595 unsigned id
= cf
->id
;
1596 const struct cf_op_info
*cfop
= r600_isa_cf(cf
->op
);
1597 unsigned opcode
= r600_isa_cf_opcode(bc
->isa
->hw_class
, cf
->op
);
1600 if (cf
->op
== CF_NATIVE
) {
1601 bc
->bytecode
[id
++] = cf
->isa
[0];
1602 bc
->bytecode
[id
++] = cf
->isa
[1];
1603 } else if (cfop
->flags
& CF_ALU
) {
1604 bc
->bytecode
[id
++] = S_SQ_CF_ALU_WORD0_ADDR(cf
->addr
>> 1) |
1605 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf
->kcache
[0].mode
) |
1606 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf
->kcache
[0].bank
) |
1607 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf
->kcache
[1].bank
);
1609 bc
->bytecode
[id
++] = S_SQ_CF_ALU_WORD1_CF_INST(opcode
) |
1610 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf
->kcache
[1].mode
) |
1611 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf
->kcache
[0].addr
) |
1612 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf
->kcache
[1].addr
) |
1613 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1614 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc
->chip_class
== R600
? cf
->r6xx_uses_waterfall
: 0) |
1615 S_SQ_CF_ALU_WORD1_COUNT((cf
->ndw
/ 2) - 1);
1616 } else if (cfop
->flags
& CF_FETCH
) {
1617 if (bc
->chip_class
== R700
)
1618 r700_bytecode_cf_vtx_build(&bc
->bytecode
[id
], cf
);
1620 r600_bytecode_cf_vtx_build(&bc
->bytecode
[id
], cf
);
1621 } else if (cfop
->flags
& CF_EXP
) {
1622 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf
->output
.gpr
) |
1623 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf
->output
.elem_size
) |
1624 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf
->output
.array_base
) |
1625 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf
->output
.type
) |
1626 S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(cf
->output
.index_gpr
);
1627 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf
->output
.burst_count
- 1) |
1628 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf
->output
.swizzle_x
) |
1629 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf
->output
.swizzle_y
) |
1630 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf
->output
.swizzle_z
) |
1631 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf
->output
.swizzle_w
) |
1632 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf
->barrier
) |
1633 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode
) |
1634 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf
->end_of_program
);
1635 } else if (cfop
->flags
& CF_MEM
) {
1636 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf
->output
.gpr
) |
1637 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf
->output
.elem_size
) |
1638 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf
->output
.array_base
) |
1639 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf
->output
.type
) |
1640 S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(cf
->output
.index_gpr
);
1641 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf
->output
.burst_count
- 1) |
1642 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf
->barrier
) |
1643 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode
) |
1644 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf
->end_of_program
) |
1645 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf
->output
.array_size
) |
1646 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf
->output
.comp_mask
);
1648 bc
->bytecode
[id
++] = S_SQ_CF_WORD0_ADDR(cf
->cf_addr
>> 1);
1649 bc
->bytecode
[id
++] = S_SQ_CF_WORD1_CF_INST(opcode
) |
1650 S_SQ_CF_WORD1_BARRIER(1) |
1651 S_SQ_CF_WORD1_COND(cf
->cond
) |
1652 S_SQ_CF_WORD1_POP_COUNT(cf
->pop_count
) |
1653 S_SQ_CF_WORD1_END_OF_PROGRAM(cf
->end_of_program
);
1658 int r600_bytecode_build(struct r600_bytecode
*bc
)
1660 struct r600_bytecode_cf
*cf
;
1661 struct r600_bytecode_alu
*alu
;
1662 struct r600_bytecode_vtx
*vtx
;
1663 struct r600_bytecode_tex
*tex
;
1664 struct r600_bytecode_gds
*gds
;
1665 uint32_t literal
[4];
1670 if (!bc
->nstack
) // If not 0, Stack_size already provided by llvm
1671 bc
->nstack
= bc
->stack
.max_entries
;
1673 if (bc
->type
== TGSI_PROCESSOR_VERTEX
&& !bc
->nstack
) {
1677 /* first path compute addr of each CF block */
1678 /* addr start after all the CF instructions */
1679 addr
= bc
->cf_last
->id
+ 2;
1680 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
1681 if (r600_isa_cf(cf
->op
)->flags
& CF_FETCH
) {
1683 addr
&= 0xFFFFFFFCUL
;
1687 bc
->ndw
= cf
->addr
+ cf
->ndw
;
1690 bc
->bytecode
= calloc(4, bc
->ndw
);
1691 if (bc
->bytecode
== NULL
)
1693 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
1694 const struct cf_op_info
*cfop
= r600_isa_cf(cf
->op
);
1696 if (bc
->chip_class
>= EVERGREEN
)
1697 r
= eg_bytecode_cf_build(bc
, cf
);
1699 r
= r600_bytecode_cf_build(bc
, cf
);
1702 if (cfop
->flags
& CF_ALU
) {
1704 memset(literal
, 0, sizeof(literal
));
1705 LIST_FOR_EACH_ENTRY(alu
, &cf
->alu
, list
) {
1706 r
= r600_bytecode_alu_nliterals(bc
, alu
, literal
, &nliteral
);
1709 r600_bytecode_alu_adjust_literals(bc
, alu
, literal
, nliteral
);
1710 r600_bytecode_assign_kcache_banks(bc
, alu
, cf
->kcache
);
1712 switch(bc
->chip_class
) {
1714 r
= r600_bytecode_alu_build(bc
, alu
, addr
);
1717 r
= r700_bytecode_alu_build(bc
, alu
, addr
);
1721 r
= eg_bytecode_alu_build(bc
, alu
, addr
);
1724 R600_ERR("unknown chip class %d.\n", bc
->chip_class
);
1731 for (i
= 0; i
< align(nliteral
, 2); ++i
) {
1732 bc
->bytecode
[addr
++] = literal
[i
];
1735 memset(literal
, 0, sizeof(literal
));
1738 } else if (cf
->op
== CF_OP_VTX
) {
1739 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
1740 r
= r600_bytecode_vtx_build(bc
, vtx
, addr
);
1745 } else if (cf
->op
== CF_OP_GDS
) {
1746 assert(bc
->chip_class
>= EVERGREEN
);
1747 LIST_FOR_EACH_ENTRY(gds
, &cf
->gds
, list
) {
1748 r
= eg_bytecode_gds_build(bc
, gds
, addr
);
1753 } else if (cf
->op
== CF_OP_TEX
) {
1754 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
1755 assert(bc
->chip_class
>= EVERGREEN
);
1756 r
= r600_bytecode_vtx_build(bc
, vtx
, addr
);
1761 LIST_FOR_EACH_ENTRY(tex
, &cf
->tex
, list
) {
1762 r
= r600_bytecode_tex_build(bc
, tex
, addr
);
1772 void r600_bytecode_clear(struct r600_bytecode
*bc
)
1774 struct r600_bytecode_cf
*cf
= NULL
, *next_cf
;
1777 bc
->bytecode
= NULL
;
1779 LIST_FOR_EACH_ENTRY_SAFE(cf
, next_cf
, &bc
->cf
, list
) {
1780 struct r600_bytecode_alu
*alu
= NULL
, *next_alu
;
1781 struct r600_bytecode_tex
*tex
= NULL
, *next_tex
;
1782 struct r600_bytecode_tex
*vtx
= NULL
, *next_vtx
;
1783 struct r600_bytecode_gds
*gds
= NULL
, *next_gds
;
1785 LIST_FOR_EACH_ENTRY_SAFE(alu
, next_alu
, &cf
->alu
, list
) {
1789 LIST_INITHEAD(&cf
->alu
);
1791 LIST_FOR_EACH_ENTRY_SAFE(tex
, next_tex
, &cf
->tex
, list
) {
1795 LIST_INITHEAD(&cf
->tex
);
1797 LIST_FOR_EACH_ENTRY_SAFE(vtx
, next_vtx
, &cf
->vtx
, list
) {
1801 LIST_INITHEAD(&cf
->vtx
);
1803 LIST_FOR_EACH_ENTRY_SAFE(gds
, next_gds
, &cf
->gds
, list
) {
1807 LIST_INITHEAD(&cf
->gds
);
1812 LIST_INITHEAD(&cf
->list
);
1815 static int print_swizzle(unsigned swz
)
1817 const char * swzchars
= "xyzw01?_";
1818 assert(swz
<8 && swz
!= 6);
1819 return fprintf(stderr
, "%c", swzchars
[swz
]);
1822 static int print_sel(unsigned sel
, unsigned rel
, unsigned index_mode
,
1823 unsigned need_brackets
)
1826 if (rel
&& index_mode
>= 5 && sel
< 128)
1827 o
+= fprintf(stderr
, "G");
1828 if (rel
|| need_brackets
) {
1829 o
+= fprintf(stderr
, "[");
1831 o
+= fprintf(stderr
, "%d", sel
);
1833 if (index_mode
== 0 || index_mode
== 6)
1834 o
+= fprintf(stderr
, "+AR");
1835 else if (index_mode
== 4)
1836 o
+= fprintf(stderr
, "+AL");
1838 if (rel
|| need_brackets
) {
1839 o
+= fprintf(stderr
, "]");
1844 static int print_dst(struct r600_bytecode_alu
*alu
)
1847 unsigned sel
= alu
->dst
.sel
;
1848 char reg_char
= 'R';
1849 if (sel
> 128 - 4) { /* clause temporary gpr */
1854 if (alu_writes(alu
)) {
1855 o
+= fprintf(stderr
, "%c", reg_char
);
1856 o
+= print_sel(alu
->dst
.sel
, alu
->dst
.rel
, alu
->index_mode
, 0);
1858 o
+= fprintf(stderr
, "__");
1860 o
+= fprintf(stderr
, ".");
1861 o
+= print_swizzle(alu
->dst
.chan
);
1865 static int print_src(struct r600_bytecode_alu
*alu
, unsigned idx
)
1868 struct r600_bytecode_alu_src
*src
= &alu
->src
[idx
];
1869 unsigned sel
= src
->sel
, need_sel
= 1, need_chan
= 1, need_brackets
= 0;
1872 o
+= fprintf(stderr
,"-");
1874 o
+= fprintf(stderr
,"|");
1876 if (sel
< 128 - 4) {
1877 o
+= fprintf(stderr
, "R");
1878 } else if (sel
< 128) {
1879 o
+= fprintf(stderr
, "T");
1881 } else if (sel
< 160) {
1882 o
+= fprintf(stderr
, "KC0");
1885 } else if (sel
< 192) {
1886 o
+= fprintf(stderr
, "KC1");
1889 } else if (sel
>= 512) {
1890 o
+= fprintf(stderr
, "C%d", src
->kc_bank
);
1893 } else if (sel
>= 448) {
1894 o
+= fprintf(stderr
, "Param");
1897 } else if (sel
>= 288) {
1898 o
+= fprintf(stderr
, "KC3");
1901 } else if (sel
>= 256) {
1902 o
+= fprintf(stderr
, "KC2");
1909 case EG_V_SQ_ALU_SRC_LDS_DIRECT_A
:
1910 o
+= fprintf(stderr
, "LDS_A[0x%08X]", src
->value
);
1912 case EG_V_SQ_ALU_SRC_LDS_DIRECT_B
:
1913 o
+= fprintf(stderr
, "LDS_B[0x%08X]", src
->value
);
1915 case EG_V_SQ_ALU_SRC_LDS_OQ_A
:
1916 o
+= fprintf(stderr
, "LDS_OQ_A");
1919 case EG_V_SQ_ALU_SRC_LDS_OQ_B
:
1920 o
+= fprintf(stderr
, "LDS_OQ_B");
1923 case EG_V_SQ_ALU_SRC_LDS_OQ_A_POP
:
1924 o
+= fprintf(stderr
, "LDS_OQ_A_POP");
1927 case EG_V_SQ_ALU_SRC_LDS_OQ_B_POP
:
1928 o
+= fprintf(stderr
, "LDS_OQ_B_POP");
1931 case V_SQ_ALU_SRC_PS
:
1932 o
+= fprintf(stderr
, "PS");
1934 case V_SQ_ALU_SRC_PV
:
1935 o
+= fprintf(stderr
, "PV");
1938 case V_SQ_ALU_SRC_LITERAL
:
1939 o
+= fprintf(stderr
, "[0x%08X %f]", src
->value
, *(float*)&src
->value
);
1941 case V_SQ_ALU_SRC_0_5
:
1942 o
+= fprintf(stderr
, "0.5");
1944 case V_SQ_ALU_SRC_M_1_INT
:
1945 o
+= fprintf(stderr
, "-1");
1947 case V_SQ_ALU_SRC_1_INT
:
1948 o
+= fprintf(stderr
, "1");
1950 case V_SQ_ALU_SRC_1
:
1951 o
+= fprintf(stderr
, "1.0");
1953 case V_SQ_ALU_SRC_0
:
1954 o
+= fprintf(stderr
, "0");
1957 o
+= fprintf(stderr
, "??IMM_%d", sel
);
1963 o
+= print_sel(sel
, src
->rel
, alu
->index_mode
, need_brackets
);
1966 o
+= fprintf(stderr
, ".");
1967 o
+= print_swizzle(src
->chan
);
1971 o
+= fprintf(stderr
,"|");
1976 static int print_indent(int p
, int c
)
1980 o
+= fprintf(stderr
, " ");
1984 void r600_bytecode_disasm(struct r600_bytecode
*bc
)
1986 const char *index_mode
[] = {"CF_INDEX_NONE", "CF_INDEX_0", "CF_INDEX_1"};
1987 static int index
= 0;
1988 struct r600_bytecode_cf
*cf
= NULL
;
1989 struct r600_bytecode_alu
*alu
= NULL
;
1990 struct r600_bytecode_vtx
*vtx
= NULL
;
1991 struct r600_bytecode_tex
*tex
= NULL
;
1992 struct r600_bytecode_gds
*gds
= NULL
;
1994 unsigned i
, id
, ngr
= 0, last
;
1995 uint32_t literal
[4];
1999 switch (bc
->chip_class
) {
2014 fprintf(stderr
, "bytecode %d dw -- %d gprs -- %d nstack -------------\n",
2015 bc
->ndw
, bc
->ngpr
, bc
->nstack
);
2016 fprintf(stderr
, "shader %d -- %c\n", index
++, chip
);
2018 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
2020 if (cf
->op
== CF_NATIVE
) {
2021 fprintf(stderr
, "%04d %08X %08X CF_NATIVE\n", id
, bc
->bytecode
[id
],
2022 bc
->bytecode
[id
+ 1]);
2024 const struct cf_op_info
*cfop
= r600_isa_cf(cf
->op
);
2025 if (cfop
->flags
& CF_ALU
) {
2026 if (cf
->eg_alu_extended
) {
2027 fprintf(stderr
, "%04d %08X %08X %s\n", id
, bc
->bytecode
[id
],
2028 bc
->bytecode
[id
+ 1], "ALU_EXT");
2031 fprintf(stderr
, "%04d %08X %08X %s ", id
, bc
->bytecode
[id
],
2032 bc
->bytecode
[id
+ 1], cfop
->name
);
2033 fprintf(stderr
, "%d @%d ", cf
->ndw
/ 2, cf
->addr
);
2034 for (i
= 0; i
< 4; ++i
) {
2035 if (cf
->kcache
[i
].mode
) {
2036 int c_start
= (cf
->kcache
[i
].addr
<< 4);
2037 int c_end
= c_start
+ (cf
->kcache
[i
].mode
<< 4);
2038 fprintf(stderr
, "KC%d[CB%d:%d-%d%s%s] ",
2039 i
, cf
->kcache
[i
].bank
, c_start
, c_end
,
2040 cf
->kcache
[i
].index_mode
? " " : "",
2041 cf
->kcache
[i
].index_mode
? index_mode
[cf
->kcache
[i
].index_mode
] : "");
2044 fprintf(stderr
, "\n");
2045 } else if (cfop
->flags
& CF_FETCH
) {
2046 fprintf(stderr
, "%04d %08X %08X %s ", id
, bc
->bytecode
[id
],
2047 bc
->bytecode
[id
+ 1], cfop
->name
);
2048 fprintf(stderr
, "%d @%d ", cf
->ndw
/ 4, cf
->addr
);
2049 fprintf(stderr
, "\n");
2050 } else if (cfop
->flags
& CF_EXP
) {
2052 const char *exp_type
[] = {"PIXEL", "POS ", "PARAM"};
2053 o
+= fprintf(stderr
, "%04d %08X %08X %s ", id
, bc
->bytecode
[id
],
2054 bc
->bytecode
[id
+ 1], cfop
->name
);
2055 o
+= print_indent(o
, 43);
2056 o
+= fprintf(stderr
, "%s ", exp_type
[cf
->output
.type
]);
2057 if (cf
->output
.burst_count
> 1) {
2058 o
+= fprintf(stderr
, "%d-%d ", cf
->output
.array_base
,
2059 cf
->output
.array_base
+ cf
->output
.burst_count
- 1);
2061 o
+= print_indent(o
, 55);
2062 o
+= fprintf(stderr
, "R%d-%d.", cf
->output
.gpr
,
2063 cf
->output
.gpr
+ cf
->output
.burst_count
- 1);
2065 o
+= fprintf(stderr
, "%d ", cf
->output
.array_base
);
2066 o
+= print_indent(o
, 55);
2067 o
+= fprintf(stderr
, "R%d.", cf
->output
.gpr
);
2070 o
+= print_swizzle(cf
->output
.swizzle_x
);
2071 o
+= print_swizzle(cf
->output
.swizzle_y
);
2072 o
+= print_swizzle(cf
->output
.swizzle_z
);
2073 o
+= print_swizzle(cf
->output
.swizzle_w
);
2075 print_indent(o
, 67);
2077 fprintf(stderr
, " ES:%X ", cf
->output
.elem_size
);
2079 fprintf(stderr
, "NO_BARRIER ");
2080 if (cf
->end_of_program
)
2081 fprintf(stderr
, "EOP ");
2082 fprintf(stderr
, "\n");
2083 } else if (r600_isa_cf(cf
->op
)->flags
& CF_MEM
) {
2085 const char *exp_type
[] = {"WRITE", "WRITE_IND", "WRITE_ACK",
2087 o
+= fprintf(stderr
, "%04d %08X %08X %s ", id
,
2088 bc
->bytecode
[id
], bc
->bytecode
[id
+ 1], cfop
->name
);
2089 o
+= print_indent(o
, 43);
2090 o
+= fprintf(stderr
, "%s ", exp_type
[cf
->output
.type
]);
2091 if (cf
->output
.burst_count
> 1) {
2092 o
+= fprintf(stderr
, "%d-%d ", cf
->output
.array_base
,
2093 cf
->output
.array_base
+ cf
->output
.burst_count
- 1);
2094 o
+= print_indent(o
, 55);
2095 o
+= fprintf(stderr
, "R%d-%d.", cf
->output
.gpr
,
2096 cf
->output
.gpr
+ cf
->output
.burst_count
- 1);
2098 o
+= fprintf(stderr
, "%d ", cf
->output
.array_base
);
2099 o
+= print_indent(o
, 55);
2100 o
+= fprintf(stderr
, "R%d.", cf
->output
.gpr
);
2102 for (i
= 0; i
< 4; ++i
) {
2103 if (cf
->output
.comp_mask
& (1 << i
))
2104 o
+= print_swizzle(i
);
2106 o
+= print_swizzle(7);
2109 if (cf
->output
.type
== V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND
)
2110 o
+= fprintf(stderr
, " R%d", cf
->output
.index_gpr
);
2112 o
+= print_indent(o
, 67);
2114 fprintf(stderr
, " ES:%i ", cf
->output
.elem_size
);
2115 if (cf
->output
.array_size
!= 0xFFF)
2116 fprintf(stderr
, "AS:%i ", cf
->output
.array_size
);
2118 fprintf(stderr
, "NO_BARRIER ");
2119 if (cf
->end_of_program
)
2120 fprintf(stderr
, "EOP ");
2121 fprintf(stderr
, "\n");
2123 fprintf(stderr
, "%04d %08X %08X %s ", id
, bc
->bytecode
[id
],
2124 bc
->bytecode
[id
+ 1], cfop
->name
);
2125 fprintf(stderr
, "@%d ", cf
->cf_addr
);
2127 fprintf(stderr
, "CND:%X ", cf
->cond
);
2129 fprintf(stderr
, "POP:%X ", cf
->pop_count
);
2130 if (cf
->count
&& (cfop
->flags
& CF_EMIT
))
2131 fprintf(stderr
, "STREAM%d ", cf
->count
);
2132 if (cf
->end_of_program
)
2133 fprintf(stderr
, "EOP ");
2134 fprintf(stderr
, "\n");
2141 LIST_FOR_EACH_ENTRY(alu
, &cf
->alu
, list
) {
2142 const char *omod_str
[] = {"","*2","*4","/2"};
2143 const struct alu_op_info
*aop
= r600_isa_alu(alu
->op
);
2146 r600_bytecode_alu_nliterals(bc
, alu
, literal
, &nliteral
);
2147 o
+= fprintf(stderr
, " %04d %08X %08X ", id
, bc
->bytecode
[id
], bc
->bytecode
[id
+1]);
2149 o
+= fprintf(stderr
, "%4d ", ++ngr
);
2151 o
+= fprintf(stderr
, " ");
2152 o
+= fprintf(stderr
, "%c%c %c ", alu
->execute_mask
? 'M':' ',
2153 alu
->update_pred
? 'P':' ',
2154 alu
->pred_sel
? alu
->pred_sel
==2 ? '0':'1':' ');
2156 o
+= fprintf(stderr
, "%s%s%s ", aop
->name
,
2157 omod_str
[alu
->omod
], alu
->dst
.clamp
? "_sat":"");
2159 o
+= print_indent(o
,60);
2160 o
+= print_dst(alu
);
2161 for (i
= 0; i
< aop
->src_count
; ++i
) {
2162 o
+= fprintf(stderr
, i
== 0 ? ", ": ", ");
2163 o
+= print_src(alu
, i
);
2166 if (alu
->bank_swizzle
) {
2167 o
+= print_indent(o
,75);
2168 o
+= fprintf(stderr
, " BS:%d", alu
->bank_swizzle
);
2171 fprintf(stderr
, "\n");
2175 for (i
= 0; i
< nliteral
; i
++, id
++) {
2176 float *f
= (float*)(bc
->bytecode
+ id
);
2177 o
= fprintf(stderr
, " %04d %08X", id
, bc
->bytecode
[id
]);
2178 print_indent(o
, 60);
2179 fprintf(stderr
, " %f (%d)\n", *f
, *(bc
->bytecode
+ id
));
2187 LIST_FOR_EACH_ENTRY(tex
, &cf
->tex
, list
) {
2189 o
+= fprintf(stderr
, " %04d %08X %08X %08X ", id
, bc
->bytecode
[id
],
2190 bc
->bytecode
[id
+ 1], bc
->bytecode
[id
+ 2]);
2192 o
+= fprintf(stderr
, "%s ", r600_isa_fetch(tex
->op
)->name
);
2194 o
+= print_indent(o
, 50);
2196 o
+= fprintf(stderr
, "R%d.", tex
->dst_gpr
);
2197 o
+= print_swizzle(tex
->dst_sel_x
);
2198 o
+= print_swizzle(tex
->dst_sel_y
);
2199 o
+= print_swizzle(tex
->dst_sel_z
);
2200 o
+= print_swizzle(tex
->dst_sel_w
);
2202 o
+= fprintf(stderr
, ", R%d.", tex
->src_gpr
);
2203 o
+= print_swizzle(tex
->src_sel_x
);
2204 o
+= print_swizzle(tex
->src_sel_y
);
2205 o
+= print_swizzle(tex
->src_sel_z
);
2206 o
+= print_swizzle(tex
->src_sel_w
);
2208 o
+= fprintf(stderr
, ", RID:%d", tex
->resource_id
);
2209 o
+= fprintf(stderr
, ", SID:%d ", tex
->sampler_id
);
2211 if (tex
->sampler_index_mode
)
2212 fprintf(stderr
, "SQ_%s ", index_mode
[tex
->sampler_index_mode
]);
2215 fprintf(stderr
, "LB:%d ", tex
->lod_bias
);
2217 fprintf(stderr
, "CT:%c%c%c%c ",
2218 tex
->coord_type_x
? 'N' : 'U',
2219 tex
->coord_type_y
? 'N' : 'U',
2220 tex
->coord_type_z
? 'N' : 'U',
2221 tex
->coord_type_w
? 'N' : 'U');
2224 fprintf(stderr
, "OX:%d ", tex
->offset_x
);
2226 fprintf(stderr
, "OY:%d ", tex
->offset_y
);
2228 fprintf(stderr
, "OZ:%d ", tex
->offset_z
);
2231 fprintf(stderr
, "\n");
2234 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
2236 const char * fetch_type
[] = {"VERTEX", "INSTANCE", ""};
2237 o
+= fprintf(stderr
, " %04d %08X %08X %08X ", id
, bc
->bytecode
[id
],
2238 bc
->bytecode
[id
+ 1], bc
->bytecode
[id
+ 2]);
2240 o
+= fprintf(stderr
, "%s ", r600_isa_fetch(vtx
->op
)->name
);
2242 o
+= print_indent(o
, 50);
2244 o
+= fprintf(stderr
, "R%d.", vtx
->dst_gpr
);
2245 o
+= print_swizzle(vtx
->dst_sel_x
);
2246 o
+= print_swizzle(vtx
->dst_sel_y
);
2247 o
+= print_swizzle(vtx
->dst_sel_z
);
2248 o
+= print_swizzle(vtx
->dst_sel_w
);
2250 o
+= fprintf(stderr
, ", R%d.", vtx
->src_gpr
);
2251 o
+= print_swizzle(vtx
->src_sel_x
);
2254 fprintf(stderr
, " +%db", vtx
->offset
);
2256 o
+= print_indent(o
, 55);
2258 fprintf(stderr
, ", RID:%d ", vtx
->buffer_id
);
2260 fprintf(stderr
, "%s ", fetch_type
[vtx
->fetch_type
]);
2262 if (bc
->chip_class
< CAYMAN
&& vtx
->mega_fetch_count
)
2263 fprintf(stderr
, "MFC:%d ", vtx
->mega_fetch_count
);
2265 if (bc
->chip_class
>= EVERGREEN
&& vtx
->buffer_index_mode
)
2266 fprintf(stderr
, "SQ_%s ", index_mode
[vtx
->buffer_index_mode
]);
2268 fprintf(stderr
, "UCF:%d ", vtx
->use_const_fields
);
2269 fprintf(stderr
, "FMT(DTA:%d ", vtx
->data_format
);
2270 fprintf(stderr
, "NUM:%d ", vtx
->num_format_all
);
2271 fprintf(stderr
, "COMP:%d ", vtx
->format_comp_all
);
2272 fprintf(stderr
, "MODE:%d)\n", vtx
->srf_mode_all
);
2277 LIST_FOR_EACH_ENTRY(gds
, &cf
->gds
, list
) {
2279 o
+= fprintf(stderr
, " %04d %08X %08X %08X ", id
, bc
->bytecode
[id
],
2280 bc
->bytecode
[id
+ 1], bc
->bytecode
[id
+ 2]);
2282 o
+= fprintf(stderr
, "%s ", r600_isa_fetch(gds
->op
)->name
);
2284 if (gds
->op
!= FETCH_OP_TF_WRITE
) {
2285 o
+= fprintf(stderr
, "R%d.", gds
->dst_gpr
);
2286 o
+= print_swizzle(gds
->dst_sel_x
);
2287 o
+= print_swizzle(gds
->dst_sel_y
);
2288 o
+= print_swizzle(gds
->dst_sel_z
);
2289 o
+= print_swizzle(gds
->dst_sel_w
);
2292 o
+= fprintf(stderr
, ", R%d.", gds
->src_gpr
);
2293 o
+= print_swizzle(gds
->src_sel_x
);
2294 o
+= print_swizzle(gds
->src_sel_y
);
2295 o
+= print_swizzle(gds
->src_sel_z
);
2297 if (gds
->op
!= FETCH_OP_TF_WRITE
) {
2298 o
+= fprintf(stderr
, ", R%d.", gds
->src_gpr2
);
2300 fprintf(stderr
, "\n");
2305 fprintf(stderr
, "--------------------------------------\n");
2308 void r600_vertex_data_type(enum pipe_format pformat
,
2310 unsigned *num_format
, unsigned *format_comp
, unsigned *endian
)
2312 const struct util_format_description
*desc
;
2318 *endian
= ENDIAN_NONE
;
2320 if (pformat
== PIPE_FORMAT_R11G11B10_FLOAT
) {
2321 *format
= FMT_10_11_11_FLOAT
;
2322 *endian
= r600_endian_swap(32);
2326 desc
= util_format_description(pformat
);
2327 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
) {
2331 /* Find the first non-VOID channel. */
2332 for (i
= 0; i
< 4; i
++) {
2333 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2338 *endian
= r600_endian_swap(desc
->channel
[i
].size
);
2340 switch (desc
->channel
[i
].type
) {
2341 /* Half-floats, floats, ints */
2342 case UTIL_FORMAT_TYPE_FLOAT
:
2343 switch (desc
->channel
[i
].size
) {
2345 switch (desc
->nr_channels
) {
2347 *format
= FMT_16_FLOAT
;
2350 *format
= FMT_16_16_FLOAT
;
2354 *format
= FMT_16_16_16_16_FLOAT
;
2359 switch (desc
->nr_channels
) {
2361 *format
= FMT_32_FLOAT
;
2364 *format
= FMT_32_32_FLOAT
;
2367 *format
= FMT_32_32_32_FLOAT
;
2370 *format
= FMT_32_32_32_32_FLOAT
;
2379 case UTIL_FORMAT_TYPE_UNSIGNED
:
2381 case UTIL_FORMAT_TYPE_SIGNED
:
2382 switch (desc
->channel
[i
].size
) {
2384 switch (desc
->nr_channels
) {
2393 *format
= FMT_8_8_8_8
;
2398 if (desc
->nr_channels
!= 4)
2401 *format
= FMT_2_10_10_10
;
2404 switch (desc
->nr_channels
) {
2409 *format
= FMT_16_16
;
2413 *format
= FMT_16_16_16_16
;
2418 switch (desc
->nr_channels
) {
2423 *format
= FMT_32_32
;
2426 *format
= FMT_32_32_32
;
2429 *format
= FMT_32_32_32_32
;
2441 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2446 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
||
2447 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2448 if (!desc
->channel
[i
].normalized
) {
2449 if (desc
->channel
[i
].pure_integer
)
2457 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat
));
2460 void *r600_create_vertex_fetch_shader(struct pipe_context
*ctx
,
2462 const struct pipe_vertex_element
*elements
)
2464 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2465 struct r600_bytecode bc
;
2466 struct r600_bytecode_vtx vtx
;
2467 const struct util_format_description
*desc
;
2468 unsigned fetch_resource_start
= rctx
->b
.chip_class
>= EVERGREEN
? 0 : 160;
2469 unsigned format
, num_format
, format_comp
, endian
;
2471 int i
, j
, r
, fs_size
;
2472 struct r600_fetch_shader
*shader
;
2473 unsigned no_sb
= rctx
->screen
->b
.debug_flags
& DBG_NO_SB
;
2474 unsigned sb_disasm
= !no_sb
|| (rctx
->screen
->b
.debug_flags
& DBG_SB_DISASM
);
2478 memset(&bc
, 0, sizeof(bc
));
2479 r600_bytecode_init(&bc
, rctx
->b
.chip_class
, rctx
->b
.family
,
2480 rctx
->screen
->has_compressed_msaa_texturing
);
2484 for (i
= 0; i
< count
; i
++) {
2485 if (elements
[i
].instance_divisor
> 1) {
2486 if (rctx
->b
.chip_class
== CAYMAN
) {
2487 for (j
= 0; j
< 4; j
++) {
2488 struct r600_bytecode_alu alu
;
2489 memset(&alu
, 0, sizeof(alu
));
2490 alu
.op
= ALU_OP2_MULHI_UINT
;
2492 alu
.src
[0].chan
= 3;
2493 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2494 alu
.src
[1].value
= (1ll << 32) / elements
[i
].instance_divisor
+ 1;
2495 alu
.dst
.sel
= i
+ 1;
2497 alu
.dst
.write
= j
== 3;
2499 if ((r
= r600_bytecode_add_alu(&bc
, &alu
))) {
2500 r600_bytecode_clear(&bc
);
2505 struct r600_bytecode_alu alu
;
2506 memset(&alu
, 0, sizeof(alu
));
2507 alu
.op
= ALU_OP2_MULHI_UINT
;
2509 alu
.src
[0].chan
= 3;
2510 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2511 alu
.src
[1].value
= (1ll << 32) / elements
[i
].instance_divisor
+ 1;
2512 alu
.dst
.sel
= i
+ 1;
2516 if ((r
= r600_bytecode_add_alu(&bc
, &alu
))) {
2517 r600_bytecode_clear(&bc
);
2524 for (i
= 0; i
< count
; i
++) {
2525 r600_vertex_data_type(elements
[i
].src_format
,
2526 &format
, &num_format
, &format_comp
, &endian
);
2528 desc
= util_format_description(elements
[i
].src_format
);
2530 r600_bytecode_clear(&bc
);
2531 R600_ERR("unknown format %d\n", elements
[i
].src_format
);
2535 if (elements
[i
].src_offset
> 65535) {
2536 r600_bytecode_clear(&bc
);
2537 R600_ERR("too big src_offset: %u\n", elements
[i
].src_offset
);
2541 memset(&vtx
, 0, sizeof(vtx
));
2542 vtx
.buffer_id
= elements
[i
].vertex_buffer_index
+ fetch_resource_start
;
2543 vtx
.fetch_type
= elements
[i
].instance_divisor
? SQ_VTX_FETCH_INSTANCE_DATA
: SQ_VTX_FETCH_VERTEX_DATA
;
2544 vtx
.src_gpr
= elements
[i
].instance_divisor
> 1 ? i
+ 1 : 0;
2545 vtx
.src_sel_x
= elements
[i
].instance_divisor
? 3 : 0;
2546 vtx
.mega_fetch_count
= 0x1F;
2547 vtx
.dst_gpr
= i
+ 1;
2548 vtx
.dst_sel_x
= desc
->swizzle
[0];
2549 vtx
.dst_sel_y
= desc
->swizzle
[1];
2550 vtx
.dst_sel_z
= desc
->swizzle
[2];
2551 vtx
.dst_sel_w
= desc
->swizzle
[3];
2552 vtx
.data_format
= format
;
2553 vtx
.num_format_all
= num_format
;
2554 vtx
.format_comp_all
= format_comp
;
2555 vtx
.offset
= elements
[i
].src_offset
;
2556 vtx
.endian
= endian
;
2558 if ((r
= r600_bytecode_add_vtx(&bc
, &vtx
))) {
2559 r600_bytecode_clear(&bc
);
2564 r600_bytecode_add_cfinst(&bc
, CF_OP_RET
);
2566 if ((r
= r600_bytecode_build(&bc
))) {
2567 r600_bytecode_clear(&bc
);
2571 if (rctx
->screen
->b
.debug_flags
& DBG_FS
) {
2572 fprintf(stderr
, "--------------------------------------------------------------\n");
2573 fprintf(stderr
, "Vertex elements state:\n");
2574 for (i
= 0; i
< count
; i
++) {
2575 fprintf(stderr
, " ");
2576 util_dump_vertex_element(stderr
, elements
+i
);
2577 fprintf(stderr
, "\n");
2581 r600_bytecode_disasm(&bc
);
2583 fprintf(stderr
, "______________________________________________________________\n");
2585 r600_sb_bytecode_process(rctx
, &bc
, NULL
, 1 /*dump*/, 0 /*optimize*/);
2591 /* Allocate the CSO. */
2592 shader
= CALLOC_STRUCT(r600_fetch_shader
);
2594 r600_bytecode_clear(&bc
);
2598 u_suballocator_alloc(rctx
->allocator_fetch_shader
, fs_size
, &shader
->offset
,
2599 (struct pipe_resource
**)&shader
->buffer
);
2600 if (!shader
->buffer
) {
2601 r600_bytecode_clear(&bc
);
2606 bytecode
= r600_buffer_map_sync_with_rings(&rctx
->b
, shader
->buffer
, PIPE_TRANSFER_WRITE
| PIPE_TRANSFER_UNSYNCHRONIZED
);
2607 bytecode
+= shader
->offset
/ 4;
2609 if (R600_BIG_ENDIAN
) {
2610 for (i
= 0; i
< fs_size
/ 4; ++i
) {
2611 bytecode
[i
] = util_cpu_to_le32(bc
.bytecode
[i
]);
2614 memcpy(bytecode
, bc
.bytecode
, fs_size
);
2616 rctx
->b
.ws
->buffer_unmap(shader
->buffer
->cs_buf
);
2618 r600_bytecode_clear(&bc
);
2622 void r600_bytecode_alu_read(struct r600_bytecode
*bc
,
2623 struct r600_bytecode_alu
*alu
, uint32_t word0
, uint32_t word1
)
2626 alu
->src
[0].sel
= G_SQ_ALU_WORD0_SRC0_SEL(word0
);
2627 alu
->src
[0].rel
= G_SQ_ALU_WORD0_SRC0_REL(word0
);
2628 alu
->src
[0].chan
= G_SQ_ALU_WORD0_SRC0_CHAN(word0
);
2629 alu
->src
[0].neg
= G_SQ_ALU_WORD0_SRC0_NEG(word0
);
2630 alu
->src
[1].sel
= G_SQ_ALU_WORD0_SRC1_SEL(word0
);
2631 alu
->src
[1].rel
= G_SQ_ALU_WORD0_SRC1_REL(word0
);
2632 alu
->src
[1].chan
= G_SQ_ALU_WORD0_SRC1_CHAN(word0
);
2633 alu
->src
[1].neg
= G_SQ_ALU_WORD0_SRC1_NEG(word0
);
2634 alu
->index_mode
= G_SQ_ALU_WORD0_INDEX_MODE(word0
);
2635 alu
->pred_sel
= G_SQ_ALU_WORD0_PRED_SEL(word0
);
2636 alu
->last
= G_SQ_ALU_WORD0_LAST(word0
);
2639 alu
->bank_swizzle
= G_SQ_ALU_WORD1_BANK_SWIZZLE(word1
);
2640 if (alu
->bank_swizzle
)
2641 alu
->bank_swizzle_force
= alu
->bank_swizzle
;
2642 alu
->dst
.sel
= G_SQ_ALU_WORD1_DST_GPR(word1
);
2643 alu
->dst
.rel
= G_SQ_ALU_WORD1_DST_REL(word1
);
2644 alu
->dst
.chan
= G_SQ_ALU_WORD1_DST_CHAN(word1
);
2645 alu
->dst
.clamp
= G_SQ_ALU_WORD1_CLAMP(word1
);
2646 if (G_SQ_ALU_WORD1_ENCODING(word1
)) /*ALU_DWORD1_OP3*/
2649 alu
->src
[2].sel
= G_SQ_ALU_WORD1_OP3_SRC2_SEL(word1
);
2650 alu
->src
[2].rel
= G_SQ_ALU_WORD1_OP3_SRC2_REL(word1
);
2651 alu
->src
[2].chan
= G_SQ_ALU_WORD1_OP3_SRC2_CHAN(word1
);
2652 alu
->src
[2].neg
= G_SQ_ALU_WORD1_OP3_SRC2_NEG(word1
);
2653 alu
->op
= r600_isa_alu_by_opcode(bc
->isa
,
2654 G_SQ_ALU_WORD1_OP3_ALU_INST(word1
), /* is_op3 = */ 1);
2657 else /*ALU_DWORD1_OP2*/
2659 alu
->src
[0].abs
= G_SQ_ALU_WORD1_OP2_SRC0_ABS(word1
);
2660 alu
->src
[1].abs
= G_SQ_ALU_WORD1_OP2_SRC1_ABS(word1
);
2661 alu
->op
= r600_isa_alu_by_opcode(bc
->isa
,
2662 G_SQ_ALU_WORD1_OP2_ALU_INST(word1
), /* is_op3 = */ 0);
2663 alu
->omod
= G_SQ_ALU_WORD1_OP2_OMOD(word1
);
2664 alu
->dst
.write
= G_SQ_ALU_WORD1_OP2_WRITE_MASK(word1
);
2665 alu
->update_pred
= G_SQ_ALU_WORD1_OP2_UPDATE_PRED(word1
);
2667 G_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(word1
);
2672 void r600_bytecode_export_read(struct r600_bytecode
*bc
,
2673 struct r600_bytecode_output
*output
, uint32_t word0
, uint32_t word1
)
2675 output
->array_base
= G_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(word0
);
2676 output
->type
= G_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(word0
);
2677 output
->gpr
= G_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(word0
);
2678 output
->elem_size
= G_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(word0
);
2680 output
->swizzle_x
= G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(word1
);
2681 output
->swizzle_y
= G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(word1
);
2682 output
->swizzle_z
= G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(word1
);
2683 output
->swizzle_w
= G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(word1
);
2684 output
->burst_count
= G_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(word1
);
2685 output
->end_of_program
= G_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(word1
);
2686 output
->op
= r600_isa_cf_by_opcode(bc
->isa
,
2687 G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(word1
), 0);
2688 output
->barrier
= G_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(word1
);
2689 output
->array_size
= G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(word1
);
2690 output
->comp_mask
= G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(word1
);