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r600g: make if's use PRED_SETNE_INT no matter what.
[mesa.git] / src / gallium / drivers / r600 / r600_asm.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include <stdio.h>
24 #include <errno.h>
25 #include <byteswap.h>
26 #include "util/u_format.h"
27 #include "util/u_memory.h"
28 #include "pipe/p_shader_tokens.h"
29 #include "r600_pipe.h"
30 #include "r600_sq.h"
31 #include "r600_opcodes.h"
32 #include "r600_asm.h"
33 #include "r600_formats.h"
34 #include "r600d.h"
35
36 #define NUM_OF_CYCLES 3
37 #define NUM_OF_COMPONENTS 4
38
39 static inline unsigned int r600_bytecode_get_num_operands(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
40 {
41 if(alu->is_op3)
42 return 3;
43
44 switch (bc->chip_class) {
45 case R600:
46 case R700:
47 switch (alu->inst) {
48 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
49 return 0;
50 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
51 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT:
52 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT:
53 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
54 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
55 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
56 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
57 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
58 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT:
59 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT:
60 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT:
61 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT:
62 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
63 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
64 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
65 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
66 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
67 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
68 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
69 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
70 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
71 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
72 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
73 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
74 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
75 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT:
76 return 2;
77
78 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
79 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA:
80 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR:
81 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
82 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
83 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
84 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
85 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
86 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
87 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
88 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
89 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
90 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
91 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
92 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
93 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT:
94 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
95 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
96 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE:
97 return 1;
98 default: R600_ERR(
99 "Need instruction operand number for 0x%x.\n", alu->inst);
100 }
101 break;
102 case EVERGREEN:
103 case CAYMAN:
104 switch (alu->inst) {
105 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
106 return 0;
107 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
108 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT:
109 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT:
110 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT:
111 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT:
112 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
113 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
114 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
115 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
116 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
117 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT:
118 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT:
119 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT:
120 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT:
121 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
122 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
123 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT:
124 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT:
125 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT:
126 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT:
127 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
128 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT:
129 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
130 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT:
131 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
132 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT:
133 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT:
134 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
135 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT:
136 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT:
137 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
138 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
139 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
140 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
141 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT:
142 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
143 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
144 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
145 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY:
146 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW:
147 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT:
148 return 2;
149
150 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
151 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
152 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
153 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
154 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
155 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
156 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
157 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
158 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
159 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
160 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
161 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
162 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
163 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR:
164 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT:
165 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
166 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
167 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE:
168 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT:
169 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_LOAD_P0:
170 return 1;
171 default: R600_ERR(
172 "Need instruction operand number for 0x%x.\n", alu->inst);
173 }
174 break;
175 }
176
177 return 3;
178 }
179
180 int r700_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id);
181
182 static struct r600_bytecode_cf *r600_bytecode_cf(void)
183 {
184 struct r600_bytecode_cf *cf = CALLOC_STRUCT(r600_bytecode_cf);
185
186 if (cf == NULL)
187 return NULL;
188 LIST_INITHEAD(&cf->list);
189 LIST_INITHEAD(&cf->alu);
190 LIST_INITHEAD(&cf->vtx);
191 LIST_INITHEAD(&cf->tex);
192 return cf;
193 }
194
195 static struct r600_bytecode_alu *r600_bytecode_alu(void)
196 {
197 struct r600_bytecode_alu *alu = CALLOC_STRUCT(r600_bytecode_alu);
198
199 if (alu == NULL)
200 return NULL;
201 LIST_INITHEAD(&alu->list);
202 return alu;
203 }
204
205 static struct r600_bytecode_vtx *r600_bytecode_vtx(void)
206 {
207 struct r600_bytecode_vtx *vtx = CALLOC_STRUCT(r600_bytecode_vtx);
208
209 if (vtx == NULL)
210 return NULL;
211 LIST_INITHEAD(&vtx->list);
212 return vtx;
213 }
214
215 static struct r600_bytecode_tex *r600_bytecode_tex(void)
216 {
217 struct r600_bytecode_tex *tex = CALLOC_STRUCT(r600_bytecode_tex);
218
219 if (tex == NULL)
220 return NULL;
221 LIST_INITHEAD(&tex->list);
222 return tex;
223 }
224
225 void r600_bytecode_init(struct r600_bytecode *bc, enum chip_class chip_class)
226 {
227 LIST_INITHEAD(&bc->cf);
228 bc->chip_class = chip_class;
229 }
230
231 static int r600_bytecode_add_cf(struct r600_bytecode *bc)
232 {
233 struct r600_bytecode_cf *cf = r600_bytecode_cf();
234
235 if (cf == NULL)
236 return -ENOMEM;
237 LIST_ADDTAIL(&cf->list, &bc->cf);
238 if (bc->cf_last)
239 cf->id = bc->cf_last->id + 2;
240 bc->cf_last = cf;
241 bc->ncf++;
242 bc->ndw += 2;
243 bc->force_add_cf = 0;
244 return 0;
245 }
246
247 int r600_bytecode_add_output(struct r600_bytecode *bc, const struct r600_bytecode_output *output)
248 {
249 int r;
250
251 if (bc->cf_last && (bc->cf_last->inst == output->inst ||
252 (bc->cf_last->inst == BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT) &&
253 output->inst == BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE))) &&
254 output->type == bc->cf_last->output.type &&
255 output->elem_size == bc->cf_last->output.elem_size &&
256 output->swizzle_x == bc->cf_last->output.swizzle_x &&
257 output->swizzle_y == bc->cf_last->output.swizzle_y &&
258 output->swizzle_z == bc->cf_last->output.swizzle_z &&
259 output->swizzle_w == bc->cf_last->output.swizzle_w &&
260 (output->burst_count + bc->cf_last->output.burst_count) <= 16) {
261
262 if ((output->gpr + output->burst_count) == bc->cf_last->output.gpr &&
263 (output->array_base + output->burst_count) == bc->cf_last->output.array_base) {
264
265 bc->cf_last->output.end_of_program |= output->end_of_program;
266 bc->cf_last->output.inst = output->inst;
267 bc->cf_last->output.gpr = output->gpr;
268 bc->cf_last->output.array_base = output->array_base;
269 bc->cf_last->output.burst_count += output->burst_count;
270 return 0;
271
272 } else if (output->gpr == (bc->cf_last->output.gpr + bc->cf_last->output.burst_count) &&
273 output->array_base == (bc->cf_last->output.array_base + bc->cf_last->output.burst_count)) {
274
275 bc->cf_last->output.end_of_program |= output->end_of_program;
276 bc->cf_last->output.inst = output->inst;
277 bc->cf_last->output.burst_count += output->burst_count;
278 return 0;
279 }
280 }
281
282 r = r600_bytecode_add_cf(bc);
283 if (r)
284 return r;
285 bc->cf_last->inst = output->inst;
286 memcpy(&bc->cf_last->output, output, sizeof(struct r600_bytecode_output));
287 return 0;
288 }
289
290 /* alu instructions that can ony exits once per group */
291 static int is_alu_once_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
292 {
293 switch (bc->chip_class) {
294 case R600:
295 case R700:
296 return !alu->is_op3 && (
297 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
298 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
299 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
300 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
301 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
302 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
303 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
304 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
305 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
306 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
307 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
308 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
309 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
310 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
311 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
312 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
313 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
314 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
315 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
316 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
317 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
318 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
319 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
320 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
321 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
322 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
323 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
324 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
325 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
326 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
327 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
328 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
329 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
330 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
331 case EVERGREEN:
332 case CAYMAN:
333 default:
334 return !alu->is_op3 && (
335 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
336 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
337 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
338 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
339 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
340 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
341 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
342 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
343 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
344 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
345 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
346 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
347 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
348 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
349 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
350 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
351 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
352 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
353 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
354 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
355 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
356 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
357 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
358 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
359 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
360 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
361 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
362 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
363 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
364 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
365 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
366 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
367 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
368 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
369 }
370 }
371
372 static int is_alu_reduction_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
373 {
374 switch (bc->chip_class) {
375 case R600:
376 case R700:
377 return !alu->is_op3 && (
378 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
379 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
380 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
381 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
382 case EVERGREEN:
383 case CAYMAN:
384 default:
385 return !alu->is_op3 && (
386 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
387 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
388 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
389 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
390 }
391 }
392
393 static int is_alu_cube_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
394 {
395 switch (bc->chip_class) {
396 case R600:
397 case R700:
398 return !alu->is_op3 &&
399 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
400 case EVERGREEN:
401 case CAYMAN:
402 default:
403 return !alu->is_op3 &&
404 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
405 }
406 }
407
408 static int is_alu_mova_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
409 {
410 switch (bc->chip_class) {
411 case R600:
412 case R700:
413 return !alu->is_op3 && (
414 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA ||
415 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR ||
416 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
417 case EVERGREEN:
418 case CAYMAN:
419 default:
420 return !alu->is_op3 && (
421 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
422 }
423 }
424
425 /* alu instructions that can only execute on the vector unit */
426 static int is_alu_vec_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
427 {
428 return is_alu_reduction_inst(bc, alu) ||
429 is_alu_mova_inst(bc, alu) ||
430 (bc->chip_class == EVERGREEN &&
431 (alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT ||
432 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR));
433 }
434
435 /* alu instructions that can only execute on the trans unit */
436 static int is_alu_trans_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
437 {
438 switch (bc->chip_class) {
439 case R600:
440 case R700:
441 if (!alu->is_op3)
442 return alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT ||
443 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT ||
444 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT ||
445 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT ||
446 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT ||
447 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT ||
448 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT ||
449 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT ||
450 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT ||
451 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT ||
452 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT ||
453 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT ||
454 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS ||
455 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE ||
456 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED ||
457 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE ||
458 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED ||
459 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_FF ||
460 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE ||
461 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED ||
462 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF ||
463 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE ||
464 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN ||
465 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_IEEE;
466 else
467 return alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT ||
468 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_D2 ||
469 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M2 ||
470 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M4;
471 case EVERGREEN:
472 case CAYMAN:
473 default:
474 if (!alu->is_op3)
475 /* Note that FLT_TO_INT_* instructions are vector-only instructions
476 * on Evergreen, despite what the documentation says. FLT_TO_INT
477 * can do both vector and scalar. */
478 return alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT ||
479 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT ||
480 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT ||
481 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT ||
482 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT ||
483 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT ||
484 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT ||
485 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT ||
486 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT ||
487 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT ||
488 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT ||
489 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS ||
490 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE ||
491 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED ||
492 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE ||
493 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED ||
494 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_FF ||
495 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE ||
496 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED ||
497 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF ||
498 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE ||
499 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN ||
500 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_IEEE;
501 else
502 return alu->inst == EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
503 }
504 }
505
506 /* alu instructions that can execute on any unit */
507 static int is_alu_any_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
508 {
509 return !is_alu_vec_unit_inst(bc, alu) &&
510 !is_alu_trans_unit_inst(bc, alu);
511 }
512
513 static int assign_alu_units(struct r600_bytecode *bc, struct r600_bytecode_alu *alu_first,
514 struct r600_bytecode_alu *assignment[5])
515 {
516 struct r600_bytecode_alu *alu;
517 unsigned i, chan, trans;
518 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
519
520 for (i = 0; i < max_slots; i++)
521 assignment[i] = NULL;
522
523 for (alu = alu_first; alu; alu = LIST_ENTRY(struct r600_bytecode_alu, alu->list.next, list)) {
524 chan = alu->dst.chan;
525 if (max_slots == 4)
526 trans = 0;
527 else if (is_alu_trans_unit_inst(bc, alu))
528 trans = 1;
529 else if (is_alu_vec_unit_inst(bc, alu))
530 trans = 0;
531 else if (assignment[chan])
532 trans = 1; /* Assume ALU_INST_PREFER_VECTOR. */
533 else
534 trans = 0;
535
536 if (trans) {
537 if (assignment[4]) {
538 assert(0); /* ALU.Trans has already been allocated. */
539 return -1;
540 }
541 assignment[4] = alu;
542 } else {
543 if (assignment[chan]) {
544 assert(0); /* ALU.chan has already been allocated. */
545 return -1;
546 }
547 assignment[chan] = alu;
548 }
549
550 if (alu->last)
551 break;
552 }
553 return 0;
554 }
555
556 struct alu_bank_swizzle {
557 int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
558 int hw_cfile_addr[4];
559 int hw_cfile_elem[4];
560 };
561
562 static const unsigned cycle_for_bank_swizzle_vec[][3] = {
563 [SQ_ALU_VEC_012] = { 0, 1, 2 },
564 [SQ_ALU_VEC_021] = { 0, 2, 1 },
565 [SQ_ALU_VEC_120] = { 1, 2, 0 },
566 [SQ_ALU_VEC_102] = { 1, 0, 2 },
567 [SQ_ALU_VEC_201] = { 2, 0, 1 },
568 [SQ_ALU_VEC_210] = { 2, 1, 0 }
569 };
570
571 static const unsigned cycle_for_bank_swizzle_scl[][3] = {
572 [SQ_ALU_SCL_210] = { 2, 1, 0 },
573 [SQ_ALU_SCL_122] = { 1, 2, 2 },
574 [SQ_ALU_SCL_212] = { 2, 1, 2 },
575 [SQ_ALU_SCL_221] = { 2, 2, 1 }
576 };
577
578 static void init_bank_swizzle(struct alu_bank_swizzle *bs)
579 {
580 int i, cycle, component;
581 /* set up gpr use */
582 for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
583 for (component = 0; component < NUM_OF_COMPONENTS; component++)
584 bs->hw_gpr[cycle][component] = -1;
585 for (i = 0; i < 4; i++)
586 bs->hw_cfile_addr[i] = -1;
587 for (i = 0; i < 4; i++)
588 bs->hw_cfile_elem[i] = -1;
589 }
590
591 static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan, unsigned cycle)
592 {
593 if (bs->hw_gpr[cycle][chan] == -1)
594 bs->hw_gpr[cycle][chan] = sel;
595 else if (bs->hw_gpr[cycle][chan] != (int)sel) {
596 /* Another scalar operation has already used the GPR read port for the channel. */
597 return -1;
598 }
599 return 0;
600 }
601
602 static int reserve_cfile(struct r600_bytecode *bc, struct alu_bank_swizzle *bs, unsigned sel, unsigned chan)
603 {
604 int res, num_res = 4;
605 if (bc->chip_class >= R700) {
606 num_res = 2;
607 chan /= 2;
608 }
609 for (res = 0; res < num_res; ++res) {
610 if (bs->hw_cfile_addr[res] == -1) {
611 bs->hw_cfile_addr[res] = sel;
612 bs->hw_cfile_elem[res] = chan;
613 return 0;
614 } else if (bs->hw_cfile_addr[res] == sel &&
615 bs->hw_cfile_elem[res] == chan)
616 return 0; /* Read for this scalar element already reserved, nothing to do here. */
617 }
618 /* All cfile read ports are used, cannot reference vector element. */
619 return -1;
620 }
621
622 static int is_gpr(unsigned sel)
623 {
624 return (sel >= 0 && sel <= 127);
625 }
626
627 /* CB constants start at 512, and get translated to a kcache index when ALU
628 * clauses are constructed. Note that we handle kcache constants the same way
629 * as (the now gone) cfile constants, is that really required? */
630 static int is_cfile(unsigned sel)
631 {
632 return (sel > 255 && sel < 512) ||
633 (sel > 511 && sel < 4607) || /* Kcache before translation. */
634 (sel > 127 && sel < 192); /* Kcache after translation. */
635 }
636
637 static int is_const(int sel)
638 {
639 return is_cfile(sel) ||
640 (sel >= V_SQ_ALU_SRC_0 &&
641 sel <= V_SQ_ALU_SRC_LITERAL);
642 }
643
644 static int check_vector(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
645 struct alu_bank_swizzle *bs, int bank_swizzle)
646 {
647 int r, src, num_src, sel, elem, cycle;
648
649 num_src = r600_bytecode_get_num_operands(bc, alu);
650 for (src = 0; src < num_src; src++) {
651 sel = alu->src[src].sel;
652 elem = alu->src[src].chan;
653 if (is_gpr(sel)) {
654 cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src];
655 if (src == 1 && sel == alu->src[0].sel && elem == alu->src[0].chan)
656 /* Nothing to do; special-case optimization,
657 * second source uses first source’s reservation. */
658 continue;
659 else {
660 r = reserve_gpr(bs, sel, elem, cycle);
661 if (r)
662 return r;
663 }
664 } else if (is_cfile(sel)) {
665 r = reserve_cfile(bc, bs, sel, elem);
666 if (r)
667 return r;
668 }
669 /* No restrictions on PV, PS, literal or special constants. */
670 }
671 return 0;
672 }
673
674 static int check_scalar(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
675 struct alu_bank_swizzle *bs, int bank_swizzle)
676 {
677 int r, src, num_src, const_count, sel, elem, cycle;
678
679 num_src = r600_bytecode_get_num_operands(bc, alu);
680 for (const_count = 0, src = 0; src < num_src; ++src) {
681 sel = alu->src[src].sel;
682 elem = alu->src[src].chan;
683 if (is_const(sel)) { /* Any constant, including literal and inline constants. */
684 if (const_count >= 2)
685 /* More than two references to a constant in
686 * transcendental operation. */
687 return -1;
688 else
689 const_count++;
690 }
691 if (is_cfile(sel)) {
692 r = reserve_cfile(bc, bs, sel, elem);
693 if (r)
694 return r;
695 }
696 }
697 for (src = 0; src < num_src; ++src) {
698 sel = alu->src[src].sel;
699 elem = alu->src[src].chan;
700 if (is_gpr(sel)) {
701 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
702 if (cycle < const_count)
703 /* Cycle for GPR load conflicts with
704 * constant load in transcendental operation. */
705 return -1;
706 r = reserve_gpr(bs, sel, elem, cycle);
707 if (r)
708 return r;
709 }
710 /* PV PS restrictions */
711 if (const_count && (sel == 254 || sel == 255)) {
712 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
713 if (cycle < const_count)
714 return -1;
715 }
716 }
717 return 0;
718 }
719
720 static int check_and_set_bank_swizzle(struct r600_bytecode *bc,
721 struct r600_bytecode_alu *slots[5])
722 {
723 struct alu_bank_swizzle bs;
724 int bank_swizzle[5];
725 int i, r = 0, forced = 1;
726 boolean scalar_only = bc->chip_class == CAYMAN ? false : true;
727 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
728
729 for (i = 0; i < max_slots; i++) {
730 if (slots[i]) {
731 if (slots[i]->bank_swizzle_force) {
732 slots[i]->bank_swizzle = slots[i]->bank_swizzle_force;
733 } else {
734 forced = 0;
735 }
736 }
737
738 if (i < 4 && slots[i])
739 scalar_only = false;
740 }
741 if (forced)
742 return 0;
743
744 /* Just check every possible combination of bank swizzle.
745 * Not very efficent, but works on the first try in most of the cases. */
746 for (i = 0; i < 4; i++)
747 if (!slots[i] || !slots[i]->bank_swizzle_force)
748 bank_swizzle[i] = SQ_ALU_VEC_012;
749 else
750 bank_swizzle[i] = slots[i]->bank_swizzle;
751
752 bank_swizzle[4] = SQ_ALU_SCL_210;
753 while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
754
755 if (max_slots == 4) {
756 for (i = 0; i < max_slots; i++) {
757 if (bank_swizzle[i] == SQ_ALU_VEC_210)
758 return -1;
759 }
760 }
761 init_bank_swizzle(&bs);
762 if (scalar_only == false) {
763 for (i = 0; i < 4; i++) {
764 if (slots[i]) {
765 r = check_vector(bc, slots[i], &bs, bank_swizzle[i]);
766 if (r)
767 break;
768 }
769 }
770 } else
771 r = 0;
772
773 if (!r && slots[4] && max_slots == 5) {
774 r = check_scalar(bc, slots[4], &bs, bank_swizzle[4]);
775 }
776 if (!r) {
777 for (i = 0; i < max_slots; i++) {
778 if (slots[i])
779 slots[i]->bank_swizzle = bank_swizzle[i];
780 }
781 return 0;
782 }
783
784 if (scalar_only) {
785 bank_swizzle[4]++;
786 } else {
787 for (i = 0; i < max_slots; i++) {
788 if (!slots[i] || !slots[i]->bank_swizzle_force) {
789 bank_swizzle[i]++;
790 if (bank_swizzle[i] <= SQ_ALU_VEC_210)
791 break;
792 else
793 bank_swizzle[i] = SQ_ALU_VEC_012;
794 }
795 }
796 }
797 }
798
799 /* Couldn't find a working swizzle. */
800 return -1;
801 }
802
803 static int replace_gpr_with_pv_ps(struct r600_bytecode *bc,
804 struct r600_bytecode_alu *slots[5], struct r600_bytecode_alu *alu_prev)
805 {
806 struct r600_bytecode_alu *prev[5];
807 int gpr[5], chan[5];
808 int i, j, r, src, num_src;
809 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
810
811 r = assign_alu_units(bc, alu_prev, prev);
812 if (r)
813 return r;
814
815 for (i = 0; i < max_slots; ++i) {
816 if (prev[i] && (prev[i]->dst.write || prev[i]->is_op3) && !prev[i]->dst.rel) {
817 gpr[i] = prev[i]->dst.sel;
818 /* cube writes more than PV.X */
819 if (!is_alu_cube_inst(bc, prev[i]) && is_alu_reduction_inst(bc, prev[i]))
820 chan[i] = 0;
821 else
822 chan[i] = prev[i]->dst.chan;
823 } else
824 gpr[i] = -1;
825 }
826
827 for (i = 0; i < max_slots; ++i) {
828 struct r600_bytecode_alu *alu = slots[i];
829 if(!alu)
830 continue;
831
832 num_src = r600_bytecode_get_num_operands(bc, alu);
833 for (src = 0; src < num_src; ++src) {
834 if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
835 continue;
836
837 if (bc->chip_class < CAYMAN) {
838 if (alu->src[src].sel == gpr[4] &&
839 alu->src[src].chan == chan[4]) {
840 alu->src[src].sel = V_SQ_ALU_SRC_PS;
841 alu->src[src].chan = 0;
842 continue;
843 }
844 }
845
846 for (j = 0; j < 4; ++j) {
847 if (alu->src[src].sel == gpr[j] &&
848 alu->src[src].chan == j) {
849 alu->src[src].sel = V_SQ_ALU_SRC_PV;
850 alu->src[src].chan = chan[j];
851 break;
852 }
853 }
854 }
855 }
856
857 return 0;
858 }
859
860 void r600_bytecode_special_constants(u32 value, unsigned *sel, unsigned *neg)
861 {
862 switch(value) {
863 case 0:
864 *sel = V_SQ_ALU_SRC_0;
865 break;
866 case 1:
867 *sel = V_SQ_ALU_SRC_1_INT;
868 break;
869 case -1:
870 *sel = V_SQ_ALU_SRC_M_1_INT;
871 break;
872 case 0x3F800000: /* 1.0f */
873 *sel = V_SQ_ALU_SRC_1;
874 break;
875 case 0x3F000000: /* 0.5f */
876 *sel = V_SQ_ALU_SRC_0_5;
877 break;
878 case 0xBF800000: /* -1.0f */
879 *sel = V_SQ_ALU_SRC_1;
880 *neg ^= 1;
881 break;
882 case 0xBF000000: /* -0.5f */
883 *sel = V_SQ_ALU_SRC_0_5;
884 *neg ^= 1;
885 break;
886 default:
887 *sel = V_SQ_ALU_SRC_LITERAL;
888 break;
889 }
890 }
891
892 /* compute how many literal are needed */
893 static int r600_bytecode_alu_nliterals(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
894 uint32_t literal[4], unsigned *nliteral)
895 {
896 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
897 unsigned i, j;
898
899 for (i = 0; i < num_src; ++i) {
900 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
901 uint32_t value = alu->src[i].value;
902 unsigned found = 0;
903 for (j = 0; j < *nliteral; ++j) {
904 if (literal[j] == value) {
905 found = 1;
906 break;
907 }
908 }
909 if (!found) {
910 if (*nliteral >= 4)
911 return -EINVAL;
912 literal[(*nliteral)++] = value;
913 }
914 }
915 }
916 return 0;
917 }
918
919 static void r600_bytecode_alu_adjust_literals(struct r600_bytecode *bc,
920 struct r600_bytecode_alu *alu,
921 uint32_t literal[4], unsigned nliteral)
922 {
923 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
924 unsigned i, j;
925
926 for (i = 0; i < num_src; ++i) {
927 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
928 uint32_t value = alu->src[i].value;
929 for (j = 0; j < nliteral; ++j) {
930 if (literal[j] == value) {
931 alu->src[i].chan = j;
932 break;
933 }
934 }
935 }
936 }
937 }
938
939 static int merge_inst_groups(struct r600_bytecode *bc, struct r600_bytecode_alu *slots[5],
940 struct r600_bytecode_alu *alu_prev)
941 {
942 struct r600_bytecode_alu *prev[5];
943 struct r600_bytecode_alu *result[5] = { NULL };
944
945 uint32_t literal[4], prev_literal[4];
946 unsigned nliteral = 0, prev_nliteral = 0;
947
948 int i, j, r, src, num_src;
949 int num_once_inst = 0;
950 int have_mova = 0, have_rel = 0;
951 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
952
953 r = assign_alu_units(bc, alu_prev, prev);
954 if (r)
955 return r;
956
957 for (i = 0; i < max_slots; ++i) {
958 struct r600_bytecode_alu *alu;
959
960 /* check number of literals */
961 if (prev[i]) {
962 if (r600_bytecode_alu_nliterals(bc, prev[i], literal, &nliteral))
963 return 0;
964 if (r600_bytecode_alu_nliterals(bc, prev[i], prev_literal, &prev_nliteral))
965 return 0;
966 if (is_alu_mova_inst(bc, prev[i])) {
967 if (have_rel)
968 return 0;
969 have_mova = 1;
970 }
971 num_once_inst += is_alu_once_inst(bc, prev[i]);
972 }
973 if (slots[i] && r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral))
974 return 0;
975
976 /* Let's check used slots. */
977 if (prev[i] && !slots[i]) {
978 result[i] = prev[i];
979 continue;
980 } else if (prev[i] && slots[i]) {
981 if (max_slots == 5 && result[4] == NULL && prev[4] == NULL && slots[4] == NULL) {
982 /* Trans unit is still free try to use it. */
983 if (is_alu_any_unit_inst(bc, slots[i])) {
984 result[i] = prev[i];
985 result[4] = slots[i];
986 } else if (is_alu_any_unit_inst(bc, prev[i])) {
987 result[i] = slots[i];
988 result[4] = prev[i];
989 } else
990 return 0;
991 } else
992 return 0;
993 } else if(!slots[i]) {
994 continue;
995 } else
996 result[i] = slots[i];
997
998 alu = slots[i];
999 num_once_inst += is_alu_once_inst(bc, alu);
1000
1001 /* Let's check dst gpr. */
1002 if (alu->dst.rel) {
1003 if (have_mova)
1004 return 0;
1005 have_rel = 1;
1006 }
1007
1008 /* Let's check source gprs */
1009 num_src = r600_bytecode_get_num_operands(bc, alu);
1010 for (src = 0; src < num_src; ++src) {
1011 if (alu->src[src].rel) {
1012 if (have_mova)
1013 return 0;
1014 have_rel = 1;
1015 }
1016
1017 /* Constants don't matter. */
1018 if (!is_gpr(alu->src[src].sel))
1019 continue;
1020
1021 for (j = 0; j < max_slots; ++j) {
1022 if (!prev[j] || !prev[j]->dst.write)
1023 continue;
1024
1025 /* If it's relative then we can't determin which gpr is really used. */
1026 if (prev[j]->dst.chan == alu->src[src].chan &&
1027 (prev[j]->dst.sel == alu->src[src].sel ||
1028 prev[j]->dst.rel || alu->src[src].rel))
1029 return 0;
1030 }
1031 }
1032 }
1033
1034 /* more than one PRED_ or KILL_ ? */
1035 if (num_once_inst > 1)
1036 return 0;
1037
1038 /* check if the result can still be swizzlet */
1039 r = check_and_set_bank_swizzle(bc, result);
1040 if (r)
1041 return 0;
1042
1043 /* looks like everything worked out right, apply the changes */
1044
1045 /* undo adding previus literals */
1046 bc->cf_last->ndw -= align(prev_nliteral, 2);
1047
1048 /* sort instructions */
1049 for (i = 0; i < max_slots; ++i) {
1050 slots[i] = result[i];
1051 if (result[i]) {
1052 LIST_DEL(&result[i]->list);
1053 result[i]->last = 0;
1054 LIST_ADDTAIL(&result[i]->list, &bc->cf_last->alu);
1055 }
1056 }
1057
1058 /* determine new last instruction */
1059 LIST_ENTRY(struct r600_bytecode_alu, bc->cf_last->alu.prev, list)->last = 1;
1060
1061 /* determine new first instruction */
1062 for (i = 0; i < max_slots; ++i) {
1063 if (result[i]) {
1064 bc->cf_last->curr_bs_head = result[i];
1065 break;
1066 }
1067 }
1068
1069 bc->cf_last->prev_bs_head = bc->cf_last->prev2_bs_head;
1070 bc->cf_last->prev2_bs_head = NULL;
1071
1072 return 0;
1073 }
1074
1075 /* This code handles kcache lines as single blocks of 32 constants. We could
1076 * probably do slightly better by recognizing that we actually have two
1077 * consecutive lines of 16 constants, but the resulting code would also be
1078 * somewhat more complicated. */
1079 static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, int type)
1080 {
1081 struct r600_bytecode_kcache *kcache = bc->cf_last->kcache;
1082 unsigned int required_lines;
1083 unsigned int free_lines = 0;
1084 unsigned int cache_line[3];
1085 unsigned int count = 0;
1086 unsigned int i, j;
1087 int r;
1088
1089 /* Collect required cache lines. */
1090 for (i = 0; i < 3; ++i) {
1091 boolean found = false;
1092 unsigned int line;
1093
1094 if (alu->src[i].sel < 512)
1095 continue;
1096
1097 line = ((alu->src[i].sel - 512) / 32) * 2;
1098
1099 for (j = 0; j < count; ++j) {
1100 if (cache_line[j] == line) {
1101 found = true;
1102 break;
1103 }
1104 }
1105
1106 if (!found)
1107 cache_line[count++] = line;
1108 }
1109
1110 /* This should never actually happen. */
1111 if (count >= 3) return -ENOMEM;
1112
1113 for (i = 0; i < 2; ++i) {
1114 if (kcache[i].mode == V_SQ_CF_KCACHE_NOP) {
1115 ++free_lines;
1116 }
1117 }
1118
1119 /* Filter lines pulled in by previous intructions. Note that this is
1120 * only for the required_lines count, we can't remove these from the
1121 * cache_line array since we may have to start a new ALU clause. */
1122 for (i = 0, required_lines = count; i < count; ++i) {
1123 for (j = 0; j < 2; ++j) {
1124 if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
1125 kcache[j].addr == cache_line[i]) {
1126 --required_lines;
1127 break;
1128 }
1129 }
1130 }
1131
1132 /* Start a new ALU clause if needed. */
1133 if (required_lines > free_lines) {
1134 if ((r = r600_bytecode_add_cf(bc))) {
1135 return r;
1136 }
1137 bc->cf_last->inst = (type << 3);
1138 kcache = bc->cf_last->kcache;
1139 }
1140
1141 /* Setup the kcache lines. */
1142 for (i = 0; i < count; ++i) {
1143 boolean found = false;
1144
1145 for (j = 0; j < 2; ++j) {
1146 if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
1147 kcache[j].addr == cache_line[i]) {
1148 found = true;
1149 break;
1150 }
1151 }
1152
1153 if (found) continue;
1154
1155 for (j = 0; j < 2; ++j) {
1156 if (kcache[j].mode == V_SQ_CF_KCACHE_NOP) {
1157 kcache[j].bank = 0;
1158 kcache[j].addr = cache_line[i];
1159 kcache[j].mode = V_SQ_CF_KCACHE_LOCK_2;
1160 break;
1161 }
1162 }
1163 }
1164
1165 /* Alter the src operands to refer to the kcache. */
1166 for (i = 0; i < 3; ++i) {
1167 static const unsigned int base[] = {128, 160, 256, 288};
1168 unsigned int line;
1169
1170 if (alu->src[i].sel < 512)
1171 continue;
1172
1173 alu->src[i].sel -= 512;
1174 line = (alu->src[i].sel / 32) * 2;
1175
1176 for (j = 0; j < 2; ++j) {
1177 if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
1178 kcache[j].addr == line) {
1179 alu->src[i].sel &= 0x1f;
1180 alu->src[i].sel += base[j];
1181 break;
1182 }
1183 }
1184 }
1185
1186 return 0;
1187 }
1188
1189 int r600_bytecode_add_alu_type(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu, int type)
1190 {
1191 struct r600_bytecode_alu *nalu = r600_bytecode_alu();
1192 struct r600_bytecode_alu *lalu;
1193 int i, r;
1194
1195 if (nalu == NULL)
1196 return -ENOMEM;
1197 memcpy(nalu, alu, sizeof(struct r600_bytecode_alu));
1198
1199 if (bc->cf_last != NULL && bc->cf_last->inst != (type << 3)) {
1200 /* check if we could add it anyway */
1201 if (bc->cf_last->inst == (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3) &&
1202 type == V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE) {
1203 LIST_FOR_EACH_ENTRY(lalu, &bc->cf_last->alu, list) {
1204 if (lalu->predicate) {
1205 bc->force_add_cf = 1;
1206 break;
1207 }
1208 }
1209 } else
1210 bc->force_add_cf = 1;
1211 }
1212
1213 /* cf can contains only alu or only vtx or only tex */
1214 if (bc->cf_last == NULL || bc->force_add_cf) {
1215 r = r600_bytecode_add_cf(bc);
1216 if (r) {
1217 free(nalu);
1218 return r;
1219 }
1220 }
1221 bc->cf_last->inst = (type << 3);
1222
1223 /* Setup the kcache for this ALU instruction. This will start a new
1224 * ALU clause if needed. */
1225 if ((r = r600_bytecode_alloc_kcache_lines(bc, nalu, type))) {
1226 free(nalu);
1227 return r;
1228 }
1229
1230 if (!bc->cf_last->curr_bs_head) {
1231 bc->cf_last->curr_bs_head = nalu;
1232 }
1233 /* number of gpr == the last gpr used in any alu */
1234 for (i = 0; i < 3; i++) {
1235 if (nalu->src[i].sel >= bc->ngpr && nalu->src[i].sel < 128) {
1236 bc->ngpr = nalu->src[i].sel + 1;
1237 }
1238 if (nalu->src[i].sel == V_SQ_ALU_SRC_LITERAL)
1239 r600_bytecode_special_constants(nalu->src[i].value,
1240 &nalu->src[i].sel, &nalu->src[i].neg);
1241 }
1242 if (nalu->dst.sel >= bc->ngpr) {
1243 bc->ngpr = nalu->dst.sel + 1;
1244 }
1245 LIST_ADDTAIL(&nalu->list, &bc->cf_last->alu);
1246 /* each alu use 2 dwords */
1247 bc->cf_last->ndw += 2;
1248 bc->ndw += 2;
1249
1250 /* process cur ALU instructions for bank swizzle */
1251 if (nalu->last) {
1252 uint32_t literal[4];
1253 unsigned nliteral;
1254 struct r600_bytecode_alu *slots[5];
1255 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
1256 r = assign_alu_units(bc, bc->cf_last->curr_bs_head, slots);
1257 if (r)
1258 return r;
1259
1260 if (bc->cf_last->prev_bs_head) {
1261 r = merge_inst_groups(bc, slots, bc->cf_last->prev_bs_head);
1262 if (r)
1263 return r;
1264 }
1265
1266 if (bc->cf_last->prev_bs_head) {
1267 r = replace_gpr_with_pv_ps(bc, slots, bc->cf_last->prev_bs_head);
1268 if (r)
1269 return r;
1270 }
1271
1272 r = check_and_set_bank_swizzle(bc, slots);
1273 if (r)
1274 return r;
1275
1276 for (i = 0, nliteral = 0; i < max_slots; i++) {
1277 if (slots[i]) {
1278 r = r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral);
1279 if (r)
1280 return r;
1281 }
1282 }
1283 bc->cf_last->ndw += align(nliteral, 2);
1284
1285 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1286 * worst case */
1287 if ((bc->cf_last->ndw >> 1) >= 120) {
1288 bc->force_add_cf = 1;
1289 }
1290
1291 bc->cf_last->prev2_bs_head = bc->cf_last->prev_bs_head;
1292 bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head;
1293 bc->cf_last->curr_bs_head = NULL;
1294 }
1295 return 0;
1296 }
1297
1298 int r600_bytecode_add_alu(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu)
1299 {
1300 return r600_bytecode_add_alu_type(bc, alu, BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
1301 }
1302
1303 static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode *bc)
1304 {
1305 switch (bc->chip_class) {
1306 case R600:
1307 return 8;
1308
1309 case R700:
1310 return 16;
1311
1312 case EVERGREEN:
1313 case CAYMAN:
1314 return 64;
1315
1316 default:
1317 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1318 return 8;
1319 }
1320 }
1321
1322 static inline boolean last_inst_was_vtx_fetch(struct r600_bytecode *bc)
1323 {
1324 if (bc->chip_class == CAYMAN) {
1325 if (bc->cf_last->inst != CM_V_SQ_CF_WORD1_SQ_CF_INST_TC)
1326 return TRUE;
1327 } else {
1328 if (bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX &&
1329 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC)
1330 return TRUE;
1331 }
1332 return FALSE;
1333 }
1334
1335 int r600_bytecode_add_vtx(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx)
1336 {
1337 struct r600_bytecode_vtx *nvtx = r600_bytecode_vtx();
1338 int r;
1339
1340 if (nvtx == NULL)
1341 return -ENOMEM;
1342 memcpy(nvtx, vtx, sizeof(struct r600_bytecode_vtx));
1343
1344 /* cf can contains only alu or only vtx or only tex */
1345 if (bc->cf_last == NULL ||
1346 last_inst_was_vtx_fetch(bc) ||
1347 bc->force_add_cf) {
1348 r = r600_bytecode_add_cf(bc);
1349 if (r) {
1350 free(nvtx);
1351 return r;
1352 }
1353 if (bc->chip_class == CAYMAN)
1354 bc->cf_last->inst = CM_V_SQ_CF_WORD1_SQ_CF_INST_TC;
1355 else
1356 bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1357 }
1358 LIST_ADDTAIL(&nvtx->list, &bc->cf_last->vtx);
1359 /* each fetch use 4 dwords */
1360 bc->cf_last->ndw += 4;
1361 bc->ndw += 4;
1362 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1363 bc->force_add_cf = 1;
1364 return 0;
1365 }
1366
1367 int r600_bytecode_add_tex(struct r600_bytecode *bc, const struct r600_bytecode_tex *tex)
1368 {
1369 struct r600_bytecode_tex *ntex = r600_bytecode_tex();
1370 int r;
1371
1372 if (ntex == NULL)
1373 return -ENOMEM;
1374 memcpy(ntex, tex, sizeof(struct r600_bytecode_tex));
1375
1376 /* we can't fetch data und use it as texture lookup address in the same TEX clause */
1377 if (bc->cf_last != NULL &&
1378 bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_TEX) {
1379 struct r600_bytecode_tex *ttex;
1380 LIST_FOR_EACH_ENTRY(ttex, &bc->cf_last->tex, list) {
1381 if (ttex->dst_gpr == ntex->src_gpr) {
1382 bc->force_add_cf = 1;
1383 break;
1384 }
1385 }
1386 /* slight hack to make gradients always go into same cf */
1387 if (ntex->inst == SQ_TEX_INST_SET_GRADIENTS_H)
1388 bc->force_add_cf = 1;
1389 }
1390
1391 /* cf can contains only alu or only vtx or only tex */
1392 if (bc->cf_last == NULL ||
1393 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_TEX ||
1394 bc->force_add_cf) {
1395 r = r600_bytecode_add_cf(bc);
1396 if (r) {
1397 free(ntex);
1398 return r;
1399 }
1400 bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_TEX;
1401 }
1402 if (ntex->src_gpr >= bc->ngpr) {
1403 bc->ngpr = ntex->src_gpr + 1;
1404 }
1405 if (ntex->dst_gpr >= bc->ngpr) {
1406 bc->ngpr = ntex->dst_gpr + 1;
1407 }
1408 LIST_ADDTAIL(&ntex->list, &bc->cf_last->tex);
1409 /* each texture fetch use 4 dwords */
1410 bc->cf_last->ndw += 4;
1411 bc->ndw += 4;
1412 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1413 bc->force_add_cf = 1;
1414 return 0;
1415 }
1416
1417 int r600_bytecode_add_cfinst(struct r600_bytecode *bc, int inst)
1418 {
1419 int r;
1420 r = r600_bytecode_add_cf(bc);
1421 if (r)
1422 return r;
1423
1424 bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
1425 bc->cf_last->inst = inst;
1426 return 0;
1427 }
1428
1429 int cm_bytecode_add_cf_end(struct r600_bytecode *bc)
1430 {
1431 return r600_bytecode_add_cfinst(bc, CM_V_SQ_CF_WORD1_SQ_CF_INST_END);
1432 }
1433
1434 /* common to all 3 families */
1435 static int r600_bytecode_vtx_build(struct r600_bytecode *bc, struct r600_bytecode_vtx *vtx, unsigned id)
1436 {
1437 bc->bytecode[id] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) |
1438 S_SQ_VTX_WORD0_FETCH_TYPE(vtx->fetch_type) |
1439 S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
1440 S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x);
1441 if (bc->chip_class < CAYMAN)
1442 bc->bytecode[id] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
1443 id++;
1444 bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
1445 S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
1446 S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
1447 S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
1448 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) |
1449 S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) |
1450 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) |
1451 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) |
1452 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
1453 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
1454 bc->bytecode[id] = S_SQ_VTX_WORD2_OFFSET(vtx->offset)|
1455 S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx->endian);
1456 if (bc->chip_class < CAYMAN)
1457 bc->bytecode[id] |= S_SQ_VTX_WORD2_MEGA_FETCH(1);
1458 id++;
1459 bc->bytecode[id++] = 0;
1460 return 0;
1461 }
1462
1463 /* common to all 3 families */
1464 static int r600_bytecode_tex_build(struct r600_bytecode *bc, struct r600_bytecode_tex *tex, unsigned id)
1465 {
1466 bc->bytecode[id++] = S_SQ_TEX_WORD0_TEX_INST(tex->inst) |
1467 S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
1468 S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
1469 S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
1470 bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
1471 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
1472 S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
1473 S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
1474 S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
1475 S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
1476 S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
1477 S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
1478 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
1479 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
1480 S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
1481 bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
1482 S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
1483 S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
1484 S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
1485 S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
1486 S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
1487 S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
1488 S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
1489 bc->bytecode[id++] = 0;
1490 return 0;
1491 }
1492
1493 /* r600 only, r700/eg bits in r700_asm.c */
1494 static int r600_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id)
1495 {
1496 /* don't replace gpr by pv or ps for destination register */
1497 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
1498 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
1499 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
1500 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
1501 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
1502 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
1503 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
1504 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
1505 S_SQ_ALU_WORD0_LAST(alu->last);
1506
1507 if (alu->is_op3) {
1508 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1509 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1510 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1511 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1512 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
1513 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
1514 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
1515 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
1516 S_SQ_ALU_WORD1_OP3_ALU_INST(alu->inst) |
1517 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
1518 } else {
1519 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1520 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1521 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1522 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1523 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
1524 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
1525 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
1526 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
1527 S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
1528 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
1529 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->predicate) |
1530 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->predicate);
1531 }
1532 return 0;
1533 }
1534
1535 static void r600_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_cf *cf)
1536 {
1537 *bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
1538 *bytecode++ = S_SQ_CF_WORD1_CF_INST(cf->inst) |
1539 S_SQ_CF_WORD1_BARRIER(1) |
1540 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
1541 }
1542
1543 /* common for r600/r700 - eg in eg_asm.c */
1544 static int r600_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf)
1545 {
1546 unsigned id = cf->id;
1547
1548 switch (cf->inst) {
1549 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1550 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1551 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1552 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1553 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
1554 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
1555 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
1556 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank);
1557
1558 bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(cf->inst >> 3) |
1559 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) |
1560 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
1561 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
1562 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1563 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chip_class == R600 ? cf->r6xx_uses_waterfall : 0) |
1564 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
1565 break;
1566 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1567 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1568 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1569 if (bc->chip_class == R700)
1570 r700_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1571 else
1572 r600_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1573 break;
1574 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1575 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1576 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1577 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1578 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1579 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
1580 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1581 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
1582 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
1583 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
1584 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
1585 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
1586 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst) |
1587 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program);
1588 break;
1589 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1590 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1591 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1592 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1593 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1594 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1595 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1596 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1597 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1598 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
1599 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) |
1600 S_SQ_CF_WORD1_BARRIER(1) |
1601 S_SQ_CF_WORD1_COND(cf->cond) |
1602 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count);
1603
1604 break;
1605 default:
1606 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1607 return -EINVAL;
1608 }
1609 return 0;
1610 }
1611
1612 int r600_bytecode_build(struct r600_bytecode *bc)
1613 {
1614 struct r600_bytecode_cf *cf;
1615 struct r600_bytecode_alu *alu;
1616 struct r600_bytecode_vtx *vtx;
1617 struct r600_bytecode_tex *tex;
1618 uint32_t literal[4];
1619 unsigned nliteral;
1620 unsigned addr;
1621 int i, r;
1622
1623 if (bc->callstack[0].max > 0)
1624 bc->nstack = ((bc->callstack[0].max + 3) >> 2) + 2;
1625 if (bc->type == TGSI_PROCESSOR_VERTEX && !bc->nstack) {
1626 bc->nstack = 1;
1627 }
1628
1629 /* first path compute addr of each CF block */
1630 /* addr start after all the CF instructions */
1631 addr = bc->cf_last->id + 2;
1632 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1633 switch (cf->inst) {
1634 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1635 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1636 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1637 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1638 break;
1639 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1640 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1641 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1642 /* fetch node need to be 16 bytes aligned*/
1643 addr += 3;
1644 addr &= 0xFFFFFFFCUL;
1645 break;
1646 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1647 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1648 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1649 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1650 break;
1651 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1652 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1653 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1654 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1655 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1656 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1657 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1658 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1659 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1660 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
1661 break;
1662 default:
1663 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1664 return -EINVAL;
1665 }
1666 cf->addr = addr;
1667 addr += cf->ndw;
1668 bc->ndw = cf->addr + cf->ndw;
1669 }
1670 free(bc->bytecode);
1671 bc->bytecode = calloc(1, bc->ndw * 4);
1672 if (bc->bytecode == NULL)
1673 return -ENOMEM;
1674 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1675 addr = cf->addr;
1676 if (bc->chip_class >= EVERGREEN)
1677 r = eg_bytecode_cf_build(bc, cf);
1678 else
1679 r = r600_bytecode_cf_build(bc, cf);
1680 if (r)
1681 return r;
1682 switch (cf->inst) {
1683 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1684 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1685 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1686 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1687 nliteral = 0;
1688 memset(literal, 0, sizeof(literal));
1689 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1690 r = r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
1691 if (r)
1692 return r;
1693 r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral);
1694 switch(bc->chip_class) {
1695 case R600:
1696 r = r600_bytecode_alu_build(bc, alu, addr);
1697 break;
1698 case R700:
1699 case EVERGREEN: /* eg alu is same encoding as r700 */
1700 case CAYMAN: /* eg alu is same encoding as r700 */
1701 r = r700_bytecode_alu_build(bc, alu, addr);
1702 break;
1703 default:
1704 R600_ERR("unknown chip class %d.\n", bc->chip_class);
1705 return -EINVAL;
1706 }
1707 if (r)
1708 return r;
1709 addr += 2;
1710 if (alu->last) {
1711 for (i = 0; i < align(nliteral, 2); ++i) {
1712 bc->bytecode[addr++] = literal[i];
1713 }
1714 nliteral = 0;
1715 memset(literal, 0, sizeof(literal));
1716 }
1717 }
1718 break;
1719 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1720 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1721 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1722 r = r600_bytecode_vtx_build(bc, vtx, addr);
1723 if (r)
1724 return r;
1725 addr += 4;
1726 }
1727 break;
1728 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1729 if (bc->chip_class == CAYMAN) {
1730 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1731 r = r600_bytecode_vtx_build(bc, vtx, addr);
1732 if (r)
1733 return r;
1734 addr += 4;
1735 }
1736 }
1737 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
1738 r = r600_bytecode_tex_build(bc, tex, addr);
1739 if (r)
1740 return r;
1741 addr += 4;
1742 }
1743 break;
1744 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1745 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1746 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1747 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1748 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1749 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1750 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1751 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1752 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1753 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1754 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1755 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1756 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1757 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
1758 break;
1759 default:
1760 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1761 return -EINVAL;
1762 }
1763 }
1764 return 0;
1765 }
1766
1767 void r600_bytecode_clear(struct r600_bytecode *bc)
1768 {
1769 struct r600_bytecode_cf *cf = NULL, *next_cf;
1770
1771 free(bc->bytecode);
1772 bc->bytecode = NULL;
1773
1774 LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
1775 struct r600_bytecode_alu *alu = NULL, *next_alu;
1776 struct r600_bytecode_tex *tex = NULL, *next_tex;
1777 struct r600_bytecode_tex *vtx = NULL, *next_vtx;
1778
1779 LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
1780 free(alu);
1781 }
1782
1783 LIST_INITHEAD(&cf->alu);
1784
1785 LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) {
1786 free(tex);
1787 }
1788
1789 LIST_INITHEAD(&cf->tex);
1790
1791 LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) {
1792 free(vtx);
1793 }
1794
1795 LIST_INITHEAD(&cf->vtx);
1796
1797 free(cf);
1798 }
1799
1800 LIST_INITHEAD(&cf->list);
1801 }
1802
1803 void r600_bytecode_dump(struct r600_bytecode *bc)
1804 {
1805 struct r600_bytecode_cf *cf = NULL;
1806 struct r600_bytecode_alu *alu = NULL;
1807 struct r600_bytecode_vtx *vtx = NULL;
1808 struct r600_bytecode_tex *tex = NULL;
1809
1810 unsigned i, id;
1811 uint32_t literal[4];
1812 unsigned nliteral;
1813 char chip = '6';
1814
1815 switch (bc->chip_class) {
1816 case R700:
1817 chip = '7';
1818 break;
1819 case EVERGREEN:
1820 chip = 'E';
1821 break;
1822 case CAYMAN:
1823 chip = 'C';
1824 break;
1825 case R600:
1826 default:
1827 chip = '6';
1828 break;
1829 }
1830 fprintf(stderr, "bytecode %d dw -- %d gprs ---------------------\n", bc->ndw, bc->ngpr);
1831 fprintf(stderr, " %c\n", chip);
1832
1833 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1834 id = cf->id;
1835
1836 switch (cf->inst) {
1837 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1838 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1839 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1840 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1841 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
1842 fprintf(stderr, "ADDR:%d ", cf->addr);
1843 fprintf(stderr, "KCACHE_MODE0:%X ", cf->kcache[0].mode);
1844 fprintf(stderr, "KCACHE_BANK0:%X ", cf->kcache[0].bank);
1845 fprintf(stderr, "KCACHE_BANK1:%X\n", cf->kcache[1].bank);
1846 id++;
1847 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
1848 fprintf(stderr, "INST:0x%x ", cf->inst);
1849 fprintf(stderr, "KCACHE_MODE1:%X ", cf->kcache[1].mode);
1850 fprintf(stderr, "KCACHE_ADDR0:%X ", cf->kcache[0].addr);
1851 fprintf(stderr, "KCACHE_ADDR1:%X ", cf->kcache[1].addr);
1852 fprintf(stderr, "COUNT:%d\n", cf->ndw / 2);
1853 break;
1854 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1855 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1856 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1857 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
1858 fprintf(stderr, "ADDR:%d\n", cf->addr);
1859 id++;
1860 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
1861 fprintf(stderr, "INST:0x%x ", cf->inst);
1862 fprintf(stderr, "COUNT:%d\n", cf->ndw / 4);
1863 break;
1864 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1865 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1866 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1867 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1868 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
1869 fprintf(stderr, "GPR:%X ", cf->output.gpr);
1870 fprintf(stderr, "ELEM_SIZE:%X ", cf->output.elem_size);
1871 fprintf(stderr, "ARRAY_BASE:%X ", cf->output.array_base);
1872 fprintf(stderr, "TYPE:%X\n", cf->output.type);
1873 id++;
1874 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
1875 fprintf(stderr, "SWIZ_X:%X ", cf->output.swizzle_x);
1876 fprintf(stderr, "SWIZ_Y:%X ", cf->output.swizzle_y);
1877 fprintf(stderr, "SWIZ_Z:%X ", cf->output.swizzle_z);
1878 fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
1879 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
1880 fprintf(stderr, "INST:0x%x ", cf->output.inst);
1881 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
1882 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
1883 break;
1884 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1885 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1886 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1887 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1888 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1889 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1890 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1891 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1892 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1893 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
1894 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
1895 fprintf(stderr, "ADDR:%d\n", cf->cf_addr);
1896 id++;
1897 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
1898 fprintf(stderr, "INST:0x%x ", cf->inst);
1899 fprintf(stderr, "COND:%X ", cf->cond);
1900 fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
1901 break;
1902 }
1903
1904 id = cf->addr;
1905 nliteral = 0;
1906 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1907 r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
1908
1909 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
1910 fprintf(stderr, "SRC0(SEL:%d ", alu->src[0].sel);
1911 fprintf(stderr, "REL:%d ", alu->src[0].rel);
1912 fprintf(stderr, "CHAN:%d ", alu->src[0].chan);
1913 fprintf(stderr, "NEG:%d) ", alu->src[0].neg);
1914 fprintf(stderr, "SRC1(SEL:%d ", alu->src[1].sel);
1915 fprintf(stderr, "REL:%d ", alu->src[1].rel);
1916 fprintf(stderr, "CHAN:%d ", alu->src[1].chan);
1917 fprintf(stderr, "NEG:%d) ", alu->src[1].neg);
1918 fprintf(stderr, "LAST:%d)\n", alu->last);
1919 id++;
1920 fprintf(stderr, "%04d %08X %c ", id, bc->bytecode[id], alu->last ? '*' : ' ');
1921 fprintf(stderr, "INST:0x%x ", alu->inst);
1922 fprintf(stderr, "DST(SEL:%d ", alu->dst.sel);
1923 fprintf(stderr, "CHAN:%d ", alu->dst.chan);
1924 fprintf(stderr, "REL:%d ", alu->dst.rel);
1925 fprintf(stderr, "CLAMP:%d) ", alu->dst.clamp);
1926 fprintf(stderr, "BANK_SWIZZLE:%d ", alu->bank_swizzle);
1927 if (alu->is_op3) {
1928 fprintf(stderr, "SRC2(SEL:%d ", alu->src[2].sel);
1929 fprintf(stderr, "REL:%d ", alu->src[2].rel);
1930 fprintf(stderr, "CHAN:%d ", alu->src[2].chan);
1931 fprintf(stderr, "NEG:%d)\n", alu->src[2].neg);
1932 } else {
1933 fprintf(stderr, "SRC0_ABS:%d ", alu->src[0].abs);
1934 fprintf(stderr, "SRC1_ABS:%d ", alu->src[1].abs);
1935 fprintf(stderr, "WRITE_MASK:%d ", alu->dst.write);
1936 fprintf(stderr, "OMOD:%d ", alu->omod);
1937 fprintf(stderr, "EXECUTE_MASK:%d ", alu->predicate);
1938 fprintf(stderr, "UPDATE_PRED:%d\n", alu->predicate);
1939 }
1940
1941 id++;
1942 if (alu->last) {
1943 for (i = 0; i < nliteral; i++, id++) {
1944 float *f = (float*)(bc->bytecode + id);
1945 fprintf(stderr, "%04d %08X\t%f\n", id, bc->bytecode[id], *f);
1946 }
1947 id += nliteral & 1;
1948 nliteral = 0;
1949 }
1950 }
1951
1952 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
1953 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
1954 fprintf(stderr, "INST:0x%x ", tex->inst);
1955 fprintf(stderr, "RESOURCE_ID:%d ", tex->resource_id);
1956 fprintf(stderr, "SRC(GPR:%d ", tex->src_gpr);
1957 fprintf(stderr, "REL:%d)\n", tex->src_rel);
1958 id++;
1959 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
1960 fprintf(stderr, "DST(GPR:%d ", tex->dst_gpr);
1961 fprintf(stderr, "REL:%d ", tex->dst_rel);
1962 fprintf(stderr, "SEL_X:%d ", tex->dst_sel_x);
1963 fprintf(stderr, "SEL_Y:%d ", tex->dst_sel_y);
1964 fprintf(stderr, "SEL_Z:%d ", tex->dst_sel_z);
1965 fprintf(stderr, "SEL_W:%d) ", tex->dst_sel_w);
1966 fprintf(stderr, "LOD_BIAS:%d ", tex->lod_bias);
1967 fprintf(stderr, "COORD_TYPE_X:%d ", tex->coord_type_x);
1968 fprintf(stderr, "COORD_TYPE_Y:%d ", tex->coord_type_y);
1969 fprintf(stderr, "COORD_TYPE_Z:%d ", tex->coord_type_z);
1970 fprintf(stderr, "COORD_TYPE_W:%d\n", tex->coord_type_w);
1971 id++;
1972 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
1973 fprintf(stderr, "OFFSET_X:%d ", tex->offset_x);
1974 fprintf(stderr, "OFFSET_Y:%d ", tex->offset_y);
1975 fprintf(stderr, "OFFSET_Z:%d ", tex->offset_z);
1976 fprintf(stderr, "SAMPLER_ID:%d ", tex->sampler_id);
1977 fprintf(stderr, "SRC(SEL_X:%d ", tex->src_sel_x);
1978 fprintf(stderr, "SEL_Y:%d ", tex->src_sel_y);
1979 fprintf(stderr, "SEL_Z:%d ", tex->src_sel_z);
1980 fprintf(stderr, "SEL_W:%d)\n", tex->src_sel_w);
1981 id++;
1982 fprintf(stderr, "%04d %08X \n", id, bc->bytecode[id]);
1983 id++;
1984 }
1985
1986 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1987 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
1988 fprintf(stderr, "INST:%d ", vtx->inst);
1989 fprintf(stderr, "FETCH_TYPE:%d ", vtx->fetch_type);
1990 fprintf(stderr, "BUFFER_ID:%d\n", vtx->buffer_id);
1991 id++;
1992 /* This assumes that no semantic fetches exist */
1993 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
1994 fprintf(stderr, "SRC(GPR:%d ", vtx->src_gpr);
1995 fprintf(stderr, "SEL_X:%d) ", vtx->src_sel_x);
1996 if (bc->chip_class < CAYMAN)
1997 fprintf(stderr, "MEGA_FETCH_COUNT:%d ", vtx->mega_fetch_count);
1998 else
1999 fprintf(stderr, "SEL_Y:%d) ", 0);
2000 fprintf(stderr, "DST(GPR:%d ", vtx->dst_gpr);
2001 fprintf(stderr, "SEL_X:%d ", vtx->dst_sel_x);
2002 fprintf(stderr, "SEL_Y:%d ", vtx->dst_sel_y);
2003 fprintf(stderr, "SEL_Z:%d ", vtx->dst_sel_z);
2004 fprintf(stderr, "SEL_W:%d) ", vtx->dst_sel_w);
2005 fprintf(stderr, "USE_CONST_FIELDS:%d ", vtx->use_const_fields);
2006 fprintf(stderr, "FORMAT(DATA:%d ", vtx->data_format);
2007 fprintf(stderr, "NUM:%d ", vtx->num_format_all);
2008 fprintf(stderr, "COMP:%d ", vtx->format_comp_all);
2009 fprintf(stderr, "MODE:%d)\n", vtx->srf_mode_all);
2010 id++;
2011 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2012 fprintf(stderr, "ENDIAN:%d ", vtx->endian);
2013 fprintf(stderr, "OFFSET:%d\n", vtx->offset);
2014 /* TODO */
2015 id++;
2016 fprintf(stderr, "%04d %08X \n", id, bc->bytecode[id]);
2017 id++;
2018 }
2019 }
2020
2021 fprintf(stderr, "--------------------------------------\n");
2022 }
2023
2024 static void r600_vertex_data_type(enum pipe_format pformat,
2025 unsigned *format,
2026 unsigned *num_format, unsigned *format_comp, unsigned *endian)
2027 {
2028 const struct util_format_description *desc;
2029 unsigned i;
2030
2031 *format = 0;
2032 *num_format = 0;
2033 *format_comp = 0;
2034 *endian = ENDIAN_NONE;
2035
2036 desc = util_format_description(pformat);
2037 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
2038 goto out_unknown;
2039 }
2040
2041 /* Find the first non-VOID channel. */
2042 for (i = 0; i < 4; i++) {
2043 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2044 break;
2045 }
2046 }
2047
2048 *endian = r600_endian_swap(desc->channel[i].size);
2049
2050 switch (desc->channel[i].type) {
2051 /* Half-floats, floats, ints */
2052 case UTIL_FORMAT_TYPE_FLOAT:
2053 switch (desc->channel[i].size) {
2054 case 16:
2055 switch (desc->nr_channels) {
2056 case 1:
2057 *format = FMT_16_FLOAT;
2058 break;
2059 case 2:
2060 *format = FMT_16_16_FLOAT;
2061 break;
2062 case 3:
2063 case 4:
2064 *format = FMT_16_16_16_16_FLOAT;
2065 break;
2066 }
2067 break;
2068 case 32:
2069 switch (desc->nr_channels) {
2070 case 1:
2071 *format = FMT_32_FLOAT;
2072 break;
2073 case 2:
2074 *format = FMT_32_32_FLOAT;
2075 break;
2076 case 3:
2077 *format = FMT_32_32_32_FLOAT;
2078 break;
2079 case 4:
2080 *format = FMT_32_32_32_32_FLOAT;
2081 break;
2082 }
2083 break;
2084 default:
2085 goto out_unknown;
2086 }
2087 break;
2088 /* Unsigned ints */
2089 case UTIL_FORMAT_TYPE_UNSIGNED:
2090 /* Signed ints */
2091 case UTIL_FORMAT_TYPE_SIGNED:
2092 switch (desc->channel[i].size) {
2093 case 8:
2094 switch (desc->nr_channels) {
2095 case 1:
2096 *format = FMT_8;
2097 break;
2098 case 2:
2099 *format = FMT_8_8;
2100 break;
2101 case 3:
2102 case 4:
2103 *format = FMT_8_8_8_8;
2104 break;
2105 }
2106 break;
2107 case 10:
2108 if (desc->nr_channels != 4)
2109 goto out_unknown;
2110
2111 *format = FMT_2_10_10_10;
2112 break;
2113 case 16:
2114 switch (desc->nr_channels) {
2115 case 1:
2116 *format = FMT_16;
2117 break;
2118 case 2:
2119 *format = FMT_16_16;
2120 break;
2121 case 3:
2122 case 4:
2123 *format = FMT_16_16_16_16;
2124 break;
2125 }
2126 break;
2127 case 32:
2128 switch (desc->nr_channels) {
2129 case 1:
2130 *format = FMT_32;
2131 break;
2132 case 2:
2133 *format = FMT_32_32;
2134 break;
2135 case 3:
2136 *format = FMT_32_32_32;
2137 break;
2138 case 4:
2139 *format = FMT_32_32_32_32;
2140 break;
2141 }
2142 break;
2143 default:
2144 goto out_unknown;
2145 }
2146 break;
2147 default:
2148 goto out_unknown;
2149 }
2150
2151 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2152 *format_comp = 1;
2153 }
2154
2155 *num_format = 0;
2156 if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED ||
2157 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2158 if (!desc->channel[i].normalized) {
2159 if (desc->channel[i].pure_integer)
2160 *num_format = 1;
2161 else
2162 *num_format = 2;
2163 }
2164 }
2165 return;
2166 out_unknown:
2167 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
2168 }
2169
2170 int r600_vertex_elements_build_fetch_shader(struct r600_pipe_context *rctx, struct r600_vertex_element *ve)
2171 {
2172 static int dump_shaders = -1;
2173
2174 struct r600_bytecode bc;
2175 struct r600_bytecode_vtx vtx;
2176 struct pipe_vertex_element *elements = ve->elements;
2177 const struct util_format_description *desc;
2178 unsigned fetch_resource_start = rctx->chip_class >= EVERGREEN ? 0 : 160;
2179 unsigned format, num_format, format_comp, endian;
2180 u32 *bytecode;
2181 int i, r;
2182
2183 /* Vertex element offsets need special handling. If the offset is
2184 * bigger than what we can put in the fetch instruction we need to
2185 * alter the vertex resource offset. In order to simplify code we
2186 * will bind one resource per element in such cases. It's a worst
2187 * case scenario. */
2188 for (i = 0; i < ve->count; i++) {
2189 ve->vbuffer_offset[i] = C_SQ_VTX_WORD2_OFFSET & elements[i].src_offset;
2190 if (ve->vbuffer_offset[i]) {
2191 ve->vbuffer_need_offset = 1;
2192 }
2193 }
2194
2195 memset(&bc, 0, sizeof(bc));
2196 r600_bytecode_init(&bc, rctx->chip_class);
2197
2198 for (i = 0; i < ve->count; i++) {
2199 if (elements[i].instance_divisor > 1) {
2200 struct r600_bytecode_alu alu;
2201
2202 memset(&alu, 0, sizeof(alu));
2203 alu.inst = BC_INST(&bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
2204 alu.src[0].sel = 0;
2205 alu.src[0].chan = 3;
2206
2207 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2208 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2209
2210 alu.dst.sel = i + 1;
2211 alu.dst.chan = 3;
2212 alu.dst.write = 1;
2213 alu.last = 1;
2214
2215 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2216 r600_bytecode_clear(&bc);
2217 return r;
2218 }
2219 }
2220 }
2221
2222 for (i = 0; i < ve->count; i++) {
2223 unsigned vbuffer_index;
2224 r600_vertex_data_type(ve->elements[i].src_format,
2225 &format, &num_format, &format_comp, &endian);
2226 desc = util_format_description(ve->elements[i].src_format);
2227 if (desc == NULL) {
2228 r600_bytecode_clear(&bc);
2229 R600_ERR("unknown format %d\n", ve->elements[i].src_format);
2230 return -EINVAL;
2231 }
2232
2233 /* see above for vbuffer_need_offset explanation */
2234 vbuffer_index = elements[i].vertex_buffer_index;
2235 memset(&vtx, 0, sizeof(vtx));
2236 vtx.buffer_id = (ve->vbuffer_need_offset ? i : vbuffer_index) + fetch_resource_start;
2237 vtx.fetch_type = elements[i].instance_divisor ? 1 : 0;
2238 vtx.src_gpr = elements[i].instance_divisor > 1 ? i + 1 : 0;
2239 vtx.src_sel_x = elements[i].instance_divisor ? 3 : 0;
2240 vtx.mega_fetch_count = 0x1F;
2241 vtx.dst_gpr = i + 1;
2242 vtx.dst_sel_x = desc->swizzle[0];
2243 vtx.dst_sel_y = desc->swizzle[1];
2244 vtx.dst_sel_z = desc->swizzle[2];
2245 vtx.dst_sel_w = desc->swizzle[3];
2246 vtx.data_format = format;
2247 vtx.num_format_all = num_format;
2248 vtx.format_comp_all = format_comp;
2249 vtx.srf_mode_all = 1;
2250 vtx.offset = elements[i].src_offset;
2251 vtx.endian = endian;
2252
2253 if ((r = r600_bytecode_add_vtx(&bc, &vtx))) {
2254 r600_bytecode_clear(&bc);
2255 return r;
2256 }
2257 }
2258
2259 r600_bytecode_add_cfinst(&bc, BC_INST(&bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN));
2260
2261 if ((r = r600_bytecode_build(&bc))) {
2262 r600_bytecode_clear(&bc);
2263 return r;
2264 }
2265
2266 if (dump_shaders == -1)
2267 dump_shaders = debug_get_bool_option("R600_DUMP_SHADERS", FALSE);
2268
2269 if (dump_shaders) {
2270 fprintf(stderr, "--------------------------------------------------------------\n");
2271 r600_bytecode_dump(&bc);
2272 fprintf(stderr, "______________________________________________________________\n");
2273 }
2274
2275 ve->fs_size = bc.ndw*4;
2276
2277 ve->fetch_shader = (struct r600_resource*)
2278 pipe_buffer_create(rctx->context.screen,
2279 PIPE_BIND_CUSTOM,
2280 PIPE_USAGE_IMMUTABLE, ve->fs_size);
2281 if (ve->fetch_shader == NULL) {
2282 r600_bytecode_clear(&bc);
2283 return -ENOMEM;
2284 }
2285
2286 bytecode = rctx->ws->buffer_map(ve->fetch_shader->buf, rctx->ctx.cs, PIPE_TRANSFER_WRITE);
2287 if (bytecode == NULL) {
2288 r600_bytecode_clear(&bc);
2289 pipe_resource_reference((struct pipe_resource**)&ve->fetch_shader, NULL);
2290 return -ENOMEM;
2291 }
2292
2293 if (R600_BIG_ENDIAN) {
2294 for (i = 0; i < ve->fs_size / 4; ++i) {
2295 bytecode[i] = bswap_32(bc.bytecode[i]);
2296 }
2297 } else {
2298 memcpy(bytecode, bc.bytecode, ve->fs_size);
2299 }
2300
2301 rctx->ws->buffer_unmap(ve->fetch_shader->buf);
2302 r600_bytecode_clear(&bc);
2303
2304 if (rctx->chip_class >= EVERGREEN)
2305 evergreen_fetch_shader(&rctx->context, ve);
2306 else
2307 r600_fetch_shader(&rctx->context, ve);
2308
2309 return 0;
2310 }