projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
r600g: Use util_cpu_to_le32() instead of bswap32() on big-endian systems
[mesa.git] / src / gallium / drivers / r600 / r600_asm.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_opcodes.h"
25 #include "r600_formats.h"
26 #include "r600_shader.h"
27 #include "r600d.h"
28
29 #include <errno.h>
30 #include "util/u_dump.h"
31 #include "util/u_memory.h"
32 #include "util/u_math.h"
33 #include "pipe/p_shader_tokens.h"
34
35 #include "sb/sb_public.h"
36
37 #define NUM_OF_CYCLES 3
38 #define NUM_OF_COMPONENTS 4
39
40 static inline unsigned int r600_bytecode_get_num_operands(
41 struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
42 {
43 return r600_isa_alu(alu->op)->src_count;
44 }
45
46 int r700_bytecode_alu_build(struct r600_bytecode *bc,
47 struct r600_bytecode_alu *alu, unsigned id);
48
49 static struct r600_bytecode_cf *r600_bytecode_cf(void)
50 {
51 struct r600_bytecode_cf *cf = CALLOC_STRUCT(r600_bytecode_cf);
52
53 if (cf == NULL)
54 return NULL;
55 LIST_INITHEAD(&cf->list);
56 LIST_INITHEAD(&cf->alu);
57 LIST_INITHEAD(&cf->vtx);
58 LIST_INITHEAD(&cf->tex);
59 return cf;
60 }
61
62 static struct r600_bytecode_alu *r600_bytecode_alu(void)
63 {
64 struct r600_bytecode_alu *alu = CALLOC_STRUCT(r600_bytecode_alu);
65
66 if (alu == NULL)
67 return NULL;
68 LIST_INITHEAD(&alu->list);
69 return alu;
70 }
71
72 static struct r600_bytecode_vtx *r600_bytecode_vtx(void)
73 {
74 struct r600_bytecode_vtx *vtx = CALLOC_STRUCT(r600_bytecode_vtx);
75
76 if (vtx == NULL)
77 return NULL;
78 LIST_INITHEAD(&vtx->list);
79 return vtx;
80 }
81
82 static struct r600_bytecode_tex *r600_bytecode_tex(void)
83 {
84 struct r600_bytecode_tex *tex = CALLOC_STRUCT(r600_bytecode_tex);
85
86 if (tex == NULL)
87 return NULL;
88 LIST_INITHEAD(&tex->list);
89 return tex;
90 }
91
92 static unsigned stack_entry_size(enum radeon_family chip) {
93 /* Wavefront size:
94 * 64: R600/RV670/RV770/Cypress/R740/Barts/Turks/Caicos/
95 * Aruba/Sumo/Sumo2/redwood/juniper
96 * 32: R630/R730/R710/Palm/Cedar
97 * 16: R610/Rs780
98 *
99 * Stack row size:
100 * Wavefront Size 16 32 48 64
101 * Columns per Row (R6xx/R7xx/R8xx only) 8 8 4 4
102 * Columns per Row (R9xx+) 8 4 4 4 */
103
104 switch (chip) {
105 /* FIXME: are some chips missing here? */
106 /* wavefront size 16 */
107 case CHIP_RV610:
108 case CHIP_RS780:
109 case CHIP_RV620:
110 case CHIP_RS880:
111 /* wavefront size 32 */
112 case CHIP_RV630:
113 case CHIP_RV635:
114 case CHIP_RV730:
115 case CHIP_RV710:
116 case CHIP_PALM:
117 case CHIP_CEDAR:
118 return 8;
119
120 /* wavefront size 64 */
121 default:
122 return 4;
123 }
124 }
125
126 void r600_bytecode_init(struct r600_bytecode *bc,
127 enum chip_class chip_class,
128 enum radeon_family family,
129 bool has_compressed_msaa_texturing)
130 {
131 static unsigned next_shader_id = 0;
132
133 bc->debug_id = ++next_shader_id;
134
135 if ((chip_class == R600) &&
136 (family != CHIP_RV670 && family != CHIP_RS780 && family != CHIP_RS880)) {
137 bc->ar_handling = AR_HANDLE_RV6XX;
138 bc->r6xx_nop_after_rel_dst = 1;
139 } else {
140 bc->ar_handling = AR_HANDLE_NORMAL;
141 bc->r6xx_nop_after_rel_dst = 0;
142 }
143
144 LIST_INITHEAD(&bc->cf);
145 bc->chip_class = chip_class;
146 bc->has_compressed_msaa_texturing = has_compressed_msaa_texturing;
147 bc->stack.entry_size = stack_entry_size(family);
148 }
149
150 int r600_bytecode_add_cf(struct r600_bytecode *bc)
151 {
152 struct r600_bytecode_cf *cf = r600_bytecode_cf();
153
154 if (cf == NULL)
155 return -ENOMEM;
156 LIST_ADDTAIL(&cf->list, &bc->cf);
157 if (bc->cf_last) {
158 cf->id = bc->cf_last->id + 2;
159 if (bc->cf_last->eg_alu_extended) {
160 /* take into account extended alu size */
161 cf->id += 2;
162 bc->ndw += 2;
163 }
164 }
165 bc->cf_last = cf;
166 bc->ncf++;
167 bc->ndw += 2;
168 bc->force_add_cf = 0;
169 bc->ar_loaded = 0;
170 return 0;
171 }
172
173 int r600_bytecode_add_output(struct r600_bytecode *bc,
174 const struct r600_bytecode_output *output)
175 {
176 int r;
177
178 if (output->gpr >= bc->ngpr)
179 bc->ngpr = output->gpr + 1;
180
181 if (bc->cf_last && (bc->cf_last->op == output->op ||
182 (bc->cf_last->op == CF_OP_EXPORT &&
183 output->op == CF_OP_EXPORT_DONE)) &&
184 output->type == bc->cf_last->output.type &&
185 output->elem_size == bc->cf_last->output.elem_size &&
186 output->swizzle_x == bc->cf_last->output.swizzle_x &&
187 output->swizzle_y == bc->cf_last->output.swizzle_y &&
188 output->swizzle_z == bc->cf_last->output.swizzle_z &&
189 output->swizzle_w == bc->cf_last->output.swizzle_w &&
190 output->comp_mask == bc->cf_last->output.comp_mask &&
191 (output->burst_count + bc->cf_last->output.burst_count) <= 16) {
192
193 if ((output->gpr + output->burst_count) == bc->cf_last->output.gpr &&
194 (output->array_base + output->burst_count) == bc->cf_last->output.array_base) {
195
196 bc->cf_last->op = bc->cf_last->output.op = output->op;
197 bc->cf_last->output.gpr = output->gpr;
198 bc->cf_last->output.array_base = output->array_base;
199 bc->cf_last->output.burst_count += output->burst_count;
200 return 0;
201
202 } else if (output->gpr == (bc->cf_last->output.gpr + bc->cf_last->output.burst_count) &&
203 output->array_base == (bc->cf_last->output.array_base + bc->cf_last->output.burst_count)) {
204
205 bc->cf_last->op = bc->cf_last->output.op = output->op;
206 bc->cf_last->output.burst_count += output->burst_count;
207 return 0;
208 }
209 }
210
211 r = r600_bytecode_add_cf(bc);
212 if (r)
213 return r;
214 bc->cf_last->op = output->op;
215 memcpy(&bc->cf_last->output, output, sizeof(struct r600_bytecode_output));
216 bc->cf_last->barrier = 1;
217 return 0;
218 }
219
220 /* alu instructions that can ony exits once per group */
221 static int is_alu_once_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
222 {
223 return r600_isa_alu(alu->op)->flags & (AF_KILL | AF_PRED);
224 }
225
226 static int is_alu_reduction_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
227 {
228 return (r600_isa_alu(alu->op)->flags & AF_REPL) &&
229 (r600_isa_alu_slots(bc->isa->hw_class, alu->op) == AF_4V);
230 }
231
232 static int is_alu_mova_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
233 {
234 return r600_isa_alu(alu->op)->flags & AF_MOVA;
235 }
236
237 static int alu_uses_rel(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
238 {
239 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
240 unsigned src;
241
242 if (alu->dst.rel) {
243 return 1;
244 }
245
246 for (src = 0; src < num_src; ++src) {
247 if (alu->src[src].rel) {
248 return 1;
249 }
250 }
251 return 0;
252 }
253
254 static int is_alu_vec_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
255 {
256 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
257 return !(slots & AF_S);
258 }
259
260 static int is_alu_trans_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
261 {
262 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
263 return !(slots & AF_V);
264 }
265
266 /* alu instructions that can execute on any unit */
267 static int is_alu_any_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
268 {
269 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
270 return slots == AF_VS;
271 }
272
273 static int is_nop_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
274 {
275 return alu->op == ALU_OP0_NOP;
276 }
277
278 static int assign_alu_units(struct r600_bytecode *bc, struct r600_bytecode_alu *alu_first,
279 struct r600_bytecode_alu *assignment[5])
280 {
281 struct r600_bytecode_alu *alu;
282 unsigned i, chan, trans;
283 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
284
285 for (i = 0; i < max_slots; i++)
286 assignment[i] = NULL;
287
288 for (alu = alu_first; alu; alu = LIST_ENTRY(struct r600_bytecode_alu, alu->list.next, list)) {
289 chan = alu->dst.chan;
290 if (max_slots == 4)
291 trans = 0;
292 else if (is_alu_trans_unit_inst(bc, alu))
293 trans = 1;
294 else if (is_alu_vec_unit_inst(bc, alu))
295 trans = 0;
296 else if (assignment[chan])
297 trans = 1; /* Assume ALU_INST_PREFER_VECTOR. */
298 else
299 trans = 0;
300
301 if (trans) {
302 if (assignment[4]) {
303 assert(0); /* ALU.Trans has already been allocated. */
304 return -1;
305 }
306 assignment[4] = alu;
307 } else {
308 if (assignment[chan]) {
309 assert(0); /* ALU.chan has already been allocated. */
310 return -1;
311 }
312 assignment[chan] = alu;
313 }
314
315 if (alu->last)
316 break;
317 }
318 return 0;
319 }
320
321 struct alu_bank_swizzle {
322 int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
323 int hw_cfile_addr[4];
324 int hw_cfile_elem[4];
325 };
326
327 static const unsigned cycle_for_bank_swizzle_vec[][3] = {
328 [SQ_ALU_VEC_012] = { 0, 1, 2 },
329 [SQ_ALU_VEC_021] = { 0, 2, 1 },
330 [SQ_ALU_VEC_120] = { 1, 2, 0 },
331 [SQ_ALU_VEC_102] = { 1, 0, 2 },
332 [SQ_ALU_VEC_201] = { 2, 0, 1 },
333 [SQ_ALU_VEC_210] = { 2, 1, 0 }
334 };
335
336 static const unsigned cycle_for_bank_swizzle_scl[][3] = {
337 [SQ_ALU_SCL_210] = { 2, 1, 0 },
338 [SQ_ALU_SCL_122] = { 1, 2, 2 },
339 [SQ_ALU_SCL_212] = { 2, 1, 2 },
340 [SQ_ALU_SCL_221] = { 2, 2, 1 }
341 };
342
343 static void init_bank_swizzle(struct alu_bank_swizzle *bs)
344 {
345 int i, cycle, component;
346 /* set up gpr use */
347 for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
348 for (component = 0; component < NUM_OF_COMPONENTS; component++)
349 bs->hw_gpr[cycle][component] = -1;
350 for (i = 0; i < 4; i++)
351 bs->hw_cfile_addr[i] = -1;
352 for (i = 0; i < 4; i++)
353 bs->hw_cfile_elem[i] = -1;
354 }
355
356 static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan, unsigned cycle)
357 {
358 if (bs->hw_gpr[cycle][chan] == -1)
359 bs->hw_gpr[cycle][chan] = sel;
360 else if (bs->hw_gpr[cycle][chan] != (int)sel) {
361 /* Another scalar operation has already used the GPR read port for the channel. */
362 return -1;
363 }
364 return 0;
365 }
366
367 static int reserve_cfile(struct r600_bytecode *bc, struct alu_bank_swizzle *bs, unsigned sel, unsigned chan)
368 {
369 int res, num_res = 4;
370 if (bc->chip_class >= R700) {
371 num_res = 2;
372 chan /= 2;
373 }
374 for (res = 0; res < num_res; ++res) {
375 if (bs->hw_cfile_addr[res] == -1) {
376 bs->hw_cfile_addr[res] = sel;
377 bs->hw_cfile_elem[res] = chan;
378 return 0;
379 } else if (bs->hw_cfile_addr[res] == sel &&
380 bs->hw_cfile_elem[res] == chan)
381 return 0; /* Read for this scalar element already reserved, nothing to do here. */
382 }
383 /* All cfile read ports are used, cannot reference vector element. */
384 return -1;
385 }
386
387 static int is_gpr(unsigned sel)
388 {
389 return (sel <= 127);
390 }
391
392 /* CB constants start at 512, and get translated to a kcache index when ALU
393 * clauses are constructed. Note that we handle kcache constants the same way
394 * as (the now gone) cfile constants, is that really required? */
395 static int is_cfile(unsigned sel)
396 {
397 return (sel > 255 && sel < 512) ||
398 (sel > 511 && sel < 4607) || /* Kcache before translation. */
399 (sel > 127 && sel < 192); /* Kcache after translation. */
400 }
401
402 static int is_const(int sel)
403 {
404 return is_cfile(sel) ||
405 (sel >= V_SQ_ALU_SRC_0 &&
406 sel <= V_SQ_ALU_SRC_LITERAL);
407 }
408
409 static int check_vector(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
410 struct alu_bank_swizzle *bs, int bank_swizzle)
411 {
412 int r, src, num_src, sel, elem, cycle;
413
414 num_src = r600_bytecode_get_num_operands(bc, alu);
415 for (src = 0; src < num_src; src++) {
416 sel = alu->src[src].sel;
417 elem = alu->src[src].chan;
418 if (is_gpr(sel)) {
419 cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src];
420 if (src == 1 && sel == alu->src[0].sel && elem == alu->src[0].chan)
421 /* Nothing to do; special-case optimization,
422 * second source uses first source’s reservation. */
423 continue;
424 else {
425 r = reserve_gpr(bs, sel, elem, cycle);
426 if (r)
427 return r;
428 }
429 } else if (is_cfile(sel)) {
430 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
431 if (r)
432 return r;
433 }
434 /* No restrictions on PV, PS, literal or special constants. */
435 }
436 return 0;
437 }
438
439 static int check_scalar(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
440 struct alu_bank_swizzle *bs, int bank_swizzle)
441 {
442 int r, src, num_src, const_count, sel, elem, cycle;
443
444 num_src = r600_bytecode_get_num_operands(bc, alu);
445 for (const_count = 0, src = 0; src < num_src; ++src) {
446 sel = alu->src[src].sel;
447 elem = alu->src[src].chan;
448 if (is_const(sel)) { /* Any constant, including literal and inline constants. */
449 if (const_count >= 2)
450 /* More than two references to a constant in
451 * transcendental operation. */
452 return -1;
453 else
454 const_count++;
455 }
456 if (is_cfile(sel)) {
457 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
458 if (r)
459 return r;
460 }
461 }
462 for (src = 0; src < num_src; ++src) {
463 sel = alu->src[src].sel;
464 elem = alu->src[src].chan;
465 if (is_gpr(sel)) {
466 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
467 if (cycle < const_count)
468 /* Cycle for GPR load conflicts with
469 * constant load in transcendental operation. */
470 return -1;
471 r = reserve_gpr(bs, sel, elem, cycle);
472 if (r)
473 return r;
474 }
475 /* PV PS restrictions */
476 if (const_count && (sel == 254 || sel == 255)) {
477 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
478 if (cycle < const_count)
479 return -1;
480 }
481 }
482 return 0;
483 }
484
485 static int check_and_set_bank_swizzle(struct r600_bytecode *bc,
486 struct r600_bytecode_alu *slots[5])
487 {
488 struct alu_bank_swizzle bs;
489 int bank_swizzle[5];
490 int i, r = 0, forced = 1;
491 boolean scalar_only = bc->chip_class == CAYMAN ? false : true;
492 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
493
494 for (i = 0; i < max_slots; i++) {
495 if (slots[i]) {
496 if (slots[i]->bank_swizzle_force) {
497 slots[i]->bank_swizzle = slots[i]->bank_swizzle_force;
498 } else {
499 forced = 0;
500 }
501 }
502
503 if (i < 4 && slots[i])
504 scalar_only = false;
505 }
506 if (forced)
507 return 0;
508
509 /* Just check every possible combination of bank swizzle.
510 * Not very efficent, but works on the first try in most of the cases. */
511 for (i = 0; i < 4; i++)
512 if (!slots[i] || !slots[i]->bank_swizzle_force)
513 bank_swizzle[i] = SQ_ALU_VEC_012;
514 else
515 bank_swizzle[i] = slots[i]->bank_swizzle;
516
517 bank_swizzle[4] = SQ_ALU_SCL_210;
518 while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
519
520 init_bank_swizzle(&bs);
521 if (scalar_only == false) {
522 for (i = 0; i < 4; i++) {
523 if (slots[i]) {
524 r = check_vector(bc, slots[i], &bs, bank_swizzle[i]);
525 if (r)
526 break;
527 }
528 }
529 } else
530 r = 0;
531
532 if (!r && max_slots == 5 && slots[4]) {
533 r = check_scalar(bc, slots[4], &bs, bank_swizzle[4]);
534 }
535 if (!r) {
536 for (i = 0; i < max_slots; i++) {
537 if (slots[i])
538 slots[i]->bank_swizzle = bank_swizzle[i];
539 }
540 return 0;
541 }
542
543 if (scalar_only) {
544 bank_swizzle[4]++;
545 } else {
546 for (i = 0; i < max_slots; i++) {
547 if (!slots[i] || !slots[i]->bank_swizzle_force) {
548 bank_swizzle[i]++;
549 if (bank_swizzle[i] <= SQ_ALU_VEC_210)
550 break;
551 else if (i < max_slots - 1)
552 bank_swizzle[i] = SQ_ALU_VEC_012;
553 else
554 return -1;
555 }
556 }
557 }
558 }
559
560 /* Couldn't find a working swizzle. */
561 return -1;
562 }
563
564 static int replace_gpr_with_pv_ps(struct r600_bytecode *bc,
565 struct r600_bytecode_alu *slots[5], struct r600_bytecode_alu *alu_prev)
566 {
567 struct r600_bytecode_alu *prev[5];
568 int gpr[5], chan[5];
569 int i, j, r, src, num_src;
570 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
571
572 r = assign_alu_units(bc, alu_prev, prev);
573 if (r)
574 return r;
575
576 for (i = 0; i < max_slots; ++i) {
577 if (prev[i] && (prev[i]->dst.write || prev[i]->is_op3) && !prev[i]->dst.rel) {
578 gpr[i] = prev[i]->dst.sel;
579 /* cube writes more than PV.X */
580 if (is_alu_reduction_inst(bc, prev[i]))
581 chan[i] = 0;
582 else
583 chan[i] = prev[i]->dst.chan;
584 } else
585 gpr[i] = -1;
586 }
587
588 for (i = 0; i < max_slots; ++i) {
589 struct r600_bytecode_alu *alu = slots[i];
590 if(!alu)
591 continue;
592
593 num_src = r600_bytecode_get_num_operands(bc, alu);
594 for (src = 0; src < num_src; ++src) {
595 if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
596 continue;
597
598 if (bc->chip_class < CAYMAN) {
599 if (alu->src[src].sel == gpr[4] &&
600 alu->src[src].chan == chan[4] &&
601 alu_prev->pred_sel == alu->pred_sel) {
602 alu->src[src].sel = V_SQ_ALU_SRC_PS;
603 alu->src[src].chan = 0;
604 continue;
605 }
606 }
607
608 for (j = 0; j < 4; ++j) {
609 if (alu->src[src].sel == gpr[j] &&
610 alu->src[src].chan == j &&
611 alu_prev->pred_sel == alu->pred_sel) {
612 alu->src[src].sel = V_SQ_ALU_SRC_PV;
613 alu->src[src].chan = chan[j];
614 break;
615 }
616 }
617 }
618 }
619
620 return 0;
621 }
622
623 void r600_bytecode_special_constants(uint32_t value, unsigned *sel, unsigned *neg)
624 {
625 switch(value) {
626 case 0:
627 *sel = V_SQ_ALU_SRC_0;
628 break;
629 case 1:
630 *sel = V_SQ_ALU_SRC_1_INT;
631 break;
632 case -1:
633 *sel = V_SQ_ALU_SRC_M_1_INT;
634 break;
635 case 0x3F800000: /* 1.0f */
636 *sel = V_SQ_ALU_SRC_1;
637 break;
638 case 0x3F000000: /* 0.5f */
639 *sel = V_SQ_ALU_SRC_0_5;
640 break;
641 case 0xBF800000: /* -1.0f */
642 *sel = V_SQ_ALU_SRC_1;
643 *neg ^= 1;
644 break;
645 case 0xBF000000: /* -0.5f */
646 *sel = V_SQ_ALU_SRC_0_5;
647 *neg ^= 1;
648 break;
649 default:
650 *sel = V_SQ_ALU_SRC_LITERAL;
651 break;
652 }
653 }
654
655 /* compute how many literal are needed */
656 static int r600_bytecode_alu_nliterals(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
657 uint32_t literal[4], unsigned *nliteral)
658 {
659 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
660 unsigned i, j;
661
662 for (i = 0; i < num_src; ++i) {
663 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
664 uint32_t value = alu->src[i].value;
665 unsigned found = 0;
666 for (j = 0; j < *nliteral; ++j) {
667 if (literal[j] == value) {
668 found = 1;
669 break;
670 }
671 }
672 if (!found) {
673 if (*nliteral >= 4)
674 return -EINVAL;
675 literal[(*nliteral)++] = value;
676 }
677 }
678 }
679 return 0;
680 }
681
682 static void r600_bytecode_alu_adjust_literals(struct r600_bytecode *bc,
683 struct r600_bytecode_alu *alu,
684 uint32_t literal[4], unsigned nliteral)
685 {
686 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
687 unsigned i, j;
688
689 for (i = 0; i < num_src; ++i) {
690 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
691 uint32_t value = alu->src[i].value;
692 for (j = 0; j < nliteral; ++j) {
693 if (literal[j] == value) {
694 alu->src[i].chan = j;
695 break;
696 }
697 }
698 }
699 }
700 }
701
702 static int merge_inst_groups(struct r600_bytecode *bc, struct r600_bytecode_alu *slots[5],
703 struct r600_bytecode_alu *alu_prev)
704 {
705 struct r600_bytecode_alu *prev[5];
706 struct r600_bytecode_alu *result[5] = { NULL };
707
708 uint32_t literal[4], prev_literal[4];
709 unsigned nliteral = 0, prev_nliteral = 0;
710
711 int i, j, r, src, num_src;
712 int num_once_inst = 0;
713 int have_mova = 0, have_rel = 0;
714 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
715
716 r = assign_alu_units(bc, alu_prev, prev);
717 if (r)
718 return r;
719
720 for (i = 0; i < max_slots; ++i) {
721 if (prev[i]) {
722 if (prev[i]->pred_sel)
723 return 0;
724 if (is_alu_once_inst(bc, prev[i]))
725 return 0;
726 }
727 if (slots[i]) {
728 if (slots[i]->pred_sel)
729 return 0;
730 if (is_alu_once_inst(bc, slots[i]))
731 return 0;
732 }
733 }
734
735 for (i = 0; i < max_slots; ++i) {
736 struct r600_bytecode_alu *alu;
737
738 if (num_once_inst > 0)
739 return 0;
740
741 /* check number of literals */
742 if (prev[i]) {
743 if (r600_bytecode_alu_nliterals(bc, prev[i], literal, &nliteral))
744 return 0;
745 if (r600_bytecode_alu_nliterals(bc, prev[i], prev_literal, &prev_nliteral))
746 return 0;
747 if (is_alu_mova_inst(bc, prev[i])) {
748 if (have_rel)
749 return 0;
750 have_mova = 1;
751 }
752
753 if (alu_uses_rel(bc, prev[i])) {
754 if (have_mova) {
755 return 0;
756 }
757 have_rel = 1;
758 }
759
760 num_once_inst += is_alu_once_inst(bc, prev[i]);
761 }
762 if (slots[i] && r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral))
763 return 0;
764
765 /* Let's check used slots. */
766 if (prev[i] && !slots[i]) {
767 result[i] = prev[i];
768 continue;
769 } else if (prev[i] && slots[i]) {
770 if (max_slots == 5 && result[4] == NULL && prev[4] == NULL && slots[4] == NULL) {
771 /* Trans unit is still free try to use it. */
772 if (is_alu_any_unit_inst(bc, slots[i])) {
773 result[i] = prev[i];
774 result[4] = slots[i];
775 } else if (is_alu_any_unit_inst(bc, prev[i])) {
776 if (slots[i]->dst.sel == prev[i]->dst.sel &&
777 (slots[i]->dst.write == 1 || slots[i]->is_op3) &&
778 (prev[i]->dst.write == 1 || prev[i]->is_op3))
779 return 0;
780
781 result[i] = slots[i];
782 result[4] = prev[i];
783 } else
784 return 0;
785 } else
786 return 0;
787 } else if(!slots[i]) {
788 continue;
789 } else {
790 if (max_slots == 5 && slots[i] && prev[4] &&
791 slots[i]->dst.sel == prev[4]->dst.sel &&
792 slots[i]->dst.chan == prev[4]->dst.chan &&
793 (slots[i]->dst.write == 1 || slots[i]->is_op3) &&
794 (prev[4]->dst.write == 1 || prev[4]->is_op3))
795 return 0;
796
797 result[i] = slots[i];
798 }
799
800 alu = slots[i];
801 num_once_inst += is_alu_once_inst(bc, alu);
802
803 /* don't reschedule NOPs */
804 if (is_nop_inst(bc, alu))
805 return 0;
806
807 if (is_alu_mova_inst(bc, alu)) {
808 if (have_rel) {
809 return 0;
810 }
811 have_mova = 1;
812 }
813
814 if (alu_uses_rel(bc, alu)) {
815 if (have_mova) {
816 return 0;
817 }
818 have_rel = 1;
819 }
820
821 /* Let's check source gprs */
822 num_src = r600_bytecode_get_num_operands(bc, alu);
823 for (src = 0; src < num_src; ++src) {
824
825 /* Constants don't matter. */
826 if (!is_gpr(alu->src[src].sel))
827 continue;
828
829 for (j = 0; j < max_slots; ++j) {
830 if (!prev[j] || !(prev[j]->dst.write || prev[j]->is_op3))
831 continue;
832
833 /* If it's relative then we can't determin which gpr is really used. */
834 if (prev[j]->dst.chan == alu->src[src].chan &&
835 (prev[j]->dst.sel == alu->src[src].sel ||
836 prev[j]->dst.rel || alu->src[src].rel))
837 return 0;
838 }
839 }
840 }
841
842 /* more than one PRED_ or KILL_ ? */
843 if (num_once_inst > 1)
844 return 0;
845
846 /* check if the result can still be swizzlet */
847 r = check_and_set_bank_swizzle(bc, result);
848 if (r)
849 return 0;
850
851 /* looks like everything worked out right, apply the changes */
852
853 /* undo adding previus literals */
854 bc->cf_last->ndw -= align(prev_nliteral, 2);
855
856 /* sort instructions */
857 for (i = 0; i < max_slots; ++i) {
858 slots[i] = result[i];
859 if (result[i]) {
860 LIST_DEL(&result[i]->list);
861 result[i]->last = 0;
862 LIST_ADDTAIL(&result[i]->list, &bc->cf_last->alu);
863 }
864 }
865
866 /* determine new last instruction */
867 LIST_ENTRY(struct r600_bytecode_alu, bc->cf_last->alu.prev, list)->last = 1;
868
869 /* determine new first instruction */
870 for (i = 0; i < max_slots; ++i) {
871 if (result[i]) {
872 bc->cf_last->curr_bs_head = result[i];
873 break;
874 }
875 }
876
877 bc->cf_last->prev_bs_head = bc->cf_last->prev2_bs_head;
878 bc->cf_last->prev2_bs_head = NULL;
879
880 return 0;
881 }
882
883 /* we'll keep kcache sets sorted by bank & addr */
884 static int r600_bytecode_alloc_kcache_line(struct r600_bytecode *bc,
885 struct r600_bytecode_kcache *kcache,
886 unsigned bank, unsigned line)
887 {
888 int i, kcache_banks = bc->chip_class >= EVERGREEN ? 4 : 2;
889
890 for (i = 0; i < kcache_banks; i++) {
891 if (kcache[i].mode) {
892 int d;
893
894 if (kcache[i].bank < bank)
895 continue;
896
897 if ((kcache[i].bank == bank && kcache[i].addr > line+1) ||
898 kcache[i].bank > bank) {
899 /* try to insert new line */
900 if (kcache[kcache_banks-1].mode) {
901 /* all sets are in use */
902 return -ENOMEM;
903 }
904
905 memmove(&kcache[i+1],&kcache[i], (kcache_banks-i-1)*sizeof(struct r600_bytecode_kcache));
906 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
907 kcache[i].bank = bank;
908 kcache[i].addr = line;
909 return 0;
910 }
911
912 d = line - kcache[i].addr;
913
914 if (d == -1) {
915 kcache[i].addr--;
916 if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_2) {
917 /* we are prepending the line to the current set,
918 * discarding the existing second line,
919 * so we'll have to insert line+2 after it */
920 line += 2;
921 continue;
922 } else if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_1) {
923 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
924 return 0;
925 } else {
926 /* V_SQ_CF_KCACHE_LOCK_LOOP_INDEX is not supported */
927 return -ENOMEM;
928 }
929 } else if (d == 1) {
930 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
931 return 0;
932 } else if (d == 0)
933 return 0;
934 } else { /* free kcache set - use it */
935 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
936 kcache[i].bank = bank;
937 kcache[i].addr = line;
938 return 0;
939 }
940 }
941 return -ENOMEM;
942 }
943
944 static int r600_bytecode_alloc_inst_kcache_lines(struct r600_bytecode *bc,
945 struct r600_bytecode_kcache *kcache,
946 struct r600_bytecode_alu *alu)
947 {
948 int i, r;
949
950 for (i = 0; i < 3; i++) {
951 unsigned bank, line, sel = alu->src[i].sel;
952
953 if (sel < 512)
954 continue;
955
956 bank = alu->src[i].kc_bank;
957 line = (sel-512)>>4;
958
959 if ((r = r600_bytecode_alloc_kcache_line(bc, kcache, bank, line)))
960 return r;
961 }
962 return 0;
963 }
964
965 static int r600_bytecode_assign_kcache_banks(struct r600_bytecode *bc,
966 struct r600_bytecode_alu *alu,
967 struct r600_bytecode_kcache * kcache)
968 {
969 int i, j;
970
971 /* Alter the src operands to refer to the kcache. */
972 for (i = 0; i < 3; ++i) {
973 static const unsigned int base[] = {128, 160, 256, 288};
974 unsigned int line, sel = alu->src[i].sel, found = 0;
975
976 if (sel < 512)
977 continue;
978
979 sel -= 512;
980 line = sel>>4;
981
982 for (j = 0; j < 4 && !found; ++j) {
983 switch (kcache[j].mode) {
984 case V_SQ_CF_KCACHE_NOP:
985 case V_SQ_CF_KCACHE_LOCK_LOOP_INDEX:
986 R600_ERR("unexpected kcache line mode\n");
987 return -ENOMEM;
988 default:
989 if (kcache[j].bank == alu->src[i].kc_bank &&
990 kcache[j].addr <= line &&
991 line < kcache[j].addr + kcache[j].mode) {
992 alu->src[i].sel = sel - (kcache[j].addr<<4);
993 alu->src[i].sel += base[j];
994 found=1;
995 }
996 }
997 }
998 }
999 return 0;
1000 }
1001
1002 static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode *bc,
1003 struct r600_bytecode_alu *alu,
1004 unsigned type)
1005 {
1006 struct r600_bytecode_kcache kcache_sets[4];
1007 struct r600_bytecode_kcache *kcache = kcache_sets;
1008 int r;
1009
1010 memcpy(kcache, bc->cf_last->kcache, 4 * sizeof(struct r600_bytecode_kcache));
1011
1012 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1013 /* can't alloc, need to start new clause */
1014 if ((r = r600_bytecode_add_cf(bc))) {
1015 return r;
1016 }
1017 bc->cf_last->op = type;
1018
1019 /* retry with the new clause */
1020 kcache = bc->cf_last->kcache;
1021 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1022 /* can't alloc again- should never happen */
1023 return r;
1024 }
1025 } else {
1026 /* update kcache sets */
1027 memcpy(bc->cf_last->kcache, kcache, 4 * sizeof(struct r600_bytecode_kcache));
1028 }
1029
1030 /* if we actually used more than 2 kcache sets - use ALU_EXTENDED on eg+ */
1031 if (kcache[2].mode != V_SQ_CF_KCACHE_NOP) {
1032 if (bc->chip_class < EVERGREEN)
1033 return -ENOMEM;
1034 bc->cf_last->eg_alu_extended = 1;
1035 }
1036
1037 return 0;
1038 }
1039
1040 static int insert_nop_r6xx(struct r600_bytecode *bc)
1041 {
1042 struct r600_bytecode_alu alu;
1043 int r, i;
1044
1045 for (i = 0; i < 4; i++) {
1046 memset(&alu, 0, sizeof(alu));
1047 alu.op = ALU_OP0_NOP;
1048 alu.src[0].chan = i;
1049 alu.dst.chan = i;
1050 alu.last = (i == 3);
1051 r = r600_bytecode_add_alu(bc, &alu);
1052 if (r)
1053 return r;
1054 }
1055 return 0;
1056 }
1057
1058 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1059 static int load_ar_r6xx(struct r600_bytecode *bc)
1060 {
1061 struct r600_bytecode_alu alu;
1062 int r;
1063
1064 if (bc->ar_loaded)
1065 return 0;
1066
1067 /* hack to avoid making MOVA the last instruction in the clause */
1068 if ((bc->cf_last->ndw>>1) >= 110)
1069 bc->force_add_cf = 1;
1070
1071 memset(&alu, 0, sizeof(alu));
1072 alu.op = ALU_OP1_MOVA_GPR_INT;
1073 alu.src[0].sel = bc->ar_reg;
1074 alu.src[0].chan = bc->ar_chan;
1075 alu.last = 1;
1076 alu.index_mode = INDEX_MODE_LOOP;
1077 r = r600_bytecode_add_alu(bc, &alu);
1078 if (r)
1079 return r;
1080
1081 /* no requirement to set uses waterfall on MOVA_GPR_INT */
1082 bc->ar_loaded = 1;
1083 return 0;
1084 }
1085
1086 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1087 static int load_ar(struct r600_bytecode *bc)
1088 {
1089 struct r600_bytecode_alu alu;
1090 int r;
1091
1092 if (bc->ar_handling)
1093 return load_ar_r6xx(bc);
1094
1095 if (bc->ar_loaded)
1096 return 0;
1097
1098 /* hack to avoid making MOVA the last instruction in the clause */
1099 if ((bc->cf_last->ndw>>1) >= 110)
1100 bc->force_add_cf = 1;
1101
1102 memset(&alu, 0, sizeof(alu));
1103 alu.op = ALU_OP1_MOVA_INT;
1104 alu.src[0].sel = bc->ar_reg;
1105 alu.src[0].chan = bc->ar_chan;
1106 alu.last = 1;
1107 r = r600_bytecode_add_alu(bc, &alu);
1108 if (r)
1109 return r;
1110
1111 bc->cf_last->r6xx_uses_waterfall = 1;
1112 bc->ar_loaded = 1;
1113 return 0;
1114 }
1115
1116 int r600_bytecode_add_alu_type(struct r600_bytecode *bc,
1117 const struct r600_bytecode_alu *alu, unsigned type)
1118 {
1119 struct r600_bytecode_alu *nalu = r600_bytecode_alu();
1120 struct r600_bytecode_alu *lalu;
1121 int i, r;
1122
1123 if (nalu == NULL)
1124 return -ENOMEM;
1125 memcpy(nalu, alu, sizeof(struct r600_bytecode_alu));
1126
1127 if (bc->cf_last != NULL && bc->cf_last->op != type) {
1128 /* check if we could add it anyway */
1129 if (bc->cf_last->op == CF_OP_ALU &&
1130 type == CF_OP_ALU_PUSH_BEFORE) {
1131 LIST_FOR_EACH_ENTRY(lalu, &bc->cf_last->alu, list) {
1132 if (lalu->execute_mask) {
1133 bc->force_add_cf = 1;
1134 break;
1135 }
1136 }
1137 } else
1138 bc->force_add_cf = 1;
1139 }
1140
1141 /* cf can contains only alu or only vtx or only tex */
1142 if (bc->cf_last == NULL || bc->force_add_cf) {
1143 r = r600_bytecode_add_cf(bc);
1144 if (r) {
1145 free(nalu);
1146 return r;
1147 }
1148 }
1149 bc->cf_last->op = type;
1150
1151 /* Check AR usage and load it if required */
1152 for (i = 0; i < 3; i++)
1153 if (nalu->src[i].rel && !bc->ar_loaded)
1154 load_ar(bc);
1155
1156 if (nalu->dst.rel && !bc->ar_loaded)
1157 load_ar(bc);
1158
1159 /* Setup the kcache for this ALU instruction. This will start a new
1160 * ALU clause if needed. */
1161 if ((r = r600_bytecode_alloc_kcache_lines(bc, nalu, type))) {
1162 free(nalu);
1163 return r;
1164 }
1165
1166 if (!bc->cf_last->curr_bs_head) {
1167 bc->cf_last->curr_bs_head = nalu;
1168 }
1169 /* number of gpr == the last gpr used in any alu */
1170 for (i = 0; i < 3; i++) {
1171 if (nalu->src[i].sel >= bc->ngpr && nalu->src[i].sel < 128) {
1172 bc->ngpr = nalu->src[i].sel + 1;
1173 }
1174 if (nalu->src[i].sel == V_SQ_ALU_SRC_LITERAL)
1175 r600_bytecode_special_constants(nalu->src[i].value,
1176 &nalu->src[i].sel, &nalu->src[i].neg);
1177 }
1178 if (nalu->dst.sel >= bc->ngpr) {
1179 bc->ngpr = nalu->dst.sel + 1;
1180 }
1181 LIST_ADDTAIL(&nalu->list, &bc->cf_last->alu);
1182 /* each alu use 2 dwords */
1183 bc->cf_last->ndw += 2;
1184 bc->ndw += 2;
1185
1186 /* process cur ALU instructions for bank swizzle */
1187 if (nalu->last) {
1188 uint32_t literal[4];
1189 unsigned nliteral;
1190 struct r600_bytecode_alu *slots[5];
1191 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
1192 r = assign_alu_units(bc, bc->cf_last->curr_bs_head, slots);
1193 if (r)
1194 return r;
1195
1196 if (bc->cf_last->prev_bs_head) {
1197 r = merge_inst_groups(bc, slots, bc->cf_last->prev_bs_head);
1198 if (r)
1199 return r;
1200 }
1201
1202 if (bc->cf_last->prev_bs_head) {
1203 r = replace_gpr_with_pv_ps(bc, slots, bc->cf_last->prev_bs_head);
1204 if (r)
1205 return r;
1206 }
1207
1208 r = check_and_set_bank_swizzle(bc, slots);
1209 if (r)
1210 return r;
1211
1212 for (i = 0, nliteral = 0; i < max_slots; i++) {
1213 if (slots[i]) {
1214 r = r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral);
1215 if (r)
1216 return r;
1217 }
1218 }
1219 bc->cf_last->ndw += align(nliteral, 2);
1220
1221 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1222 * worst case */
1223 if ((bc->cf_last->ndw >> 1) >= 120) {
1224 bc->force_add_cf = 1;
1225 }
1226
1227 bc->cf_last->prev2_bs_head = bc->cf_last->prev_bs_head;
1228 bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head;
1229 bc->cf_last->curr_bs_head = NULL;
1230 }
1231
1232 if (nalu->dst.rel && bc->r6xx_nop_after_rel_dst)
1233 insert_nop_r6xx(bc);
1234
1235 return 0;
1236 }
1237
1238 int r600_bytecode_add_alu(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu)
1239 {
1240 return r600_bytecode_add_alu_type(bc, alu, CF_OP_ALU);
1241 }
1242
1243 static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode *bc)
1244 {
1245 switch (bc->chip_class) {
1246 case R600:
1247 return 8;
1248
1249 case R700:
1250 case EVERGREEN:
1251 case CAYMAN:
1252 return 16;
1253
1254 default:
1255 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1256 return 8;
1257 }
1258 }
1259
1260 static inline boolean last_inst_was_not_vtx_fetch(struct r600_bytecode *bc)
1261 {
1262 return !((r600_isa_cf(bc->cf_last->op)->flags & CF_FETCH) &&
1263 (bc->chip_class == CAYMAN ||
1264 bc->cf_last->op != CF_OP_TEX));
1265 }
1266
1267 int r600_bytecode_add_vtx(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx)
1268 {
1269 struct r600_bytecode_vtx *nvtx = r600_bytecode_vtx();
1270 int r;
1271
1272 if (nvtx == NULL)
1273 return -ENOMEM;
1274 memcpy(nvtx, vtx, sizeof(struct r600_bytecode_vtx));
1275
1276 /* cf can contains only alu or only vtx or only tex */
1277 if (bc->cf_last == NULL ||
1278 last_inst_was_not_vtx_fetch(bc) ||
1279 bc->force_add_cf) {
1280 r = r600_bytecode_add_cf(bc);
1281 if (r) {
1282 free(nvtx);
1283 return r;
1284 }
1285 switch (bc->chip_class) {
1286 case R600:
1287 case R700:
1288 case EVERGREEN:
1289 bc->cf_last->op = CF_OP_VTX;
1290 break;
1291 case CAYMAN:
1292 bc->cf_last->op = CF_OP_TEX;
1293 break;
1294 default:
1295 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1296 free(nvtx);
1297 return -EINVAL;
1298 }
1299 }
1300 LIST_ADDTAIL(&nvtx->list, &bc->cf_last->vtx);
1301 /* each fetch use 4 dwords */
1302 bc->cf_last->ndw += 4;
1303 bc->ndw += 4;
1304 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1305 bc->force_add_cf = 1;
1306
1307 bc->ngpr = MAX2(bc->ngpr, vtx->src_gpr + 1);
1308 bc->ngpr = MAX2(bc->ngpr, vtx->dst_gpr + 1);
1309
1310 return 0;
1311 }
1312
1313 int r600_bytecode_add_tex(struct r600_bytecode *bc, const struct r600_bytecode_tex *tex)
1314 {
1315 struct r600_bytecode_tex *ntex = r600_bytecode_tex();
1316 int r;
1317
1318 if (ntex == NULL)
1319 return -ENOMEM;
1320 memcpy(ntex, tex, sizeof(struct r600_bytecode_tex));
1321
1322 /* we can't fetch data und use it as texture lookup address in the same TEX clause */
1323 if (bc->cf_last != NULL &&
1324 bc->cf_last->op == CF_OP_TEX) {
1325 struct r600_bytecode_tex *ttex;
1326 LIST_FOR_EACH_ENTRY(ttex, &bc->cf_last->tex, list) {
1327 if (ttex->dst_gpr == ntex->src_gpr) {
1328 bc->force_add_cf = 1;
1329 break;
1330 }
1331 }
1332 /* slight hack to make gradients always go into same cf */
1333 if (ntex->op == FETCH_OP_SET_GRADIENTS_H)
1334 bc->force_add_cf = 1;
1335 }
1336
1337 /* cf can contains only alu or only vtx or only tex */
1338 if (bc->cf_last == NULL ||
1339 bc->cf_last->op != CF_OP_TEX ||
1340 bc->force_add_cf) {
1341 r = r600_bytecode_add_cf(bc);
1342 if (r) {
1343 free(ntex);
1344 return r;
1345 }
1346 bc->cf_last->op = CF_OP_TEX;
1347 }
1348 if (ntex->src_gpr >= bc->ngpr) {
1349 bc->ngpr = ntex->src_gpr + 1;
1350 }
1351 if (ntex->dst_gpr >= bc->ngpr) {
1352 bc->ngpr = ntex->dst_gpr + 1;
1353 }
1354 LIST_ADDTAIL(&ntex->list, &bc->cf_last->tex);
1355 /* each texture fetch use 4 dwords */
1356 bc->cf_last->ndw += 4;
1357 bc->ndw += 4;
1358 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1359 bc->force_add_cf = 1;
1360 return 0;
1361 }
1362
1363 int r600_bytecode_add_cfinst(struct r600_bytecode *bc, unsigned op)
1364 {
1365 int r;
1366 r = r600_bytecode_add_cf(bc);
1367 if (r)
1368 return r;
1369
1370 bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
1371 bc->cf_last->op = op;
1372 return 0;
1373 }
1374
1375 int cm_bytecode_add_cf_end(struct r600_bytecode *bc)
1376 {
1377 return r600_bytecode_add_cfinst(bc, CF_OP_CF_END);
1378 }
1379
1380 /* common to all 3 families */
1381 static int r600_bytecode_vtx_build(struct r600_bytecode *bc, struct r600_bytecode_vtx *vtx, unsigned id)
1382 {
1383 bc->bytecode[id] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) |
1384 S_SQ_VTX_WORD0_FETCH_TYPE(vtx->fetch_type) |
1385 S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
1386 S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x);
1387 if (bc->chip_class < CAYMAN)
1388 bc->bytecode[id] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
1389 id++;
1390 bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
1391 S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
1392 S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
1393 S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
1394 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) |
1395 S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) |
1396 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) |
1397 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) |
1398 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
1399 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
1400 bc->bytecode[id] = S_SQ_VTX_WORD2_OFFSET(vtx->offset)|
1401 S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx->endian);
1402 if (bc->chip_class < CAYMAN)
1403 bc->bytecode[id] |= S_SQ_VTX_WORD2_MEGA_FETCH(1);
1404 id++;
1405 bc->bytecode[id++] = 0;
1406 return 0;
1407 }
1408
1409 /* common to all 3 families */
1410 static int r600_bytecode_tex_build(struct r600_bytecode *bc, struct r600_bytecode_tex *tex, unsigned id)
1411 {
1412 bc->bytecode[id++] = S_SQ_TEX_WORD0_TEX_INST(
1413 r600_isa_fetch_opcode(bc->isa->hw_class, tex->op)) |
1414 EG_S_SQ_TEX_WORD0_INST_MOD(tex->inst_mod) |
1415 S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
1416 S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
1417 S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
1418 bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
1419 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
1420 S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
1421 S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
1422 S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
1423 S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
1424 S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
1425 S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
1426 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
1427 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
1428 S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
1429 bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
1430 S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
1431 S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
1432 S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
1433 S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
1434 S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
1435 S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
1436 S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
1437 bc->bytecode[id++] = 0;
1438 return 0;
1439 }
1440
1441 /* r600 only, r700/eg bits in r700_asm.c */
1442 static int r600_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id)
1443 {
1444 unsigned opcode = r600_isa_alu_opcode(bc->isa->hw_class, alu->op);
1445
1446 /* don't replace gpr by pv or ps for destination register */
1447 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
1448 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
1449 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
1450 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
1451 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
1452 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
1453 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
1454 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
1455 S_SQ_ALU_WORD0_INDEX_MODE(alu->index_mode) |
1456 S_SQ_ALU_WORD0_PRED_SEL(alu->pred_sel) |
1457 S_SQ_ALU_WORD0_LAST(alu->last);
1458
1459 if (alu->is_op3) {
1460 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1461 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1462 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1463 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1464 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
1465 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
1466 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
1467 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
1468 S_SQ_ALU_WORD1_OP3_ALU_INST(opcode) |
1469 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
1470 } else {
1471 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1472 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1473 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1474 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1475 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
1476 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
1477 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
1478 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
1479 S_SQ_ALU_WORD1_OP2_ALU_INST(opcode) |
1480 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
1481 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->execute_mask) |
1482 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->update_pred);
1483 }
1484 return 0;
1485 }
1486
1487 static void r600_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_cf *cf)
1488 {
1489 *bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
1490 *bytecode++ = S_SQ_CF_WORD1_CF_INST(r600_isa_cf_opcode(ISA_CC_R600, cf->op)) |
1491 S_SQ_CF_WORD1_BARRIER(1) |
1492 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
1493 }
1494
1495 /* common for r600/r700 - eg in eg_asm.c */
1496 static int r600_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf)
1497 {
1498 unsigned id = cf->id;
1499 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
1500 unsigned opcode = r600_isa_cf_opcode(bc->isa->hw_class, cf->op);
1501
1502
1503 if (cf->op == CF_NATIVE) {
1504 bc->bytecode[id++] = cf->isa[0];
1505 bc->bytecode[id++] = cf->isa[1];
1506 } else if (cfop->flags & CF_ALU) {
1507 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
1508 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
1509 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
1510 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank);
1511
1512 bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(opcode) |
1513 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) |
1514 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
1515 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
1516 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1517 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chip_class == R600 ? cf->r6xx_uses_waterfall : 0) |
1518 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
1519 } else if (cfop->flags & CF_FETCH) {
1520 if (bc->chip_class == R700)
1521 r700_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1522 else
1523 r600_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1524 } else if (cfop->flags & CF_EXP) {
1525 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1526 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1527 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1528 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type) |
1529 S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(cf->output.index_gpr);
1530 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1531 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
1532 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
1533 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
1534 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
1535 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->barrier) |
1536 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) |
1537 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->end_of_program);
1538 } else if (cfop->flags & CF_MEM) {
1539 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1540 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1541 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1542 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type) |
1543 S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(cf->output.index_gpr);
1544 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1545 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->barrier) |
1546 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) |
1547 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->end_of_program) |
1548 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf->output.array_size) |
1549 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf->output.comp_mask);
1550 } else {
1551 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
1552 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(opcode) |
1553 S_SQ_CF_WORD1_BARRIER(1) |
1554 S_SQ_CF_WORD1_COND(cf->cond) |
1555 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count) |
1556 S_SQ_CF_WORD1_END_OF_PROGRAM(cf->end_of_program);
1557 }
1558 return 0;
1559 }
1560
1561 int r600_bytecode_build(struct r600_bytecode *bc)
1562 {
1563 struct r600_bytecode_cf *cf;
1564 struct r600_bytecode_alu *alu;
1565 struct r600_bytecode_vtx *vtx;
1566 struct r600_bytecode_tex *tex;
1567 uint32_t literal[4];
1568 unsigned nliteral;
1569 unsigned addr;
1570 int i, r;
1571
1572 if (!bc->nstack) // If not 0, Stack_size already provided by llvm
1573 bc->nstack = bc->stack.max_entries;
1574
1575 if (bc->type == TGSI_PROCESSOR_VERTEX && !bc->nstack) {
1576 bc->nstack = 1;
1577 }
1578
1579 /* first path compute addr of each CF block */
1580 /* addr start after all the CF instructions */
1581 addr = bc->cf_last->id + 2;
1582 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1583 if (r600_isa_cf(cf->op)->flags & CF_FETCH) {
1584 addr += 3;
1585 addr &= 0xFFFFFFFCUL;
1586 }
1587 cf->addr = addr;
1588 addr += cf->ndw;
1589 bc->ndw = cf->addr + cf->ndw;
1590 }
1591 free(bc->bytecode);
1592 bc->bytecode = calloc(1, bc->ndw * 4);
1593 if (bc->bytecode == NULL)
1594 return -ENOMEM;
1595 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1596 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
1597 addr = cf->addr;
1598 if (bc->chip_class >= EVERGREEN)
1599 r = eg_bytecode_cf_build(bc, cf);
1600 else
1601 r = r600_bytecode_cf_build(bc, cf);
1602 if (r)
1603 return r;
1604 if (cfop->flags & CF_ALU) {
1605 nliteral = 0;
1606 memset(literal, 0, sizeof(literal));
1607 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1608 r = r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
1609 if (r)
1610 return r;
1611 r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral);
1612 r600_bytecode_assign_kcache_banks(bc, alu, cf->kcache);
1613
1614 switch(bc->chip_class) {
1615 case R600:
1616 r = r600_bytecode_alu_build(bc, alu, addr);
1617 break;
1618 case R700:
1619 case EVERGREEN: /* eg alu is same encoding as r700 */
1620 case CAYMAN:
1621 r = r700_bytecode_alu_build(bc, alu, addr);
1622 break;
1623 default:
1624 R600_ERR("unknown chip class %d.\n", bc->chip_class);
1625 return -EINVAL;
1626 }
1627 if (r)
1628 return r;
1629 addr += 2;
1630 if (alu->last) {
1631 for (i = 0; i < align(nliteral, 2); ++i) {
1632 bc->bytecode[addr++] = literal[i];
1633 }
1634 nliteral = 0;
1635 memset(literal, 0, sizeof(literal));
1636 }
1637 }
1638 } else if (cf->op == CF_OP_VTX) {
1639 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1640 r = r600_bytecode_vtx_build(bc, vtx, addr);
1641 if (r)
1642 return r;
1643 addr += 4;
1644 }
1645 } else if (cf->op == CF_OP_TEX) {
1646 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1647 assert(bc->chip_class >= EVERGREEN);
1648 r = r600_bytecode_vtx_build(bc, vtx, addr);
1649 if (r)
1650 return r;
1651 addr += 4;
1652 }
1653 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
1654 r = r600_bytecode_tex_build(bc, tex, addr);
1655 if (r)
1656 return r;
1657 addr += 4;
1658 }
1659 }
1660 }
1661 return 0;
1662 }
1663
1664 void r600_bytecode_clear(struct r600_bytecode *bc)
1665 {
1666 struct r600_bytecode_cf *cf = NULL, *next_cf;
1667
1668 free(bc->bytecode);
1669 bc->bytecode = NULL;
1670
1671 LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
1672 struct r600_bytecode_alu *alu = NULL, *next_alu;
1673 struct r600_bytecode_tex *tex = NULL, *next_tex;
1674 struct r600_bytecode_tex *vtx = NULL, *next_vtx;
1675
1676 LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
1677 free(alu);
1678 }
1679
1680 LIST_INITHEAD(&cf->alu);
1681
1682 LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) {
1683 free(tex);
1684 }
1685
1686 LIST_INITHEAD(&cf->tex);
1687
1688 LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) {
1689 free(vtx);
1690 }
1691
1692 LIST_INITHEAD(&cf->vtx);
1693
1694 free(cf);
1695 }
1696
1697 LIST_INITHEAD(&cf->list);
1698 }
1699
1700 static int print_swizzle(unsigned swz)
1701 {
1702 const char * swzchars = "xyzw01?_";
1703 assert(swz<8 && swz != 6);
1704 return fprintf(stderr, "%c", swzchars[swz]);
1705 }
1706
1707 static int print_sel(unsigned sel, unsigned rel, unsigned index_mode,
1708 unsigned need_brackets)
1709 {
1710 int o = 0;
1711 if (rel && index_mode >= 5 && sel < 128)
1712 o += fprintf(stderr, "G");
1713 if (rel || need_brackets) {
1714 o += fprintf(stderr, "[");
1715 }
1716 o += fprintf(stderr, "%d", sel);
1717 if (rel) {
1718 if (index_mode == 0 || index_mode == 6)
1719 o += fprintf(stderr, "+AR");
1720 else if (index_mode == 4)
1721 o += fprintf(stderr, "+AL");
1722 }
1723 if (rel || need_brackets) {
1724 o += fprintf(stderr, "]");
1725 }
1726 return o;
1727 }
1728
1729 static int print_dst(struct r600_bytecode_alu *alu)
1730 {
1731 int o = 0;
1732 unsigned sel = alu->dst.sel;
1733 char reg_char = 'R';
1734 if (sel > 128 - 4) { /* clause temporary gpr */
1735 sel -= 128 - 4;
1736 reg_char = 'T';
1737 }
1738
1739 if (alu->dst.write || alu->is_op3) {
1740 o += fprintf(stderr, "%c", reg_char);
1741 o += print_sel(alu->dst.sel, alu->dst.rel, alu->index_mode, 0);
1742 } else {
1743 o += fprintf(stderr, "__");
1744 }
1745 o += fprintf(stderr, ".");
1746 o += print_swizzle(alu->dst.chan);
1747 return o;
1748 }
1749
1750 static int print_src(struct r600_bytecode_alu *alu, unsigned idx)
1751 {
1752 int o = 0;
1753 struct r600_bytecode_alu_src *src = &alu->src[idx];
1754 unsigned sel = src->sel, need_sel = 1, need_chan = 1, need_brackets = 0;
1755
1756 if (src->neg)
1757 o += fprintf(stderr,"-");
1758 if (src->abs)
1759 o += fprintf(stderr,"|");
1760
1761 if (sel < 128 - 4) {
1762 o += fprintf(stderr, "R");
1763 } else if (sel < 128) {
1764 o += fprintf(stderr, "T");
1765 sel -= 128 - 4;
1766 } else if (sel < 160) {
1767 o += fprintf(stderr, "KC0");
1768 need_brackets = 1;
1769 sel -= 128;
1770 } else if (sel < 192) {
1771 o += fprintf(stderr, "KC1");
1772 need_brackets = 1;
1773 sel -= 160;
1774 } else if (sel >= 512) {
1775 o += fprintf(stderr, "C%d", src->kc_bank);
1776 need_brackets = 1;
1777 sel -= 512;
1778 } else if (sel >= 448) {
1779 o += fprintf(stderr, "Param");
1780 sel -= 448;
1781 need_chan = 0;
1782 } else if (sel >= 288) {
1783 o += fprintf(stderr, "KC3");
1784 need_brackets = 1;
1785 sel -= 288;
1786 } else if (sel >= 256) {
1787 o += fprintf(stderr, "KC2");
1788 need_brackets = 1;
1789 sel -= 256;
1790 } else {
1791 need_sel = 0;
1792 need_chan = 0;
1793 switch (sel) {
1794 case V_SQ_ALU_SRC_PS:
1795 o += fprintf(stderr, "PS");
1796 break;
1797 case V_SQ_ALU_SRC_PV:
1798 o += fprintf(stderr, "PV");
1799 need_chan = 1;
1800 break;
1801 case V_SQ_ALU_SRC_LITERAL:
1802 o += fprintf(stderr, "[0x%08X %f]", src->value, *(float*)&src->value);
1803 break;
1804 case V_SQ_ALU_SRC_0_5:
1805 o += fprintf(stderr, "0.5");
1806 break;
1807 case V_SQ_ALU_SRC_M_1_INT:
1808 o += fprintf(stderr, "-1");
1809 break;
1810 case V_SQ_ALU_SRC_1_INT:
1811 o += fprintf(stderr, "1");
1812 break;
1813 case V_SQ_ALU_SRC_1:
1814 o += fprintf(stderr, "1.0");
1815 break;
1816 case V_SQ_ALU_SRC_0:
1817 o += fprintf(stderr, "0");
1818 break;
1819 default:
1820 o += fprintf(stderr, "??IMM_%d", sel);
1821 break;
1822 }
1823 }
1824
1825 if (need_sel)
1826 o += print_sel(sel, src->rel, alu->index_mode, need_brackets);
1827
1828 if (need_chan) {
1829 o += fprintf(stderr, ".");
1830 o += print_swizzle(src->chan);
1831 }
1832
1833 if (src->abs)
1834 o += fprintf(stderr,"|");
1835
1836 return o;
1837 }
1838
1839 static int print_indent(int p, int c)
1840 {
1841 int o = 0;
1842 while (p++ < c)
1843 o += fprintf(stderr, " ");
1844 return o;
1845 }
1846
1847 void r600_bytecode_disasm(struct r600_bytecode *bc)
1848 {
1849 static int index = 0;
1850 struct r600_bytecode_cf *cf = NULL;
1851 struct r600_bytecode_alu *alu = NULL;
1852 struct r600_bytecode_vtx *vtx = NULL;
1853 struct r600_bytecode_tex *tex = NULL;
1854
1855 unsigned i, id, ngr = 0, last;
1856 uint32_t literal[4];
1857 unsigned nliteral;
1858 char chip = '6';
1859
1860 switch (bc->chip_class) {
1861 case R700:
1862 chip = '7';
1863 break;
1864 case EVERGREEN:
1865 chip = 'E';
1866 break;
1867 case CAYMAN:
1868 chip = 'C';
1869 break;
1870 case R600:
1871 default:
1872 chip = '6';
1873 break;
1874 }
1875 fprintf(stderr, "bytecode %d dw -- %d gprs -- %d nstack -------------\n",
1876 bc->ndw, bc->ngpr, bc->nstack);
1877 fprintf(stderr, "shader %d -- %c\n", index++, chip);
1878
1879 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1880 id = cf->id;
1881 if (cf->op == CF_NATIVE) {
1882 fprintf(stderr, "%04d %08X %08X CF_NATIVE\n", id, bc->bytecode[id],
1883 bc->bytecode[id + 1]);
1884 } else {
1885 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
1886 if (cfop->flags & CF_ALU) {
1887 if (cf->eg_alu_extended) {
1888 fprintf(stderr, "%04d %08X %08X %s\n", id, bc->bytecode[id],
1889 bc->bytecode[id + 1], "ALU_EXT");
1890 id += 2;
1891 }
1892 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
1893 bc->bytecode[id + 1], cfop->name);
1894 fprintf(stderr, "%d @%d ", cf->ndw / 2, cf->addr);
1895 for (i = 0; i < 4; ++i) {
1896 if (cf->kcache[i].mode) {
1897 int c_start = (cf->kcache[i].addr << 4);
1898 int c_end = c_start + (cf->kcache[i].mode << 4);
1899 fprintf(stderr, "KC%d[CB%d:%d-%d] ",
1900 i, cf->kcache[i].bank, c_start, c_end);
1901 }
1902 }
1903 fprintf(stderr, "\n");
1904 } else if (cfop->flags & CF_FETCH) {
1905 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
1906 bc->bytecode[id + 1], cfop->name);
1907 fprintf(stderr, "%d @%d ", cf->ndw / 4, cf->addr);
1908 fprintf(stderr, "\n");
1909 } else if (cfop->flags & CF_EXP) {
1910 int o = 0;
1911 const char *exp_type[] = {"PIXEL", "POS ", "PARAM"};
1912 o += fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
1913 bc->bytecode[id + 1], cfop->name);
1914 o += print_indent(o, 43);
1915 o += fprintf(stderr, "%s ", exp_type[cf->output.type]);
1916 if (cf->output.burst_count > 1) {
1917 o += fprintf(stderr, "%d-%d ", cf->output.array_base,
1918 cf->output.array_base + cf->output.burst_count - 1);
1919
1920 o += print_indent(o, 55);
1921 o += fprintf(stderr, "R%d-%d.", cf->output.gpr,
1922 cf->output.gpr + cf->output.burst_count - 1);
1923 } else {
1924 o += fprintf(stderr, "%d ", cf->output.array_base);
1925 o += print_indent(o, 55);
1926 o += fprintf(stderr, "R%d.", cf->output.gpr);
1927 }
1928
1929 o += print_swizzle(cf->output.swizzle_x);
1930 o += print_swizzle(cf->output.swizzle_y);
1931 o += print_swizzle(cf->output.swizzle_z);
1932 o += print_swizzle(cf->output.swizzle_w);
1933
1934 print_indent(o, 67);
1935
1936 fprintf(stderr, " ES:%X ", cf->output.elem_size);
1937 if (!cf->barrier)
1938 fprintf(stderr, "NO_BARRIER ");
1939 if (cf->end_of_program)
1940 fprintf(stderr, "EOP ");
1941 fprintf(stderr, "\n");
1942 } else if (r600_isa_cf(cf->op)->flags & CF_MEM) {
1943 int o = 0;
1944 const char *exp_type[] = {"WRITE", "WRITE_IND", "WRITE_ACK",
1945 "WRITE_IND_ACK"};
1946 o += fprintf(stderr, "%04d %08X %08X %s ", id,
1947 bc->bytecode[id], bc->bytecode[id + 1], cfop->name);
1948 o += print_indent(o, 43);
1949 o += fprintf(stderr, "%s ", exp_type[cf->output.type]);
1950 if (cf->output.burst_count > 1) {
1951 o += fprintf(stderr, "%d-%d ", cf->output.array_base,
1952 cf->output.array_base + cf->output.burst_count - 1);
1953 o += print_indent(o, 55);
1954 o += fprintf(stderr, "R%d-%d.", cf->output.gpr,
1955 cf->output.gpr + cf->output.burst_count - 1);
1956 } else {
1957 o += fprintf(stderr, "%d ", cf->output.array_base);
1958 o += print_indent(o, 55);
1959 o += fprintf(stderr, "R%d.", cf->output.gpr);
1960 }
1961 for (i = 0; i < 4; ++i) {
1962 if (cf->output.comp_mask & (1 << i))
1963 o += print_swizzle(i);
1964 else
1965 o += print_swizzle(7);
1966 }
1967
1968 if (cf->output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND)
1969 o += fprintf(stderr, " R%d", cf->output.index_gpr);
1970
1971 o += print_indent(o, 67);
1972
1973 fprintf(stderr, " ES:%i ", cf->output.elem_size);
1974 if (cf->output.array_size != 0xFFF)
1975 fprintf(stderr, "AS:%i ", cf->output.array_size);
1976 if (!cf->barrier)
1977 fprintf(stderr, "NO_BARRIER ");
1978 if (cf->end_of_program)
1979 fprintf(stderr, "EOP ");
1980 fprintf(stderr, "\n");
1981 } else {
1982 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
1983 bc->bytecode[id + 1], cfop->name);
1984 fprintf(stderr, "@%d ", cf->cf_addr);
1985 if (cf->cond)
1986 fprintf(stderr, "CND:%X ", cf->cond);
1987 if (cf->pop_count)
1988 fprintf(stderr, "POP:%X ", cf->pop_count);
1989 fprintf(stderr, "\n");
1990 }
1991 }
1992
1993 id = cf->addr;
1994 nliteral = 0;
1995 last = 1;
1996 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1997 const char *omod_str[] = {"","*2","*4","/2"};
1998 const struct alu_op_info *aop = r600_isa_alu(alu->op);
1999 int o = 0;
2000
2001 r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
2002 o += fprintf(stderr, " %04d %08X %08X ", id, bc->bytecode[id], bc->bytecode[id+1]);
2003 if (last)
2004 o += fprintf(stderr, "%4d ", ++ngr);
2005 else
2006 o += fprintf(stderr, " ");
2007 o += fprintf(stderr, "%c%c %c ", alu->execute_mask ? 'M':' ',
2008 alu->update_pred ? 'P':' ',
2009 alu->pred_sel ? alu->pred_sel==2 ? '0':'1':' ');
2010
2011 o += fprintf(stderr, "%s%s%s ", aop->name,
2012 omod_str[alu->omod], alu->dst.clamp ? "_sat":"");
2013
2014 o += print_indent(o,60);
2015 o += print_dst(alu);
2016 for (i = 0; i < aop->src_count; ++i) {
2017 o += fprintf(stderr, i == 0 ? ", ": ", ");
2018 o += print_src(alu, i);
2019 }
2020
2021 if (alu->bank_swizzle) {
2022 o += print_indent(o,75);
2023 o += fprintf(stderr, " BS:%d", alu->bank_swizzle);
2024 }
2025
2026 fprintf(stderr, "\n");
2027 id += 2;
2028
2029 if (alu->last) {
2030 for (i = 0; i < nliteral; i++, id++) {
2031 float *f = (float*)(bc->bytecode + id);
2032 o = fprintf(stderr, " %04d %08X", id, bc->bytecode[id]);
2033 print_indent(o, 60);
2034 fprintf(stderr, " %f (%d)\n", *f, *(bc->bytecode + id));
2035 }
2036 id += nliteral & 1;
2037 nliteral = 0;
2038 }
2039 last = alu->last;
2040 }
2041
2042 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2043 int o = 0;
2044 o += fprintf(stderr, " %04d %08X %08X %08X ", id, bc->bytecode[id],
2045 bc->bytecode[id + 1], bc->bytecode[id + 2]);
2046
2047 o += fprintf(stderr, "%s ", r600_isa_fetch(tex->op)->name);
2048
2049 o += print_indent(o, 50);
2050
2051 o += fprintf(stderr, "R%d.", tex->dst_gpr);
2052 o += print_swizzle(tex->dst_sel_x);
2053 o += print_swizzle(tex->dst_sel_y);
2054 o += print_swizzle(tex->dst_sel_z);
2055 o += print_swizzle(tex->dst_sel_w);
2056
2057 o += fprintf(stderr, ", R%d.", tex->src_gpr);
2058 o += print_swizzle(tex->src_sel_x);
2059 o += print_swizzle(tex->src_sel_y);
2060 o += print_swizzle(tex->src_sel_z);
2061 o += print_swizzle(tex->src_sel_w);
2062
2063 o += fprintf(stderr, ", RID:%d", tex->resource_id);
2064 o += fprintf(stderr, ", SID:%d ", tex->sampler_id);
2065
2066 if (tex->lod_bias)
2067 fprintf(stderr, "LB:%d ", tex->lod_bias);
2068
2069 fprintf(stderr, "CT:%c%c%c%c ",
2070 tex->coord_type_x ? 'N' : 'U',
2071 tex->coord_type_y ? 'N' : 'U',
2072 tex->coord_type_z ? 'N' : 'U',
2073 tex->coord_type_w ? 'N' : 'U');
2074
2075 if (tex->offset_x)
2076 fprintf(stderr, "OX:%d ", tex->offset_x);
2077 if (tex->offset_y)
2078 fprintf(stderr, "OY:%d ", tex->offset_y);
2079 if (tex->offset_z)
2080 fprintf(stderr, "OZ:%d ", tex->offset_z);
2081
2082 id += 4;
2083 fprintf(stderr, "\n");
2084 }
2085
2086 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2087 int o = 0;
2088 const char * fetch_type[] = {"VERTEX", "INSTANCE", ""};
2089 o += fprintf(stderr, " %04d %08X %08X %08X ", id, bc->bytecode[id],
2090 bc->bytecode[id + 1], bc->bytecode[id + 2]);
2091
2092 o += fprintf(stderr, "%s ", r600_isa_fetch(vtx->op)->name);
2093
2094 o += print_indent(o, 50);
2095
2096 o += fprintf(stderr, "R%d.", vtx->dst_gpr);
2097 o += print_swizzle(vtx->dst_sel_x);
2098 o += print_swizzle(vtx->dst_sel_y);
2099 o += print_swizzle(vtx->dst_sel_z);
2100 o += print_swizzle(vtx->dst_sel_w);
2101
2102 o += fprintf(stderr, ", R%d.", vtx->src_gpr);
2103 o += print_swizzle(vtx->src_sel_x);
2104
2105 if (vtx->offset)
2106 fprintf(stderr, " +%db", vtx->offset);
2107
2108 o += print_indent(o, 55);
2109
2110 fprintf(stderr, ", RID:%d ", vtx->buffer_id);
2111
2112 fprintf(stderr, "%s ", fetch_type[vtx->fetch_type]);
2113
2114 if (bc->chip_class < CAYMAN && vtx->mega_fetch_count)
2115 fprintf(stderr, "MFC:%d ", vtx->mega_fetch_count);
2116
2117 fprintf(stderr, "UCF:%d ", vtx->use_const_fields);
2118 fprintf(stderr, "FMT(DTA:%d ", vtx->data_format);
2119 fprintf(stderr, "NUM:%d ", vtx->num_format_all);
2120 fprintf(stderr, "COMP:%d ", vtx->format_comp_all);
2121 fprintf(stderr, "MODE:%d)\n", vtx->srf_mode_all);
2122
2123 id += 4;
2124 }
2125 }
2126
2127 fprintf(stderr, "--------------------------------------\n");
2128 }
2129
2130 void r600_vertex_data_type(enum pipe_format pformat,
2131 unsigned *format,
2132 unsigned *num_format, unsigned *format_comp, unsigned *endian)
2133 {
2134 const struct util_format_description *desc;
2135 unsigned i;
2136
2137 *format = 0;
2138 *num_format = 0;
2139 *format_comp = 0;
2140 *endian = ENDIAN_NONE;
2141
2142 if (pformat == PIPE_FORMAT_R11G11B10_FLOAT) {
2143 *format = FMT_10_11_11_FLOAT;
2144 *endian = r600_endian_swap(32);
2145 return;
2146 }
2147
2148 desc = util_format_description(pformat);
2149 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
2150 goto out_unknown;
2151 }
2152
2153 /* Find the first non-VOID channel. */
2154 for (i = 0; i < 4; i++) {
2155 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2156 break;
2157 }
2158 }
2159
2160 *endian = r600_endian_swap(desc->channel[i].size);
2161
2162 switch (desc->channel[i].type) {
2163 /* Half-floats, floats, ints */
2164 case UTIL_FORMAT_TYPE_FLOAT:
2165 switch (desc->channel[i].size) {
2166 case 16:
2167 switch (desc->nr_channels) {
2168 case 1:
2169 *format = FMT_16_FLOAT;
2170 break;
2171 case 2:
2172 *format = FMT_16_16_FLOAT;
2173 break;
2174 case 3:
2175 case 4:
2176 *format = FMT_16_16_16_16_FLOAT;
2177 break;
2178 }
2179 break;
2180 case 32:
2181 switch (desc->nr_channels) {
2182 case 1:
2183 *format = FMT_32_FLOAT;
2184 break;
2185 case 2:
2186 *format = FMT_32_32_FLOAT;
2187 break;
2188 case 3:
2189 *format = FMT_32_32_32_FLOAT;
2190 break;
2191 case 4:
2192 *format = FMT_32_32_32_32_FLOAT;
2193 break;
2194 }
2195 break;
2196 default:
2197 goto out_unknown;
2198 }
2199 break;
2200 /* Unsigned ints */
2201 case UTIL_FORMAT_TYPE_UNSIGNED:
2202 /* Signed ints */
2203 case UTIL_FORMAT_TYPE_SIGNED:
2204 switch (desc->channel[i].size) {
2205 case 8:
2206 switch (desc->nr_channels) {
2207 case 1:
2208 *format = FMT_8;
2209 break;
2210 case 2:
2211 *format = FMT_8_8;
2212 break;
2213 case 3:
2214 case 4:
2215 *format = FMT_8_8_8_8;
2216 break;
2217 }
2218 break;
2219 case 10:
2220 if (desc->nr_channels != 4)
2221 goto out_unknown;
2222
2223 *format = FMT_2_10_10_10;
2224 break;
2225 case 16:
2226 switch (desc->nr_channels) {
2227 case 1:
2228 *format = FMT_16;
2229 break;
2230 case 2:
2231 *format = FMT_16_16;
2232 break;
2233 case 3:
2234 case 4:
2235 *format = FMT_16_16_16_16;
2236 break;
2237 }
2238 break;
2239 case 32:
2240 switch (desc->nr_channels) {
2241 case 1:
2242 *format = FMT_32;
2243 break;
2244 case 2:
2245 *format = FMT_32_32;
2246 break;
2247 case 3:
2248 *format = FMT_32_32_32;
2249 break;
2250 case 4:
2251 *format = FMT_32_32_32_32;
2252 break;
2253 }
2254 break;
2255 default:
2256 goto out_unknown;
2257 }
2258 break;
2259 default:
2260 goto out_unknown;
2261 }
2262
2263 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2264 *format_comp = 1;
2265 }
2266
2267 *num_format = 0;
2268 if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED ||
2269 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2270 if (!desc->channel[i].normalized) {
2271 if (desc->channel[i].pure_integer)
2272 *num_format = 1;
2273 else
2274 *num_format = 2;
2275 }
2276 }
2277 return;
2278 out_unknown:
2279 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
2280 }
2281
2282 void *r600_create_vertex_fetch_shader(struct pipe_context *ctx,
2283 unsigned count,
2284 const struct pipe_vertex_element *elements)
2285 {
2286 struct r600_context *rctx = (struct r600_context *)ctx;
2287 struct r600_bytecode bc;
2288 struct r600_bytecode_vtx vtx;
2289 const struct util_format_description *desc;
2290 unsigned fetch_resource_start = rctx->b.chip_class >= EVERGREEN ? 0 : 160;
2291 unsigned format, num_format, format_comp, endian;
2292 uint32_t *bytecode;
2293 int i, j, r, fs_size;
2294 struct r600_fetch_shader *shader;
2295 unsigned no_sb = rctx->screen->b.debug_flags & DBG_NO_SB;
2296 unsigned sb_disasm = !no_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
2297
2298 assert(count < 32);
2299
2300 memset(&bc, 0, sizeof(bc));
2301 r600_bytecode_init(&bc, rctx->b.chip_class, rctx->b.family,
2302 rctx->screen->has_compressed_msaa_texturing);
2303
2304 bc.isa = rctx->isa;
2305
2306 for (i = 0; i < count; i++) {
2307 if (elements[i].instance_divisor > 1) {
2308 if (rctx->b.chip_class == CAYMAN) {
2309 for (j = 0; j < 4; j++) {
2310 struct r600_bytecode_alu alu;
2311 memset(&alu, 0, sizeof(alu));
2312 alu.op = ALU_OP2_MULHI_UINT;
2313 alu.src[0].sel = 0;
2314 alu.src[0].chan = 3;
2315 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2316 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2317 alu.dst.sel = i + 1;
2318 alu.dst.chan = j;
2319 alu.dst.write = j == 3;
2320 alu.last = j == 3;
2321 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2322 r600_bytecode_clear(&bc);
2323 return NULL;
2324 }
2325 }
2326 } else {
2327 struct r600_bytecode_alu alu;
2328 memset(&alu, 0, sizeof(alu));
2329 alu.op = ALU_OP2_MULHI_UINT;
2330 alu.src[0].sel = 0;
2331 alu.src[0].chan = 3;
2332 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2333 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2334 alu.dst.sel = i + 1;
2335 alu.dst.chan = 3;
2336 alu.dst.write = 1;
2337 alu.last = 1;
2338 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2339 r600_bytecode_clear(&bc);
2340 return NULL;
2341 }
2342 }
2343 }
2344 }
2345
2346 for (i = 0; i < count; i++) {
2347 r600_vertex_data_type(elements[i].src_format,
2348 &format, &num_format, &format_comp, &endian);
2349
2350 desc = util_format_description(elements[i].src_format);
2351 if (desc == NULL) {
2352 r600_bytecode_clear(&bc);
2353 R600_ERR("unknown format %d\n", elements[i].src_format);
2354 return NULL;
2355 }
2356
2357 if (elements[i].src_offset > 65535) {
2358 r600_bytecode_clear(&bc);
2359 R600_ERR("too big src_offset: %u\n", elements[i].src_offset);
2360 return NULL;
2361 }
2362
2363 memset(&vtx, 0, sizeof(vtx));
2364 vtx.buffer_id = elements[i].vertex_buffer_index + fetch_resource_start;
2365 vtx.fetch_type = elements[i].instance_divisor ? 1 : 0;
2366 vtx.src_gpr = elements[i].instance_divisor > 1 ? i + 1 : 0;
2367 vtx.src_sel_x = elements[i].instance_divisor ? 3 : 0;
2368 vtx.mega_fetch_count = 0x1F;
2369 vtx.dst_gpr = i + 1;
2370 vtx.dst_sel_x = desc->swizzle[0];
2371 vtx.dst_sel_y = desc->swizzle[1];
2372 vtx.dst_sel_z = desc->swizzle[2];
2373 vtx.dst_sel_w = desc->swizzle[3];
2374 vtx.data_format = format;
2375 vtx.num_format_all = num_format;
2376 vtx.format_comp_all = format_comp;
2377 vtx.srf_mode_all = 1;
2378 vtx.offset = elements[i].src_offset;
2379 vtx.endian = endian;
2380
2381 if ((r = r600_bytecode_add_vtx(&bc, &vtx))) {
2382 r600_bytecode_clear(&bc);
2383 return NULL;
2384 }
2385 }
2386
2387 r600_bytecode_add_cfinst(&bc, CF_OP_RET);
2388
2389 if ((r = r600_bytecode_build(&bc))) {
2390 r600_bytecode_clear(&bc);
2391 return NULL;
2392 }
2393
2394 if (rctx->screen->b.debug_flags & DBG_FS) {
2395 fprintf(stderr, "--------------------------------------------------------------\n");
2396 fprintf(stderr, "Vertex elements state:\n");
2397 for (i = 0; i < count; i++) {
2398 fprintf(stderr, " ");
2399 util_dump_vertex_element(stderr, elements+i);
2400 fprintf(stderr, "\n");
2401 }
2402
2403 if (!sb_disasm) {
2404 r600_bytecode_disasm(&bc);
2405
2406 fprintf(stderr, "______________________________________________________________\n");
2407 } else {
2408 r600_sb_bytecode_process(rctx, &bc, NULL, 1 /*dump*/, 0 /*optimize*/);
2409 }
2410 }
2411
2412 fs_size = bc.ndw*4;
2413
2414 /* Allocate the CSO. */
2415 shader = CALLOC_STRUCT(r600_fetch_shader);
2416 if (!shader) {
2417 r600_bytecode_clear(&bc);
2418 return NULL;
2419 }
2420
2421 u_suballocator_alloc(rctx->allocator_fetch_shader, fs_size, &shader->offset,
2422 (struct pipe_resource**)&shader->buffer);
2423 if (!shader->buffer) {
2424 r600_bytecode_clear(&bc);
2425 FREE(shader);
2426 return NULL;
2427 }
2428
2429 bytecode = r600_buffer_map_sync_with_rings(&rctx->b, shader->buffer, PIPE_TRANSFER_WRITE | PIPE_TRANSFER_UNSYNCHRONIZED);
2430 bytecode += shader->offset / 4;
2431
2432 if (R600_BIG_ENDIAN) {
2433 for (i = 0; i < fs_size / 4; ++i) {
2434 bytecode[i] = util_cpu_to_le32(bc.bytecode[i]);
2435 }
2436 } else {
2437 memcpy(bytecode, bc.bytecode, fs_size);
2438 }
2439 rctx->b.ws->buffer_unmap(shader->buffer->cs_buf);
2440
2441 r600_bytecode_clear(&bc);
2442 return shader;
2443 }
2444
2445 void r600_bytecode_alu_read(struct r600_bytecode *bc,
2446 struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1)
2447 {
2448 /* WORD0 */
2449 alu->src[0].sel = G_SQ_ALU_WORD0_SRC0_SEL(word0);
2450 alu->src[0].rel = G_SQ_ALU_WORD0_SRC0_REL(word0);
2451 alu->src[0].chan = G_SQ_ALU_WORD0_SRC0_CHAN(word0);
2452 alu->src[0].neg = G_SQ_ALU_WORD0_SRC0_NEG(word0);
2453 alu->src[1].sel = G_SQ_ALU_WORD0_SRC1_SEL(word0);
2454 alu->src[1].rel = G_SQ_ALU_WORD0_SRC1_REL(word0);
2455 alu->src[1].chan = G_SQ_ALU_WORD0_SRC1_CHAN(word0);
2456 alu->src[1].neg = G_SQ_ALU_WORD0_SRC1_NEG(word0);
2457 alu->index_mode = G_SQ_ALU_WORD0_INDEX_MODE(word0);
2458 alu->pred_sel = G_SQ_ALU_WORD0_PRED_SEL(word0);
2459 alu->last = G_SQ_ALU_WORD0_LAST(word0);
2460
2461 /* WORD1 */
2462 alu->bank_swizzle = G_SQ_ALU_WORD1_BANK_SWIZZLE(word1);
2463 if (alu->bank_swizzle)
2464 alu->bank_swizzle_force = alu->bank_swizzle;
2465 alu->dst.sel = G_SQ_ALU_WORD1_DST_GPR(word1);
2466 alu->dst.rel = G_SQ_ALU_WORD1_DST_REL(word1);
2467 alu->dst.chan = G_SQ_ALU_WORD1_DST_CHAN(word1);
2468 alu->dst.clamp = G_SQ_ALU_WORD1_CLAMP(word1);
2469 if (G_SQ_ALU_WORD1_ENCODING(word1)) /*ALU_DWORD1_OP3*/
2470 {
2471 alu->is_op3 = 1;
2472 alu->src[2].sel = G_SQ_ALU_WORD1_OP3_SRC2_SEL(word1);
2473 alu->src[2].rel = G_SQ_ALU_WORD1_OP3_SRC2_REL(word1);
2474 alu->src[2].chan = G_SQ_ALU_WORD1_OP3_SRC2_CHAN(word1);
2475 alu->src[2].neg = G_SQ_ALU_WORD1_OP3_SRC2_NEG(word1);
2476 alu->op = r600_isa_alu_by_opcode(bc->isa,
2477 G_SQ_ALU_WORD1_OP3_ALU_INST(word1), /* is_op3 = */ 1);
2478
2479 }
2480 else /*ALU_DWORD1_OP2*/
2481 {
2482 alu->src[0].abs = G_SQ_ALU_WORD1_OP2_SRC0_ABS(word1);
2483 alu->src[1].abs = G_SQ_ALU_WORD1_OP2_SRC1_ABS(word1);
2484 alu->op = r600_isa_alu_by_opcode(bc->isa,
2485 G_SQ_ALU_WORD1_OP2_ALU_INST(word1), /* is_op3 = */ 0);
2486 alu->omod = G_SQ_ALU_WORD1_OP2_OMOD(word1);
2487 alu->dst.write = G_SQ_ALU_WORD1_OP2_WRITE_MASK(word1);
2488 alu->update_pred = G_SQ_ALU_WORD1_OP2_UPDATE_PRED(word1);
2489 alu->execute_mask =
2490 G_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(word1);
2491 }
2492 }
2493
2494 #if 0
2495 void r600_bytecode_export_read(struct r600_bytecode *bc,
2496 struct r600_bytecode_output *output, uint32_t word0, uint32_t word1)
2497 {
2498 output->array_base = G_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(word0);
2499 output->type = G_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(word0);
2500 output->gpr = G_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(word0);
2501 output->elem_size = G_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(word0);
2502
2503 output->swizzle_x = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(word1);
2504 output->swizzle_y = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(word1);
2505 output->swizzle_z = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(word1);
2506 output->swizzle_w = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(word1);
2507 output->burst_count = G_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(word1);
2508 output->end_of_program = G_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(word1);
2509 output->op = r600_isa_cf_by_opcode(bc->isa,
2510 G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(word1), 0);
2511 output->barrier = G_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(word1);
2512 output->array_size = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(word1);
2513 output->comp_mask = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(word1);
2514 }
2515 #endif