projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
r600g: don't reserve more stack space than required v5
[mesa.git] / src / gallium / drivers / r600 / r600_asm.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_opcodes.h"
25 #include "r600_formats.h"
26 #include "r600_shader.h"
27 #include "r600d.h"
28
29 #include <errno.h>
30 #include <byteswap.h>
31 #include "util/u_dump.h"
32 #include "util/u_memory.h"
33 #include "pipe/p_shader_tokens.h"
34
35 #define NUM_OF_CYCLES 3
36 #define NUM_OF_COMPONENTS 4
37
38 static inline unsigned int r600_bytecode_get_num_operands(
39 struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
40 {
41 return r600_isa_alu(alu->op)->src_count;
42 }
43
44 int r700_bytecode_alu_build(struct r600_bytecode *bc,
45 struct r600_bytecode_alu *alu, unsigned id);
46
47 static struct r600_bytecode_cf *r600_bytecode_cf(void)
48 {
49 struct r600_bytecode_cf *cf = CALLOC_STRUCT(r600_bytecode_cf);
50
51 if (cf == NULL)
52 return NULL;
53 LIST_INITHEAD(&cf->list);
54 LIST_INITHEAD(&cf->alu);
55 LIST_INITHEAD(&cf->vtx);
56 LIST_INITHEAD(&cf->tex);
57 return cf;
58 }
59
60 static struct r600_bytecode_alu *r600_bytecode_alu(void)
61 {
62 struct r600_bytecode_alu *alu = CALLOC_STRUCT(r600_bytecode_alu);
63
64 if (alu == NULL)
65 return NULL;
66 LIST_INITHEAD(&alu->list);
67 return alu;
68 }
69
70 static struct r600_bytecode_vtx *r600_bytecode_vtx(void)
71 {
72 struct r600_bytecode_vtx *vtx = CALLOC_STRUCT(r600_bytecode_vtx);
73
74 if (vtx == NULL)
75 return NULL;
76 LIST_INITHEAD(&vtx->list);
77 return vtx;
78 }
79
80 static struct r600_bytecode_tex *r600_bytecode_tex(void)
81 {
82 struct r600_bytecode_tex *tex = CALLOC_STRUCT(r600_bytecode_tex);
83
84 if (tex == NULL)
85 return NULL;
86 LIST_INITHEAD(&tex->list);
87 return tex;
88 }
89
90 static unsigned stack_entry_size(enum radeon_family chip) {
91 /* Wavefront size:
92 * 64: R600/RV670/RV770/Cypress/R740/Barts/Turks/Caicos/
93 * Aruba/Sumo/Sumo2/redwood/juniper
94 * 32: R630/R730/R710/Palm/Cedar
95 * 16: R610/Rs780
96 *
97 * Stack row size:
98 * Wavefront Size 16 32 48 64
99 * Columns per Row (R6xx/R7xx/R8xx only) 8 8 4 4
100 * Columns per Row (R9xx+) 8 4 4 4 */
101
102 switch (chip) {
103 /* FIXME: are some chips missing here? */
104 /* wavefront size 16 */
105 case CHIP_RV610:
106 case CHIP_RS780:
107 case CHIP_RV620:
108 case CHIP_RS880:
109 /* wavefront size 32 */
110 case CHIP_RV630:
111 case CHIP_RV635:
112 case CHIP_RV730:
113 case CHIP_RV710:
114 case CHIP_PALM:
115 case CHIP_CEDAR:
116 return 8;
117
118 /* wavefront size 64 */
119 default:
120 return 4;
121 }
122 }
123
124 void r600_bytecode_init(struct r600_bytecode *bc,
125 enum chip_class chip_class,
126 enum radeon_family family,
127 enum r600_msaa_texture_mode msaa_texture_mode)
128 {
129 if ((chip_class == R600) &&
130 (family != CHIP_RV670 && family != CHIP_RS780 && family != CHIP_RS880)) {
131 bc->ar_handling = AR_HANDLE_RV6XX;
132 bc->r6xx_nop_after_rel_dst = 1;
133 } else {
134 bc->ar_handling = AR_HANDLE_NORMAL;
135 bc->r6xx_nop_after_rel_dst = 0;
136 }
137
138 LIST_INITHEAD(&bc->cf);
139 bc->chip_class = chip_class;
140 bc->msaa_texture_mode = msaa_texture_mode;
141 bc->stack.entry_size = stack_entry_size(family);
142 }
143
144 int r600_bytecode_add_cf(struct r600_bytecode *bc)
145 {
146 struct r600_bytecode_cf *cf = r600_bytecode_cf();
147
148 if (cf == NULL)
149 return -ENOMEM;
150 LIST_ADDTAIL(&cf->list, &bc->cf);
151 if (bc->cf_last) {
152 cf->id = bc->cf_last->id + 2;
153 if (bc->cf_last->eg_alu_extended) {
154 /* take into account extended alu size */
155 cf->id += 2;
156 bc->ndw += 2;
157 }
158 }
159 bc->cf_last = cf;
160 bc->ncf++;
161 bc->ndw += 2;
162 bc->force_add_cf = 0;
163 bc->ar_loaded = 0;
164 return 0;
165 }
166
167 int r600_bytecode_add_output(struct r600_bytecode *bc,
168 const struct r600_bytecode_output *output)
169 {
170 int r;
171
172 if (output->gpr >= bc->ngpr)
173 bc->ngpr = output->gpr + 1;
174
175 if (bc->cf_last && (bc->cf_last->op == output->op ||
176 (bc->cf_last->op == CF_OP_EXPORT &&
177 output->op == CF_OP_EXPORT_DONE)) &&
178 output->type == bc->cf_last->output.type &&
179 output->elem_size == bc->cf_last->output.elem_size &&
180 output->swizzle_x == bc->cf_last->output.swizzle_x &&
181 output->swizzle_y == bc->cf_last->output.swizzle_y &&
182 output->swizzle_z == bc->cf_last->output.swizzle_z &&
183 output->swizzle_w == bc->cf_last->output.swizzle_w &&
184 output->comp_mask == bc->cf_last->output.comp_mask &&
185 (output->burst_count + bc->cf_last->output.burst_count) <= 16) {
186
187 if ((output->gpr + output->burst_count) == bc->cf_last->output.gpr &&
188 (output->array_base + output->burst_count) == bc->cf_last->output.array_base) {
189
190 bc->cf_last->output.end_of_program |= output->end_of_program;
191 bc->cf_last->op = bc->cf_last->output.op = output->op;
192 bc->cf_last->output.gpr = output->gpr;
193 bc->cf_last->output.array_base = output->array_base;
194 bc->cf_last->output.burst_count += output->burst_count;
195 return 0;
196
197 } else if (output->gpr == (bc->cf_last->output.gpr + bc->cf_last->output.burst_count) &&
198 output->array_base == (bc->cf_last->output.array_base + bc->cf_last->output.burst_count)) {
199
200 bc->cf_last->output.end_of_program |= output->end_of_program;
201 bc->cf_last->op = bc->cf_last->output.op = output->op;
202 bc->cf_last->output.burst_count += output->burst_count;
203 return 0;
204 }
205 }
206
207 r = r600_bytecode_add_cf(bc);
208 if (r)
209 return r;
210 bc->cf_last->op = output->op;
211 memcpy(&bc->cf_last->output, output, sizeof(struct r600_bytecode_output));
212 return 0;
213 }
214
215 /* alu instructions that can ony exits once per group */
216 static int is_alu_once_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
217 {
218 return r600_isa_alu(alu->op)->flags & (AF_KILL | AF_PRED);
219 }
220
221 static int is_alu_reduction_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
222 {
223 return (r600_isa_alu(alu->op)->flags & AF_REPL) &&
224 (r600_isa_alu_slots(bc->isa->hw_class, alu->op) == AF_4V);
225 }
226
227 static int is_alu_mova_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
228 {
229 return r600_isa_alu(alu->op)->flags & AF_MOVA;
230 }
231
232 static int alu_uses_rel(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
233 {
234 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
235 unsigned src;
236
237 if (alu->dst.rel) {
238 return 1;
239 }
240
241 for (src = 0; src < num_src; ++src) {
242 if (alu->src[src].rel) {
243 return 1;
244 }
245 }
246 return 0;
247 }
248
249 static int is_alu_vec_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
250 {
251 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
252 return !(slots & AF_S);
253 }
254
255 static int is_alu_trans_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
256 {
257 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
258 return !(slots & AF_V);
259 }
260
261 /* alu instructions that can execute on any unit */
262 static int is_alu_any_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
263 {
264 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
265 return slots == AF_VS;
266 }
267
268 static int is_nop_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
269 {
270 return alu->op == ALU_OP0_NOP;
271 }
272
273 static int assign_alu_units(struct r600_bytecode *bc, struct r600_bytecode_alu *alu_first,
274 struct r600_bytecode_alu *assignment[5])
275 {
276 struct r600_bytecode_alu *alu;
277 unsigned i, chan, trans;
278 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
279
280 for (i = 0; i < max_slots; i++)
281 assignment[i] = NULL;
282
283 for (alu = alu_first; alu; alu = LIST_ENTRY(struct r600_bytecode_alu, alu->list.next, list)) {
284 chan = alu->dst.chan;
285 if (max_slots == 4)
286 trans = 0;
287 else if (is_alu_trans_unit_inst(bc, alu))
288 trans = 1;
289 else if (is_alu_vec_unit_inst(bc, alu))
290 trans = 0;
291 else if (assignment[chan])
292 trans = 1; /* Assume ALU_INST_PREFER_VECTOR. */
293 else
294 trans = 0;
295
296 if (trans) {
297 if (assignment[4]) {
298 assert(0); /* ALU.Trans has already been allocated. */
299 return -1;
300 }
301 assignment[4] = alu;
302 } else {
303 if (assignment[chan]) {
304 assert(0); /* ALU.chan has already been allocated. */
305 return -1;
306 }
307 assignment[chan] = alu;
308 }
309
310 if (alu->last)
311 break;
312 }
313 return 0;
314 }
315
316 struct alu_bank_swizzle {
317 int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
318 int hw_cfile_addr[4];
319 int hw_cfile_elem[4];
320 };
321
322 static const unsigned cycle_for_bank_swizzle_vec[][3] = {
323 [SQ_ALU_VEC_012] = { 0, 1, 2 },
324 [SQ_ALU_VEC_021] = { 0, 2, 1 },
325 [SQ_ALU_VEC_120] = { 1, 2, 0 },
326 [SQ_ALU_VEC_102] = { 1, 0, 2 },
327 [SQ_ALU_VEC_201] = { 2, 0, 1 },
328 [SQ_ALU_VEC_210] = { 2, 1, 0 }
329 };
330
331 static const unsigned cycle_for_bank_swizzle_scl[][3] = {
332 [SQ_ALU_SCL_210] = { 2, 1, 0 },
333 [SQ_ALU_SCL_122] = { 1, 2, 2 },
334 [SQ_ALU_SCL_212] = { 2, 1, 2 },
335 [SQ_ALU_SCL_221] = { 2, 2, 1 }
336 };
337
338 static void init_bank_swizzle(struct alu_bank_swizzle *bs)
339 {
340 int i, cycle, component;
341 /* set up gpr use */
342 for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
343 for (component = 0; component < NUM_OF_COMPONENTS; component++)
344 bs->hw_gpr[cycle][component] = -1;
345 for (i = 0; i < 4; i++)
346 bs->hw_cfile_addr[i] = -1;
347 for (i = 0; i < 4; i++)
348 bs->hw_cfile_elem[i] = -1;
349 }
350
351 static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan, unsigned cycle)
352 {
353 if (bs->hw_gpr[cycle][chan] == -1)
354 bs->hw_gpr[cycle][chan] = sel;
355 else if (bs->hw_gpr[cycle][chan] != (int)sel) {
356 /* Another scalar operation has already used the GPR read port for the channel. */
357 return -1;
358 }
359 return 0;
360 }
361
362 static int reserve_cfile(struct r600_bytecode *bc, struct alu_bank_swizzle *bs, unsigned sel, unsigned chan)
363 {
364 int res, num_res = 4;
365 if (bc->chip_class >= R700) {
366 num_res = 2;
367 chan /= 2;
368 }
369 for (res = 0; res < num_res; ++res) {
370 if (bs->hw_cfile_addr[res] == -1) {
371 bs->hw_cfile_addr[res] = sel;
372 bs->hw_cfile_elem[res] = chan;
373 return 0;
374 } else if (bs->hw_cfile_addr[res] == sel &&
375 bs->hw_cfile_elem[res] == chan)
376 return 0; /* Read for this scalar element already reserved, nothing to do here. */
377 }
378 /* All cfile read ports are used, cannot reference vector element. */
379 return -1;
380 }
381
382 static int is_gpr(unsigned sel)
383 {
384 return (sel >= 0 && sel <= 127);
385 }
386
387 /* CB constants start at 512, and get translated to a kcache index when ALU
388 * clauses are constructed. Note that we handle kcache constants the same way
389 * as (the now gone) cfile constants, is that really required? */
390 static int is_cfile(unsigned sel)
391 {
392 return (sel > 255 && sel < 512) ||
393 (sel > 511 && sel < 4607) || /* Kcache before translation. */
394 (sel > 127 && sel < 192); /* Kcache after translation. */
395 }
396
397 static int is_const(int sel)
398 {
399 return is_cfile(sel) ||
400 (sel >= V_SQ_ALU_SRC_0 &&
401 sel <= V_SQ_ALU_SRC_LITERAL);
402 }
403
404 static int check_vector(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
405 struct alu_bank_swizzle *bs, int bank_swizzle)
406 {
407 int r, src, num_src, sel, elem, cycle;
408
409 num_src = r600_bytecode_get_num_operands(bc, alu);
410 for (src = 0; src < num_src; src++) {
411 sel = alu->src[src].sel;
412 elem = alu->src[src].chan;
413 if (is_gpr(sel)) {
414 cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src];
415 if (src == 1 && sel == alu->src[0].sel && elem == alu->src[0].chan)
416 /* Nothing to do; special-case optimization,
417 * second source uses first source’s reservation. */
418 continue;
419 else {
420 r = reserve_gpr(bs, sel, elem, cycle);
421 if (r)
422 return r;
423 }
424 } else if (is_cfile(sel)) {
425 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
426 if (r)
427 return r;
428 }
429 /* No restrictions on PV, PS, literal or special constants. */
430 }
431 return 0;
432 }
433
434 static int check_scalar(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
435 struct alu_bank_swizzle *bs, int bank_swizzle)
436 {
437 int r, src, num_src, const_count, sel, elem, cycle;
438
439 num_src = r600_bytecode_get_num_operands(bc, alu);
440 for (const_count = 0, src = 0; src < num_src; ++src) {
441 sel = alu->src[src].sel;
442 elem = alu->src[src].chan;
443 if (is_const(sel)) { /* Any constant, including literal and inline constants. */
444 if (const_count >= 2)
445 /* More than two references to a constant in
446 * transcendental operation. */
447 return -1;
448 else
449 const_count++;
450 }
451 if (is_cfile(sel)) {
452 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
453 if (r)
454 return r;
455 }
456 }
457 for (src = 0; src < num_src; ++src) {
458 sel = alu->src[src].sel;
459 elem = alu->src[src].chan;
460 if (is_gpr(sel)) {
461 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
462 if (cycle < const_count)
463 /* Cycle for GPR load conflicts with
464 * constant load in transcendental operation. */
465 return -1;
466 r = reserve_gpr(bs, sel, elem, cycle);
467 if (r)
468 return r;
469 }
470 /* PV PS restrictions */
471 if (const_count && (sel == 254 || sel == 255)) {
472 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
473 if (cycle < const_count)
474 return -1;
475 }
476 }
477 return 0;
478 }
479
480 static int check_and_set_bank_swizzle(struct r600_bytecode *bc,
481 struct r600_bytecode_alu *slots[5])
482 {
483 struct alu_bank_swizzle bs;
484 int bank_swizzle[5];
485 int i, r = 0, forced = 1;
486 boolean scalar_only = bc->chip_class == CAYMAN ? false : true;
487 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
488
489 for (i = 0; i < max_slots; i++) {
490 if (slots[i]) {
491 if (slots[i]->bank_swizzle_force) {
492 slots[i]->bank_swizzle = slots[i]->bank_swizzle_force;
493 } else {
494 forced = 0;
495 }
496 }
497
498 if (i < 4 && slots[i])
499 scalar_only = false;
500 }
501 if (forced)
502 return 0;
503
504 /* Just check every possible combination of bank swizzle.
505 * Not very efficent, but works on the first try in most of the cases. */
506 for (i = 0; i < 4; i++)
507 if (!slots[i] || !slots[i]->bank_swizzle_force)
508 bank_swizzle[i] = SQ_ALU_VEC_012;
509 else
510 bank_swizzle[i] = slots[i]->bank_swizzle;
511
512 bank_swizzle[4] = SQ_ALU_SCL_210;
513 while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
514
515 init_bank_swizzle(&bs);
516 if (scalar_only == false) {
517 for (i = 0; i < 4; i++) {
518 if (slots[i]) {
519 r = check_vector(bc, slots[i], &bs, bank_swizzle[i]);
520 if (r)
521 break;
522 }
523 }
524 } else
525 r = 0;
526
527 if (!r && slots[4] && max_slots == 5) {
528 r = check_scalar(bc, slots[4], &bs, bank_swizzle[4]);
529 }
530 if (!r) {
531 for (i = 0; i < max_slots; i++) {
532 if (slots[i])
533 slots[i]->bank_swizzle = bank_swizzle[i];
534 }
535 return 0;
536 }
537
538 if (scalar_only) {
539 bank_swizzle[4]++;
540 } else {
541 for (i = 0; i < max_slots; i++) {
542 if (!slots[i] || !slots[i]->bank_swizzle_force) {
543 bank_swizzle[i]++;
544 if (bank_swizzle[i] <= SQ_ALU_VEC_210)
545 break;
546 else if (i < max_slots - 1)
547 bank_swizzle[i] = SQ_ALU_VEC_012;
548 else
549 return -1;
550 }
551 }
552 }
553 }
554
555 /* Couldn't find a working swizzle. */
556 return -1;
557 }
558
559 static int replace_gpr_with_pv_ps(struct r600_bytecode *bc,
560 struct r600_bytecode_alu *slots[5], struct r600_bytecode_alu *alu_prev)
561 {
562 struct r600_bytecode_alu *prev[5];
563 int gpr[5], chan[5];
564 int i, j, r, src, num_src;
565 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
566
567 r = assign_alu_units(bc, alu_prev, prev);
568 if (r)
569 return r;
570
571 for (i = 0; i < max_slots; ++i) {
572 if (prev[i] && (prev[i]->dst.write || prev[i]->is_op3) && !prev[i]->dst.rel) {
573 gpr[i] = prev[i]->dst.sel;
574 /* cube writes more than PV.X */
575 if (is_alu_reduction_inst(bc, prev[i]))
576 chan[i] = 0;
577 else
578 chan[i] = prev[i]->dst.chan;
579 } else
580 gpr[i] = -1;
581 }
582
583 for (i = 0; i < max_slots; ++i) {
584 struct r600_bytecode_alu *alu = slots[i];
585 if(!alu)
586 continue;
587
588 num_src = r600_bytecode_get_num_operands(bc, alu);
589 for (src = 0; src < num_src; ++src) {
590 if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
591 continue;
592
593 if (bc->chip_class < CAYMAN) {
594 if (alu->src[src].sel == gpr[4] &&
595 alu->src[src].chan == chan[4] &&
596 alu_prev->pred_sel == alu->pred_sel) {
597 alu->src[src].sel = V_SQ_ALU_SRC_PS;
598 alu->src[src].chan = 0;
599 continue;
600 }
601 }
602
603 for (j = 0; j < 4; ++j) {
604 if (alu->src[src].sel == gpr[j] &&
605 alu->src[src].chan == j &&
606 alu_prev->pred_sel == alu->pred_sel) {
607 alu->src[src].sel = V_SQ_ALU_SRC_PV;
608 alu->src[src].chan = chan[j];
609 break;
610 }
611 }
612 }
613 }
614
615 return 0;
616 }
617
618 void r600_bytecode_special_constants(uint32_t value, unsigned *sel, unsigned *neg)
619 {
620 switch(value) {
621 case 0:
622 *sel = V_SQ_ALU_SRC_0;
623 break;
624 case 1:
625 *sel = V_SQ_ALU_SRC_1_INT;
626 break;
627 case -1:
628 *sel = V_SQ_ALU_SRC_M_1_INT;
629 break;
630 case 0x3F800000: /* 1.0f */
631 *sel = V_SQ_ALU_SRC_1;
632 break;
633 case 0x3F000000: /* 0.5f */
634 *sel = V_SQ_ALU_SRC_0_5;
635 break;
636 case 0xBF800000: /* -1.0f */
637 *sel = V_SQ_ALU_SRC_1;
638 *neg ^= 1;
639 break;
640 case 0xBF000000: /* -0.5f */
641 *sel = V_SQ_ALU_SRC_0_5;
642 *neg ^= 1;
643 break;
644 default:
645 *sel = V_SQ_ALU_SRC_LITERAL;
646 break;
647 }
648 }
649
650 /* compute how many literal are needed */
651 static int r600_bytecode_alu_nliterals(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
652 uint32_t literal[4], unsigned *nliteral)
653 {
654 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
655 unsigned i, j;
656
657 for (i = 0; i < num_src; ++i) {
658 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
659 uint32_t value = alu->src[i].value;
660 unsigned found = 0;
661 for (j = 0; j < *nliteral; ++j) {
662 if (literal[j] == value) {
663 found = 1;
664 break;
665 }
666 }
667 if (!found) {
668 if (*nliteral >= 4)
669 return -EINVAL;
670 literal[(*nliteral)++] = value;
671 }
672 }
673 }
674 return 0;
675 }
676
677 static void r600_bytecode_alu_adjust_literals(struct r600_bytecode *bc,
678 struct r600_bytecode_alu *alu,
679 uint32_t literal[4], unsigned nliteral)
680 {
681 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
682 unsigned i, j;
683
684 for (i = 0; i < num_src; ++i) {
685 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
686 uint32_t value = alu->src[i].value;
687 for (j = 0; j < nliteral; ++j) {
688 if (literal[j] == value) {
689 alu->src[i].chan = j;
690 break;
691 }
692 }
693 }
694 }
695 }
696
697 static int merge_inst_groups(struct r600_bytecode *bc, struct r600_bytecode_alu *slots[5],
698 struct r600_bytecode_alu *alu_prev)
699 {
700 struct r600_bytecode_alu *prev[5];
701 struct r600_bytecode_alu *result[5] = { NULL };
702
703 uint32_t literal[4], prev_literal[4];
704 unsigned nliteral = 0, prev_nliteral = 0;
705
706 int i, j, r, src, num_src;
707 int num_once_inst = 0;
708 int have_mova = 0, have_rel = 0;
709 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
710
711 r = assign_alu_units(bc, alu_prev, prev);
712 if (r)
713 return r;
714
715 for (i = 0; i < max_slots; ++i) {
716 if (prev[i]) {
717 if (prev[i]->pred_sel)
718 return 0;
719 if (is_alu_once_inst(bc, prev[i]))
720 return 0;
721 }
722 if (slots[i]) {
723 if (slots[i]->pred_sel)
724 return 0;
725 if (is_alu_once_inst(bc, slots[i]))
726 return 0;
727 }
728 }
729
730 for (i = 0; i < max_slots; ++i) {
731 struct r600_bytecode_alu *alu;
732
733 if (num_once_inst > 0)
734 return 0;
735
736 /* check number of literals */
737 if (prev[i]) {
738 if (r600_bytecode_alu_nliterals(bc, prev[i], literal, &nliteral))
739 return 0;
740 if (r600_bytecode_alu_nliterals(bc, prev[i], prev_literal, &prev_nliteral))
741 return 0;
742 if (is_alu_mova_inst(bc, prev[i])) {
743 if (have_rel)
744 return 0;
745 have_mova = 1;
746 }
747
748 if (alu_uses_rel(bc, prev[i])) {
749 if (have_mova) {
750 return 0;
751 }
752 have_rel = 1;
753 }
754
755 num_once_inst += is_alu_once_inst(bc, prev[i]);
756 }
757 if (slots[i] && r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral))
758 return 0;
759
760 /* Let's check used slots. */
761 if (prev[i] && !slots[i]) {
762 result[i] = prev[i];
763 continue;
764 } else if (prev[i] && slots[i]) {
765 if (max_slots == 5 && result[4] == NULL && prev[4] == NULL && slots[4] == NULL) {
766 /* Trans unit is still free try to use it. */
767 if (is_alu_any_unit_inst(bc, slots[i])) {
768 result[i] = prev[i];
769 result[4] = slots[i];
770 } else if (is_alu_any_unit_inst(bc, prev[i])) {
771 if (slots[i]->dst.sel == prev[i]->dst.sel &&
772 (slots[i]->dst.write == 1 || slots[i]->is_op3) &&
773 (prev[i]->dst.write == 1 || prev[i]->is_op3))
774 return 0;
775
776 result[i] = slots[i];
777 result[4] = prev[i];
778 } else
779 return 0;
780 } else
781 return 0;
782 } else if(!slots[i]) {
783 continue;
784 } else {
785 if (max_slots == 5 && slots[i] && prev[4] &&
786 slots[i]->dst.sel == prev[4]->dst.sel &&
787 slots[i]->dst.chan == prev[4]->dst.chan &&
788 (slots[i]->dst.write == 1 || slots[i]->is_op3) &&
789 (prev[4]->dst.write == 1 || prev[4]->is_op3))
790 return 0;
791
792 result[i] = slots[i];
793 }
794
795 alu = slots[i];
796 num_once_inst += is_alu_once_inst(bc, alu);
797
798 /* don't reschedule NOPs */
799 if (is_nop_inst(bc, alu))
800 return 0;
801
802 if (is_alu_mova_inst(bc, alu)) {
803 if (have_rel) {
804 return 0;
805 }
806 have_mova = 1;
807 }
808
809 if (alu_uses_rel(bc, alu)) {
810 if (have_mova) {
811 return 0;
812 }
813 have_rel = 1;
814 }
815
816 /* Let's check source gprs */
817 num_src = r600_bytecode_get_num_operands(bc, alu);
818 for (src = 0; src < num_src; ++src) {
819
820 /* Constants don't matter. */
821 if (!is_gpr(alu->src[src].sel))
822 continue;
823
824 for (j = 0; j < max_slots; ++j) {
825 if (!prev[j] || !(prev[j]->dst.write || prev[j]->is_op3))
826 continue;
827
828 /* If it's relative then we can't determin which gpr is really used. */
829 if (prev[j]->dst.chan == alu->src[src].chan &&
830 (prev[j]->dst.sel == alu->src[src].sel ||
831 prev[j]->dst.rel || alu->src[src].rel))
832 return 0;
833 }
834 }
835 }
836
837 /* more than one PRED_ or KILL_ ? */
838 if (num_once_inst > 1)
839 return 0;
840
841 /* check if the result can still be swizzlet */
842 r = check_and_set_bank_swizzle(bc, result);
843 if (r)
844 return 0;
845
846 /* looks like everything worked out right, apply the changes */
847
848 /* undo adding previus literals */
849 bc->cf_last->ndw -= align(prev_nliteral, 2);
850
851 /* sort instructions */
852 for (i = 0; i < max_slots; ++i) {
853 slots[i] = result[i];
854 if (result[i]) {
855 LIST_DEL(&result[i]->list);
856 result[i]->last = 0;
857 LIST_ADDTAIL(&result[i]->list, &bc->cf_last->alu);
858 }
859 }
860
861 /* determine new last instruction */
862 LIST_ENTRY(struct r600_bytecode_alu, bc->cf_last->alu.prev, list)->last = 1;
863
864 /* determine new first instruction */
865 for (i = 0; i < max_slots; ++i) {
866 if (result[i]) {
867 bc->cf_last->curr_bs_head = result[i];
868 break;
869 }
870 }
871
872 bc->cf_last->prev_bs_head = bc->cf_last->prev2_bs_head;
873 bc->cf_last->prev2_bs_head = NULL;
874
875 return 0;
876 }
877
878 /* we'll keep kcache sets sorted by bank & addr */
879 static int r600_bytecode_alloc_kcache_line(struct r600_bytecode *bc,
880 struct r600_bytecode_kcache *kcache,
881 unsigned bank, unsigned line)
882 {
883 int i, kcache_banks = bc->chip_class >= EVERGREEN ? 4 : 2;
884
885 for (i = 0; i < kcache_banks; i++) {
886 if (kcache[i].mode) {
887 int d;
888
889 if (kcache[i].bank < bank)
890 continue;
891
892 if ((kcache[i].bank == bank && kcache[i].addr > line+1) ||
893 kcache[i].bank > bank) {
894 /* try to insert new line */
895 if (kcache[kcache_banks-1].mode) {
896 /* all sets are in use */
897 return -ENOMEM;
898 }
899
900 memmove(&kcache[i+1],&kcache[i], (kcache_banks-i-1)*sizeof(struct r600_bytecode_kcache));
901 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
902 kcache[i].bank = bank;
903 kcache[i].addr = line;
904 return 0;
905 }
906
907 d = line - kcache[i].addr;
908
909 if (d == -1) {
910 kcache[i].addr--;
911 if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_2) {
912 /* we are prepending the line to the current set,
913 * discarding the existing second line,
914 * so we'll have to insert line+2 after it */
915 line += 2;
916 continue;
917 } else if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_1) {
918 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
919 return 0;
920 } else {
921 /* V_SQ_CF_KCACHE_LOCK_LOOP_INDEX is not supported */
922 return -ENOMEM;
923 }
924 } else if (d == 1) {
925 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
926 return 0;
927 } else if (d == 0)
928 return 0;
929 } else { /* free kcache set - use it */
930 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
931 kcache[i].bank = bank;
932 kcache[i].addr = line;
933 return 0;
934 }
935 }
936 return -ENOMEM;
937 }
938
939 static int r600_bytecode_alloc_inst_kcache_lines(struct r600_bytecode *bc,
940 struct r600_bytecode_kcache *kcache,
941 struct r600_bytecode_alu *alu)
942 {
943 int i, r;
944
945 for (i = 0; i < 3; i++) {
946 unsigned bank, line, sel = alu->src[i].sel;
947
948 if (sel < 512)
949 continue;
950
951 bank = alu->src[i].kc_bank;
952 line = (sel-512)>>4;
953
954 if ((r = r600_bytecode_alloc_kcache_line(bc, kcache, bank, line)))
955 return r;
956 }
957 return 0;
958 }
959
960 static int r600_bytecode_assign_kcache_banks(struct r600_bytecode *bc,
961 struct r600_bytecode_alu *alu,
962 struct r600_bytecode_kcache * kcache)
963 {
964 int i, j;
965
966 /* Alter the src operands to refer to the kcache. */
967 for (i = 0; i < 3; ++i) {
968 static const unsigned int base[] = {128, 160, 256, 288};
969 unsigned int line, sel = alu->src[i].sel, found = 0;
970
971 if (sel < 512)
972 continue;
973
974 sel -= 512;
975 line = sel>>4;
976
977 for (j = 0; j < 4 && !found; ++j) {
978 switch (kcache[j].mode) {
979 case V_SQ_CF_KCACHE_NOP:
980 case V_SQ_CF_KCACHE_LOCK_LOOP_INDEX:
981 R600_ERR("unexpected kcache line mode\n");
982 return -ENOMEM;
983 default:
984 if (kcache[j].bank == alu->src[i].kc_bank &&
985 kcache[j].addr <= line &&
986 line < kcache[j].addr + kcache[j].mode) {
987 alu->src[i].sel = sel - (kcache[j].addr<<4);
988 alu->src[i].sel += base[j];
989 found=1;
990 }
991 }
992 }
993 }
994 return 0;
995 }
996
997 static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode *bc,
998 struct r600_bytecode_alu *alu,
999 unsigned type)
1000 {
1001 struct r600_bytecode_kcache kcache_sets[4];
1002 struct r600_bytecode_kcache *kcache = kcache_sets;
1003 int r;
1004
1005 memcpy(kcache, bc->cf_last->kcache, 4 * sizeof(struct r600_bytecode_kcache));
1006
1007 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1008 /* can't alloc, need to start new clause */
1009 if ((r = r600_bytecode_add_cf(bc))) {
1010 return r;
1011 }
1012 bc->cf_last->op = type;
1013
1014 /* retry with the new clause */
1015 kcache = bc->cf_last->kcache;
1016 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1017 /* can't alloc again- should never happen */
1018 return r;
1019 }
1020 } else {
1021 /* update kcache sets */
1022 memcpy(bc->cf_last->kcache, kcache, 4 * sizeof(struct r600_bytecode_kcache));
1023 }
1024
1025 /* if we actually used more than 2 kcache sets - use ALU_EXTENDED on eg+ */
1026 if (kcache[2].mode != V_SQ_CF_KCACHE_NOP) {
1027 if (bc->chip_class < EVERGREEN)
1028 return -ENOMEM;
1029 bc->cf_last->eg_alu_extended = 1;
1030 }
1031
1032 return 0;
1033 }
1034
1035 static int insert_nop_r6xx(struct r600_bytecode *bc)
1036 {
1037 struct r600_bytecode_alu alu;
1038 int r, i;
1039
1040 for (i = 0; i < 4; i++) {
1041 memset(&alu, 0, sizeof(alu));
1042 alu.op = ALU_OP0_NOP;
1043 alu.src[0].chan = i;
1044 alu.dst.chan = i;
1045 alu.last = (i == 3);
1046 r = r600_bytecode_add_alu(bc, &alu);
1047 if (r)
1048 return r;
1049 }
1050 return 0;
1051 }
1052
1053 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1054 static int load_ar_r6xx(struct r600_bytecode *bc)
1055 {
1056 struct r600_bytecode_alu alu;
1057 int r;
1058
1059 if (bc->ar_loaded)
1060 return 0;
1061
1062 /* hack to avoid making MOVA the last instruction in the clause */
1063 if ((bc->cf_last->ndw>>1) >= 110)
1064 bc->force_add_cf = 1;
1065
1066 memset(&alu, 0, sizeof(alu));
1067 alu.op = ALU_OP1_MOVA_GPR_INT;
1068 alu.src[0].sel = bc->ar_reg;
1069 alu.src[0].chan = bc->ar_chan;
1070 alu.last = 1;
1071 alu.index_mode = INDEX_MODE_LOOP;
1072 r = r600_bytecode_add_alu(bc, &alu);
1073 if (r)
1074 return r;
1075
1076 /* no requirement to set uses waterfall on MOVA_GPR_INT */
1077 bc->ar_loaded = 1;
1078 return 0;
1079 }
1080
1081 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1082 static int load_ar(struct r600_bytecode *bc)
1083 {
1084 struct r600_bytecode_alu alu;
1085 int r;
1086
1087 if (bc->ar_handling)
1088 return load_ar_r6xx(bc);
1089
1090 if (bc->ar_loaded)
1091 return 0;
1092
1093 /* hack to avoid making MOVA the last instruction in the clause */
1094 if ((bc->cf_last->ndw>>1) >= 110)
1095 bc->force_add_cf = 1;
1096
1097 memset(&alu, 0, sizeof(alu));
1098 alu.op = ALU_OP1_MOVA_INT;
1099 alu.src[0].sel = bc->ar_reg;
1100 alu.src[0].chan = bc->ar_chan;
1101 alu.last = 1;
1102 r = r600_bytecode_add_alu(bc, &alu);
1103 if (r)
1104 return r;
1105
1106 bc->cf_last->r6xx_uses_waterfall = 1;
1107 bc->ar_loaded = 1;
1108 return 0;
1109 }
1110
1111 int r600_bytecode_add_alu_type(struct r600_bytecode *bc,
1112 const struct r600_bytecode_alu *alu, unsigned type)
1113 {
1114 struct r600_bytecode_alu *nalu = r600_bytecode_alu();
1115 struct r600_bytecode_alu *lalu;
1116 int i, r;
1117
1118 if (nalu == NULL)
1119 return -ENOMEM;
1120 memcpy(nalu, alu, sizeof(struct r600_bytecode_alu));
1121
1122 if (bc->cf_last != NULL && bc->cf_last->op != type) {
1123 /* check if we could add it anyway */
1124 if (bc->cf_last->op == CF_OP_ALU &&
1125 type == CF_OP_ALU_PUSH_BEFORE) {
1126 LIST_FOR_EACH_ENTRY(lalu, &bc->cf_last->alu, list) {
1127 if (lalu->execute_mask) {
1128 bc->force_add_cf = 1;
1129 break;
1130 }
1131 }
1132 } else
1133 bc->force_add_cf = 1;
1134 }
1135
1136 /* cf can contains only alu or only vtx or only tex */
1137 if (bc->cf_last == NULL || bc->force_add_cf) {
1138 r = r600_bytecode_add_cf(bc);
1139 if (r) {
1140 free(nalu);
1141 return r;
1142 }
1143 }
1144 bc->cf_last->op = type;
1145
1146 /* Check AR usage and load it if required */
1147 for (i = 0; i < 3; i++)
1148 if (nalu->src[i].rel && !bc->ar_loaded)
1149 load_ar(bc);
1150
1151 if (nalu->dst.rel && !bc->ar_loaded)
1152 load_ar(bc);
1153
1154 /* Setup the kcache for this ALU instruction. This will start a new
1155 * ALU clause if needed. */
1156 if ((r = r600_bytecode_alloc_kcache_lines(bc, nalu, type))) {
1157 free(nalu);
1158 return r;
1159 }
1160
1161 if (!bc->cf_last->curr_bs_head) {
1162 bc->cf_last->curr_bs_head = nalu;
1163 }
1164 /* number of gpr == the last gpr used in any alu */
1165 for (i = 0; i < 3; i++) {
1166 if (nalu->src[i].sel >= bc->ngpr && nalu->src[i].sel < 128) {
1167 bc->ngpr = nalu->src[i].sel + 1;
1168 }
1169 if (nalu->src[i].sel == V_SQ_ALU_SRC_LITERAL)
1170 r600_bytecode_special_constants(nalu->src[i].value,
1171 &nalu->src[i].sel, &nalu->src[i].neg);
1172 }
1173 if (nalu->dst.sel >= bc->ngpr) {
1174 bc->ngpr = nalu->dst.sel + 1;
1175 }
1176 LIST_ADDTAIL(&nalu->list, &bc->cf_last->alu);
1177 /* each alu use 2 dwords */
1178 bc->cf_last->ndw += 2;
1179 bc->ndw += 2;
1180
1181 /* process cur ALU instructions for bank swizzle */
1182 if (nalu->last) {
1183 uint32_t literal[4];
1184 unsigned nliteral;
1185 struct r600_bytecode_alu *slots[5];
1186 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
1187 r = assign_alu_units(bc, bc->cf_last->curr_bs_head, slots);
1188 if (r)
1189 return r;
1190
1191 if (bc->cf_last->prev_bs_head) {
1192 r = merge_inst_groups(bc, slots, bc->cf_last->prev_bs_head);
1193 if (r)
1194 return r;
1195 }
1196
1197 if (bc->cf_last->prev_bs_head) {
1198 r = replace_gpr_with_pv_ps(bc, slots, bc->cf_last->prev_bs_head);
1199 if (r)
1200 return r;
1201 }
1202
1203 r = check_and_set_bank_swizzle(bc, slots);
1204 if (r)
1205 return r;
1206
1207 for (i = 0, nliteral = 0; i < max_slots; i++) {
1208 if (slots[i]) {
1209 r = r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral);
1210 if (r)
1211 return r;
1212 }
1213 }
1214 bc->cf_last->ndw += align(nliteral, 2);
1215
1216 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1217 * worst case */
1218 if ((bc->cf_last->ndw >> 1) >= 120) {
1219 bc->force_add_cf = 1;
1220 }
1221
1222 bc->cf_last->prev2_bs_head = bc->cf_last->prev_bs_head;
1223 bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head;
1224 bc->cf_last->curr_bs_head = NULL;
1225 }
1226
1227 if (nalu->dst.rel && bc->r6xx_nop_after_rel_dst)
1228 insert_nop_r6xx(bc);
1229
1230 return 0;
1231 }
1232
1233 int r600_bytecode_add_alu(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu)
1234 {
1235 return r600_bytecode_add_alu_type(bc, alu, CF_OP_ALU);
1236 }
1237
1238 static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode *bc)
1239 {
1240 switch (bc->chip_class) {
1241 case R600:
1242 return 8;
1243
1244 case R700:
1245 case EVERGREEN:
1246 case CAYMAN:
1247 return 16;
1248
1249 default:
1250 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1251 return 8;
1252 }
1253 }
1254
1255 static inline boolean last_inst_was_not_vtx_fetch(struct r600_bytecode *bc)
1256 {
1257 return !((r600_isa_cf(bc->cf_last->op)->flags & CF_FETCH) &&
1258 (bc->chip_class == CAYMAN ||
1259 bc->cf_last->op != CF_OP_TEX));
1260 }
1261
1262 int r600_bytecode_add_vtx(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx)
1263 {
1264 struct r600_bytecode_vtx *nvtx = r600_bytecode_vtx();
1265 int r;
1266
1267 if (nvtx == NULL)
1268 return -ENOMEM;
1269 memcpy(nvtx, vtx, sizeof(struct r600_bytecode_vtx));
1270
1271 /* cf can contains only alu or only vtx or only tex */
1272 if (bc->cf_last == NULL ||
1273 last_inst_was_not_vtx_fetch(bc) ||
1274 bc->force_add_cf) {
1275 r = r600_bytecode_add_cf(bc);
1276 if (r) {
1277 free(nvtx);
1278 return r;
1279 }
1280 switch (bc->chip_class) {
1281 case R600:
1282 case R700:
1283 case EVERGREEN:
1284 bc->cf_last->op = CF_OP_VTX;
1285 break;
1286 case CAYMAN:
1287 bc->cf_last->op = CF_OP_TEX;
1288 break;
1289 default:
1290 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1291 free(nvtx);
1292 return -EINVAL;
1293 }
1294 }
1295 LIST_ADDTAIL(&nvtx->list, &bc->cf_last->vtx);
1296 /* each fetch use 4 dwords */
1297 bc->cf_last->ndw += 4;
1298 bc->ndw += 4;
1299 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1300 bc->force_add_cf = 1;
1301
1302 bc->ngpr = MAX2(bc->ngpr, vtx->src_gpr + 1);
1303 bc->ngpr = MAX2(bc->ngpr, vtx->dst_gpr + 1);
1304
1305 return 0;
1306 }
1307
1308 int r600_bytecode_add_tex(struct r600_bytecode *bc, const struct r600_bytecode_tex *tex)
1309 {
1310 struct r600_bytecode_tex *ntex = r600_bytecode_tex();
1311 int r;
1312
1313 if (ntex == NULL)
1314 return -ENOMEM;
1315 memcpy(ntex, tex, sizeof(struct r600_bytecode_tex));
1316
1317 /* we can't fetch data und use it as texture lookup address in the same TEX clause */
1318 if (bc->cf_last != NULL &&
1319 bc->cf_last->op == CF_OP_TEX) {
1320 struct r600_bytecode_tex *ttex;
1321 LIST_FOR_EACH_ENTRY(ttex, &bc->cf_last->tex, list) {
1322 if (ttex->dst_gpr == ntex->src_gpr) {
1323 bc->force_add_cf = 1;
1324 break;
1325 }
1326 }
1327 /* slight hack to make gradients always go into same cf */
1328 if (ntex->op == FETCH_OP_SET_GRADIENTS_H)
1329 bc->force_add_cf = 1;
1330 }
1331
1332 /* cf can contains only alu or only vtx or only tex */
1333 if (bc->cf_last == NULL ||
1334 bc->cf_last->op != CF_OP_TEX ||
1335 bc->force_add_cf) {
1336 r = r600_bytecode_add_cf(bc);
1337 if (r) {
1338 free(ntex);
1339 return r;
1340 }
1341 bc->cf_last->op = CF_OP_TEX;
1342 }
1343 if (ntex->src_gpr >= bc->ngpr) {
1344 bc->ngpr = ntex->src_gpr + 1;
1345 }
1346 if (ntex->dst_gpr >= bc->ngpr) {
1347 bc->ngpr = ntex->dst_gpr + 1;
1348 }
1349 LIST_ADDTAIL(&ntex->list, &bc->cf_last->tex);
1350 /* each texture fetch use 4 dwords */
1351 bc->cf_last->ndw += 4;
1352 bc->ndw += 4;
1353 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1354 bc->force_add_cf = 1;
1355 return 0;
1356 }
1357
1358 int r600_bytecode_add_cfinst(struct r600_bytecode *bc, unsigned op)
1359 {
1360 int r;
1361 r = r600_bytecode_add_cf(bc);
1362 if (r)
1363 return r;
1364
1365 bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
1366 bc->cf_last->op = op;
1367 return 0;
1368 }
1369
1370 int cm_bytecode_add_cf_end(struct r600_bytecode *bc)
1371 {
1372 return r600_bytecode_add_cfinst(bc, CF_OP_CF_END);
1373 }
1374
1375 /* common to all 3 families */
1376 static int r600_bytecode_vtx_build(struct r600_bytecode *bc, struct r600_bytecode_vtx *vtx, unsigned id)
1377 {
1378 bc->bytecode[id] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) |
1379 S_SQ_VTX_WORD0_FETCH_TYPE(vtx->fetch_type) |
1380 S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
1381 S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x);
1382 if (bc->chip_class < CAYMAN)
1383 bc->bytecode[id] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
1384 id++;
1385 bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
1386 S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
1387 S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
1388 S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
1389 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) |
1390 S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) |
1391 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) |
1392 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) |
1393 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
1394 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
1395 bc->bytecode[id] = S_SQ_VTX_WORD2_OFFSET(vtx->offset)|
1396 S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx->endian);
1397 if (bc->chip_class < CAYMAN)
1398 bc->bytecode[id] |= S_SQ_VTX_WORD2_MEGA_FETCH(1);
1399 id++;
1400 bc->bytecode[id++] = 0;
1401 return 0;
1402 }
1403
1404 /* common to all 3 families */
1405 static int r600_bytecode_tex_build(struct r600_bytecode *bc, struct r600_bytecode_tex *tex, unsigned id)
1406 {
1407 bc->bytecode[id++] = S_SQ_TEX_WORD0_TEX_INST(
1408 r600_isa_fetch_opcode(bc->isa->hw_class, tex->op)) |
1409 EG_S_SQ_TEX_WORD0_INST_MOD(tex->inst_mod) |
1410 S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
1411 S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
1412 S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
1413 bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
1414 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
1415 S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
1416 S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
1417 S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
1418 S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
1419 S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
1420 S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
1421 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
1422 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
1423 S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
1424 bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
1425 S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
1426 S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
1427 S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
1428 S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
1429 S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
1430 S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
1431 S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
1432 bc->bytecode[id++] = 0;
1433 return 0;
1434 }
1435
1436 /* r600 only, r700/eg bits in r700_asm.c */
1437 static int r600_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id)
1438 {
1439 unsigned opcode = r600_isa_alu_opcode(bc->isa->hw_class, alu->op);
1440
1441 /* don't replace gpr by pv or ps for destination register */
1442 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
1443 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
1444 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
1445 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
1446 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
1447 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
1448 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
1449 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
1450 S_SQ_ALU_WORD0_INDEX_MODE(alu->index_mode) |
1451 S_SQ_ALU_WORD0_PRED_SEL(alu->pred_sel) |
1452 S_SQ_ALU_WORD0_LAST(alu->last);
1453
1454 if (alu->is_op3) {
1455 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1456 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1457 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1458 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1459 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
1460 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
1461 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
1462 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
1463 S_SQ_ALU_WORD1_OP3_ALU_INST(opcode) |
1464 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
1465 } else {
1466 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1467 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1468 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1469 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1470 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
1471 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
1472 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
1473 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
1474 S_SQ_ALU_WORD1_OP2_ALU_INST(opcode) |
1475 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
1476 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->execute_mask) |
1477 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->update_pred);
1478 }
1479 return 0;
1480 }
1481
1482 static void r600_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_cf *cf)
1483 {
1484 *bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
1485 *bytecode++ = S_SQ_CF_WORD1_CF_INST(r600_isa_cf_opcode(ISA_CC_R600, cf->op)) |
1486 S_SQ_CF_WORD1_BARRIER(1) |
1487 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
1488 }
1489
1490 /* common for r600/r700 - eg in eg_asm.c */
1491 static int r600_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf)
1492 {
1493 unsigned id = cf->id;
1494 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
1495 unsigned opcode = r600_isa_cf_opcode(bc->isa->hw_class, cf->op);
1496
1497 if (cfop->flags & CF_ALU) {
1498 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
1499 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
1500 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
1501 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank);
1502
1503 bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(opcode) |
1504 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) |
1505 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
1506 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
1507 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1508 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chip_class == R600 ? cf->r6xx_uses_waterfall : 0) |
1509 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
1510 } else if (cfop->flags & CF_FETCH) {
1511 if (bc->chip_class == R700)
1512 r700_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1513 else
1514 r600_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1515 } else if (cfop->flags & CF_EXP) {
1516 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1517 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1518 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1519 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
1520 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1521 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
1522 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
1523 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
1524 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
1525 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
1526 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) |
1527 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program);
1528 } else if (cfop->flags & CF_STRM) {
1529 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1530 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1531 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1532 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
1533 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1534 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
1535 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) |
1536 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program) |
1537 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf->output.array_size) |
1538 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf->output.comp_mask);
1539 } else {
1540 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
1541 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(opcode) |
1542 S_SQ_CF_WORD1_BARRIER(1) |
1543 S_SQ_CF_WORD1_COND(cf->cond) |
1544 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count);
1545 }
1546 return 0;
1547 }
1548
1549 int r600_bytecode_build(struct r600_bytecode *bc)
1550 {
1551 struct r600_bytecode_cf *cf;
1552 struct r600_bytecode_alu *alu;
1553 struct r600_bytecode_vtx *vtx;
1554 struct r600_bytecode_tex *tex;
1555 uint32_t literal[4];
1556 unsigned nliteral;
1557 unsigned addr;
1558 int i, r;
1559
1560 bc->nstack = bc->stack.max_entries;
1561
1562 if (bc->type == TGSI_PROCESSOR_VERTEX && !bc->nstack) {
1563 bc->nstack = 1;
1564 }
1565
1566 /* first path compute addr of each CF block */
1567 /* addr start after all the CF instructions */
1568 addr = bc->cf_last->id + 2;
1569 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1570 if (r600_isa_cf(cf->op)->flags & CF_FETCH) {
1571 addr += 3;
1572 addr &= 0xFFFFFFFCUL;
1573 }
1574 cf->addr = addr;
1575 addr += cf->ndw;
1576 bc->ndw = cf->addr + cf->ndw;
1577 }
1578 free(bc->bytecode);
1579 bc->bytecode = calloc(1, bc->ndw * 4);
1580 if (bc->bytecode == NULL)
1581 return -ENOMEM;
1582 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1583 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
1584 addr = cf->addr;
1585 if (bc->chip_class >= EVERGREEN)
1586 r = eg_bytecode_cf_build(bc, cf);
1587 else
1588 r = r600_bytecode_cf_build(bc, cf);
1589 if (r)
1590 return r;
1591 if (cfop->flags & CF_ALU) {
1592 nliteral = 0;
1593 memset(literal, 0, sizeof(literal));
1594 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1595 r = r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
1596 if (r)
1597 return r;
1598 r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral);
1599 r600_bytecode_assign_kcache_banks(bc, alu, cf->kcache);
1600
1601 switch(bc->chip_class) {
1602 case R600:
1603 r = r600_bytecode_alu_build(bc, alu, addr);
1604 break;
1605 case R700:
1606 case EVERGREEN: /* eg alu is same encoding as r700 */
1607 case CAYMAN:
1608 r = r700_bytecode_alu_build(bc, alu, addr);
1609 break;
1610 default:
1611 R600_ERR("unknown chip class %d.\n", bc->chip_class);
1612 return -EINVAL;
1613 }
1614 if (r)
1615 return r;
1616 addr += 2;
1617 if (alu->last) {
1618 for (i = 0; i < align(nliteral, 2); ++i) {
1619 bc->bytecode[addr++] = literal[i];
1620 }
1621 nliteral = 0;
1622 memset(literal, 0, sizeof(literal));
1623 }
1624 }
1625 } else if (cf->op == CF_OP_VTX) {
1626 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1627 r = r600_bytecode_vtx_build(bc, vtx, addr);
1628 if (r)
1629 return r;
1630 addr += 4;
1631 }
1632 } else if (cf->op == CF_OP_TEX) {
1633 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1634 assert(bc->chip_class >= EVERGREEN);
1635 r = r600_bytecode_vtx_build(bc, vtx, addr);
1636 if (r)
1637 return r;
1638 addr += 4;
1639 }
1640 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
1641 r = r600_bytecode_tex_build(bc, tex, addr);
1642 if (r)
1643 return r;
1644 addr += 4;
1645 }
1646 }
1647 }
1648 return 0;
1649 }
1650
1651 void r600_bytecode_clear(struct r600_bytecode *bc)
1652 {
1653 struct r600_bytecode_cf *cf = NULL, *next_cf;
1654
1655 free(bc->bytecode);
1656 bc->bytecode = NULL;
1657
1658 LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
1659 struct r600_bytecode_alu *alu = NULL, *next_alu;
1660 struct r600_bytecode_tex *tex = NULL, *next_tex;
1661 struct r600_bytecode_tex *vtx = NULL, *next_vtx;
1662
1663 LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
1664 free(alu);
1665 }
1666
1667 LIST_INITHEAD(&cf->alu);
1668
1669 LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) {
1670 free(tex);
1671 }
1672
1673 LIST_INITHEAD(&cf->tex);
1674
1675 LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) {
1676 free(vtx);
1677 }
1678
1679 LIST_INITHEAD(&cf->vtx);
1680
1681 free(cf);
1682 }
1683
1684 LIST_INITHEAD(&cf->list);
1685 }
1686
1687 static int print_swizzle(unsigned swz)
1688 {
1689 const char * swzchars = "xyzw01?_";
1690 assert(swz<8 && swz != 6);
1691 return fprintf(stderr, "%c", swzchars[swz]);
1692 }
1693
1694 static int print_sel(unsigned sel, unsigned rel, unsigned index_mode,
1695 unsigned need_brackets)
1696 {
1697 int o = 0;
1698 if (rel && index_mode >= 5 && sel < 128)
1699 o += fprintf(stderr, "G");
1700 if (rel || need_brackets) {
1701 o += fprintf(stderr, "[");
1702 }
1703 o += fprintf(stderr, "%d", sel);
1704 if (rel) {
1705 if (index_mode == 0 || index_mode == 6)
1706 o += fprintf(stderr, "+AR");
1707 else if (index_mode == 4)
1708 o += fprintf(stderr, "+AL");
1709 }
1710 if (rel || need_brackets) {
1711 o += fprintf(stderr, "]");
1712 }
1713 return o;
1714 }
1715
1716 static int print_dst(struct r600_bytecode_alu *alu)
1717 {
1718 int o = 0;
1719 unsigned sel = alu->dst.sel;
1720 char reg_char = 'R';
1721 if (sel > 128 - 4) { /* clause temporary gpr */
1722 sel -= 128 - 4;
1723 reg_char = 'T';
1724 }
1725
1726 if (alu->dst.write || alu->is_op3) {
1727 o += fprintf(stderr, "%c", reg_char);
1728 o += print_sel(alu->dst.sel, alu->dst.rel, alu->index_mode, 0);
1729 } else {
1730 o += fprintf(stderr, "__");
1731 }
1732 o += fprintf(stderr, ".");
1733 o += print_swizzle(alu->dst.chan);
1734 return o;
1735 }
1736
1737 static int print_src(struct r600_bytecode_alu *alu, unsigned idx)
1738 {
1739 int o = 0;
1740 struct r600_bytecode_alu_src *src = &alu->src[idx];
1741 unsigned sel = src->sel, need_sel = 1, need_chan = 1, need_brackets = 0;
1742
1743 if (src->neg)
1744 o += fprintf(stderr,"-");
1745 if (src->abs)
1746 o += fprintf(stderr,"|");
1747
1748 if (sel < 128 - 4) {
1749 o += fprintf(stderr, "R");
1750 } else if (sel < 128) {
1751 o += fprintf(stderr, "T");
1752 sel -= 128 - 4;
1753 } else if (sel < 160) {
1754 o += fprintf(stderr, "KC0");
1755 need_brackets = 1;
1756 sel -= 128;
1757 } else if (sel < 192) {
1758 o += fprintf(stderr, "KC1");
1759 need_brackets = 1;
1760 sel -= 160;
1761 } else if (sel >= 512) {
1762 o += fprintf(stderr, "C%d", src->kc_bank);
1763 need_brackets = 1;
1764 sel -= 512;
1765 } else if (sel >= 448) {
1766 o += fprintf(stderr, "Param");
1767 sel -= 448;
1768 need_chan = 0;
1769 } else if (sel >= 288) {
1770 o += fprintf(stderr, "KC3");
1771 need_brackets = 1;
1772 sel -= 288;
1773 } else if (sel >= 256) {
1774 o += fprintf(stderr, "KC2");
1775 need_brackets = 1;
1776 sel -= 256;
1777 } else {
1778 need_sel = 0;
1779 need_chan = 0;
1780 switch (sel) {
1781 case V_SQ_ALU_SRC_PS:
1782 o += fprintf(stderr, "PS");
1783 break;
1784 case V_SQ_ALU_SRC_PV:
1785 o += fprintf(stderr, "PV");
1786 need_chan = 1;
1787 break;
1788 case V_SQ_ALU_SRC_LITERAL:
1789 o += fprintf(stderr, "[0x%08X %f]", src->value, *(float*)&src->value);
1790 break;
1791 case V_SQ_ALU_SRC_0_5:
1792 o += fprintf(stderr, "0.5");
1793 break;
1794 case V_SQ_ALU_SRC_M_1_INT:
1795 o += fprintf(stderr, "-1");
1796 break;
1797 case V_SQ_ALU_SRC_1_INT:
1798 o += fprintf(stderr, "1");
1799 break;
1800 case V_SQ_ALU_SRC_1:
1801 o += fprintf(stderr, "1.0");
1802 break;
1803 case V_SQ_ALU_SRC_0:
1804 o += fprintf(stderr, "0");
1805 break;
1806 default:
1807 o += fprintf(stderr, "??IMM_%d", sel);
1808 break;
1809 }
1810 }
1811
1812 if (need_sel)
1813 o += print_sel(sel, src->rel, alu->index_mode, need_brackets);
1814
1815 if (need_chan) {
1816 o += fprintf(stderr, ".");
1817 o += print_swizzle(src->chan);
1818 }
1819
1820 if (src->abs)
1821 o += fprintf(stderr,"|");
1822
1823 return o;
1824 }
1825
1826 static int print_indent(int p, int c)
1827 {
1828 int o = 0;
1829 while (p++ < c)
1830 o += fprintf(stderr, " ");
1831 return o;
1832 }
1833
1834 void r600_bytecode_disasm(struct r600_bytecode *bc)
1835 {
1836 static int index = 0;
1837 struct r600_bytecode_cf *cf = NULL;
1838 struct r600_bytecode_alu *alu = NULL;
1839 struct r600_bytecode_vtx *vtx = NULL;
1840 struct r600_bytecode_tex *tex = NULL;
1841
1842 unsigned i, id, ngr = 0, last;
1843 uint32_t literal[4];
1844 unsigned nliteral;
1845 char chip = '6';
1846
1847 switch (bc->chip_class) {
1848 case R700:
1849 chip = '7';
1850 break;
1851 case EVERGREEN:
1852 chip = 'E';
1853 break;
1854 case CAYMAN:
1855 chip = 'C';
1856 break;
1857 case R600:
1858 default:
1859 chip = '6';
1860 break;
1861 }
1862 fprintf(stderr, "bytecode %d dw -- %d gprs -- %d nstack -------------\n",
1863 bc->ndw, bc->ngpr, bc->nstack);
1864 fprintf(stderr, "shader %d -- %c\n", index++, chip);
1865
1866 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1867 id = cf->id;
1868 if (cf->op == CF_NATIVE) {
1869 fprintf(stderr, "%04d %08X %08X CF_NATIVE\n", id, bc->bytecode[id],
1870 bc->bytecode[id + 1]);
1871 } else {
1872 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
1873 if (cfop->flags & CF_ALU) {
1874 if (cf->eg_alu_extended) {
1875 fprintf(stderr, "%04d %08X %08X %s\n", id, bc->bytecode[id],
1876 bc->bytecode[id + 1], "ALU_EXT");
1877 id += 2;
1878 }
1879 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
1880 bc->bytecode[id + 1], cfop->name);
1881 fprintf(stderr, "%d @%d ", cf->ndw / 2, cf->addr);
1882 for (i = 0; i < 4; ++i) {
1883 if (cf->kcache[i].mode) {
1884 int c_start = (cf->kcache[i].addr << 4);
1885 int c_end = c_start + (cf->kcache[i].mode << 4);
1886 fprintf(stderr, "KC%d[CB%d:%d-%d] ",
1887 i, cf->kcache[i].bank, c_start, c_end);
1888 }
1889 }
1890 fprintf(stderr, "\n");
1891 } else if (cfop->flags & CF_FETCH) {
1892 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
1893 bc->bytecode[id + 1], cfop->name);
1894 fprintf(stderr, "%d @%d ", cf->ndw / 4, cf->addr);
1895 fprintf(stderr, "\n");
1896 } else if (cfop->flags & CF_EXP) {
1897 int o = 0;
1898 const char *exp_type[] = {"PIXEL", "POS ", "PARAM"};
1899 o += fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
1900 bc->bytecode[id + 1], cfop->name);
1901 o += print_indent(o, 43);
1902 o += fprintf(stderr, "%s ", exp_type[cf->output.type]);
1903 if (cf->output.burst_count > 1) {
1904 o += fprintf(stderr, "%d-%d ", cf->output.array_base,
1905 cf->output.array_base + cf->output.burst_count - 1);
1906
1907 o += print_indent(o, 55);
1908 o += fprintf(stderr, "R%d-%d.", cf->output.gpr,
1909 cf->output.gpr + cf->output.burst_count - 1);
1910 } else {
1911 o += fprintf(stderr, "%d ", cf->output.array_base);
1912 o += print_indent(o, 55);
1913 o += fprintf(stderr, "R%d.", cf->output.gpr);
1914 }
1915
1916 o += print_swizzle(cf->output.swizzle_x);
1917 o += print_swizzle(cf->output.swizzle_y);
1918 o += print_swizzle(cf->output.swizzle_z);
1919 o += print_swizzle(cf->output.swizzle_w);
1920
1921 print_indent(o, 67);
1922
1923 fprintf(stderr, " ES:%X ", cf->output.elem_size);
1924 if (!cf->output.barrier)
1925 fprintf(stderr, "NO_BARRIER ");
1926 if (cf->output.end_of_program)
1927 fprintf(stderr, "EOP ");
1928 fprintf(stderr, "\n");
1929 } else if (r600_isa_cf(cf->op)->flags & CF_STRM) {
1930 int o = 0;
1931 const char *exp_type[] = {"WRITE", "WRITE_IND", "WRITE_ACK",
1932 "WRITE_IND_ACK"};
1933 o += fprintf(stderr, "%04d %08X %08X %s ", id,
1934 bc->bytecode[id], bc->bytecode[id + 1], cfop->name);
1935 o += print_indent(o, 43);
1936 o += fprintf(stderr, "%s ", exp_type[cf->output.type]);
1937 if (cf->output.burst_count > 1) {
1938 o += fprintf(stderr, "%d-%d ", cf->output.array_base,
1939 cf->output.array_base + cf->output.burst_count - 1);
1940 o += print_indent(o, 55);
1941 o += fprintf(stderr, "R%d-%d.", cf->output.gpr,
1942 cf->output.gpr + cf->output.burst_count - 1);
1943 } else {
1944 o += fprintf(stderr, "%d ", cf->output.array_base);
1945 o += print_indent(o, 55);
1946 o += fprintf(stderr, "R%d.", cf->output.gpr);
1947 }
1948 for (i = 0; i < 4; ++i) {
1949 if (cf->output.comp_mask & (1 << i))
1950 o += print_swizzle(i);
1951 else
1952 o += print_swizzle(7);
1953 }
1954
1955 o += print_indent(o, 67);
1956
1957 fprintf(stderr, " ES:%i ", cf->output.elem_size);
1958 if (cf->output.array_size != 0xFFF)
1959 fprintf(stderr, "AS:%i ", cf->output.array_size);
1960 if (!cf->output.barrier)
1961 fprintf(stderr, "NO_BARRIER ");
1962 if (cf->output.end_of_program)
1963 fprintf(stderr, "EOP ");
1964 fprintf(stderr, "\n");
1965 } else {
1966 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
1967 bc->bytecode[id + 1], cfop->name);
1968 fprintf(stderr, "@%d ", cf->cf_addr);
1969 if (cf->cond)
1970 fprintf(stderr, "CND:%X ", cf->cond);
1971 if (cf->pop_count)
1972 fprintf(stderr, "POP:%X ", cf->pop_count);
1973 fprintf(stderr, "\n");
1974 }
1975 }
1976
1977 id = cf->addr;
1978 nliteral = 0;
1979 last = 1;
1980 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1981 const char *omod_str[] = {"","*2","*4","/2"};
1982 const struct alu_op_info *aop = r600_isa_alu(alu->op);
1983 int o = 0;
1984
1985 r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
1986 o += fprintf(stderr, " %04d %08X %08X ", id, bc->bytecode[id], bc->bytecode[id+1]);
1987 if (last)
1988 o += fprintf(stderr, "%4d ", ++ngr);
1989 else
1990 o += fprintf(stderr, " ");
1991 o += fprintf(stderr, "%c%c %c ", alu->execute_mask ? 'M':' ',
1992 alu->update_pred ? 'P':' ',
1993 alu->pred_sel ? alu->pred_sel==2 ? '0':'1':' ');
1994
1995 o += fprintf(stderr, "%s%s%s ", aop->name,
1996 omod_str[alu->omod], alu->dst.clamp ? "_sat":"");
1997
1998 o += print_indent(o,60);
1999 o += print_dst(alu);
2000 for (i = 0; i < aop->src_count; ++i) {
2001 o += fprintf(stderr, i == 0 ? ", ": ", ");
2002 o += print_src(alu, i);
2003 }
2004
2005 if (alu->bank_swizzle) {
2006 o += print_indent(o,75);
2007 o += fprintf(stderr, " BS:%d", alu->bank_swizzle);
2008 }
2009
2010 fprintf(stderr, "\n");
2011 id += 2;
2012
2013 if (alu->last) {
2014 for (i = 0; i < nliteral; i++, id++) {
2015 float *f = (float*)(bc->bytecode + id);
2016 o = fprintf(stderr, " %04d %08X", id, bc->bytecode[id]);
2017 print_indent(o, 60);
2018 fprintf(stderr, " %f (%d)\n", *f, *(bc->bytecode + id));
2019 }
2020 id += nliteral & 1;
2021 nliteral = 0;
2022 }
2023 last = alu->last;
2024 }
2025
2026 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2027 int o = 0;
2028 o += fprintf(stderr, " %04d %08X %08X %08X ", id, bc->bytecode[id],
2029 bc->bytecode[id + 1], bc->bytecode[id + 2]);
2030
2031 o += fprintf(stderr, "%s ", r600_isa_fetch(tex->op)->name);
2032
2033 o += print_indent(o, 50);
2034
2035 o += fprintf(stderr, "R%d.", tex->dst_gpr);
2036 o += print_swizzle(tex->dst_sel_x);
2037 o += print_swizzle(tex->dst_sel_y);
2038 o += print_swizzle(tex->dst_sel_z);
2039 o += print_swizzle(tex->dst_sel_w);
2040
2041 o += fprintf(stderr, ", R%d.", tex->src_gpr);
2042 o += print_swizzle(tex->src_sel_x);
2043 o += print_swizzle(tex->src_sel_y);
2044 o += print_swizzle(tex->src_sel_z);
2045 o += print_swizzle(tex->src_sel_w);
2046
2047 o += fprintf(stderr, ", RID:%d", tex->resource_id);
2048 o += fprintf(stderr, ", SID:%d ", tex->sampler_id);
2049
2050 if (tex->lod_bias)
2051 fprintf(stderr, "LB:%d ", tex->lod_bias);
2052
2053 fprintf(stderr, "CT:%c%c%c%c ",
2054 tex->coord_type_x ? 'N' : 'U',
2055 tex->coord_type_y ? 'N' : 'U',
2056 tex->coord_type_z ? 'N' : 'U',
2057 tex->coord_type_w ? 'N' : 'U');
2058
2059 if (tex->offset_x)
2060 fprintf(stderr, "OX:%d ", tex->offset_x);
2061 if (tex->offset_y)
2062 fprintf(stderr, "OY:%d ", tex->offset_y);
2063 if (tex->offset_z)
2064 fprintf(stderr, "OZ:%d ", tex->offset_z);
2065
2066 id += 4;
2067 fprintf(stderr, "\n");
2068 }
2069
2070 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2071 int o = 0;
2072 const char * fetch_type[] = {"VERTEX", "INSTANCE", ""};
2073 o += fprintf(stderr, " %04d %08X %08X %08X ", id, bc->bytecode[id],
2074 bc->bytecode[id + 1], bc->bytecode[id + 2]);
2075
2076 o += fprintf(stderr, "%s ", r600_isa_fetch(vtx->op)->name);
2077
2078 o += print_indent(o, 50);
2079
2080 o += fprintf(stderr, "R%d.", vtx->dst_gpr);
2081 o += print_swizzle(vtx->dst_sel_x);
2082 o += print_swizzle(vtx->dst_sel_y);
2083 o += print_swizzle(vtx->dst_sel_z);
2084 o += print_swizzle(vtx->dst_sel_w);
2085
2086 o += fprintf(stderr, ", R%d.", vtx->src_gpr);
2087 o += print_swizzle(vtx->src_sel_x);
2088
2089 if (vtx->offset)
2090 fprintf(stderr, " +%db", vtx->offset);
2091
2092 o += print_indent(o, 55);
2093
2094 fprintf(stderr, ", RID:%d ", vtx->buffer_id);
2095
2096 fprintf(stderr, "%s ", fetch_type[vtx->fetch_type]);
2097
2098 if (bc->chip_class < CAYMAN && vtx->mega_fetch_count)
2099 fprintf(stderr, "MFC:%d ", vtx->mega_fetch_count);
2100
2101 fprintf(stderr, "UCF:%d ", vtx->use_const_fields);
2102 fprintf(stderr, "FMT(DTA:%d ", vtx->data_format);
2103 fprintf(stderr, "NUM:%d ", vtx->num_format_all);
2104 fprintf(stderr, "COMP:%d ", vtx->format_comp_all);
2105 fprintf(stderr, "MODE:%d)\n", vtx->srf_mode_all);
2106
2107 id += 4;
2108 }
2109 }
2110
2111 fprintf(stderr, "--------------------------------------\n");
2112 }
2113
2114 void r600_vertex_data_type(enum pipe_format pformat,
2115 unsigned *format,
2116 unsigned *num_format, unsigned *format_comp, unsigned *endian)
2117 {
2118 const struct util_format_description *desc;
2119 unsigned i;
2120
2121 *format = 0;
2122 *num_format = 0;
2123 *format_comp = 0;
2124 *endian = ENDIAN_NONE;
2125
2126 desc = util_format_description(pformat);
2127 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
2128 goto out_unknown;
2129 }
2130
2131 /* Find the first non-VOID channel. */
2132 for (i = 0; i < 4; i++) {
2133 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2134 break;
2135 }
2136 }
2137
2138 *endian = r600_endian_swap(desc->channel[i].size);
2139
2140 switch (desc->channel[i].type) {
2141 /* Half-floats, floats, ints */
2142 case UTIL_FORMAT_TYPE_FLOAT:
2143 switch (desc->channel[i].size) {
2144 case 16:
2145 switch (desc->nr_channels) {
2146 case 1:
2147 *format = FMT_16_FLOAT;
2148 break;
2149 case 2:
2150 *format = FMT_16_16_FLOAT;
2151 break;
2152 case 3:
2153 case 4:
2154 *format = FMT_16_16_16_16_FLOAT;
2155 break;
2156 }
2157 break;
2158 case 32:
2159 switch (desc->nr_channels) {
2160 case 1:
2161 *format = FMT_32_FLOAT;
2162 break;
2163 case 2:
2164 *format = FMT_32_32_FLOAT;
2165 break;
2166 case 3:
2167 *format = FMT_32_32_32_FLOAT;
2168 break;
2169 case 4:
2170 *format = FMT_32_32_32_32_FLOAT;
2171 break;
2172 }
2173 break;
2174 default:
2175 goto out_unknown;
2176 }
2177 break;
2178 /* Unsigned ints */
2179 case UTIL_FORMAT_TYPE_UNSIGNED:
2180 /* Signed ints */
2181 case UTIL_FORMAT_TYPE_SIGNED:
2182 switch (desc->channel[i].size) {
2183 case 8:
2184 switch (desc->nr_channels) {
2185 case 1:
2186 *format = FMT_8;
2187 break;
2188 case 2:
2189 *format = FMT_8_8;
2190 break;
2191 case 3:
2192 case 4:
2193 *format = FMT_8_8_8_8;
2194 break;
2195 }
2196 break;
2197 case 10:
2198 if (desc->nr_channels != 4)
2199 goto out_unknown;
2200
2201 *format = FMT_2_10_10_10;
2202 break;
2203 case 16:
2204 switch (desc->nr_channels) {
2205 case 1:
2206 *format = FMT_16;
2207 break;
2208 case 2:
2209 *format = FMT_16_16;
2210 break;
2211 case 3:
2212 case 4:
2213 *format = FMT_16_16_16_16;
2214 break;
2215 }
2216 break;
2217 case 32:
2218 switch (desc->nr_channels) {
2219 case 1:
2220 *format = FMT_32;
2221 break;
2222 case 2:
2223 *format = FMT_32_32;
2224 break;
2225 case 3:
2226 *format = FMT_32_32_32;
2227 break;
2228 case 4:
2229 *format = FMT_32_32_32_32;
2230 break;
2231 }
2232 break;
2233 default:
2234 goto out_unknown;
2235 }
2236 break;
2237 default:
2238 goto out_unknown;
2239 }
2240
2241 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2242 *format_comp = 1;
2243 }
2244
2245 *num_format = 0;
2246 if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED ||
2247 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2248 if (!desc->channel[i].normalized) {
2249 if (desc->channel[i].pure_integer)
2250 *num_format = 1;
2251 else
2252 *num_format = 2;
2253 }
2254 }
2255 return;
2256 out_unknown:
2257 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
2258 }
2259
2260 void *r600_create_vertex_fetch_shader(struct pipe_context *ctx,
2261 unsigned count,
2262 const struct pipe_vertex_element *elements)
2263 {
2264 struct r600_context *rctx = (struct r600_context *)ctx;
2265 struct r600_bytecode bc;
2266 struct r600_bytecode_vtx vtx;
2267 const struct util_format_description *desc;
2268 unsigned fetch_resource_start = rctx->chip_class >= EVERGREEN ? 0 : 160;
2269 unsigned format, num_format, format_comp, endian;
2270 uint32_t *bytecode;
2271 int i, j, r, fs_size;
2272 struct r600_fetch_shader *shader;
2273
2274 assert(count < 32);
2275
2276 memset(&bc, 0, sizeof(bc));
2277 r600_bytecode_init(&bc, rctx->chip_class, rctx->family,
2278 rctx->screen->msaa_texture_support);
2279
2280 bc.isa = rctx->isa;
2281
2282 for (i = 0; i < count; i++) {
2283 if (elements[i].instance_divisor > 1) {
2284 if (rctx->chip_class == CAYMAN) {
2285 for (j = 0; j < 4; j++) {
2286 struct r600_bytecode_alu alu;
2287 memset(&alu, 0, sizeof(alu));
2288 alu.op = ALU_OP2_MULHI_UINT;
2289 alu.src[0].sel = 0;
2290 alu.src[0].chan = 3;
2291 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2292 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2293 alu.dst.sel = i + 1;
2294 alu.dst.chan = j;
2295 alu.dst.write = j == 3;
2296 alu.last = j == 3;
2297 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2298 r600_bytecode_clear(&bc);
2299 return NULL;
2300 }
2301 }
2302 } else {
2303 struct r600_bytecode_alu alu;
2304 memset(&alu, 0, sizeof(alu));
2305 alu.op = ALU_OP2_MULHI_UINT;
2306 alu.src[0].sel = 0;
2307 alu.src[0].chan = 3;
2308 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2309 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2310 alu.dst.sel = i + 1;
2311 alu.dst.chan = 3;
2312 alu.dst.write = 1;
2313 alu.last = 1;
2314 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2315 r600_bytecode_clear(&bc);
2316 return NULL;
2317 }
2318 }
2319 }
2320 }
2321
2322 for (i = 0; i < count; i++) {
2323 r600_vertex_data_type(elements[i].src_format,
2324 &format, &num_format, &format_comp, &endian);
2325
2326 desc = util_format_description(elements[i].src_format);
2327 if (desc == NULL) {
2328 r600_bytecode_clear(&bc);
2329 R600_ERR("unknown format %d\n", elements[i].src_format);
2330 return NULL;
2331 }
2332
2333 if (elements[i].src_offset > 65535) {
2334 r600_bytecode_clear(&bc);
2335 R600_ERR("too big src_offset: %u\n", elements[i].src_offset);
2336 return NULL;
2337 }
2338
2339 memset(&vtx, 0, sizeof(vtx));
2340 vtx.buffer_id = elements[i].vertex_buffer_index + fetch_resource_start;
2341 vtx.fetch_type = elements[i].instance_divisor ? 1 : 0;
2342 vtx.src_gpr = elements[i].instance_divisor > 1 ? i + 1 : 0;
2343 vtx.src_sel_x = elements[i].instance_divisor ? 3 : 0;
2344 vtx.mega_fetch_count = 0x1F;
2345 vtx.dst_gpr = i + 1;
2346 vtx.dst_sel_x = desc->swizzle[0];
2347 vtx.dst_sel_y = desc->swizzle[1];
2348 vtx.dst_sel_z = desc->swizzle[2];
2349 vtx.dst_sel_w = desc->swizzle[3];
2350 vtx.data_format = format;
2351 vtx.num_format_all = num_format;
2352 vtx.format_comp_all = format_comp;
2353 vtx.srf_mode_all = 1;
2354 vtx.offset = elements[i].src_offset;
2355 vtx.endian = endian;
2356
2357 if ((r = r600_bytecode_add_vtx(&bc, &vtx))) {
2358 r600_bytecode_clear(&bc);
2359 return NULL;
2360 }
2361 }
2362
2363 r600_bytecode_add_cfinst(&bc, CF_OP_RET);
2364
2365 if ((r = r600_bytecode_build(&bc))) {
2366 r600_bytecode_clear(&bc);
2367 return NULL;
2368 }
2369
2370 if (rctx->screen->debug_flags & DBG_FS) {
2371 fprintf(stderr, "--------------------------------------------------------------\n");
2372 fprintf(stderr, "Vertex elements state:\n");
2373 for (i = 0; i < count; i++) {
2374 fprintf(stderr, " ");
2375 util_dump_vertex_element(stderr, elements+i);
2376 fprintf(stderr, "\n");
2377 }
2378
2379 r600_bytecode_disasm(&bc);
2380 fprintf(stderr, "______________________________________________________________\n");
2381 }
2382
2383 fs_size = bc.ndw*4;
2384
2385 /* Allocate the CSO. */
2386 shader = CALLOC_STRUCT(r600_fetch_shader);
2387 if (!shader) {
2388 r600_bytecode_clear(&bc);
2389 return NULL;
2390 }
2391
2392 u_suballocator_alloc(rctx->allocator_fetch_shader, fs_size, &shader->offset,
2393 (struct pipe_resource**)&shader->buffer);
2394 if (!shader->buffer) {
2395 r600_bytecode_clear(&bc);
2396 FREE(shader);
2397 return NULL;
2398 }
2399
2400 bytecode = r600_buffer_mmap_sync_with_rings(rctx, shader->buffer, PIPE_TRANSFER_WRITE | PIPE_TRANSFER_UNSYNCHRONIZED);
2401 bytecode += shader->offset / 4;
2402
2403 if (R600_BIG_ENDIAN) {
2404 for (i = 0; i < fs_size / 4; ++i) {
2405 bytecode[i] = bswap_32(bc.bytecode[i]);
2406 }
2407 } else {
2408 memcpy(bytecode, bc.bytecode, fs_size);
2409 }
2410 rctx->ws->buffer_unmap(shader->buffer->cs_buf);
2411
2412 r600_bytecode_clear(&bc);
2413 return shader;
2414 }
2415
2416 void r600_bytecode_alu_read(struct r600_bytecode *bc,
2417 struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1)
2418 {
2419 /* WORD0 */
2420 alu->src[0].sel = G_SQ_ALU_WORD0_SRC0_SEL(word0);
2421 alu->src[0].rel = G_SQ_ALU_WORD0_SRC0_REL(word0);
2422 alu->src[0].chan = G_SQ_ALU_WORD0_SRC0_CHAN(word0);
2423 alu->src[0].neg = G_SQ_ALU_WORD0_SRC0_NEG(word0);
2424 alu->src[1].sel = G_SQ_ALU_WORD0_SRC1_SEL(word0);
2425 alu->src[1].rel = G_SQ_ALU_WORD0_SRC1_REL(word0);
2426 alu->src[1].chan = G_SQ_ALU_WORD0_SRC1_CHAN(word0);
2427 alu->src[1].neg = G_SQ_ALU_WORD0_SRC1_NEG(word0);
2428 alu->index_mode = G_SQ_ALU_WORD0_INDEX_MODE(word0);
2429 alu->pred_sel = G_SQ_ALU_WORD0_PRED_SEL(word0);
2430 alu->last = G_SQ_ALU_WORD0_LAST(word0);
2431
2432 /* WORD1 */
2433 alu->bank_swizzle = G_SQ_ALU_WORD1_BANK_SWIZZLE(word1);
2434 if (alu->bank_swizzle)
2435 alu->bank_swizzle_force = alu->bank_swizzle;
2436 alu->dst.sel = G_SQ_ALU_WORD1_DST_GPR(word1);
2437 alu->dst.rel = G_SQ_ALU_WORD1_DST_REL(word1);
2438 alu->dst.chan = G_SQ_ALU_WORD1_DST_CHAN(word1);
2439 alu->dst.clamp = G_SQ_ALU_WORD1_CLAMP(word1);
2440 if (G_SQ_ALU_WORD1_ENCODING(word1)) /*ALU_DWORD1_OP3*/
2441 {
2442 alu->is_op3 = 1;
2443 alu->src[2].sel = G_SQ_ALU_WORD1_OP3_SRC2_SEL(word1);
2444 alu->src[2].rel = G_SQ_ALU_WORD1_OP3_SRC2_REL(word1);
2445 alu->src[2].chan = G_SQ_ALU_WORD1_OP3_SRC2_CHAN(word1);
2446 alu->src[2].neg = G_SQ_ALU_WORD1_OP3_SRC2_NEG(word1);
2447 alu->op = r600_isa_alu_by_opcode(bc->isa,
2448 G_SQ_ALU_WORD1_OP3_ALU_INST(word1), /* is_op3 = */ 1);
2449
2450 }
2451 else /*ALU_DWORD1_OP2*/
2452 {
2453 alu->src[0].abs = G_SQ_ALU_WORD1_OP2_SRC0_ABS(word1);
2454 alu->src[1].abs = G_SQ_ALU_WORD1_OP2_SRC1_ABS(word1);
2455 alu->op = r600_isa_alu_by_opcode(bc->isa,
2456 G_SQ_ALU_WORD1_OP2_ALU_INST(word1), /* is_op3 = */ 0);
2457 alu->omod = G_SQ_ALU_WORD1_OP2_OMOD(word1);
2458 alu->dst.write = G_SQ_ALU_WORD1_OP2_WRITE_MASK(word1);
2459 alu->update_pred = G_SQ_ALU_WORD1_OP2_UPDATE_PRED(word1);
2460 alu->execute_mask =
2461 G_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(word1);
2462 }
2463 }
2464
2465 void r600_bytecode_export_read(struct r600_bytecode *bc,
2466 struct r600_bytecode_output *output, uint32_t word0, uint32_t word1)
2467 {
2468 output->array_base = G_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(word0);
2469 output->type = G_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(word0);
2470 output->gpr = G_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(word0);
2471 output->elem_size = G_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(word0);
2472
2473 output->swizzle_x = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(word1);
2474 output->swizzle_y = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(word1);
2475 output->swizzle_z = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(word1);
2476 output->swizzle_w = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(word1);
2477 output->burst_count = G_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(word1);
2478 output->end_of_program = G_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(word1);
2479 output->op = r600_isa_cf_by_opcode(bc->isa,
2480 G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(word1), 0);
2481 output->barrier = G_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(word1);
2482 output->array_size = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(word1);
2483 output->comp_mask = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(word1);
2484 }