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r600g: delete old path
[mesa.git] / src / gallium / drivers / r600 / r600_asm.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include <stdio.h>
24 #include <errno.h>
25 #include "util/u_memory.h"
26 #include "r600_pipe.h"
27 #include "r600_sq.h"
28 #include "r600_opcodes.h"
29 #include "r600_asm.h"
30
31 static inline unsigned int r600_bc_get_num_operands(struct r600_bc_alu *alu)
32 {
33 if(alu->is_op3)
34 return 3;
35
36 switch (alu->inst) {
37 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
38 return 0;
39 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
40 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
41 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
42 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
43 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
44 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
45 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
46 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
47 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
48 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
49 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
50 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
51 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
52 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
53 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
54 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
55 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
56 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
57 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
58 return 2;
59
60 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
61 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR:
62 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
63 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
64 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
65 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
66 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
67 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
68 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
69 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
70 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
71 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
72 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
73 return 1;
74 default: R600_ERR(
75 "Need instruction operand number for 0x%x.\n", alu->inst);
76 };
77
78 return 3;
79 }
80
81 int r700_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id);
82
83 static struct r600_bc_cf *r600_bc_cf(void)
84 {
85 struct r600_bc_cf *cf = CALLOC_STRUCT(r600_bc_cf);
86
87 if (cf == NULL)
88 return NULL;
89 LIST_INITHEAD(&cf->list);
90 LIST_INITHEAD(&cf->alu);
91 LIST_INITHEAD(&cf->vtx);
92 LIST_INITHEAD(&cf->tex);
93 return cf;
94 }
95
96 static struct r600_bc_alu *r600_bc_alu(void)
97 {
98 struct r600_bc_alu *alu = CALLOC_STRUCT(r600_bc_alu);
99
100 if (alu == NULL)
101 return NULL;
102 LIST_INITHEAD(&alu->list);
103 LIST_INITHEAD(&alu->bs_list);
104 return alu;
105 }
106
107 static struct r600_bc_vtx *r600_bc_vtx(void)
108 {
109 struct r600_bc_vtx *vtx = CALLOC_STRUCT(r600_bc_vtx);
110
111 if (vtx == NULL)
112 return NULL;
113 LIST_INITHEAD(&vtx->list);
114 return vtx;
115 }
116
117 static struct r600_bc_tex *r600_bc_tex(void)
118 {
119 struct r600_bc_tex *tex = CALLOC_STRUCT(r600_bc_tex);
120
121 if (tex == NULL)
122 return NULL;
123 LIST_INITHEAD(&tex->list);
124 return tex;
125 }
126
127 int r600_bc_init(struct r600_bc *bc, enum radeon_family family)
128 {
129 LIST_INITHEAD(&bc->cf);
130 bc->family = family;
131 switch (bc->family) {
132 case CHIP_R600:
133 case CHIP_RV610:
134 case CHIP_RV630:
135 case CHIP_RV670:
136 case CHIP_RV620:
137 case CHIP_RV635:
138 case CHIP_RS780:
139 case CHIP_RS880:
140 bc->chiprev = 0;
141 break;
142 case CHIP_RV770:
143 case CHIP_RV730:
144 case CHIP_RV710:
145 case CHIP_RV740:
146 bc->chiprev = 1;
147 break;
148 case CHIP_CEDAR:
149 case CHIP_REDWOOD:
150 case CHIP_JUNIPER:
151 case CHIP_CYPRESS:
152 case CHIP_HEMLOCK:
153 bc->chiprev = 2;
154 break;
155 default:
156 R600_ERR("unknown family %d\n", bc->family);
157 return -EINVAL;
158 }
159 return 0;
160 }
161
162 static int r600_bc_add_cf(struct r600_bc *bc)
163 {
164 struct r600_bc_cf *cf = r600_bc_cf();
165
166 if (cf == NULL)
167 return -ENOMEM;
168 LIST_ADDTAIL(&cf->list, &bc->cf);
169 if (bc->cf_last)
170 cf->id = bc->cf_last->id + 2;
171 bc->cf_last = cf;
172 bc->ncf++;
173 bc->ndw += 2;
174 bc->force_add_cf = 0;
175 return 0;
176 }
177
178 int r600_bc_add_output(struct r600_bc *bc, const struct r600_bc_output *output)
179 {
180 int r;
181
182 r = r600_bc_add_cf(bc);
183 if (r)
184 return r;
185 bc->cf_last->inst = output->inst;
186 memcpy(&bc->cf_last->output, output, sizeof(struct r600_bc_output));
187 return 0;
188 }
189
190 const unsigned bank_swizzle_vec[8] = {SQ_ALU_VEC_210, //000
191 SQ_ALU_VEC_120, //001
192 SQ_ALU_VEC_102, //010
193
194 SQ_ALU_VEC_201, //011
195 SQ_ALU_VEC_012, //100
196 SQ_ALU_VEC_021, //101
197
198 SQ_ALU_VEC_012, //110
199 SQ_ALU_VEC_012}; //111
200
201 const unsigned bank_swizzle_scl[8] = {SQ_ALU_SCL_210, //000
202 SQ_ALU_SCL_122, //001
203 SQ_ALU_SCL_122, //010
204
205 SQ_ALU_SCL_221, //011
206 SQ_ALU_SCL_212, //100
207 SQ_ALU_SCL_122, //101
208
209 SQ_ALU_SCL_122, //110
210 SQ_ALU_SCL_122}; //111
211
212 static int init_gpr(struct r600_bc_alu *alu)
213 {
214 int cycle, component;
215 /* set up gpr use */
216 for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
217 for (component = 0; component < NUM_OF_COMPONENTS; component++)
218 alu->hw_gpr[cycle][component] = -1;
219 return 0;
220 }
221
222 #if 0
223 static int reserve_gpr(struct r600_bc_alu *alu, unsigned sel, unsigned chan, unsigned cycle)
224 {
225 if (alu->hw_gpr[cycle][chan] < 0)
226 alu->hw_gpr[cycle][chan] = sel;
227 else if (alu->hw_gpr[cycle][chan] != (int)sel) {
228 R600_ERR("Another scalar operation has already used GPR read port for channel\n");
229 return -1;
230 }
231 return 0;
232 }
233
234 static int cycle_for_scalar_bank_swizzle(const int swiz, const int sel, unsigned *p_cycle)
235 {
236 int table[3];
237 int ret = 0;
238 switch (swiz) {
239 case SQ_ALU_SCL_210:
240 table[0] = 2; table[1] = 1; table[2] = 0;
241 *p_cycle = table[sel];
242 break;
243 case SQ_ALU_SCL_122:
244 table[0] = 1; table[1] = 2; table[2] = 2;
245 *p_cycle = table[sel];
246 break;
247 case SQ_ALU_SCL_212:
248 table[0] = 2; table[1] = 1; table[2] = 2;
249 *p_cycle = table[sel];
250 break;
251 case SQ_ALU_SCL_221:
252 table[0] = 2; table[1] = 2; table[2] = 1;
253 *p_cycle = table[sel];
254 break;
255 break;
256 default:
257 R600_ERR("bad scalar bank swizzle value\n");
258 ret = -1;
259 break;
260 }
261 return ret;
262 }
263
264 static int cycle_for_vector_bank_swizzle(const int swiz, const int sel, unsigned *p_cycle)
265 {
266 int table[3];
267 int ret;
268
269 switch (swiz) {
270 case SQ_ALU_VEC_012:
271 table[0] = 0; table[1] = 1; table[2] = 2;
272 *p_cycle = table[sel];
273 break;
274 case SQ_ALU_VEC_021:
275 table[0] = 0; table[1] = 2; table[2] = 1;
276 *p_cycle = table[sel];
277 break;
278 case SQ_ALU_VEC_120:
279 table[0] = 1; table[1] = 2; table[2] = 0;
280 *p_cycle = table[sel];
281 break;
282 case SQ_ALU_VEC_102:
283 table[0] = 1; table[1] = 0; table[2] = 2;
284 *p_cycle = table[sel];
285 break;
286 case SQ_ALU_VEC_201:
287 table[0] = 2; table[1] = 0; table[2] = 1;
288 *p_cycle = table[sel];
289 break;
290 case SQ_ALU_VEC_210:
291 table[0] = 2; table[1] = 1; table[2] = 0;
292 *p_cycle = table[sel];
293 break;
294 default:
295 R600_ERR("bad vector bank swizzle value\n");
296 ret = -1;
297 break;
298 }
299 return ret;
300 }
301
302
303
304 static void update_chan_counter(struct r600_bc_alu *alu, int *chan_counter)
305 {
306 int num_src;
307 int i;
308 int channel_swizzle;
309
310 num_src = r600_bc_get_num_operands(alu);
311
312 for (i = 0; i < num_src; i++) {
313 channel_swizzle = alu->src[i].chan;
314 if ((alu->src[i].sel > 0 && alu->src[i].sel < 128) && channel_swizzle <= 3)
315 chan_counter[channel_swizzle]++;
316 }
317 }
318
319 /* we need something like this I think - but this is bogus */
320 int check_read_slots(struct r600_bc *bc, struct r600_bc_alu *alu_first)
321 {
322 struct r600_bc_alu *alu;
323 int chan_counter[4] = { 0 };
324
325 update_chan_counter(alu_first, chan_counter);
326
327 LIST_FOR_EACH_ENTRY(alu, &alu_first->bs_list, bs_list) {
328 update_chan_counter(alu, chan_counter);
329 }
330
331 if (chan_counter[0] > 3 ||
332 chan_counter[1] > 3 ||
333 chan_counter[2] > 3 ||
334 chan_counter[3] > 3) {
335 R600_ERR("needed to split instruction for input ran out of banks %x %d %d %d %d\n",
336 alu_first->inst, chan_counter[0], chan_counter[1], chan_counter[2], chan_counter[3]);
337 return -1;
338 }
339 return 0;
340 }
341 #endif
342
343 static int is_const(int sel)
344 {
345 if (sel > 255 && sel < 512)
346 return 1;
347 if (sel >= V_SQ_ALU_SRC_0 && sel <= V_SQ_ALU_SRC_LITERAL)
348 return 1;
349 return 0;
350 }
351
352 static int check_scalar(struct r600_bc *bc, struct r600_bc_alu *alu)
353 {
354 unsigned swizzle_key;
355
356 if (alu->bank_swizzle_force) {
357 alu->bank_swizzle = alu->bank_swizzle_force;
358 return 0;
359 }
360 swizzle_key = (is_const(alu->src[0].sel) ? 4 : 0 ) +
361 (is_const(alu->src[1].sel) ? 2 : 0 ) +
362 (is_const(alu->src[2].sel) ? 1 : 0 );
363
364 alu->bank_swizzle = bank_swizzle_scl[swizzle_key];
365 return 0;
366 }
367
368 static int check_vector(struct r600_bc *bc, struct r600_bc_alu *alu)
369 {
370 unsigned swizzle_key;
371
372 if (alu->bank_swizzle_force) {
373 alu->bank_swizzle = alu->bank_swizzle_force;
374 return 0;
375 }
376 swizzle_key = (is_const(alu->src[0].sel) ? 4 : 0 ) +
377 (is_const(alu->src[1].sel) ? 2 : 0 ) +
378 (is_const(alu->src[2].sel) ? 1 : 0 );
379
380 alu->bank_swizzle = bank_swizzle_vec[swizzle_key];
381 return 0;
382 }
383
384 static int check_and_set_bank_swizzle(struct r600_bc *bc, struct r600_bc_alu *alu_first)
385 {
386 struct r600_bc_alu *alu = NULL;
387 int num_instr = 1;
388
389 init_gpr(alu_first);
390
391 LIST_FOR_EACH_ENTRY(alu, &alu_first->bs_list, bs_list) {
392 num_instr++;
393 }
394
395 if (num_instr == 1) {
396 check_scalar(bc, alu_first);
397
398 } else {
399 /* check_read_slots(bc, bc->cf_last->curr_bs_head);*/
400 check_vector(bc, alu_first);
401 LIST_FOR_EACH_ENTRY(alu, &alu_first->bs_list, bs_list) {
402 check_vector(bc, alu);
403 }
404 }
405 return 0;
406 }
407
408 int r600_bc_add_alu_type(struct r600_bc *bc, const struct r600_bc_alu *alu, int type)
409 {
410 struct r600_bc_alu *nalu = r600_bc_alu();
411 struct r600_bc_alu *lalu;
412 int i, r;
413
414 if (nalu == NULL)
415 return -ENOMEM;
416 memcpy(nalu, alu, sizeof(struct r600_bc_alu));
417 nalu->nliteral = 0;
418
419 /* cf can contains only alu or only vtx or only tex */
420 if (bc->cf_last == NULL || bc->cf_last->inst != (type << 3) ||
421 bc->force_add_cf) {
422 r = r600_bc_add_cf(bc);
423 if (r) {
424 free(nalu);
425 return r;
426 }
427 bc->cf_last->inst = (type << 3);
428 }
429 if (!bc->cf_last->curr_bs_head) {
430 bc->cf_last->curr_bs_head = nalu;
431 LIST_INITHEAD(&nalu->bs_list);
432 } else {
433 LIST_ADDTAIL(&nalu->bs_list, &bc->cf_last->curr_bs_head->bs_list);
434 }
435 /* at most 128 slots, one add alu can add 4 slots + 4 constants(2 slots)
436 * worst case */
437 if (alu->last && (bc->cf_last->ndw >> 1) >= 120) {
438 bc->force_add_cf = 1;
439 }
440 /* number of gpr == the last gpr used in any alu */
441 for (i = 0; i < 3; i++) {
442 if (alu->src[i].sel >= bc->ngpr && alu->src[i].sel < 128) {
443 bc->ngpr = alu->src[i].sel + 1;
444 }
445 /* compute how many literal are needed
446 * either 2 or 4 literals
447 */
448 if (alu->src[i].sel == 253) {
449 if (((alu->src[i].chan + 2) & 0x6) > nalu->nliteral) {
450 nalu->nliteral = (alu->src[i].chan + 2) & 0x6;
451 }
452 }
453 }
454 if (!LIST_IS_EMPTY(&bc->cf_last->alu)) {
455 lalu = LIST_ENTRY(struct r600_bc_alu, bc->cf_last->alu.prev, list);
456 if (!lalu->last && lalu->nliteral > nalu->nliteral) {
457 nalu->nliteral = lalu->nliteral;
458 }
459 }
460 if (alu->dst.sel >= bc->ngpr) {
461 bc->ngpr = alu->dst.sel + 1;
462 }
463 LIST_ADDTAIL(&nalu->list, &bc->cf_last->alu);
464 /* each alu use 2 dwords */
465 bc->cf_last->ndw += 2;
466 bc->ndw += 2;
467
468 if (bc->use_mem_constant)
469 bc->cf_last->kcache0_mode = 2;
470
471 /* process cur ALU instructions for bank swizzle */
472 if (alu->last) {
473 check_and_set_bank_swizzle(bc, bc->cf_last->curr_bs_head);
474 bc->cf_last->curr_bs_head = NULL;
475 }
476 return 0;
477 }
478
479 int r600_bc_add_alu(struct r600_bc *bc, const struct r600_bc_alu *alu)
480 {
481 return r600_bc_add_alu_type(bc, alu, BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
482 }
483
484 int r600_bc_add_literal(struct r600_bc *bc, const u32 *value)
485 {
486 struct r600_bc_alu *alu;
487
488 if (bc->cf_last == NULL) {
489 return 0;
490 }
491 if (bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_TEX) {
492 return 0;
493 }
494 /* all same on EG */
495 if (bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_JUMP ||
496 bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_ELSE ||
497 bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL ||
498 bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK ||
499 bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE ||
500 bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END ||
501 bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_POP) {
502 return 0;
503 }
504 /* same on EG */
505 if (((bc->cf_last->inst != (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3)) &&
506 (bc->cf_last->inst != (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3))) ||
507 LIST_IS_EMPTY(&bc->cf_last->alu)) {
508 R600_ERR("last CF is not ALU (%p)\n", bc->cf_last);
509 return -EINVAL;
510 }
511 alu = LIST_ENTRY(struct r600_bc_alu, bc->cf_last->alu.prev, list);
512 if (!alu->last || !alu->nliteral || alu->literal_added) {
513 return 0;
514 }
515 memcpy(alu->value, value, 4 * 4);
516 bc->cf_last->ndw += alu->nliteral;
517 bc->ndw += alu->nliteral;
518 alu->literal_added = 1;
519 return 0;
520 }
521
522 int r600_bc_add_vtx(struct r600_bc *bc, const struct r600_bc_vtx *vtx)
523 {
524 struct r600_bc_vtx *nvtx = r600_bc_vtx();
525 int r;
526
527 if (nvtx == NULL)
528 return -ENOMEM;
529 memcpy(nvtx, vtx, sizeof(struct r600_bc_vtx));
530
531 /* cf can contains only alu or only vtx or only tex */
532 if (bc->cf_last == NULL ||
533 (bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX &&
534 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC) ||
535 bc->force_add_cf) {
536 r = r600_bc_add_cf(bc);
537 if (r) {
538 free(nvtx);
539 return r;
540 }
541 bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_VTX;
542 }
543 LIST_ADDTAIL(&nvtx->list, &bc->cf_last->vtx);
544 /* each fetch use 4 dwords */
545 bc->cf_last->ndw += 4;
546 bc->ndw += 4;
547 if ((bc->ndw / 4) > 7)
548 bc->force_add_cf = 1;
549 return 0;
550 }
551
552 int r600_bc_add_tex(struct r600_bc *bc, const struct r600_bc_tex *tex)
553 {
554 struct r600_bc_tex *ntex = r600_bc_tex();
555 int r;
556
557 if (ntex == NULL)
558 return -ENOMEM;
559 memcpy(ntex, tex, sizeof(struct r600_bc_tex));
560
561 /* cf can contains only alu or only vtx or only tex */
562 if (bc->cf_last == NULL ||
563 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_TEX ||
564 bc->force_add_cf) {
565 r = r600_bc_add_cf(bc);
566 if (r) {
567 free(ntex);
568 return r;
569 }
570 bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_TEX;
571 }
572 LIST_ADDTAIL(&ntex->list, &bc->cf_last->tex);
573 /* each texture fetch use 4 dwords */
574 bc->cf_last->ndw += 4;
575 bc->ndw += 4;
576 if ((bc->ndw / 4) > 7)
577 bc->force_add_cf = 1;
578 return 0;
579 }
580
581 int r600_bc_add_cfinst(struct r600_bc *bc, int inst)
582 {
583 int r;
584 r = r600_bc_add_cf(bc);
585 if (r)
586 return r;
587
588 bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
589 bc->cf_last->inst = inst;
590 return 0;
591 }
592
593 /* common to all 3 families */
594 static int r600_bc_vtx_build(struct r600_bc *bc, struct r600_bc_vtx *vtx, unsigned id)
595 {
596 bc->bytecode[id++] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) |
597 S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
598 S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x) |
599 S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
600 bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
601 S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
602 S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
603 S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
604 S_SQ_VTX_WORD1_USE_CONST_FIELDS(1) |
605 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
606 bc->bytecode[id++] = S_SQ_VTX_WORD2_MEGA_FETCH(1);
607 bc->bytecode[id++] = 0;
608 return 0;
609 }
610
611 /* common to all 3 families */
612 static int r600_bc_tex_build(struct r600_bc *bc, struct r600_bc_tex *tex, unsigned id)
613 {
614 bc->bytecode[id++] = S_SQ_TEX_WORD0_TEX_INST(tex->inst) |
615 S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
616 S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
617 S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
618 bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
619 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
620 S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
621 S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
622 S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
623 S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
624 S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
625 S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
626 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
627 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
628 S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
629 bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
630 S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
631 S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
632 S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
633 S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
634 S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
635 S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
636 S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
637 bc->bytecode[id++] = 0;
638 return 0;
639 }
640
641 /* r600 only, r700/eg bits in r700_asm.c */
642 static int r600_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id)
643 {
644 unsigned i;
645
646 /* don't replace gpr by pv or ps for destination register */
647 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
648 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
649 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
650 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
651 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
652 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
653 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
654 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
655 S_SQ_ALU_WORD0_LAST(alu->last);
656
657 if (alu->is_op3) {
658 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
659 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
660 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
661 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
662 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
663 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
664 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
665 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
666 S_SQ_ALU_WORD1_OP3_ALU_INST(alu->inst) |
667 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
668 } else {
669 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
670 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
671 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
672 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
673 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
674 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
675 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
676 S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
677 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
678 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->predicate) |
679 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->predicate);
680 }
681 if (alu->last) {
682 if (alu->nliteral && !alu->literal_added) {
683 R600_ERR("Bug in ALU processing for instruction 0x%08x, literal not added correctly\n", alu->inst);
684 }
685 for (i = 0; i < alu->nliteral; i++) {
686 bc->bytecode[id++] = alu->value[i];
687 }
688 }
689 return 0;
690 }
691
692 /* common for r600/r700 - eg in eg_asm.c */
693 static int r600_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf)
694 {
695 unsigned id = cf->id;
696
697 switch (cf->inst) {
698 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
699 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
700 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
701 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache0_mode);
702
703 bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(cf->inst >> 3) |
704 S_SQ_CF_ALU_WORD1_BARRIER(1) |
705 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chiprev == 0 ? cf->r6xx_uses_waterfall : 0) |
706 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
707 break;
708 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
709 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
710 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
711 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
712 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) |
713 S_SQ_CF_WORD1_BARRIER(1) |
714 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
715 break;
716 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
717 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
718 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
719 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
720 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
721 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
722 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
723 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
724 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
725 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
726 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
727 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst) |
728 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program);
729 break;
730 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
731 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
732 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
733 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
734 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
735 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
736 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
737 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
738 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) |
739 S_SQ_CF_WORD1_BARRIER(1) |
740 S_SQ_CF_WORD1_COND(cf->cond) |
741 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count);
742
743 break;
744 default:
745 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
746 return -EINVAL;
747 }
748 return 0;
749 }
750
751 int r600_bc_build(struct r600_bc *bc)
752 {
753 struct r600_bc_cf *cf;
754 struct r600_bc_alu *alu;
755 struct r600_bc_vtx *vtx;
756 struct r600_bc_tex *tex;
757 unsigned addr;
758 int r;
759
760 if (bc->callstack[0].max > 0)
761 bc->nstack = ((bc->callstack[0].max + 3) >> 2) + 2;
762
763 /* first path compute addr of each CF block */
764 /* addr start after all the CF instructions */
765 addr = bc->cf_last->id + 2;
766 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
767 switch (cf->inst) {
768 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
769 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
770 break;
771 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
772 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
773 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
774 /* fetch node need to be 16 bytes aligned*/
775 addr += 3;
776 addr &= 0xFFFFFFFCUL;
777 break;
778 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
779 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
780 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
781 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
782 break;
783 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
784 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
785 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
786 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
787 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
788 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
789 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
790 break;
791 default:
792 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
793 return -EINVAL;
794 }
795 cf->addr = addr;
796 addr += cf->ndw;
797 bc->ndw = cf->addr + cf->ndw;
798 }
799 free(bc->bytecode);
800 bc->bytecode = calloc(1, bc->ndw * 4);
801 if (bc->bytecode == NULL)
802 return -ENOMEM;
803 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
804 addr = cf->addr;
805 if (bc->chiprev == 2)
806 r = eg_bc_cf_build(bc, cf);
807 else
808 r = r600_bc_cf_build(bc, cf);
809 if (r)
810 return r;
811 switch (cf->inst) {
812 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
813 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
814 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
815 switch(bc->chiprev) {
816 case 0:
817 r = r600_bc_alu_build(bc, alu, addr);
818 break;
819 case 1:
820 case 2: /* eg alu is same encoding as r700 */
821 r = r700_bc_alu_build(bc, alu, addr);
822 break;
823 default:
824 R600_ERR("unknown family %d\n", bc->family);
825 return -EINVAL;
826 }
827 if (r)
828 return r;
829 addr += 2;
830 if (alu->last) {
831 addr += alu->nliteral;
832 }
833 }
834 break;
835 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
836 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
837 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
838 r = r600_bc_vtx_build(bc, vtx, addr);
839 if (r)
840 return r;
841 addr += 4;
842 }
843 break;
844 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
845 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
846 r = r600_bc_tex_build(bc, tex, addr);
847 if (r)
848 return r;
849 addr += 4;
850 }
851 break;
852 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
853 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
854 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
855 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
856 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
857 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
858 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
859 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
860 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
861 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
862 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
863 break;
864 default:
865 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
866 return -EINVAL;
867 }
868 }
869 return 0;
870 }