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r600g: Support emitting scratch ops
[mesa.git] / src / gallium / drivers / r600 / r600_asm.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_opcodes.h"
25 #include "r600_formats.h"
26 #include "r600_shader.h"
27 #include "r600d.h"
28
29 #include <errno.h>
30 #include "util/u_bitcast.h"
31 #include "util/u_dump.h"
32 #include "util/u_memory.h"
33 #include "util/u_math.h"
34 #include "pipe/p_shader_tokens.h"
35
36 #include "sb/sb_public.h"
37
38 #define NUM_OF_CYCLES 3
39 #define NUM_OF_COMPONENTS 4
40
41 static inline bool alu_writes(struct r600_bytecode_alu *alu)
42 {
43 return alu->dst.write || alu->is_op3;
44 }
45
46 static inline unsigned int r600_bytecode_get_num_operands(const struct r600_bytecode_alu *alu)
47 {
48 return r600_isa_alu(alu->op)->src_count;
49 }
50
51 static struct r600_bytecode_cf *r600_bytecode_cf(void)
52 {
53 struct r600_bytecode_cf *cf = CALLOC_STRUCT(r600_bytecode_cf);
54
55 if (!cf)
56 return NULL;
57 LIST_INITHEAD(&cf->list);
58 LIST_INITHEAD(&cf->alu);
59 LIST_INITHEAD(&cf->vtx);
60 LIST_INITHEAD(&cf->tex);
61 LIST_INITHEAD(&cf->gds);
62 return cf;
63 }
64
65 static struct r600_bytecode_alu *r600_bytecode_alu(void)
66 {
67 struct r600_bytecode_alu *alu = CALLOC_STRUCT(r600_bytecode_alu);
68
69 if (!alu)
70 return NULL;
71 LIST_INITHEAD(&alu->list);
72 return alu;
73 }
74
75 static struct r600_bytecode_vtx *r600_bytecode_vtx(void)
76 {
77 struct r600_bytecode_vtx *vtx = CALLOC_STRUCT(r600_bytecode_vtx);
78
79 if (!vtx)
80 return NULL;
81 LIST_INITHEAD(&vtx->list);
82 return vtx;
83 }
84
85 static struct r600_bytecode_tex *r600_bytecode_tex(void)
86 {
87 struct r600_bytecode_tex *tex = CALLOC_STRUCT(r600_bytecode_tex);
88
89 if (!tex)
90 return NULL;
91 LIST_INITHEAD(&tex->list);
92 return tex;
93 }
94
95 static struct r600_bytecode_gds *r600_bytecode_gds(void)
96 {
97 struct r600_bytecode_gds *gds = CALLOC_STRUCT(r600_bytecode_gds);
98
99 if (gds == NULL)
100 return NULL;
101 LIST_INITHEAD(&gds->list);
102 return gds;
103 }
104
105 static unsigned stack_entry_size(enum radeon_family chip) {
106 /* Wavefront size:
107 * 64: R600/RV670/RV770/Cypress/R740/Barts/Turks/Caicos/
108 * Aruba/Sumo/Sumo2/redwood/juniper
109 * 32: R630/R730/R710/Palm/Cedar
110 * 16: R610/Rs780
111 *
112 * Stack row size:
113 * Wavefront Size 16 32 48 64
114 * Columns per Row (R6xx/R7xx/R8xx only) 8 8 4 4
115 * Columns per Row (R9xx+) 8 4 4 4 */
116
117 switch (chip) {
118 /* FIXME: are some chips missing here? */
119 /* wavefront size 16 */
120 case CHIP_RV610:
121 case CHIP_RS780:
122 case CHIP_RV620:
123 case CHIP_RS880:
124 /* wavefront size 32 */
125 case CHIP_RV630:
126 case CHIP_RV635:
127 case CHIP_RV730:
128 case CHIP_RV710:
129 case CHIP_PALM:
130 case CHIP_CEDAR:
131 return 8;
132
133 /* wavefront size 64 */
134 default:
135 return 4;
136 }
137 }
138
139 void r600_bytecode_init(struct r600_bytecode *bc,
140 enum chip_class chip_class,
141 enum radeon_family family,
142 bool has_compressed_msaa_texturing)
143 {
144 static unsigned next_shader_id = 0;
145
146 bc->debug_id = ++next_shader_id;
147
148 if ((chip_class == R600) &&
149 (family != CHIP_RV670 && family != CHIP_RS780 && family != CHIP_RS880)) {
150 bc->ar_handling = AR_HANDLE_RV6XX;
151 bc->r6xx_nop_after_rel_dst = 1;
152 } else {
153 bc->ar_handling = AR_HANDLE_NORMAL;
154 bc->r6xx_nop_after_rel_dst = 0;
155 }
156
157 LIST_INITHEAD(&bc->cf);
158 bc->chip_class = chip_class;
159 bc->family = family;
160 bc->has_compressed_msaa_texturing = has_compressed_msaa_texturing;
161 bc->stack.entry_size = stack_entry_size(family);
162 }
163
164 int r600_bytecode_add_cf(struct r600_bytecode *bc)
165 {
166 struct r600_bytecode_cf *cf = r600_bytecode_cf();
167
168 if (!cf)
169 return -ENOMEM;
170 LIST_ADDTAIL(&cf->list, &bc->cf);
171 if (bc->cf_last) {
172 cf->id = bc->cf_last->id + 2;
173 if (bc->cf_last->eg_alu_extended) {
174 /* take into account extended alu size */
175 cf->id += 2;
176 bc->ndw += 2;
177 }
178 }
179 bc->cf_last = cf;
180 bc->ncf++;
181 bc->ndw += 2;
182 bc->force_add_cf = 0;
183 bc->ar_loaded = 0;
184 return 0;
185 }
186
187 int r600_bytecode_add_output(struct r600_bytecode *bc,
188 const struct r600_bytecode_output *output)
189 {
190 int r;
191
192 if (output->gpr >= bc->ngpr)
193 bc->ngpr = output->gpr + 1;
194
195 if (bc->cf_last && (bc->cf_last->op == output->op ||
196 (bc->cf_last->op == CF_OP_EXPORT &&
197 output->op == CF_OP_EXPORT_DONE)) &&
198 output->type == bc->cf_last->output.type &&
199 output->elem_size == bc->cf_last->output.elem_size &&
200 output->swizzle_x == bc->cf_last->output.swizzle_x &&
201 output->swizzle_y == bc->cf_last->output.swizzle_y &&
202 output->swizzle_z == bc->cf_last->output.swizzle_z &&
203 output->swizzle_w == bc->cf_last->output.swizzle_w &&
204 output->comp_mask == bc->cf_last->output.comp_mask &&
205 (output->burst_count + bc->cf_last->output.burst_count) <= 16) {
206
207 if ((output->gpr + output->burst_count) == bc->cf_last->output.gpr &&
208 (output->array_base + output->burst_count) == bc->cf_last->output.array_base) {
209
210 bc->cf_last->op = bc->cf_last->output.op = output->op;
211 bc->cf_last->output.gpr = output->gpr;
212 bc->cf_last->output.array_base = output->array_base;
213 bc->cf_last->output.burst_count += output->burst_count;
214 return 0;
215
216 } else if (output->gpr == (bc->cf_last->output.gpr + bc->cf_last->output.burst_count) &&
217 output->array_base == (bc->cf_last->output.array_base + bc->cf_last->output.burst_count)) {
218
219 bc->cf_last->op = bc->cf_last->output.op = output->op;
220 bc->cf_last->output.burst_count += output->burst_count;
221 return 0;
222 }
223 }
224
225 r = r600_bytecode_add_cf(bc);
226 if (r)
227 return r;
228 bc->cf_last->op = output->op;
229 memcpy(&bc->cf_last->output, output, sizeof(struct r600_bytecode_output));
230 bc->cf_last->barrier = 1;
231 return 0;
232 }
233
234 /* alu instructions that can ony exits once per group */
235 static int is_alu_once_inst(struct r600_bytecode_alu *alu)
236 {
237 return r600_isa_alu(alu->op)->flags & (AF_KILL | AF_PRED) || alu->is_lds_idx_op || alu->op == ALU_OP0_GROUP_BARRIER;
238 }
239
240 static int is_alu_reduction_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
241 {
242 return (r600_isa_alu(alu->op)->flags & AF_REPL) &&
243 (r600_isa_alu_slots(bc->isa->hw_class, alu->op) == AF_4V);
244 }
245
246 static int is_alu_mova_inst(struct r600_bytecode_alu *alu)
247 {
248 return r600_isa_alu(alu->op)->flags & AF_MOVA;
249 }
250
251 static int alu_uses_rel(struct r600_bytecode_alu *alu)
252 {
253 unsigned num_src = r600_bytecode_get_num_operands(alu);
254 unsigned src;
255
256 if (alu->dst.rel) {
257 return 1;
258 }
259
260 for (src = 0; src < num_src; ++src) {
261 if (alu->src[src].rel) {
262 return 1;
263 }
264 }
265 return 0;
266 }
267
268 static int is_lds_read(int sel)
269 {
270 return sel == EG_V_SQ_ALU_SRC_LDS_OQ_A_POP || sel == EG_V_SQ_ALU_SRC_LDS_OQ_B_POP;
271 }
272
273 static int alu_uses_lds(struct r600_bytecode_alu *alu)
274 {
275 unsigned num_src = r600_bytecode_get_num_operands(alu);
276 unsigned src;
277
278 for (src = 0; src < num_src; ++src) {
279 if (is_lds_read(alu->src[src].sel)) {
280 return 1;
281 }
282 }
283 return 0;
284 }
285
286 static int is_alu_64bit_inst(struct r600_bytecode_alu *alu)
287 {
288 const struct alu_op_info *op = r600_isa_alu(alu->op);
289 return (op->flags & AF_64);
290 }
291
292 static int is_alu_vec_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
293 {
294 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
295 return !(slots & AF_S);
296 }
297
298 static int is_alu_trans_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
299 {
300 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
301 return !(slots & AF_V);
302 }
303
304 /* alu instructions that can execute on any unit */
305 static int is_alu_any_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
306 {
307 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
308 return slots == AF_VS;
309 }
310
311 static int is_nop_inst(struct r600_bytecode_alu *alu)
312 {
313 return alu->op == ALU_OP0_NOP;
314 }
315
316 static int assign_alu_units(struct r600_bytecode *bc, struct r600_bytecode_alu *alu_first,
317 struct r600_bytecode_alu *assignment[5])
318 {
319 struct r600_bytecode_alu *alu;
320 unsigned i, chan, trans;
321 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
322
323 for (i = 0; i < max_slots; i++)
324 assignment[i] = NULL;
325
326 for (alu = alu_first; alu; alu = LIST_ENTRY(struct r600_bytecode_alu, alu->list.next, list)) {
327 chan = alu->dst.chan;
328 if (max_slots == 4)
329 trans = 0;
330 else if (is_alu_trans_unit_inst(bc, alu))
331 trans = 1;
332 else if (is_alu_vec_unit_inst(bc, alu))
333 trans = 0;
334 else if (assignment[chan])
335 trans = 1; /* Assume ALU_INST_PREFER_VECTOR. */
336 else
337 trans = 0;
338
339 if (trans) {
340 if (assignment[4]) {
341 assert(0); /* ALU.Trans has already been allocated. */
342 return -1;
343 }
344 assignment[4] = alu;
345 } else {
346 if (assignment[chan]) {
347 assert(0); /* ALU.chan has already been allocated. */
348 return -1;
349 }
350 assignment[chan] = alu;
351 }
352
353 if (alu->last)
354 break;
355 }
356 return 0;
357 }
358
359 struct alu_bank_swizzle {
360 int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
361 int hw_cfile_addr[4];
362 int hw_cfile_elem[4];
363 };
364
365 static const unsigned cycle_for_bank_swizzle_vec[][3] = {
366 [SQ_ALU_VEC_012] = { 0, 1, 2 },
367 [SQ_ALU_VEC_021] = { 0, 2, 1 },
368 [SQ_ALU_VEC_120] = { 1, 2, 0 },
369 [SQ_ALU_VEC_102] = { 1, 0, 2 },
370 [SQ_ALU_VEC_201] = { 2, 0, 1 },
371 [SQ_ALU_VEC_210] = { 2, 1, 0 }
372 };
373
374 static const unsigned cycle_for_bank_swizzle_scl[][3] = {
375 [SQ_ALU_SCL_210] = { 2, 1, 0 },
376 [SQ_ALU_SCL_122] = { 1, 2, 2 },
377 [SQ_ALU_SCL_212] = { 2, 1, 2 },
378 [SQ_ALU_SCL_221] = { 2, 2, 1 }
379 };
380
381 static void init_bank_swizzle(struct alu_bank_swizzle *bs)
382 {
383 int i, cycle, component;
384 /* set up gpr use */
385 for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
386 for (component = 0; component < NUM_OF_COMPONENTS; component++)
387 bs->hw_gpr[cycle][component] = -1;
388 for (i = 0; i < 4; i++)
389 bs->hw_cfile_addr[i] = -1;
390 for (i = 0; i < 4; i++)
391 bs->hw_cfile_elem[i] = -1;
392 }
393
394 static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan, unsigned cycle)
395 {
396 if (bs->hw_gpr[cycle][chan] == -1)
397 bs->hw_gpr[cycle][chan] = sel;
398 else if (bs->hw_gpr[cycle][chan] != (int)sel) {
399 /* Another scalar operation has already used the GPR read port for the channel. */
400 return -1;
401 }
402 return 0;
403 }
404
405 static int reserve_cfile(const struct r600_bytecode *bc,
406 struct alu_bank_swizzle *bs, unsigned sel, unsigned chan)
407 {
408 int res, num_res = 4;
409 if (bc->chip_class >= R700) {
410 num_res = 2;
411 chan /= 2;
412 }
413 for (res = 0; res < num_res; ++res) {
414 if (bs->hw_cfile_addr[res] == -1) {
415 bs->hw_cfile_addr[res] = sel;
416 bs->hw_cfile_elem[res] = chan;
417 return 0;
418 } else if (bs->hw_cfile_addr[res] == sel &&
419 bs->hw_cfile_elem[res] == chan)
420 return 0; /* Read for this scalar element already reserved, nothing to do here. */
421 }
422 /* All cfile read ports are used, cannot reference vector element. */
423 return -1;
424 }
425
426 static int is_gpr(unsigned sel)
427 {
428 return (sel <= 127);
429 }
430
431 /* CB constants start at 512, and get translated to a kcache index when ALU
432 * clauses are constructed. Note that we handle kcache constants the same way
433 * as (the now gone) cfile constants, is that really required? */
434 static int is_cfile(unsigned sel)
435 {
436 return (sel > 255 && sel < 512) ||
437 (sel > 511 && sel < 4607) || /* Kcache before translation. */
438 (sel > 127 && sel < 192); /* Kcache after translation. */
439 }
440
441 static int is_const(int sel)
442 {
443 return is_cfile(sel) ||
444 (sel >= V_SQ_ALU_SRC_0 &&
445 sel <= V_SQ_ALU_SRC_LITERAL);
446 }
447
448 static int check_vector(const struct r600_bytecode *bc, const struct r600_bytecode_alu *alu,
449 struct alu_bank_swizzle *bs, int bank_swizzle)
450 {
451 int r, src, num_src, sel, elem, cycle;
452
453 num_src = r600_bytecode_get_num_operands(alu);
454 for (src = 0; src < num_src; src++) {
455 sel = alu->src[src].sel;
456 elem = alu->src[src].chan;
457 if (is_gpr(sel)) {
458 cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src];
459 if (src == 1 && sel == alu->src[0].sel && elem == alu->src[0].chan)
460 /* Nothing to do; special-case optimization,
461 * second source uses first source’s reservation. */
462 continue;
463 else {
464 r = reserve_gpr(bs, sel, elem, cycle);
465 if (r)
466 return r;
467 }
468 } else if (is_cfile(sel)) {
469 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
470 if (r)
471 return r;
472 }
473 /* No restrictions on PV, PS, literal or special constants. */
474 }
475 return 0;
476 }
477
478 static int check_scalar(const struct r600_bytecode *bc, const struct r600_bytecode_alu *alu,
479 struct alu_bank_swizzle *bs, int bank_swizzle)
480 {
481 int r, src, num_src, const_count, sel, elem, cycle;
482
483 num_src = r600_bytecode_get_num_operands(alu);
484 for (const_count = 0, src = 0; src < num_src; ++src) {
485 sel = alu->src[src].sel;
486 elem = alu->src[src].chan;
487 if (is_const(sel)) { /* Any constant, including literal and inline constants. */
488 if (const_count >= 2)
489 /* More than two references to a constant in
490 * transcendental operation. */
491 return -1;
492 else
493 const_count++;
494 }
495 if (is_cfile(sel)) {
496 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
497 if (r)
498 return r;
499 }
500 }
501 for (src = 0; src < num_src; ++src) {
502 sel = alu->src[src].sel;
503 elem = alu->src[src].chan;
504 if (is_gpr(sel)) {
505 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
506 if (cycle < const_count)
507 /* Cycle for GPR load conflicts with
508 * constant load in transcendental operation. */
509 return -1;
510 r = reserve_gpr(bs, sel, elem, cycle);
511 if (r)
512 return r;
513 }
514 /* PV PS restrictions */
515 if (const_count && (sel == 254 || sel == 255)) {
516 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
517 if (cycle < const_count)
518 return -1;
519 }
520 }
521 return 0;
522 }
523
524 static int check_and_set_bank_swizzle(const struct r600_bytecode *bc,
525 struct r600_bytecode_alu *slots[5])
526 {
527 struct alu_bank_swizzle bs;
528 int bank_swizzle[5];
529 int i, r = 0, forced = 1;
530 boolean scalar_only = bc->chip_class == CAYMAN ? false : true;
531 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
532
533 for (i = 0; i < max_slots; i++) {
534 if (slots[i]) {
535 if (slots[i]->bank_swizzle_force) {
536 slots[i]->bank_swizzle = slots[i]->bank_swizzle_force;
537 } else {
538 forced = 0;
539 }
540 }
541
542 if (i < 4 && slots[i])
543 scalar_only = false;
544 }
545 if (forced)
546 return 0;
547
548 /* Just check every possible combination of bank swizzle.
549 * Not very efficent, but works on the first try in most of the cases. */
550 for (i = 0; i < 4; i++)
551 if (!slots[i] || !slots[i]->bank_swizzle_force)
552 bank_swizzle[i] = SQ_ALU_VEC_012;
553 else
554 bank_swizzle[i] = slots[i]->bank_swizzle;
555
556 bank_swizzle[4] = SQ_ALU_SCL_210;
557 while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
558
559 init_bank_swizzle(&bs);
560 if (scalar_only == false) {
561 for (i = 0; i < 4; i++) {
562 if (slots[i]) {
563 r = check_vector(bc, slots[i], &bs, bank_swizzle[i]);
564 if (r)
565 break;
566 }
567 }
568 } else
569 r = 0;
570
571 if (!r && max_slots == 5 && slots[4]) {
572 r = check_scalar(bc, slots[4], &bs, bank_swizzle[4]);
573 }
574 if (!r) {
575 for (i = 0; i < max_slots; i++) {
576 if (slots[i])
577 slots[i]->bank_swizzle = bank_swizzle[i];
578 }
579 return 0;
580 }
581
582 if (scalar_only) {
583 bank_swizzle[4]++;
584 } else {
585 for (i = 0; i < max_slots; i++) {
586 if (!slots[i] || !slots[i]->bank_swizzle_force) {
587 bank_swizzle[i]++;
588 if (bank_swizzle[i] <= SQ_ALU_VEC_210)
589 break;
590 else if (i < max_slots - 1)
591 bank_swizzle[i] = SQ_ALU_VEC_012;
592 else
593 return -1;
594 }
595 }
596 }
597 }
598
599 /* Couldn't find a working swizzle. */
600 return -1;
601 }
602
603 static int replace_gpr_with_pv_ps(struct r600_bytecode *bc,
604 struct r600_bytecode_alu *slots[5], struct r600_bytecode_alu *alu_prev)
605 {
606 struct r600_bytecode_alu *prev[5];
607 int gpr[5], chan[5];
608 int i, j, r, src, num_src;
609 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
610
611 r = assign_alu_units(bc, alu_prev, prev);
612 if (r)
613 return r;
614
615 for (i = 0; i < max_slots; ++i) {
616 if (prev[i] && alu_writes(prev[i]) && !prev[i]->dst.rel) {
617
618 if (is_alu_64bit_inst(prev[i])) {
619 gpr[i] = -1;
620 continue;
621 }
622
623 gpr[i] = prev[i]->dst.sel;
624 /* cube writes more than PV.X */
625 if (is_alu_reduction_inst(bc, prev[i]))
626 chan[i] = 0;
627 else
628 chan[i] = prev[i]->dst.chan;
629 } else
630 gpr[i] = -1;
631 }
632
633 for (i = 0; i < max_slots; ++i) {
634 struct r600_bytecode_alu *alu = slots[i];
635 if (!alu)
636 continue;
637
638 if (is_alu_64bit_inst(alu))
639 continue;
640 num_src = r600_bytecode_get_num_operands(alu);
641 for (src = 0; src < num_src; ++src) {
642 if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
643 continue;
644
645 if (bc->chip_class < CAYMAN) {
646 if (alu->src[src].sel == gpr[4] &&
647 alu->src[src].chan == chan[4] &&
648 alu_prev->pred_sel == alu->pred_sel) {
649 alu->src[src].sel = V_SQ_ALU_SRC_PS;
650 alu->src[src].chan = 0;
651 continue;
652 }
653 }
654
655 for (j = 0; j < 4; ++j) {
656 if (alu->src[src].sel == gpr[j] &&
657 alu->src[src].chan == j &&
658 alu_prev->pred_sel == alu->pred_sel) {
659 alu->src[src].sel = V_SQ_ALU_SRC_PV;
660 alu->src[src].chan = chan[j];
661 break;
662 }
663 }
664 }
665 }
666
667 return 0;
668 }
669
670 void r600_bytecode_special_constants(uint32_t value, unsigned *sel, unsigned *neg, unsigned abs)
671 {
672 switch(value) {
673 case 0:
674 *sel = V_SQ_ALU_SRC_0;
675 break;
676 case 1:
677 *sel = V_SQ_ALU_SRC_1_INT;
678 break;
679 case -1:
680 *sel = V_SQ_ALU_SRC_M_1_INT;
681 break;
682 case 0x3F800000: /* 1.0f */
683 *sel = V_SQ_ALU_SRC_1;
684 break;
685 case 0x3F000000: /* 0.5f */
686 *sel = V_SQ_ALU_SRC_0_5;
687 break;
688 case 0xBF800000: /* -1.0f */
689 *sel = V_SQ_ALU_SRC_1;
690 *neg ^= !abs;
691 break;
692 case 0xBF000000: /* -0.5f */
693 *sel = V_SQ_ALU_SRC_0_5;
694 *neg ^= !abs;
695 break;
696 default:
697 *sel = V_SQ_ALU_SRC_LITERAL;
698 break;
699 }
700 }
701
702 /* compute how many literal are needed */
703 static int r600_bytecode_alu_nliterals(struct r600_bytecode_alu *alu,
704 uint32_t literal[4], unsigned *nliteral)
705 {
706 unsigned num_src = r600_bytecode_get_num_operands(alu);
707 unsigned i, j;
708
709 for (i = 0; i < num_src; ++i) {
710 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
711 uint32_t value = alu->src[i].value;
712 unsigned found = 0;
713 for (j = 0; j < *nliteral; ++j) {
714 if (literal[j] == value) {
715 found = 1;
716 break;
717 }
718 }
719 if (!found) {
720 if (*nliteral >= 4)
721 return -EINVAL;
722 literal[(*nliteral)++] = value;
723 }
724 }
725 }
726 return 0;
727 }
728
729 static void r600_bytecode_alu_adjust_literals(struct r600_bytecode_alu *alu,
730 uint32_t literal[4], unsigned nliteral)
731 {
732 unsigned num_src = r600_bytecode_get_num_operands(alu);
733 unsigned i, j;
734
735 for (i = 0; i < num_src; ++i) {
736 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
737 uint32_t value = alu->src[i].value;
738 for (j = 0; j < nliteral; ++j) {
739 if (literal[j] == value) {
740 alu->src[i].chan = j;
741 break;
742 }
743 }
744 }
745 }
746 }
747
748 static int merge_inst_groups(struct r600_bytecode *bc, struct r600_bytecode_alu *slots[5],
749 struct r600_bytecode_alu *alu_prev)
750 {
751 struct r600_bytecode_alu *prev[5];
752 struct r600_bytecode_alu *result[5] = { NULL };
753
754 uint32_t literal[4], prev_literal[4];
755 unsigned nliteral = 0, prev_nliteral = 0;
756
757 int i, j, r, src, num_src;
758 int num_once_inst = 0;
759 int have_mova = 0, have_rel = 0;
760 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
761
762 r = assign_alu_units(bc, alu_prev, prev);
763 if (r)
764 return r;
765
766 for (i = 0; i < max_slots; ++i) {
767 if (prev[i]) {
768 if (prev[i]->pred_sel)
769 return 0;
770 if (is_alu_once_inst(prev[i]))
771 return 0;
772 }
773 if (slots[i]) {
774 if (slots[i]->pred_sel)
775 return 0;
776 if (is_alu_once_inst(slots[i]))
777 return 0;
778 }
779 }
780
781 for (i = 0; i < max_slots; ++i) {
782 struct r600_bytecode_alu *alu;
783
784 if (num_once_inst > 0)
785 return 0;
786
787 /* check number of literals */
788 if (prev[i]) {
789 if (r600_bytecode_alu_nliterals(prev[i], literal, &nliteral))
790 return 0;
791 if (r600_bytecode_alu_nliterals(prev[i], prev_literal, &prev_nliteral))
792 return 0;
793 if (is_alu_mova_inst(prev[i])) {
794 if (have_rel)
795 return 0;
796 have_mova = 1;
797 }
798
799 if (alu_uses_rel(prev[i])) {
800 if (have_mova) {
801 return 0;
802 }
803 have_rel = 1;
804 }
805 if (alu_uses_lds(prev[i]))
806 return 0;
807
808 num_once_inst += is_alu_once_inst(prev[i]);
809 }
810 if (slots[i] && r600_bytecode_alu_nliterals(slots[i], literal, &nliteral))
811 return 0;
812
813 /* Let's check used slots. */
814 if (prev[i] && !slots[i]) {
815 result[i] = prev[i];
816 continue;
817 } else if (prev[i] && slots[i]) {
818 if (max_slots == 5 && result[4] == NULL && prev[4] == NULL && slots[4] == NULL) {
819 /* Trans unit is still free try to use it. */
820 if (is_alu_any_unit_inst(bc, slots[i]) && !alu_uses_lds(slots[i])) {
821 result[i] = prev[i];
822 result[4] = slots[i];
823 } else if (is_alu_any_unit_inst(bc, prev[i])) {
824 if (slots[i]->dst.sel == prev[i]->dst.sel &&
825 alu_writes(slots[i]) &&
826 alu_writes(prev[i]))
827 return 0;
828
829 result[i] = slots[i];
830 result[4] = prev[i];
831 } else
832 return 0;
833 } else
834 return 0;
835 } else if(!slots[i]) {
836 continue;
837 } else {
838 if (max_slots == 5 && slots[i] && prev[4] &&
839 slots[i]->dst.sel == prev[4]->dst.sel &&
840 slots[i]->dst.chan == prev[4]->dst.chan &&
841 alu_writes(slots[i]) &&
842 alu_writes(prev[4]))
843 return 0;
844
845 result[i] = slots[i];
846 }
847
848 alu = slots[i];
849 num_once_inst += is_alu_once_inst(alu);
850
851 /* don't reschedule NOPs */
852 if (is_nop_inst(alu))
853 return 0;
854
855 if (is_alu_mova_inst(alu)) {
856 if (have_rel) {
857 return 0;
858 }
859 have_mova = 1;
860 }
861
862 if (alu_uses_rel(alu)) {
863 if (have_mova) {
864 return 0;
865 }
866 have_rel = 1;
867 }
868
869 if (alu->op == ALU_OP0_SET_CF_IDX0 ||
870 alu->op == ALU_OP0_SET_CF_IDX1)
871 return 0; /* data hazard with MOVA */
872
873 /* Let's check source gprs */
874 num_src = r600_bytecode_get_num_operands(alu);
875 for (src = 0; src < num_src; ++src) {
876
877 /* Constants don't matter. */
878 if (!is_gpr(alu->src[src].sel))
879 continue;
880
881 for (j = 0; j < max_slots; ++j) {
882 if (!prev[j] || !alu_writes(prev[j]))
883 continue;
884
885 /* If it's relative then we can't determin which gpr is really used. */
886 if (prev[j]->dst.chan == alu->src[src].chan &&
887 (prev[j]->dst.sel == alu->src[src].sel ||
888 prev[j]->dst.rel || alu->src[src].rel))
889 return 0;
890 }
891 }
892 }
893
894 /* more than one PRED_ or KILL_ ? */
895 if (num_once_inst > 1)
896 return 0;
897
898 /* check if the result can still be swizzlet */
899 r = check_and_set_bank_swizzle(bc, result);
900 if (r)
901 return 0;
902
903 /* looks like everything worked out right, apply the changes */
904
905 /* undo adding previus literals */
906 bc->cf_last->ndw -= align(prev_nliteral, 2);
907
908 /* sort instructions */
909 for (i = 0; i < max_slots; ++i) {
910 slots[i] = result[i];
911 if (result[i]) {
912 LIST_DEL(&result[i]->list);
913 result[i]->last = 0;
914 LIST_ADDTAIL(&result[i]->list, &bc->cf_last->alu);
915 }
916 }
917
918 /* determine new last instruction */
919 LIST_ENTRY(struct r600_bytecode_alu, bc->cf_last->alu.prev, list)->last = 1;
920
921 /* determine new first instruction */
922 for (i = 0; i < max_slots; ++i) {
923 if (result[i]) {
924 bc->cf_last->curr_bs_head = result[i];
925 break;
926 }
927 }
928
929 bc->cf_last->prev_bs_head = bc->cf_last->prev2_bs_head;
930 bc->cf_last->prev2_bs_head = NULL;
931
932 return 0;
933 }
934
935 /* we'll keep kcache sets sorted by bank & addr */
936 static int r600_bytecode_alloc_kcache_line(struct r600_bytecode *bc,
937 struct r600_bytecode_kcache *kcache,
938 unsigned bank, unsigned line, unsigned index_mode)
939 {
940 int i, kcache_banks = bc->chip_class >= EVERGREEN ? 4 : 2;
941
942 for (i = 0; i < kcache_banks; i++) {
943 if (kcache[i].mode) {
944 int d;
945
946 if (kcache[i].bank < bank)
947 continue;
948
949 if ((kcache[i].bank == bank && kcache[i].addr > line+1) ||
950 kcache[i].bank > bank) {
951 /* try to insert new line */
952 if (kcache[kcache_banks-1].mode) {
953 /* all sets are in use */
954 return -ENOMEM;
955 }
956
957 memmove(&kcache[i+1],&kcache[i], (kcache_banks-i-1)*sizeof(struct r600_bytecode_kcache));
958 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
959 kcache[i].bank = bank;
960 kcache[i].addr = line;
961 kcache[i].index_mode = index_mode;
962 return 0;
963 }
964
965 d = line - kcache[i].addr;
966
967 if (d == -1) {
968 kcache[i].addr--;
969 if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_2) {
970 /* we are prepending the line to the current set,
971 * discarding the existing second line,
972 * so we'll have to insert line+2 after it */
973 line += 2;
974 continue;
975 } else if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_1) {
976 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
977 return 0;
978 } else {
979 /* V_SQ_CF_KCACHE_LOCK_LOOP_INDEX is not supported */
980 return -ENOMEM;
981 }
982 } else if (d == 1) {
983 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
984 return 0;
985 } else if (d == 0)
986 return 0;
987 } else { /* free kcache set - use it */
988 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
989 kcache[i].bank = bank;
990 kcache[i].addr = line;
991 kcache[i].index_mode = index_mode;
992 return 0;
993 }
994 }
995 return -ENOMEM;
996 }
997
998 static int r600_bytecode_alloc_inst_kcache_lines(struct r600_bytecode *bc,
999 struct r600_bytecode_kcache *kcache,
1000 struct r600_bytecode_alu *alu)
1001 {
1002 int i, r;
1003
1004 for (i = 0; i < 3; i++) {
1005 unsigned bank, line, sel = alu->src[i].sel, index_mode;
1006
1007 if (sel < 512)
1008 continue;
1009
1010 bank = alu->src[i].kc_bank;
1011 assert(bank < R600_MAX_HW_CONST_BUFFERS);
1012 line = (sel-512)>>4;
1013 index_mode = alu->src[i].kc_rel ? 1 : 0; // V_SQ_CF_INDEX_0 / V_SQ_CF_INDEX_NONE
1014
1015 if ((r = r600_bytecode_alloc_kcache_line(bc, kcache, bank, line, index_mode)))
1016 return r;
1017 }
1018 return 0;
1019 }
1020
1021 static int r600_bytecode_assign_kcache_banks(
1022 struct r600_bytecode_alu *alu,
1023 struct r600_bytecode_kcache * kcache)
1024 {
1025 int i, j;
1026
1027 /* Alter the src operands to refer to the kcache. */
1028 for (i = 0; i < 3; ++i) {
1029 static const unsigned int base[] = {128, 160, 256, 288};
1030 unsigned int line, sel = alu->src[i].sel, found = 0;
1031
1032 if (sel < 512)
1033 continue;
1034
1035 sel -= 512;
1036 line = sel>>4;
1037
1038 for (j = 0; j < 4 && !found; ++j) {
1039 switch (kcache[j].mode) {
1040 case V_SQ_CF_KCACHE_NOP:
1041 case V_SQ_CF_KCACHE_LOCK_LOOP_INDEX:
1042 R600_ERR("unexpected kcache line mode\n");
1043 return -ENOMEM;
1044 default:
1045 if (kcache[j].bank == alu->src[i].kc_bank &&
1046 kcache[j].addr <= line &&
1047 line < kcache[j].addr + kcache[j].mode) {
1048 alu->src[i].sel = sel - (kcache[j].addr<<4);
1049 alu->src[i].sel += base[j];
1050 found=1;
1051 }
1052 }
1053 }
1054 }
1055 return 0;
1056 }
1057
1058 static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode *bc,
1059 struct r600_bytecode_alu *alu,
1060 unsigned type)
1061 {
1062 struct r600_bytecode_kcache kcache_sets[4];
1063 struct r600_bytecode_kcache *kcache = kcache_sets;
1064 int r;
1065
1066 memcpy(kcache, bc->cf_last->kcache, 4 * sizeof(struct r600_bytecode_kcache));
1067
1068 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1069 /* can't alloc, need to start new clause */
1070 if ((r = r600_bytecode_add_cf(bc))) {
1071 return r;
1072 }
1073 bc->cf_last->op = type;
1074
1075 /* retry with the new clause */
1076 kcache = bc->cf_last->kcache;
1077 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1078 /* can't alloc again- should never happen */
1079 return r;
1080 }
1081 } else {
1082 /* update kcache sets */
1083 memcpy(bc->cf_last->kcache, kcache, 4 * sizeof(struct r600_bytecode_kcache));
1084 }
1085
1086 /* if we actually used more than 2 kcache sets, or have relative indexing - use ALU_EXTENDED on eg+ */
1087 if (kcache[2].mode != V_SQ_CF_KCACHE_NOP ||
1088 kcache[0].index_mode || kcache[1].index_mode || kcache[2].index_mode || kcache[3].index_mode) {
1089 if (bc->chip_class < EVERGREEN)
1090 return -ENOMEM;
1091 bc->cf_last->eg_alu_extended = 1;
1092 }
1093
1094 return 0;
1095 }
1096
1097 static int insert_nop_r6xx(struct r600_bytecode *bc)
1098 {
1099 struct r600_bytecode_alu alu;
1100 int r, i;
1101
1102 for (i = 0; i < 4; i++) {
1103 memset(&alu, 0, sizeof(alu));
1104 alu.op = ALU_OP0_NOP;
1105 alu.src[0].chan = i;
1106 alu.dst.chan = i;
1107 alu.last = (i == 3);
1108 r = r600_bytecode_add_alu(bc, &alu);
1109 if (r)
1110 return r;
1111 }
1112 return 0;
1113 }
1114
1115 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1116 static int load_ar_r6xx(struct r600_bytecode *bc)
1117 {
1118 struct r600_bytecode_alu alu;
1119 int r;
1120
1121 if (bc->ar_loaded)
1122 return 0;
1123
1124 /* hack to avoid making MOVA the last instruction in the clause */
1125 if ((bc->cf_last->ndw>>1) >= 110)
1126 bc->force_add_cf = 1;
1127
1128 memset(&alu, 0, sizeof(alu));
1129 alu.op = ALU_OP1_MOVA_GPR_INT;
1130 alu.src[0].sel = bc->ar_reg;
1131 alu.src[0].chan = bc->ar_chan;
1132 alu.last = 1;
1133 alu.index_mode = INDEX_MODE_LOOP;
1134 r = r600_bytecode_add_alu(bc, &alu);
1135 if (r)
1136 return r;
1137
1138 /* no requirement to set uses waterfall on MOVA_GPR_INT */
1139 bc->ar_loaded = 1;
1140 return 0;
1141 }
1142
1143 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1144 static int load_ar(struct r600_bytecode *bc)
1145 {
1146 struct r600_bytecode_alu alu;
1147 int r;
1148
1149 if (bc->ar_handling)
1150 return load_ar_r6xx(bc);
1151
1152 if (bc->ar_loaded)
1153 return 0;
1154
1155 /* hack to avoid making MOVA the last instruction in the clause */
1156 if ((bc->cf_last->ndw>>1) >= 110)
1157 bc->force_add_cf = 1;
1158
1159 memset(&alu, 0, sizeof(alu));
1160 alu.op = ALU_OP1_MOVA_INT;
1161 alu.src[0].sel = bc->ar_reg;
1162 alu.src[0].chan = bc->ar_chan;
1163 alu.last = 1;
1164 r = r600_bytecode_add_alu(bc, &alu);
1165 if (r)
1166 return r;
1167
1168 bc->cf_last->r6xx_uses_waterfall = 1;
1169 bc->ar_loaded = 1;
1170 return 0;
1171 }
1172
1173 int r600_bytecode_add_alu_type(struct r600_bytecode *bc,
1174 const struct r600_bytecode_alu *alu, unsigned type)
1175 {
1176 struct r600_bytecode_alu *nalu = r600_bytecode_alu();
1177 struct r600_bytecode_alu *lalu;
1178 int i, r;
1179
1180 if (!nalu)
1181 return -ENOMEM;
1182 memcpy(nalu, alu, sizeof(struct r600_bytecode_alu));
1183
1184 if (alu->is_op3) {
1185 /* will fail later since alu does not support it. */
1186 assert(!alu->src[0].abs && !alu->src[1].abs && !alu->src[2].abs);
1187 }
1188
1189 if (bc->cf_last != NULL && bc->cf_last->op != type) {
1190 /* check if we could add it anyway */
1191 if (bc->cf_last->op == CF_OP_ALU &&
1192 type == CF_OP_ALU_PUSH_BEFORE) {
1193 LIST_FOR_EACH_ENTRY(lalu, &bc->cf_last->alu, list) {
1194 if (lalu->execute_mask) {
1195 bc->force_add_cf = 1;
1196 break;
1197 }
1198 }
1199 } else
1200 bc->force_add_cf = 1;
1201 }
1202
1203 /* cf can contains only alu or only vtx or only tex */
1204 if (bc->cf_last == NULL || bc->force_add_cf) {
1205 r = r600_bytecode_add_cf(bc);
1206 if (r) {
1207 free(nalu);
1208 return r;
1209 }
1210 }
1211 bc->cf_last->op = type;
1212
1213 /* Load index register if required */
1214 if (bc->chip_class >= EVERGREEN) {
1215 for (i = 0; i < 3; i++)
1216 if (nalu->src[i].kc_bank && nalu->src[i].kc_rel)
1217 egcm_load_index_reg(bc, 0, true);
1218 }
1219
1220 /* Check AR usage and load it if required */
1221 for (i = 0; i < 3; i++)
1222 if (nalu->src[i].rel && !bc->ar_loaded)
1223 load_ar(bc);
1224
1225 if (nalu->dst.rel && !bc->ar_loaded)
1226 load_ar(bc);
1227
1228 /* Setup the kcache for this ALU instruction. This will start a new
1229 * ALU clause if needed. */
1230 if ((r = r600_bytecode_alloc_kcache_lines(bc, nalu, type))) {
1231 free(nalu);
1232 return r;
1233 }
1234
1235 if (!bc->cf_last->curr_bs_head) {
1236 bc->cf_last->curr_bs_head = nalu;
1237 }
1238 /* number of gpr == the last gpr used in any alu */
1239 for (i = 0; i < 3; i++) {
1240 if (nalu->src[i].sel >= bc->ngpr && nalu->src[i].sel < 128) {
1241 bc->ngpr = nalu->src[i].sel + 1;
1242 }
1243 if (nalu->src[i].sel == V_SQ_ALU_SRC_LITERAL)
1244 r600_bytecode_special_constants(nalu->src[i].value,
1245 &nalu->src[i].sel, &nalu->src[i].neg, nalu->src[i].abs);
1246 }
1247 if (nalu->dst.sel >= bc->ngpr) {
1248 bc->ngpr = nalu->dst.sel + 1;
1249 }
1250 LIST_ADDTAIL(&nalu->list, &bc->cf_last->alu);
1251 /* each alu use 2 dwords */
1252 bc->cf_last->ndw += 2;
1253 bc->ndw += 2;
1254
1255 /* process cur ALU instructions for bank swizzle */
1256 if (nalu->last) {
1257 uint32_t literal[4];
1258 unsigned nliteral;
1259 struct r600_bytecode_alu *slots[5];
1260 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
1261 r = assign_alu_units(bc, bc->cf_last->curr_bs_head, slots);
1262 if (r)
1263 return r;
1264
1265 if (bc->cf_last->prev_bs_head) {
1266 r = merge_inst_groups(bc, slots, bc->cf_last->prev_bs_head);
1267 if (r)
1268 return r;
1269 }
1270
1271 if (bc->cf_last->prev_bs_head) {
1272 r = replace_gpr_with_pv_ps(bc, slots, bc->cf_last->prev_bs_head);
1273 if (r)
1274 return r;
1275 }
1276
1277 r = check_and_set_bank_swizzle(bc, slots);
1278 if (r)
1279 return r;
1280
1281 for (i = 0, nliteral = 0; i < max_slots; i++) {
1282 if (slots[i]) {
1283 r = r600_bytecode_alu_nliterals(slots[i], literal, &nliteral);
1284 if (r)
1285 return r;
1286 }
1287 }
1288 bc->cf_last->ndw += align(nliteral, 2);
1289
1290 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1291 * worst case */
1292 if ((bc->cf_last->ndw >> 1) >= 120) {
1293 bc->force_add_cf = 1;
1294 }
1295
1296 bc->cf_last->prev2_bs_head = bc->cf_last->prev_bs_head;
1297 bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head;
1298 bc->cf_last->curr_bs_head = NULL;
1299 }
1300
1301 if (nalu->dst.rel && bc->r6xx_nop_after_rel_dst)
1302 insert_nop_r6xx(bc);
1303
1304 return 0;
1305 }
1306
1307 int r600_bytecode_add_alu(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu)
1308 {
1309 return r600_bytecode_add_alu_type(bc, alu, CF_OP_ALU);
1310 }
1311
1312 static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode *bc)
1313 {
1314 switch (bc->chip_class) {
1315 case R600:
1316 return 8;
1317
1318 case R700:
1319 case EVERGREEN:
1320 case CAYMAN:
1321 return 16;
1322
1323 default:
1324 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1325 return 8;
1326 }
1327 }
1328
1329 static inline boolean last_inst_was_not_vtx_fetch(struct r600_bytecode *bc)
1330 {
1331 return !((r600_isa_cf(bc->cf_last->op)->flags & CF_FETCH) &&
1332 bc->cf_last->op != CF_OP_GDS &&
1333 (bc->chip_class == CAYMAN ||
1334 bc->cf_last->op != CF_OP_TEX));
1335 }
1336
1337 static int r600_bytecode_add_vtx_internal(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx,
1338 bool use_tc)
1339 {
1340 struct r600_bytecode_vtx *nvtx = r600_bytecode_vtx();
1341 int r;
1342
1343 if (!nvtx)
1344 return -ENOMEM;
1345 memcpy(nvtx, vtx, sizeof(struct r600_bytecode_vtx));
1346
1347 /* Load index register if required */
1348 if (bc->chip_class >= EVERGREEN) {
1349 if (vtx->buffer_index_mode)
1350 egcm_load_index_reg(bc, vtx->buffer_index_mode - 1, false);
1351 }
1352
1353 /* cf can contains only alu or only vtx or only tex */
1354 if (bc->cf_last == NULL ||
1355 last_inst_was_not_vtx_fetch(bc) ||
1356 bc->force_add_cf) {
1357 r = r600_bytecode_add_cf(bc);
1358 if (r) {
1359 free(nvtx);
1360 return r;
1361 }
1362 switch (bc->chip_class) {
1363 case R600:
1364 case R700:
1365 bc->cf_last->op = CF_OP_VTX;
1366 break;
1367 case EVERGREEN:
1368 if (use_tc)
1369 bc->cf_last->op = CF_OP_TEX;
1370 else
1371 bc->cf_last->op = CF_OP_VTX;
1372 break;
1373 case CAYMAN:
1374 bc->cf_last->op = CF_OP_TEX;
1375 break;
1376 default:
1377 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1378 free(nvtx);
1379 return -EINVAL;
1380 }
1381 }
1382 LIST_ADDTAIL(&nvtx->list, &bc->cf_last->vtx);
1383 /* each fetch use 4 dwords */
1384 bc->cf_last->ndw += 4;
1385 bc->ndw += 4;
1386 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1387 bc->force_add_cf = 1;
1388
1389 bc->ngpr = MAX2(bc->ngpr, vtx->src_gpr + 1);
1390 bc->ngpr = MAX2(bc->ngpr, vtx->dst_gpr + 1);
1391
1392 return 0;
1393 }
1394
1395 int r600_bytecode_add_vtx(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx)
1396 {
1397 return r600_bytecode_add_vtx_internal(bc, vtx, false);
1398 }
1399
1400 int r600_bytecode_add_vtx_tc(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx)
1401 {
1402 return r600_bytecode_add_vtx_internal(bc, vtx, true);
1403 }
1404
1405 int r600_bytecode_add_tex(struct r600_bytecode *bc, const struct r600_bytecode_tex *tex)
1406 {
1407 struct r600_bytecode_tex *ntex = r600_bytecode_tex();
1408 int r;
1409
1410 if (!ntex)
1411 return -ENOMEM;
1412 memcpy(ntex, tex, sizeof(struct r600_bytecode_tex));
1413
1414 /* Load index register if required */
1415 if (bc->chip_class >= EVERGREEN) {
1416 if (tex->sampler_index_mode || tex->resource_index_mode)
1417 egcm_load_index_reg(bc, 1, false);
1418 }
1419
1420 /* we can't fetch data und use it as texture lookup address in the same TEX clause */
1421 if (bc->cf_last != NULL &&
1422 bc->cf_last->op == CF_OP_TEX) {
1423 struct r600_bytecode_tex *ttex;
1424 LIST_FOR_EACH_ENTRY(ttex, &bc->cf_last->tex, list) {
1425 if (ttex->dst_gpr == ntex->src_gpr) {
1426 bc->force_add_cf = 1;
1427 break;
1428 }
1429 }
1430 /* slight hack to make gradients always go into same cf */
1431 if (ntex->op == FETCH_OP_SET_GRADIENTS_H)
1432 bc->force_add_cf = 1;
1433 }
1434
1435 /* cf can contains only alu or only vtx or only tex */
1436 if (bc->cf_last == NULL ||
1437 bc->cf_last->op != CF_OP_TEX ||
1438 bc->force_add_cf) {
1439 r = r600_bytecode_add_cf(bc);
1440 if (r) {
1441 free(ntex);
1442 return r;
1443 }
1444 bc->cf_last->op = CF_OP_TEX;
1445 }
1446 if (ntex->src_gpr >= bc->ngpr) {
1447 bc->ngpr = ntex->src_gpr + 1;
1448 }
1449 if (ntex->dst_gpr >= bc->ngpr) {
1450 bc->ngpr = ntex->dst_gpr + 1;
1451 }
1452 LIST_ADDTAIL(&ntex->list, &bc->cf_last->tex);
1453 /* each texture fetch use 4 dwords */
1454 bc->cf_last->ndw += 4;
1455 bc->ndw += 4;
1456 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1457 bc->force_add_cf = 1;
1458 return 0;
1459 }
1460
1461 int r600_bytecode_add_gds(struct r600_bytecode *bc, const struct r600_bytecode_gds *gds)
1462 {
1463 struct r600_bytecode_gds *ngds = r600_bytecode_gds();
1464 int r;
1465
1466 if (ngds == NULL)
1467 return -ENOMEM;
1468 memcpy(ngds, gds, sizeof(struct r600_bytecode_gds));
1469
1470 if (bc->chip_class >= EVERGREEN) {
1471 if (gds->uav_index_mode)
1472 egcm_load_index_reg(bc, gds->uav_index_mode - 1, false);
1473 }
1474
1475 if (bc->cf_last == NULL ||
1476 bc->cf_last->op != CF_OP_GDS ||
1477 bc->force_add_cf) {
1478 r = r600_bytecode_add_cf(bc);
1479 if (r) {
1480 free(ngds);
1481 return r;
1482 }
1483 bc->cf_last->op = CF_OP_GDS;
1484 }
1485
1486 LIST_ADDTAIL(&ngds->list, &bc->cf_last->gds);
1487 bc->cf_last->ndw += 4; /* each GDS uses 4 dwords */
1488 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1489 bc->force_add_cf = 1;
1490 return 0;
1491 }
1492
1493 int r600_bytecode_add_cfinst(struct r600_bytecode *bc, unsigned op)
1494 {
1495 int r;
1496 r = r600_bytecode_add_cf(bc);
1497 if (r)
1498 return r;
1499
1500 bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
1501 bc->cf_last->op = op;
1502 return 0;
1503 }
1504
1505 int cm_bytecode_add_cf_end(struct r600_bytecode *bc)
1506 {
1507 return r600_bytecode_add_cfinst(bc, CF_OP_CF_END);
1508 }
1509
1510 /* common to all 3 families */
1511 static int r600_bytecode_vtx_build(struct r600_bytecode *bc, struct r600_bytecode_vtx *vtx, unsigned id)
1512 {
1513 if (r600_isa_fetch(vtx->op)->flags & FF_MEM)
1514 return r700_bytecode_fetch_mem_build(bc, vtx, id);
1515 bc->bytecode[id] = S_SQ_VTX_WORD0_VTX_INST(r600_isa_fetch_opcode(bc->isa->hw_class, vtx->op)) |
1516 S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) |
1517 S_SQ_VTX_WORD0_FETCH_TYPE(vtx->fetch_type) |
1518 S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
1519 S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x);
1520 if (bc->chip_class < CAYMAN)
1521 bc->bytecode[id] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
1522 id++;
1523 bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
1524 S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
1525 S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
1526 S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
1527 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) |
1528 S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) |
1529 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) |
1530 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) |
1531 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
1532 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
1533 bc->bytecode[id] = S_SQ_VTX_WORD2_OFFSET(vtx->offset)|
1534 S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx->endian);
1535 if (bc->chip_class >= EVERGREEN)
1536 bc->bytecode[id] |= ((vtx->buffer_index_mode & 0x3) << 21); // S_SQ_VTX_WORD2_BIM(vtx->buffer_index_mode);
1537 if (bc->chip_class < CAYMAN)
1538 bc->bytecode[id] |= S_SQ_VTX_WORD2_MEGA_FETCH(1);
1539 id++;
1540 bc->bytecode[id++] = 0;
1541 return 0;
1542 }
1543
1544 /* common to all 3 families */
1545 static int r600_bytecode_tex_build(struct r600_bytecode *bc, struct r600_bytecode_tex *tex, unsigned id)
1546 {
1547 bc->bytecode[id] = S_SQ_TEX_WORD0_TEX_INST(
1548 r600_isa_fetch_opcode(bc->isa->hw_class, tex->op)) |
1549 EG_S_SQ_TEX_WORD0_INST_MOD(tex->inst_mod) |
1550 S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
1551 S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
1552 S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
1553 if (bc->chip_class >= EVERGREEN)
1554 bc->bytecode[id] |= ((tex->sampler_index_mode & 0x3) << 27) | // S_SQ_TEX_WORD0_SIM(tex->sampler_index_mode);
1555 ((tex->resource_index_mode & 0x3) << 25); // S_SQ_TEX_WORD0_RIM(tex->resource_index_mode)
1556 id++;
1557 bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
1558 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
1559 S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
1560 S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
1561 S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
1562 S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
1563 S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
1564 S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
1565 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
1566 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
1567 S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
1568 bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
1569 S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
1570 S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
1571 S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
1572 S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
1573 S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
1574 S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
1575 S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
1576 bc->bytecode[id++] = 0;
1577 return 0;
1578 }
1579
1580 /* r600 only, r700/eg bits in r700_asm.c */
1581 static int r600_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id)
1582 {
1583 unsigned opcode = r600_isa_alu_opcode(bc->isa->hw_class, alu->op);
1584
1585 /* don't replace gpr by pv or ps for destination register */
1586 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
1587 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
1588 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
1589 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
1590 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
1591 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
1592 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
1593 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
1594 S_SQ_ALU_WORD0_INDEX_MODE(alu->index_mode) |
1595 S_SQ_ALU_WORD0_PRED_SEL(alu->pred_sel) |
1596 S_SQ_ALU_WORD0_LAST(alu->last);
1597
1598 if (alu->is_op3) {
1599 assert(!alu->src[0].abs && !alu->src[1].abs && !alu->src[2].abs);
1600 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1601 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1602 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1603 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1604 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
1605 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
1606 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
1607 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
1608 S_SQ_ALU_WORD1_OP3_ALU_INST(opcode) |
1609 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
1610 } else {
1611 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1612 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1613 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1614 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1615 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
1616 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
1617 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
1618 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
1619 S_SQ_ALU_WORD1_OP2_ALU_INST(opcode) |
1620 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
1621 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->execute_mask) |
1622 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->update_pred);
1623 }
1624 return 0;
1625 }
1626
1627 static void r600_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_cf *cf)
1628 {
1629 *bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
1630 *bytecode++ = S_SQ_CF_WORD1_CF_INST(r600_isa_cf_opcode(ISA_CC_R600, cf->op)) |
1631 S_SQ_CF_WORD1_BARRIER(1) |
1632 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1)|
1633 S_SQ_CF_WORD1_END_OF_PROGRAM(cf->end_of_program);
1634 }
1635
1636 /* common for r600/r700 - eg in eg_asm.c */
1637 static int r600_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf)
1638 {
1639 unsigned id = cf->id;
1640 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
1641 unsigned opcode = r600_isa_cf_opcode(bc->isa->hw_class, cf->op);
1642
1643
1644 if (cf->op == CF_NATIVE) {
1645 bc->bytecode[id++] = cf->isa[0];
1646 bc->bytecode[id++] = cf->isa[1];
1647 } else if (cfop->flags & CF_ALU) {
1648 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
1649 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
1650 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
1651 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank);
1652
1653 bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(opcode) |
1654 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) |
1655 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
1656 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
1657 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1658 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chip_class == R600 ? cf->r6xx_uses_waterfall : 0) |
1659 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
1660 } else if (cfop->flags & CF_FETCH) {
1661 if (bc->chip_class == R700)
1662 r700_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1663 else
1664 r600_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1665 } else if (cfop->flags & CF_EXP) {
1666 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1667 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1668 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1669 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type) |
1670 S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(cf->output.index_gpr);
1671 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1672 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
1673 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
1674 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
1675 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
1676 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->barrier) |
1677 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) |
1678 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->end_of_program);
1679 } else if (cfop->flags & CF_MEM) {
1680 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1681 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1682 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1683 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type) |
1684 S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(cf->output.index_gpr);
1685 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1686 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->barrier) |
1687 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) |
1688 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->end_of_program) |
1689 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf->output.array_size) |
1690 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf->output.comp_mask);
1691 } else {
1692 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
1693 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(opcode) |
1694 S_SQ_CF_WORD1_BARRIER(1) |
1695 S_SQ_CF_WORD1_COND(cf->cond) |
1696 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count) |
1697 S_SQ_CF_WORD1_END_OF_PROGRAM(cf->end_of_program);
1698 }
1699 return 0;
1700 }
1701
1702 int r600_bytecode_build(struct r600_bytecode *bc)
1703 {
1704 struct r600_bytecode_cf *cf;
1705 struct r600_bytecode_alu *alu;
1706 struct r600_bytecode_vtx *vtx;
1707 struct r600_bytecode_tex *tex;
1708 struct r600_bytecode_gds *gds;
1709 uint32_t literal[4];
1710 unsigned nliteral;
1711 unsigned addr;
1712 int i, r;
1713
1714 if (!bc->nstack) { // If not 0, Stack_size already provided by llvm
1715 if (bc->stack.max_entries)
1716 bc->nstack = bc->stack.max_entries;
1717 else if (bc->type == PIPE_SHADER_VERTEX ||
1718 bc->type == PIPE_SHADER_TESS_EVAL ||
1719 bc->type == PIPE_SHADER_TESS_CTRL)
1720 bc->nstack = 1;
1721 }
1722
1723 /* first path compute addr of each CF block */
1724 /* addr start after all the CF instructions */
1725 addr = bc->cf_last->id + 2;
1726 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1727 if (r600_isa_cf(cf->op)->flags & CF_FETCH) {
1728 addr += 3;
1729 addr &= 0xFFFFFFFCUL;
1730 }
1731 cf->addr = addr;
1732 addr += cf->ndw;
1733 bc->ndw = cf->addr + cf->ndw;
1734 }
1735 free(bc->bytecode);
1736 bc->bytecode = calloc(4, bc->ndw);
1737 if (bc->bytecode == NULL)
1738 return -ENOMEM;
1739 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1740 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
1741 addr = cf->addr;
1742 if (bc->chip_class >= EVERGREEN)
1743 r = eg_bytecode_cf_build(bc, cf);
1744 else
1745 r = r600_bytecode_cf_build(bc, cf);
1746 if (r)
1747 return r;
1748 if (cfop->flags & CF_ALU) {
1749 nliteral = 0;
1750 memset(literal, 0, sizeof(literal));
1751 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1752 r = r600_bytecode_alu_nliterals(alu, literal, &nliteral);
1753 if (r)
1754 return r;
1755 r600_bytecode_alu_adjust_literals(alu, literal, nliteral);
1756 r600_bytecode_assign_kcache_banks(alu, cf->kcache);
1757
1758 switch(bc->chip_class) {
1759 case R600:
1760 r = r600_bytecode_alu_build(bc, alu, addr);
1761 break;
1762 case R700:
1763 r = r700_bytecode_alu_build(bc, alu, addr);
1764 break;
1765 case EVERGREEN:
1766 case CAYMAN:
1767 r = eg_bytecode_alu_build(bc, alu, addr);
1768 break;
1769 default:
1770 R600_ERR("unknown chip class %d.\n", bc->chip_class);
1771 return -EINVAL;
1772 }
1773 if (r)
1774 return r;
1775 addr += 2;
1776 if (alu->last) {
1777 for (i = 0; i < align(nliteral, 2); ++i) {
1778 bc->bytecode[addr++] = literal[i];
1779 }
1780 nliteral = 0;
1781 memset(literal, 0, sizeof(literal));
1782 }
1783 }
1784 } else if (cf->op == CF_OP_VTX) {
1785 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1786 r = r600_bytecode_vtx_build(bc, vtx, addr);
1787 if (r)
1788 return r;
1789 addr += 4;
1790 }
1791 } else if (cf->op == CF_OP_GDS) {
1792 assert(bc->chip_class >= EVERGREEN);
1793 LIST_FOR_EACH_ENTRY(gds, &cf->gds, list) {
1794 r = eg_bytecode_gds_build(bc, gds, addr);
1795 if (r)
1796 return r;
1797 addr += 4;
1798 }
1799 } else if (cf->op == CF_OP_TEX) {
1800 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1801 assert(bc->chip_class >= EVERGREEN);
1802 r = r600_bytecode_vtx_build(bc, vtx, addr);
1803 if (r)
1804 return r;
1805 addr += 4;
1806 }
1807 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
1808 r = r600_bytecode_tex_build(bc, tex, addr);
1809 if (r)
1810 return r;
1811 addr += 4;
1812 }
1813 }
1814 }
1815 return 0;
1816 }
1817
1818 void r600_bytecode_clear(struct r600_bytecode *bc)
1819 {
1820 struct r600_bytecode_cf *cf = NULL, *next_cf;
1821
1822 free(bc->bytecode);
1823 bc->bytecode = NULL;
1824
1825 LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
1826 struct r600_bytecode_alu *alu = NULL, *next_alu;
1827 struct r600_bytecode_tex *tex = NULL, *next_tex;
1828 struct r600_bytecode_tex *vtx = NULL, *next_vtx;
1829 struct r600_bytecode_gds *gds = NULL, *next_gds;
1830
1831 LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
1832 free(alu);
1833 }
1834
1835 LIST_INITHEAD(&cf->alu);
1836
1837 LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) {
1838 free(tex);
1839 }
1840
1841 LIST_INITHEAD(&cf->tex);
1842
1843 LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) {
1844 free(vtx);
1845 }
1846
1847 LIST_INITHEAD(&cf->vtx);
1848
1849 LIST_FOR_EACH_ENTRY_SAFE(gds, next_gds, &cf->gds, list) {
1850 free(gds);
1851 }
1852
1853 LIST_INITHEAD(&cf->gds);
1854
1855 free(cf);
1856 }
1857
1858 LIST_INITHEAD(&cf->list);
1859 }
1860
1861 static int print_swizzle(unsigned swz)
1862 {
1863 const char * swzchars = "xyzw01?_";
1864 assert(swz<8 && swz != 6);
1865 return fprintf(stderr, "%c", swzchars[swz]);
1866 }
1867
1868 static int print_sel(unsigned sel, unsigned rel, unsigned index_mode,
1869 unsigned need_brackets)
1870 {
1871 int o = 0;
1872 if (rel && index_mode >= 5 && sel < 128)
1873 o += fprintf(stderr, "G");
1874 if (rel || need_brackets) {
1875 o += fprintf(stderr, "[");
1876 }
1877 o += fprintf(stderr, "%d", sel);
1878 if (rel) {
1879 if (index_mode == 0 || index_mode == 6)
1880 o += fprintf(stderr, "+AR");
1881 else if (index_mode == 4)
1882 o += fprintf(stderr, "+AL");
1883 }
1884 if (rel || need_brackets) {
1885 o += fprintf(stderr, "]");
1886 }
1887 return o;
1888 }
1889
1890 static int print_dst(struct r600_bytecode_alu *alu)
1891 {
1892 int o = 0;
1893 unsigned sel = alu->dst.sel;
1894 char reg_char = 'R';
1895 if (sel > 128 - 4) { /* clause temporary gpr */
1896 sel -= 128 - 4;
1897 reg_char = 'T';
1898 }
1899
1900 if (alu_writes(alu)) {
1901 o += fprintf(stderr, "%c", reg_char);
1902 o += print_sel(alu->dst.sel, alu->dst.rel, alu->index_mode, 0);
1903 } else {
1904 o += fprintf(stderr, "__");
1905 }
1906 o += fprintf(stderr, ".");
1907 o += print_swizzle(alu->dst.chan);
1908 return o;
1909 }
1910
1911 static int print_src(struct r600_bytecode_alu *alu, unsigned idx)
1912 {
1913 int o = 0;
1914 struct r600_bytecode_alu_src *src = &alu->src[idx];
1915 unsigned sel = src->sel, need_sel = 1, need_chan = 1, need_brackets = 0;
1916
1917 if (src->neg)
1918 o += fprintf(stderr,"-");
1919 if (src->abs)
1920 o += fprintf(stderr,"|");
1921
1922 if (sel < 128 - 4) {
1923 o += fprintf(stderr, "R");
1924 } else if (sel < 128) {
1925 o += fprintf(stderr, "T");
1926 sel -= 128 - 4;
1927 } else if (sel < 160) {
1928 o += fprintf(stderr, "KC0");
1929 need_brackets = 1;
1930 sel -= 128;
1931 } else if (sel < 192) {
1932 o += fprintf(stderr, "KC1");
1933 need_brackets = 1;
1934 sel -= 160;
1935 } else if (sel >= 512) {
1936 o += fprintf(stderr, "C%d", src->kc_bank);
1937 need_brackets = 1;
1938 sel -= 512;
1939 } else if (sel >= 448) {
1940 o += fprintf(stderr, "Param");
1941 sel -= 448;
1942 need_chan = 0;
1943 } else if (sel >= 288) {
1944 o += fprintf(stderr, "KC3");
1945 need_brackets = 1;
1946 sel -= 288;
1947 } else if (sel >= 256) {
1948 o += fprintf(stderr, "KC2");
1949 need_brackets = 1;
1950 sel -= 256;
1951 } else {
1952 need_sel = 0;
1953 need_chan = 0;
1954 switch (sel) {
1955 case EG_V_SQ_ALU_SRC_LDS_DIRECT_A:
1956 o += fprintf(stderr, "LDS_A[0x%08X]", src->value);
1957 break;
1958 case EG_V_SQ_ALU_SRC_LDS_DIRECT_B:
1959 o += fprintf(stderr, "LDS_B[0x%08X]", src->value);
1960 break;
1961 case EG_V_SQ_ALU_SRC_LDS_OQ_A:
1962 o += fprintf(stderr, "LDS_OQ_A");
1963 need_chan = 1;
1964 break;
1965 case EG_V_SQ_ALU_SRC_LDS_OQ_B:
1966 o += fprintf(stderr, "LDS_OQ_B");
1967 need_chan = 1;
1968 break;
1969 case EG_V_SQ_ALU_SRC_LDS_OQ_A_POP:
1970 o += fprintf(stderr, "LDS_OQ_A_POP");
1971 need_chan = 1;
1972 break;
1973 case EG_V_SQ_ALU_SRC_LDS_OQ_B_POP:
1974 o += fprintf(stderr, "LDS_OQ_B_POP");
1975 need_chan = 1;
1976 break;
1977 case EG_V_SQ_ALU_SRC_SE_ID:
1978 o += fprintf(stderr, "SE_ID");
1979 break;
1980 case EG_V_SQ_ALU_SRC_SIMD_ID:
1981 o += fprintf(stderr, "SIMD_ID");
1982 break;
1983 case EG_V_SQ_ALU_SRC_HW_WAVE_ID:
1984 o += fprintf(stderr, "HW_WAVE_ID");
1985 break;
1986 case V_SQ_ALU_SRC_PS:
1987 o += fprintf(stderr, "PS");
1988 break;
1989 case V_SQ_ALU_SRC_PV:
1990 o += fprintf(stderr, "PV");
1991 need_chan = 1;
1992 break;
1993 case V_SQ_ALU_SRC_LITERAL:
1994 o += fprintf(stderr, "[0x%08X %f]", src->value, u_bitcast_u2f(src->value));
1995 break;
1996 case V_SQ_ALU_SRC_0_5:
1997 o += fprintf(stderr, "0.5");
1998 break;
1999 case V_SQ_ALU_SRC_M_1_INT:
2000 o += fprintf(stderr, "-1");
2001 break;
2002 case V_SQ_ALU_SRC_1_INT:
2003 o += fprintf(stderr, "1");
2004 break;
2005 case V_SQ_ALU_SRC_1:
2006 o += fprintf(stderr, "1.0");
2007 break;
2008 case V_SQ_ALU_SRC_0:
2009 o += fprintf(stderr, "0");
2010 break;
2011 default:
2012 o += fprintf(stderr, "??IMM_%d", sel);
2013 break;
2014 }
2015 }
2016
2017 if (need_sel)
2018 o += print_sel(sel, src->rel, alu->index_mode, need_brackets);
2019
2020 if (need_chan) {
2021 o += fprintf(stderr, ".");
2022 o += print_swizzle(src->chan);
2023 }
2024
2025 if (src->abs)
2026 o += fprintf(stderr,"|");
2027
2028 return o;
2029 }
2030
2031 static int print_indent(int p, int c)
2032 {
2033 int o = 0;
2034 while (p++ < c)
2035 o += fprintf(stderr, " ");
2036 return o;
2037 }
2038
2039 void r600_bytecode_disasm(struct r600_bytecode *bc)
2040 {
2041 const char *index_mode[] = {"CF_INDEX_NONE", "CF_INDEX_0", "CF_INDEX_1"};
2042 static int index = 0;
2043 struct r600_bytecode_cf *cf = NULL;
2044 struct r600_bytecode_alu *alu = NULL;
2045 struct r600_bytecode_vtx *vtx = NULL;
2046 struct r600_bytecode_tex *tex = NULL;
2047 struct r600_bytecode_gds *gds = NULL;
2048
2049 unsigned i, id, ngr = 0, last;
2050 uint32_t literal[4];
2051 unsigned nliteral;
2052 char chip = '6';
2053
2054 switch (bc->chip_class) {
2055 case R700:
2056 chip = '7';
2057 break;
2058 case EVERGREEN:
2059 chip = 'E';
2060 break;
2061 case CAYMAN:
2062 chip = 'C';
2063 break;
2064 case R600:
2065 default:
2066 chip = '6';
2067 break;
2068 }
2069 fprintf(stderr, "bytecode %d dw -- %d gprs -- %d nstack -------------\n",
2070 bc->ndw, bc->ngpr, bc->nstack);
2071 fprintf(stderr, "shader %d -- %c\n", index++, chip);
2072
2073 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
2074 id = cf->id;
2075 if (cf->op == CF_NATIVE) {
2076 fprintf(stderr, "%04d %08X %08X CF_NATIVE\n", id, bc->bytecode[id],
2077 bc->bytecode[id + 1]);
2078 } else {
2079 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
2080 if (cfop->flags & CF_ALU) {
2081 if (cf->eg_alu_extended) {
2082 fprintf(stderr, "%04d %08X %08X %s\n", id, bc->bytecode[id],
2083 bc->bytecode[id + 1], "ALU_EXT");
2084 id += 2;
2085 }
2086 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
2087 bc->bytecode[id + 1], cfop->name);
2088 fprintf(stderr, "%d @%d ", cf->ndw / 2, cf->addr);
2089 for (i = 0; i < 4; ++i) {
2090 if (cf->kcache[i].mode) {
2091 int c_start = (cf->kcache[i].addr << 4);
2092 int c_end = c_start + (cf->kcache[i].mode << 4);
2093 fprintf(stderr, "KC%d[CB%d:%d-%d%s%s] ",
2094 i, cf->kcache[i].bank, c_start, c_end,
2095 cf->kcache[i].index_mode ? " " : "",
2096 cf->kcache[i].index_mode ? index_mode[cf->kcache[i].index_mode] : "");
2097 }
2098 }
2099 fprintf(stderr, "\n");
2100 } else if (cfop->flags & CF_FETCH) {
2101 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
2102 bc->bytecode[id + 1], cfop->name);
2103 fprintf(stderr, "%d @%d ", cf->ndw / 4, cf->addr);
2104 if (cf->vpm)
2105 fprintf(stderr, "VPM ");
2106 if (cf->end_of_program)
2107 fprintf(stderr, "EOP ");
2108 fprintf(stderr, "\n");
2109
2110 } else if (cfop->flags & CF_EXP) {
2111 int o = 0;
2112 const char *exp_type[] = {"PIXEL", "POS ", "PARAM"};
2113 o += fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
2114 bc->bytecode[id + 1], cfop->name);
2115 o += print_indent(o, 43);
2116 o += fprintf(stderr, "%s ", exp_type[cf->output.type]);
2117 if (cf->output.burst_count > 1) {
2118 o += fprintf(stderr, "%d-%d ", cf->output.array_base,
2119 cf->output.array_base + cf->output.burst_count - 1);
2120
2121 o += print_indent(o, 55);
2122 o += fprintf(stderr, "R%d-%d.", cf->output.gpr,
2123 cf->output.gpr + cf->output.burst_count - 1);
2124 } else {
2125 o += fprintf(stderr, "%d ", cf->output.array_base);
2126 o += print_indent(o, 55);
2127 o += fprintf(stderr, "R%d.", cf->output.gpr);
2128 }
2129
2130 o += print_swizzle(cf->output.swizzle_x);
2131 o += print_swizzle(cf->output.swizzle_y);
2132 o += print_swizzle(cf->output.swizzle_z);
2133 o += print_swizzle(cf->output.swizzle_w);
2134
2135 print_indent(o, 67);
2136
2137 fprintf(stderr, " ES:%X ", cf->output.elem_size);
2138 if (cf->mark)
2139 fprintf(stderr, "MARK ");
2140 if (!cf->barrier)
2141 fprintf(stderr, "NO_BARRIER ");
2142 if (cf->end_of_program)
2143 fprintf(stderr, "EOP ");
2144 fprintf(stderr, "\n");
2145 } else if (r600_isa_cf(cf->op)->flags & CF_MEM) {
2146 int o = 0;
2147 const char *exp_type[] = {"WRITE", "WRITE_IND", "WRITE_ACK",
2148 "WRITE_IND_ACK"};
2149 o += fprintf(stderr, "%04d %08X %08X %s ", id,
2150 bc->bytecode[id], bc->bytecode[id + 1], cfop->name);
2151 o += print_indent(o, 43);
2152 o += fprintf(stderr, "%s ", exp_type[cf->output.type]);
2153
2154 if (r600_isa_cf(cf->op)->flags & CF_RAT) {
2155 o += fprintf(stderr, "RAT%d", cf->rat.id);
2156 if (cf->rat.index_mode) {
2157 o += fprintf(stderr, "[IDX%d]", cf->rat.index_mode - 1);
2158 }
2159 o += fprintf(stderr, " INST: %d ", cf->rat.inst);
2160 }
2161
2162 if (cf->output.burst_count > 1) {
2163 o += fprintf(stderr, "%d-%d ", cf->output.array_base,
2164 cf->output.array_base + cf->output.burst_count - 1);
2165 o += print_indent(o, 55);
2166 o += fprintf(stderr, "R%d-%d.", cf->output.gpr,
2167 cf->output.gpr + cf->output.burst_count - 1);
2168 } else {
2169 o += fprintf(stderr, "%d ", cf->output.array_base);
2170 o += print_indent(o, 55);
2171 o += fprintf(stderr, "R%d.", cf->output.gpr);
2172 }
2173 for (i = 0; i < 4; ++i) {
2174 if (cf->output.comp_mask & (1 << i))
2175 o += print_swizzle(i);
2176 else
2177 o += print_swizzle(7);
2178 }
2179
2180 if (cf->output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND ||
2181 cf->output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND)
2182 o += fprintf(stderr, " R%d", cf->output.index_gpr);
2183
2184 o += print_indent(o, 67);
2185
2186 fprintf(stderr, " ES:%i ", cf->output.elem_size);
2187 if (cf->output.array_size != 0xFFF)
2188 fprintf(stderr, "AS:%i ", cf->output.array_size);
2189 if (cf->mark)
2190 fprintf(stderr, "MARK ");
2191 if (!cf->barrier)
2192 fprintf(stderr, "NO_BARRIER ");
2193 if (cf->end_of_program)
2194 fprintf(stderr, "EOP ");
2195
2196 if (cf->output.mark)
2197 fprintf(stderr, "MARK ");
2198
2199 fprintf(stderr, "\n");
2200 } else {
2201 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
2202 bc->bytecode[id + 1], cfop->name);
2203 fprintf(stderr, "@%d ", cf->cf_addr);
2204 if (cf->cond)
2205 fprintf(stderr, "CND:%X ", cf->cond);
2206 if (cf->pop_count)
2207 fprintf(stderr, "POP:%X ", cf->pop_count);
2208 if (cf->count && (cfop->flags & CF_EMIT))
2209 fprintf(stderr, "STREAM%d ", cf->count);
2210 if (cf->vpm)
2211 fprintf(stderr, "VPM ");
2212 if (cf->end_of_program)
2213 fprintf(stderr, "EOP ");
2214 fprintf(stderr, "\n");
2215 }
2216 }
2217
2218 id = cf->addr;
2219 nliteral = 0;
2220 last = 1;
2221 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
2222 const char *omod_str[] = {"","*2","*4","/2"};
2223 const struct alu_op_info *aop = r600_isa_alu(alu->op);
2224 int o = 0;
2225
2226 r600_bytecode_alu_nliterals(alu, literal, &nliteral);
2227 o += fprintf(stderr, " %04d %08X %08X ", id, bc->bytecode[id], bc->bytecode[id+1]);
2228 if (last)
2229 o += fprintf(stderr, "%4d ", ++ngr);
2230 else
2231 o += fprintf(stderr, " ");
2232 o += fprintf(stderr, "%c%c %c ", alu->execute_mask ? 'M':' ',
2233 alu->update_pred ? 'P':' ',
2234 alu->pred_sel ? alu->pred_sel==2 ? '0':'1':' ');
2235
2236 o += fprintf(stderr, "%s%s%s ", aop->name,
2237 omod_str[alu->omod], alu->dst.clamp ? "_sat":"");
2238
2239 o += print_indent(o,60);
2240 o += print_dst(alu);
2241 for (i = 0; i < aop->src_count; ++i) {
2242 o += fprintf(stderr, i == 0 ? ", ": ", ");
2243 o += print_src(alu, i);
2244 }
2245
2246 if (alu->bank_swizzle) {
2247 o += print_indent(o,75);
2248 o += fprintf(stderr, " BS:%d", alu->bank_swizzle);
2249 }
2250
2251 fprintf(stderr, "\n");
2252 id += 2;
2253
2254 if (alu->last) {
2255 for (i = 0; i < nliteral; i++, id++) {
2256 float *f = (float*)(bc->bytecode + id);
2257 o = fprintf(stderr, " %04d %08X", id, bc->bytecode[id]);
2258 print_indent(o, 60);
2259 fprintf(stderr, " %f (%d)\n", *f, *(bc->bytecode + id));
2260 }
2261 id += nliteral & 1;
2262 nliteral = 0;
2263 }
2264 last = alu->last;
2265 }
2266
2267 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2268 int o = 0;
2269 o += fprintf(stderr, " %04d %08X %08X %08X ", id, bc->bytecode[id],
2270 bc->bytecode[id + 1], bc->bytecode[id + 2]);
2271
2272 o += fprintf(stderr, "%s ", r600_isa_fetch(tex->op)->name);
2273
2274 o += print_indent(o, 50);
2275
2276 o += fprintf(stderr, "R%d.", tex->dst_gpr);
2277 o += print_swizzle(tex->dst_sel_x);
2278 o += print_swizzle(tex->dst_sel_y);
2279 o += print_swizzle(tex->dst_sel_z);
2280 o += print_swizzle(tex->dst_sel_w);
2281
2282 o += fprintf(stderr, ", R%d.", tex->src_gpr);
2283 o += print_swizzle(tex->src_sel_x);
2284 o += print_swizzle(tex->src_sel_y);
2285 o += print_swizzle(tex->src_sel_z);
2286 o += print_swizzle(tex->src_sel_w);
2287
2288 o += fprintf(stderr, ", RID:%d", tex->resource_id);
2289 o += fprintf(stderr, ", SID:%d ", tex->sampler_id);
2290
2291 if (tex->sampler_index_mode)
2292 fprintf(stderr, "SQ_%s ", index_mode[tex->sampler_index_mode]);
2293
2294 if (tex->lod_bias)
2295 fprintf(stderr, "LB:%d ", tex->lod_bias);
2296
2297 fprintf(stderr, "CT:%c%c%c%c ",
2298 tex->coord_type_x ? 'N' : 'U',
2299 tex->coord_type_y ? 'N' : 'U',
2300 tex->coord_type_z ? 'N' : 'U',
2301 tex->coord_type_w ? 'N' : 'U');
2302
2303 if (tex->offset_x)
2304 fprintf(stderr, "OX:%d ", tex->offset_x);
2305 if (tex->offset_y)
2306 fprintf(stderr, "OY:%d ", tex->offset_y);
2307 if (tex->offset_z)
2308 fprintf(stderr, "OZ:%d ", tex->offset_z);
2309
2310 id += 4;
2311 fprintf(stderr, "\n");
2312 }
2313
2314 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2315 int o = 0;
2316 const char * fetch_type[] = {"VERTEX", "INSTANCE", ""};
2317 o += fprintf(stderr, " %04d %08X %08X %08X ", id, bc->bytecode[id],
2318 bc->bytecode[id + 1], bc->bytecode[id + 2]);
2319
2320 o += fprintf(stderr, "%s ", r600_isa_fetch(vtx->op)->name);
2321
2322 o += print_indent(o, 50);
2323
2324 o += fprintf(stderr, "R%d.", vtx->dst_gpr);
2325 o += print_swizzle(vtx->dst_sel_x);
2326 o += print_swizzle(vtx->dst_sel_y);
2327 o += print_swizzle(vtx->dst_sel_z);
2328 o += print_swizzle(vtx->dst_sel_w);
2329
2330 o += fprintf(stderr, ", R%d.", vtx->src_gpr);
2331 o += print_swizzle(vtx->src_sel_x);
2332 if (r600_isa_fetch(vtx->op)->flags & FF_MEM)
2333 o += print_swizzle(vtx->src_sel_y);
2334
2335 if (vtx->offset)
2336 fprintf(stderr, " +%db", vtx->offset);
2337
2338 o += print_indent(o, 55);
2339
2340 fprintf(stderr, ", RID:%d ", vtx->buffer_id);
2341
2342 fprintf(stderr, "%s ", fetch_type[vtx->fetch_type]);
2343
2344 if (bc->chip_class < CAYMAN && vtx->mega_fetch_count)
2345 fprintf(stderr, "MFC:%d ", vtx->mega_fetch_count);
2346
2347 if (bc->chip_class >= EVERGREEN && vtx->buffer_index_mode)
2348 fprintf(stderr, "SQ_%s ", index_mode[vtx->buffer_index_mode]);
2349
2350 if (r600_isa_fetch(vtx->op)->flags & FF_MEM) {
2351 if (vtx->uncached)
2352 fprintf(stderr, "UNCACHED ");
2353 if (vtx->indexed)
2354 fprintf(stderr, "INDEXED:%d ", vtx->indexed);
2355
2356 fprintf(stderr, "ELEM_SIZE:%d ", vtx->elem_size);
2357 if (vtx->burst_count)
2358 fprintf(stderr, "BURST_COUNT:%d ", vtx->burst_count);
2359 fprintf(stderr, "ARRAY_BASE:%d ", vtx->array_base);
2360 fprintf(stderr, "ARRAY_SIZE:%d ", vtx->array_size);
2361 }
2362
2363 fprintf(stderr, "UCF:%d ", vtx->use_const_fields);
2364 fprintf(stderr, "FMT(DTA:%d ", vtx->data_format);
2365 fprintf(stderr, "NUM:%d ", vtx->num_format_all);
2366 fprintf(stderr, "COMP:%d ", vtx->format_comp_all);
2367 fprintf(stderr, "MODE:%d)\n", vtx->srf_mode_all);
2368
2369 id += 4;
2370 }
2371
2372 LIST_FOR_EACH_ENTRY(gds, &cf->gds, list) {
2373 int o = 0;
2374 o += fprintf(stderr, " %04d %08X %08X %08X ", id, bc->bytecode[id],
2375 bc->bytecode[id + 1], bc->bytecode[id + 2]);
2376
2377 o += fprintf(stderr, "%s ", r600_isa_fetch(gds->op)->name);
2378
2379 if (gds->op != FETCH_OP_TF_WRITE) {
2380 o += fprintf(stderr, "R%d.", gds->dst_gpr);
2381 o += print_swizzle(gds->dst_sel_x);
2382 o += print_swizzle(gds->dst_sel_y);
2383 o += print_swizzle(gds->dst_sel_z);
2384 o += print_swizzle(gds->dst_sel_w);
2385 }
2386
2387 o += fprintf(stderr, ", R%d.", gds->src_gpr);
2388 o += print_swizzle(gds->src_sel_x);
2389 o += print_swizzle(gds->src_sel_y);
2390 o += print_swizzle(gds->src_sel_z);
2391
2392 if (gds->op != FETCH_OP_TF_WRITE) {
2393 o += fprintf(stderr, ", R%d.", gds->src_gpr2);
2394 }
2395 if (gds->alloc_consume) {
2396 o += fprintf(stderr, " UAV: %d", gds->uav_id);
2397 if (gds->uav_index_mode)
2398 o += fprintf(stderr, "[%s]", index_mode[gds->uav_index_mode]);
2399 }
2400 fprintf(stderr, "\n");
2401 id += 4;
2402 }
2403 }
2404
2405 fprintf(stderr, "--------------------------------------\n");
2406 }
2407
2408 void r600_vertex_data_type(enum pipe_format pformat,
2409 unsigned *format,
2410 unsigned *num_format, unsigned *format_comp, unsigned *endian)
2411 {
2412 const struct util_format_description *desc;
2413 unsigned i;
2414
2415 *format = 0;
2416 *num_format = 0;
2417 *format_comp = 0;
2418 *endian = ENDIAN_NONE;
2419
2420 if (pformat == PIPE_FORMAT_R11G11B10_FLOAT) {
2421 *format = FMT_10_11_11_FLOAT;
2422 *endian = r600_endian_swap(32);
2423 return;
2424 }
2425
2426 if (pformat == PIPE_FORMAT_B5G6R5_UNORM) {
2427 *format = FMT_5_6_5;
2428 *endian = r600_endian_swap(16);
2429 return;
2430 }
2431
2432 if (pformat == PIPE_FORMAT_B5G5R5A1_UNORM) {
2433 *format = FMT_1_5_5_5;
2434 *endian = r600_endian_swap(16);
2435 return;
2436 }
2437
2438 desc = util_format_description(pformat);
2439 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
2440 goto out_unknown;
2441 }
2442
2443 /* Find the first non-VOID channel. */
2444 for (i = 0; i < 4; i++) {
2445 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2446 break;
2447 }
2448 }
2449
2450 *endian = r600_endian_swap(desc->channel[i].size);
2451
2452 switch (desc->channel[i].type) {
2453 /* Half-floats, floats, ints */
2454 case UTIL_FORMAT_TYPE_FLOAT:
2455 switch (desc->channel[i].size) {
2456 case 16:
2457 switch (desc->nr_channels) {
2458 case 1:
2459 *format = FMT_16_FLOAT;
2460 break;
2461 case 2:
2462 *format = FMT_16_16_FLOAT;
2463 break;
2464 case 3:
2465 case 4:
2466 *format = FMT_16_16_16_16_FLOAT;
2467 break;
2468 }
2469 break;
2470 case 32:
2471 switch (desc->nr_channels) {
2472 case 1:
2473 *format = FMT_32_FLOAT;
2474 break;
2475 case 2:
2476 *format = FMT_32_32_FLOAT;
2477 break;
2478 case 3:
2479 *format = FMT_32_32_32_FLOAT;
2480 break;
2481 case 4:
2482 *format = FMT_32_32_32_32_FLOAT;
2483 break;
2484 }
2485 break;
2486 default:
2487 goto out_unknown;
2488 }
2489 break;
2490 /* Unsigned ints */
2491 case UTIL_FORMAT_TYPE_UNSIGNED:
2492 /* Signed ints */
2493 case UTIL_FORMAT_TYPE_SIGNED:
2494 switch (desc->channel[i].size) {
2495 case 8:
2496 switch (desc->nr_channels) {
2497 case 1:
2498 *format = FMT_8;
2499 break;
2500 case 2:
2501 *format = FMT_8_8;
2502 break;
2503 case 3:
2504 case 4:
2505 *format = FMT_8_8_8_8;
2506 break;
2507 }
2508 break;
2509 case 10:
2510 if (desc->nr_channels != 4)
2511 goto out_unknown;
2512
2513 *format = FMT_2_10_10_10;
2514 break;
2515 case 16:
2516 switch (desc->nr_channels) {
2517 case 1:
2518 *format = FMT_16;
2519 break;
2520 case 2:
2521 *format = FMT_16_16;
2522 break;
2523 case 3:
2524 case 4:
2525 *format = FMT_16_16_16_16;
2526 break;
2527 }
2528 break;
2529 case 32:
2530 switch (desc->nr_channels) {
2531 case 1:
2532 *format = FMT_32;
2533 break;
2534 case 2:
2535 *format = FMT_32_32;
2536 break;
2537 case 3:
2538 *format = FMT_32_32_32;
2539 break;
2540 case 4:
2541 *format = FMT_32_32_32_32;
2542 break;
2543 }
2544 break;
2545 default:
2546 goto out_unknown;
2547 }
2548 break;
2549 default:
2550 goto out_unknown;
2551 }
2552
2553 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2554 *format_comp = 1;
2555 }
2556
2557 *num_format = 0;
2558 if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED ||
2559 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2560 if (!desc->channel[i].normalized) {
2561 if (desc->channel[i].pure_integer)
2562 *num_format = 1;
2563 else
2564 *num_format = 2;
2565 }
2566 }
2567 return;
2568 out_unknown:
2569 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
2570 }
2571
2572 void *r600_create_vertex_fetch_shader(struct pipe_context *ctx,
2573 unsigned count,
2574 const struct pipe_vertex_element *elements)
2575 {
2576 struct r600_context *rctx = (struct r600_context *)ctx;
2577 struct r600_bytecode bc;
2578 struct r600_bytecode_vtx vtx;
2579 const struct util_format_description *desc;
2580 unsigned fetch_resource_start = rctx->b.chip_class >= EVERGREEN ? 0 : 160;
2581 unsigned format, num_format, format_comp, endian;
2582 uint32_t *bytecode;
2583 int i, j, r, fs_size;
2584 struct r600_fetch_shader *shader;
2585 unsigned no_sb = rctx->screen->b.debug_flags & DBG_NO_SB;
2586 unsigned sb_disasm = !no_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
2587
2588 assert(count < 32);
2589
2590 memset(&bc, 0, sizeof(bc));
2591 r600_bytecode_init(&bc, rctx->b.chip_class, rctx->b.family,
2592 rctx->screen->has_compressed_msaa_texturing);
2593
2594 bc.isa = rctx->isa;
2595
2596 for (i = 0; i < count; i++) {
2597 if (elements[i].instance_divisor > 1) {
2598 if (rctx->b.chip_class == CAYMAN) {
2599 for (j = 0; j < 4; j++) {
2600 struct r600_bytecode_alu alu;
2601 memset(&alu, 0, sizeof(alu));
2602 alu.op = ALU_OP2_MULHI_UINT;
2603 alu.src[0].sel = 0;
2604 alu.src[0].chan = 3;
2605 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2606 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2607 alu.dst.sel = i + 1;
2608 alu.dst.chan = j;
2609 alu.dst.write = j == 3;
2610 alu.last = j == 3;
2611 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2612 r600_bytecode_clear(&bc);
2613 return NULL;
2614 }
2615 }
2616 } else {
2617 struct r600_bytecode_alu alu;
2618 memset(&alu, 0, sizeof(alu));
2619 alu.op = ALU_OP2_MULHI_UINT;
2620 alu.src[0].sel = 0;
2621 alu.src[0].chan = 3;
2622 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2623 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2624 alu.dst.sel = i + 1;
2625 alu.dst.chan = 3;
2626 alu.dst.write = 1;
2627 alu.last = 1;
2628 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2629 r600_bytecode_clear(&bc);
2630 return NULL;
2631 }
2632 }
2633 }
2634 }
2635
2636 for (i = 0; i < count; i++) {
2637 r600_vertex_data_type(elements[i].src_format,
2638 &format, &num_format, &format_comp, &endian);
2639
2640 desc = util_format_description(elements[i].src_format);
2641 if (!desc) {
2642 r600_bytecode_clear(&bc);
2643 R600_ERR("unknown format %d\n", elements[i].src_format);
2644 return NULL;
2645 }
2646
2647 if (elements[i].src_offset > 65535) {
2648 r600_bytecode_clear(&bc);
2649 R600_ERR("too big src_offset: %u\n", elements[i].src_offset);
2650 return NULL;
2651 }
2652
2653 memset(&vtx, 0, sizeof(vtx));
2654 vtx.buffer_id = elements[i].vertex_buffer_index + fetch_resource_start;
2655 vtx.fetch_type = elements[i].instance_divisor ? SQ_VTX_FETCH_INSTANCE_DATA : SQ_VTX_FETCH_VERTEX_DATA;
2656 vtx.src_gpr = elements[i].instance_divisor > 1 ? i + 1 : 0;
2657 vtx.src_sel_x = elements[i].instance_divisor ? 3 : 0;
2658 vtx.mega_fetch_count = 0x1F;
2659 vtx.dst_gpr = i + 1;
2660 vtx.dst_sel_x = desc->swizzle[0];
2661 vtx.dst_sel_y = desc->swizzle[1];
2662 vtx.dst_sel_z = desc->swizzle[2];
2663 vtx.dst_sel_w = desc->swizzle[3];
2664 vtx.data_format = format;
2665 vtx.num_format_all = num_format;
2666 vtx.format_comp_all = format_comp;
2667 vtx.offset = elements[i].src_offset;
2668 vtx.endian = endian;
2669
2670 if ((r = r600_bytecode_add_vtx(&bc, &vtx))) {
2671 r600_bytecode_clear(&bc);
2672 return NULL;
2673 }
2674 }
2675
2676 r600_bytecode_add_cfinst(&bc, CF_OP_RET);
2677
2678 if ((r = r600_bytecode_build(&bc))) {
2679 r600_bytecode_clear(&bc);
2680 return NULL;
2681 }
2682
2683 if (rctx->screen->b.debug_flags & DBG_FS) {
2684 fprintf(stderr, "--------------------------------------------------------------\n");
2685 fprintf(stderr, "Vertex elements state:\n");
2686 for (i = 0; i < count; i++) {
2687 fprintf(stderr, " ");
2688 util_dump_vertex_element(stderr, elements+i);
2689 fprintf(stderr, "\n");
2690 }
2691
2692 if (!sb_disasm) {
2693 r600_bytecode_disasm(&bc);
2694
2695 fprintf(stderr, "______________________________________________________________\n");
2696 } else {
2697 r600_sb_bytecode_process(rctx, &bc, NULL, 1 /*dump*/, 0 /*optimize*/);
2698 }
2699 }
2700
2701 fs_size = bc.ndw*4;
2702
2703 /* Allocate the CSO. */
2704 shader = CALLOC_STRUCT(r600_fetch_shader);
2705 if (!shader) {
2706 r600_bytecode_clear(&bc);
2707 return NULL;
2708 }
2709
2710 u_suballocator_alloc(rctx->allocator_fetch_shader, fs_size, 256,
2711 &shader->offset,
2712 (struct pipe_resource**)&shader->buffer);
2713 if (!shader->buffer) {
2714 r600_bytecode_clear(&bc);
2715 FREE(shader);
2716 return NULL;
2717 }
2718
2719 bytecode = r600_buffer_map_sync_with_rings(&rctx->b, shader->buffer, PIPE_TRANSFER_WRITE | PIPE_TRANSFER_UNSYNCHRONIZED);
2720 bytecode += shader->offset / 4;
2721
2722 if (R600_BIG_ENDIAN) {
2723 for (i = 0; i < fs_size / 4; ++i) {
2724 bytecode[i] = util_cpu_to_le32(bc.bytecode[i]);
2725 }
2726 } else {
2727 memcpy(bytecode, bc.bytecode, fs_size);
2728 }
2729 rctx->b.ws->buffer_unmap(shader->buffer->buf);
2730
2731 r600_bytecode_clear(&bc);
2732 return shader;
2733 }
2734
2735 void r600_bytecode_alu_read(struct r600_bytecode *bc,
2736 struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1)
2737 {
2738 /* WORD0 */
2739 alu->src[0].sel = G_SQ_ALU_WORD0_SRC0_SEL(word0);
2740 alu->src[0].rel = G_SQ_ALU_WORD0_SRC0_REL(word0);
2741 alu->src[0].chan = G_SQ_ALU_WORD0_SRC0_CHAN(word0);
2742 alu->src[0].neg = G_SQ_ALU_WORD0_SRC0_NEG(word0);
2743 alu->src[1].sel = G_SQ_ALU_WORD0_SRC1_SEL(word0);
2744 alu->src[1].rel = G_SQ_ALU_WORD0_SRC1_REL(word0);
2745 alu->src[1].chan = G_SQ_ALU_WORD0_SRC1_CHAN(word0);
2746 alu->src[1].neg = G_SQ_ALU_WORD0_SRC1_NEG(word0);
2747 alu->index_mode = G_SQ_ALU_WORD0_INDEX_MODE(word0);
2748 alu->pred_sel = G_SQ_ALU_WORD0_PRED_SEL(word0);
2749 alu->last = G_SQ_ALU_WORD0_LAST(word0);
2750
2751 /* WORD1 */
2752 alu->bank_swizzle = G_SQ_ALU_WORD1_BANK_SWIZZLE(word1);
2753 if (alu->bank_swizzle)
2754 alu->bank_swizzle_force = alu->bank_swizzle;
2755 alu->dst.sel = G_SQ_ALU_WORD1_DST_GPR(word1);
2756 alu->dst.rel = G_SQ_ALU_WORD1_DST_REL(word1);
2757 alu->dst.chan = G_SQ_ALU_WORD1_DST_CHAN(word1);
2758 alu->dst.clamp = G_SQ_ALU_WORD1_CLAMP(word1);
2759 if (G_SQ_ALU_WORD1_ENCODING(word1)) /*ALU_DWORD1_OP3*/
2760 {
2761 alu->is_op3 = 1;
2762 alu->src[2].sel = G_SQ_ALU_WORD1_OP3_SRC2_SEL(word1);
2763 alu->src[2].rel = G_SQ_ALU_WORD1_OP3_SRC2_REL(word1);
2764 alu->src[2].chan = G_SQ_ALU_WORD1_OP3_SRC2_CHAN(word1);
2765 alu->src[2].neg = G_SQ_ALU_WORD1_OP3_SRC2_NEG(word1);
2766 alu->op = r600_isa_alu_by_opcode(bc->isa,
2767 G_SQ_ALU_WORD1_OP3_ALU_INST(word1), /* is_op3 = */ 1);
2768
2769 }
2770 else /*ALU_DWORD1_OP2*/
2771 {
2772 alu->src[0].abs = G_SQ_ALU_WORD1_OP2_SRC0_ABS(word1);
2773 alu->src[1].abs = G_SQ_ALU_WORD1_OP2_SRC1_ABS(word1);
2774 alu->op = r600_isa_alu_by_opcode(bc->isa,
2775 G_SQ_ALU_WORD1_OP2_ALU_INST(word1), /* is_op3 = */ 0);
2776 alu->omod = G_SQ_ALU_WORD1_OP2_OMOD(word1);
2777 alu->dst.write = G_SQ_ALU_WORD1_OP2_WRITE_MASK(word1);
2778 alu->update_pred = G_SQ_ALU_WORD1_OP2_UPDATE_PRED(word1);
2779 alu->execute_mask =
2780 G_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(word1);
2781 }
2782 }
2783
2784 #if 0
2785 void r600_bytecode_export_read(struct r600_bytecode *bc,
2786 struct r600_bytecode_output *output, uint32_t word0, uint32_t word1)
2787 {
2788 output->array_base = G_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(word0);
2789 output->type = G_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(word0);
2790 output->gpr = G_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(word0);
2791 output->elem_size = G_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(word0);
2792
2793 output->swizzle_x = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(word1);
2794 output->swizzle_y = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(word1);
2795 output->swizzle_z = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(word1);
2796 output->swizzle_w = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(word1);
2797 output->burst_count = G_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(word1);
2798 output->end_of_program = G_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(word1);
2799 output->op = r600_isa_cf_by_opcode(bc->isa,
2800 G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(word1), 0);
2801 output->barrier = G_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(word1);
2802 output->array_size = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(word1);
2803 output->comp_mask = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(word1);
2804 }
2805 #endif