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r600g: Add pending output function
[mesa.git] / src / gallium / drivers / r600 / r600_asm.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_opcodes.h"
25 #include "r600_formats.h"
26 #include "r600_shader.h"
27 #include "r600d.h"
28
29 #include <errno.h>
30 #include "util/u_bitcast.h"
31 #include "util/u_dump.h"
32 #include "util/u_memory.h"
33 #include "util/u_math.h"
34 #include "pipe/p_shader_tokens.h"
35
36 #include "sb/sb_public.h"
37
38 #define NUM_OF_CYCLES 3
39 #define NUM_OF_COMPONENTS 4
40
41 static inline bool alu_writes(struct r600_bytecode_alu *alu)
42 {
43 return alu->dst.write || alu->is_op3;
44 }
45
46 static inline unsigned int r600_bytecode_get_num_operands(const struct r600_bytecode_alu *alu)
47 {
48 return r600_isa_alu(alu->op)->src_count;
49 }
50
51 static struct r600_bytecode_cf *r600_bytecode_cf(void)
52 {
53 struct r600_bytecode_cf *cf = CALLOC_STRUCT(r600_bytecode_cf);
54
55 if (!cf)
56 return NULL;
57 LIST_INITHEAD(&cf->list);
58 LIST_INITHEAD(&cf->alu);
59 LIST_INITHEAD(&cf->vtx);
60 LIST_INITHEAD(&cf->tex);
61 LIST_INITHEAD(&cf->gds);
62 return cf;
63 }
64
65 static struct r600_bytecode_alu *r600_bytecode_alu(void)
66 {
67 struct r600_bytecode_alu *alu = CALLOC_STRUCT(r600_bytecode_alu);
68
69 if (!alu)
70 return NULL;
71 LIST_INITHEAD(&alu->list);
72 return alu;
73 }
74
75 static struct r600_bytecode_vtx *r600_bytecode_vtx(void)
76 {
77 struct r600_bytecode_vtx *vtx = CALLOC_STRUCT(r600_bytecode_vtx);
78
79 if (!vtx)
80 return NULL;
81 LIST_INITHEAD(&vtx->list);
82 return vtx;
83 }
84
85 static struct r600_bytecode_tex *r600_bytecode_tex(void)
86 {
87 struct r600_bytecode_tex *tex = CALLOC_STRUCT(r600_bytecode_tex);
88
89 if (!tex)
90 return NULL;
91 LIST_INITHEAD(&tex->list);
92 return tex;
93 }
94
95 static struct r600_bytecode_gds *r600_bytecode_gds(void)
96 {
97 struct r600_bytecode_gds *gds = CALLOC_STRUCT(r600_bytecode_gds);
98
99 if (gds == NULL)
100 return NULL;
101 LIST_INITHEAD(&gds->list);
102 return gds;
103 }
104
105 static unsigned stack_entry_size(enum radeon_family chip) {
106 /* Wavefront size:
107 * 64: R600/RV670/RV770/Cypress/R740/Barts/Turks/Caicos/
108 * Aruba/Sumo/Sumo2/redwood/juniper
109 * 32: R630/R730/R710/Palm/Cedar
110 * 16: R610/Rs780
111 *
112 * Stack row size:
113 * Wavefront Size 16 32 48 64
114 * Columns per Row (R6xx/R7xx/R8xx only) 8 8 4 4
115 * Columns per Row (R9xx+) 8 4 4 4 */
116
117 switch (chip) {
118 /* FIXME: are some chips missing here? */
119 /* wavefront size 16 */
120 case CHIP_RV610:
121 case CHIP_RS780:
122 case CHIP_RV620:
123 case CHIP_RS880:
124 /* wavefront size 32 */
125 case CHIP_RV630:
126 case CHIP_RV635:
127 case CHIP_RV730:
128 case CHIP_RV710:
129 case CHIP_PALM:
130 case CHIP_CEDAR:
131 return 8;
132
133 /* wavefront size 64 */
134 default:
135 return 4;
136 }
137 }
138
139 void r600_bytecode_init(struct r600_bytecode *bc,
140 enum chip_class chip_class,
141 enum radeon_family family,
142 bool has_compressed_msaa_texturing)
143 {
144 static unsigned next_shader_id = 0;
145
146 bc->debug_id = ++next_shader_id;
147
148 if ((chip_class == R600) &&
149 (family != CHIP_RV670 && family != CHIP_RS780 && family != CHIP_RS880)) {
150 bc->ar_handling = AR_HANDLE_RV6XX;
151 bc->r6xx_nop_after_rel_dst = 1;
152 } else {
153 bc->ar_handling = AR_HANDLE_NORMAL;
154 bc->r6xx_nop_after_rel_dst = 0;
155 }
156
157 LIST_INITHEAD(&bc->cf);
158 bc->chip_class = chip_class;
159 bc->family = family;
160 bc->has_compressed_msaa_texturing = has_compressed_msaa_texturing;
161 bc->stack.entry_size = stack_entry_size(family);
162 }
163
164 int r600_bytecode_add_cf(struct r600_bytecode *bc)
165 {
166 struct r600_bytecode_cf *cf = r600_bytecode_cf();
167
168 if (!cf)
169 return -ENOMEM;
170 LIST_ADDTAIL(&cf->list, &bc->cf);
171 if (bc->cf_last) {
172 cf->id = bc->cf_last->id + 2;
173 if (bc->cf_last->eg_alu_extended) {
174 /* take into account extended alu size */
175 cf->id += 2;
176 bc->ndw += 2;
177 }
178 }
179 bc->cf_last = cf;
180 bc->ncf++;
181 bc->ndw += 2;
182 bc->force_add_cf = 0;
183 bc->ar_loaded = 0;
184 return 0;
185 }
186
187 int r600_bytecode_add_output(struct r600_bytecode *bc,
188 const struct r600_bytecode_output *output)
189 {
190 int r;
191
192 if (output->gpr >= bc->ngpr)
193 bc->ngpr = output->gpr + 1;
194
195 if (bc->cf_last && (bc->cf_last->op == output->op ||
196 (bc->cf_last->op == CF_OP_EXPORT &&
197 output->op == CF_OP_EXPORT_DONE)) &&
198 output->type == bc->cf_last->output.type &&
199 output->elem_size == bc->cf_last->output.elem_size &&
200 output->swizzle_x == bc->cf_last->output.swizzle_x &&
201 output->swizzle_y == bc->cf_last->output.swizzle_y &&
202 output->swizzle_z == bc->cf_last->output.swizzle_z &&
203 output->swizzle_w == bc->cf_last->output.swizzle_w &&
204 output->comp_mask == bc->cf_last->output.comp_mask &&
205 (output->burst_count + bc->cf_last->output.burst_count) <= 16) {
206
207 if ((output->gpr + output->burst_count) == bc->cf_last->output.gpr &&
208 (output->array_base + output->burst_count) == bc->cf_last->output.array_base) {
209
210 bc->cf_last->op = bc->cf_last->output.op = output->op;
211 bc->cf_last->output.gpr = output->gpr;
212 bc->cf_last->output.array_base = output->array_base;
213 bc->cf_last->output.burst_count += output->burst_count;
214 return 0;
215
216 } else if (output->gpr == (bc->cf_last->output.gpr + bc->cf_last->output.burst_count) &&
217 output->array_base == (bc->cf_last->output.array_base + bc->cf_last->output.burst_count)) {
218
219 bc->cf_last->op = bc->cf_last->output.op = output->op;
220 bc->cf_last->output.burst_count += output->burst_count;
221 return 0;
222 }
223 }
224
225 r = r600_bytecode_add_cf(bc);
226 if (r)
227 return r;
228 bc->cf_last->op = output->op;
229 memcpy(&bc->cf_last->output, output, sizeof(struct r600_bytecode_output));
230 bc->cf_last->barrier = 1;
231 return 0;
232 }
233
234 int r600_bytecode_add_pending_output(struct r600_bytecode *bc,
235 const struct r600_bytecode_output *output)
236 {
237 assert(bc->n_pending_outputs + 1 < ARRAY_SIZE(bc->pending_outputs));
238 bc->pending_outputs[bc->n_pending_outputs++] = *output;
239
240 return 0;
241 }
242
243 /* alu instructions that can ony exits once per group */
244 static int is_alu_once_inst(struct r600_bytecode_alu *alu)
245 {
246 return r600_isa_alu(alu->op)->flags & (AF_KILL | AF_PRED) || alu->is_lds_idx_op || alu->op == ALU_OP0_GROUP_BARRIER;
247 }
248
249 static int is_alu_reduction_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
250 {
251 return (r600_isa_alu(alu->op)->flags & AF_REPL) &&
252 (r600_isa_alu_slots(bc->isa->hw_class, alu->op) == AF_4V);
253 }
254
255 static int is_alu_mova_inst(struct r600_bytecode_alu *alu)
256 {
257 return r600_isa_alu(alu->op)->flags & AF_MOVA;
258 }
259
260 static int alu_uses_rel(struct r600_bytecode_alu *alu)
261 {
262 unsigned num_src = r600_bytecode_get_num_operands(alu);
263 unsigned src;
264
265 if (alu->dst.rel) {
266 return 1;
267 }
268
269 for (src = 0; src < num_src; ++src) {
270 if (alu->src[src].rel) {
271 return 1;
272 }
273 }
274 return 0;
275 }
276
277 static int is_lds_read(int sel)
278 {
279 return sel == EG_V_SQ_ALU_SRC_LDS_OQ_A_POP || sel == EG_V_SQ_ALU_SRC_LDS_OQ_B_POP;
280 }
281
282 static int alu_uses_lds(struct r600_bytecode_alu *alu)
283 {
284 unsigned num_src = r600_bytecode_get_num_operands(alu);
285 unsigned src;
286
287 for (src = 0; src < num_src; ++src) {
288 if (is_lds_read(alu->src[src].sel)) {
289 return 1;
290 }
291 }
292 return 0;
293 }
294
295 static int is_alu_64bit_inst(struct r600_bytecode_alu *alu)
296 {
297 const struct alu_op_info *op = r600_isa_alu(alu->op);
298 return (op->flags & AF_64);
299 }
300
301 static int is_alu_vec_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
302 {
303 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
304 return !(slots & AF_S);
305 }
306
307 static int is_alu_trans_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
308 {
309 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
310 return !(slots & AF_V);
311 }
312
313 /* alu instructions that can execute on any unit */
314 static int is_alu_any_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
315 {
316 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
317 return slots == AF_VS;
318 }
319
320 static int is_nop_inst(struct r600_bytecode_alu *alu)
321 {
322 return alu->op == ALU_OP0_NOP;
323 }
324
325 static int assign_alu_units(struct r600_bytecode *bc, struct r600_bytecode_alu *alu_first,
326 struct r600_bytecode_alu *assignment[5])
327 {
328 struct r600_bytecode_alu *alu;
329 unsigned i, chan, trans;
330 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
331
332 for (i = 0; i < max_slots; i++)
333 assignment[i] = NULL;
334
335 for (alu = alu_first; alu; alu = LIST_ENTRY(struct r600_bytecode_alu, alu->list.next, list)) {
336 chan = alu->dst.chan;
337 if (max_slots == 4)
338 trans = 0;
339 else if (is_alu_trans_unit_inst(bc, alu))
340 trans = 1;
341 else if (is_alu_vec_unit_inst(bc, alu))
342 trans = 0;
343 else if (assignment[chan])
344 trans = 1; /* Assume ALU_INST_PREFER_VECTOR. */
345 else
346 trans = 0;
347
348 if (trans) {
349 if (assignment[4]) {
350 assert(0); /* ALU.Trans has already been allocated. */
351 return -1;
352 }
353 assignment[4] = alu;
354 } else {
355 if (assignment[chan]) {
356 assert(0); /* ALU.chan has already been allocated. */
357 return -1;
358 }
359 assignment[chan] = alu;
360 }
361
362 if (alu->last)
363 break;
364 }
365 return 0;
366 }
367
368 struct alu_bank_swizzle {
369 int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
370 int hw_cfile_addr[4];
371 int hw_cfile_elem[4];
372 };
373
374 static const unsigned cycle_for_bank_swizzle_vec[][3] = {
375 [SQ_ALU_VEC_012] = { 0, 1, 2 },
376 [SQ_ALU_VEC_021] = { 0, 2, 1 },
377 [SQ_ALU_VEC_120] = { 1, 2, 0 },
378 [SQ_ALU_VEC_102] = { 1, 0, 2 },
379 [SQ_ALU_VEC_201] = { 2, 0, 1 },
380 [SQ_ALU_VEC_210] = { 2, 1, 0 }
381 };
382
383 static const unsigned cycle_for_bank_swizzle_scl[][3] = {
384 [SQ_ALU_SCL_210] = { 2, 1, 0 },
385 [SQ_ALU_SCL_122] = { 1, 2, 2 },
386 [SQ_ALU_SCL_212] = { 2, 1, 2 },
387 [SQ_ALU_SCL_221] = { 2, 2, 1 }
388 };
389
390 static void init_bank_swizzle(struct alu_bank_swizzle *bs)
391 {
392 int i, cycle, component;
393 /* set up gpr use */
394 for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
395 for (component = 0; component < NUM_OF_COMPONENTS; component++)
396 bs->hw_gpr[cycle][component] = -1;
397 for (i = 0; i < 4; i++)
398 bs->hw_cfile_addr[i] = -1;
399 for (i = 0; i < 4; i++)
400 bs->hw_cfile_elem[i] = -1;
401 }
402
403 static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan, unsigned cycle)
404 {
405 if (bs->hw_gpr[cycle][chan] == -1)
406 bs->hw_gpr[cycle][chan] = sel;
407 else if (bs->hw_gpr[cycle][chan] != (int)sel) {
408 /* Another scalar operation has already used the GPR read port for the channel. */
409 return -1;
410 }
411 return 0;
412 }
413
414 static int reserve_cfile(const struct r600_bytecode *bc,
415 struct alu_bank_swizzle *bs, unsigned sel, unsigned chan)
416 {
417 int res, num_res = 4;
418 if (bc->chip_class >= R700) {
419 num_res = 2;
420 chan /= 2;
421 }
422 for (res = 0; res < num_res; ++res) {
423 if (bs->hw_cfile_addr[res] == -1) {
424 bs->hw_cfile_addr[res] = sel;
425 bs->hw_cfile_elem[res] = chan;
426 return 0;
427 } else if (bs->hw_cfile_addr[res] == sel &&
428 bs->hw_cfile_elem[res] == chan)
429 return 0; /* Read for this scalar element already reserved, nothing to do here. */
430 }
431 /* All cfile read ports are used, cannot reference vector element. */
432 return -1;
433 }
434
435 static int is_gpr(unsigned sel)
436 {
437 return (sel <= 127);
438 }
439
440 /* CB constants start at 512, and get translated to a kcache index when ALU
441 * clauses are constructed. Note that we handle kcache constants the same way
442 * as (the now gone) cfile constants, is that really required? */
443 static int is_cfile(unsigned sel)
444 {
445 return (sel > 255 && sel < 512) ||
446 (sel > 511 && sel < 4607) || /* Kcache before translation. */
447 (sel > 127 && sel < 192); /* Kcache after translation. */
448 }
449
450 static int is_const(int sel)
451 {
452 return is_cfile(sel) ||
453 (sel >= V_SQ_ALU_SRC_0 &&
454 sel <= V_SQ_ALU_SRC_LITERAL);
455 }
456
457 static int check_vector(const struct r600_bytecode *bc, const struct r600_bytecode_alu *alu,
458 struct alu_bank_swizzle *bs, int bank_swizzle)
459 {
460 int r, src, num_src, sel, elem, cycle;
461
462 num_src = r600_bytecode_get_num_operands(alu);
463 for (src = 0; src < num_src; src++) {
464 sel = alu->src[src].sel;
465 elem = alu->src[src].chan;
466 if (is_gpr(sel)) {
467 cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src];
468 if (src == 1 && sel == alu->src[0].sel && elem == alu->src[0].chan)
469 /* Nothing to do; special-case optimization,
470 * second source uses first source’s reservation. */
471 continue;
472 else {
473 r = reserve_gpr(bs, sel, elem, cycle);
474 if (r)
475 return r;
476 }
477 } else if (is_cfile(sel)) {
478 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
479 if (r)
480 return r;
481 }
482 /* No restrictions on PV, PS, literal or special constants. */
483 }
484 return 0;
485 }
486
487 static int check_scalar(const struct r600_bytecode *bc, const struct r600_bytecode_alu *alu,
488 struct alu_bank_swizzle *bs, int bank_swizzle)
489 {
490 int r, src, num_src, const_count, sel, elem, cycle;
491
492 num_src = r600_bytecode_get_num_operands(alu);
493 for (const_count = 0, src = 0; src < num_src; ++src) {
494 sel = alu->src[src].sel;
495 elem = alu->src[src].chan;
496 if (is_const(sel)) { /* Any constant, including literal and inline constants. */
497 if (const_count >= 2)
498 /* More than two references to a constant in
499 * transcendental operation. */
500 return -1;
501 else
502 const_count++;
503 }
504 if (is_cfile(sel)) {
505 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
506 if (r)
507 return r;
508 }
509 }
510 for (src = 0; src < num_src; ++src) {
511 sel = alu->src[src].sel;
512 elem = alu->src[src].chan;
513 if (is_gpr(sel)) {
514 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
515 if (cycle < const_count)
516 /* Cycle for GPR load conflicts with
517 * constant load in transcendental operation. */
518 return -1;
519 r = reserve_gpr(bs, sel, elem, cycle);
520 if (r)
521 return r;
522 }
523 /* PV PS restrictions */
524 if (const_count && (sel == 254 || sel == 255)) {
525 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
526 if (cycle < const_count)
527 return -1;
528 }
529 }
530 return 0;
531 }
532
533 static int check_and_set_bank_swizzle(const struct r600_bytecode *bc,
534 struct r600_bytecode_alu *slots[5])
535 {
536 struct alu_bank_swizzle bs;
537 int bank_swizzle[5];
538 int i, r = 0, forced = 1;
539 boolean scalar_only = bc->chip_class == CAYMAN ? false : true;
540 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
541
542 for (i = 0; i < max_slots; i++) {
543 if (slots[i]) {
544 if (slots[i]->bank_swizzle_force) {
545 slots[i]->bank_swizzle = slots[i]->bank_swizzle_force;
546 } else {
547 forced = 0;
548 }
549 }
550
551 if (i < 4 && slots[i])
552 scalar_only = false;
553 }
554 if (forced)
555 return 0;
556
557 /* Just check every possible combination of bank swizzle.
558 * Not very efficent, but works on the first try in most of the cases. */
559 for (i = 0; i < 4; i++)
560 if (!slots[i] || !slots[i]->bank_swizzle_force)
561 bank_swizzle[i] = SQ_ALU_VEC_012;
562 else
563 bank_swizzle[i] = slots[i]->bank_swizzle;
564
565 bank_swizzle[4] = SQ_ALU_SCL_210;
566 while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
567
568 init_bank_swizzle(&bs);
569 if (scalar_only == false) {
570 for (i = 0; i < 4; i++) {
571 if (slots[i]) {
572 r = check_vector(bc, slots[i], &bs, bank_swizzle[i]);
573 if (r)
574 break;
575 }
576 }
577 } else
578 r = 0;
579
580 if (!r && max_slots == 5 && slots[4]) {
581 r = check_scalar(bc, slots[4], &bs, bank_swizzle[4]);
582 }
583 if (!r) {
584 for (i = 0; i < max_slots; i++) {
585 if (slots[i])
586 slots[i]->bank_swizzle = bank_swizzle[i];
587 }
588 return 0;
589 }
590
591 if (scalar_only) {
592 bank_swizzle[4]++;
593 } else {
594 for (i = 0; i < max_slots; i++) {
595 if (!slots[i] || !slots[i]->bank_swizzle_force) {
596 bank_swizzle[i]++;
597 if (bank_swizzle[i] <= SQ_ALU_VEC_210)
598 break;
599 else if (i < max_slots - 1)
600 bank_swizzle[i] = SQ_ALU_VEC_012;
601 else
602 return -1;
603 }
604 }
605 }
606 }
607
608 /* Couldn't find a working swizzle. */
609 return -1;
610 }
611
612 static int replace_gpr_with_pv_ps(struct r600_bytecode *bc,
613 struct r600_bytecode_alu *slots[5], struct r600_bytecode_alu *alu_prev)
614 {
615 struct r600_bytecode_alu *prev[5];
616 int gpr[5], chan[5];
617 int i, j, r, src, num_src;
618 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
619
620 r = assign_alu_units(bc, alu_prev, prev);
621 if (r)
622 return r;
623
624 for (i = 0; i < max_slots; ++i) {
625 if (prev[i] && alu_writes(prev[i]) && !prev[i]->dst.rel) {
626
627 if (is_alu_64bit_inst(prev[i])) {
628 gpr[i] = -1;
629 continue;
630 }
631
632 gpr[i] = prev[i]->dst.sel;
633 /* cube writes more than PV.X */
634 if (is_alu_reduction_inst(bc, prev[i]))
635 chan[i] = 0;
636 else
637 chan[i] = prev[i]->dst.chan;
638 } else
639 gpr[i] = -1;
640 }
641
642 for (i = 0; i < max_slots; ++i) {
643 struct r600_bytecode_alu *alu = slots[i];
644 if (!alu)
645 continue;
646
647 if (is_alu_64bit_inst(alu))
648 continue;
649 num_src = r600_bytecode_get_num_operands(alu);
650 for (src = 0; src < num_src; ++src) {
651 if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
652 continue;
653
654 if (bc->chip_class < CAYMAN) {
655 if (alu->src[src].sel == gpr[4] &&
656 alu->src[src].chan == chan[4] &&
657 alu_prev->pred_sel == alu->pred_sel) {
658 alu->src[src].sel = V_SQ_ALU_SRC_PS;
659 alu->src[src].chan = 0;
660 continue;
661 }
662 }
663
664 for (j = 0; j < 4; ++j) {
665 if (alu->src[src].sel == gpr[j] &&
666 alu->src[src].chan == j &&
667 alu_prev->pred_sel == alu->pred_sel) {
668 alu->src[src].sel = V_SQ_ALU_SRC_PV;
669 alu->src[src].chan = chan[j];
670 break;
671 }
672 }
673 }
674 }
675
676 return 0;
677 }
678
679 void r600_bytecode_special_constants(uint32_t value, unsigned *sel, unsigned *neg, unsigned abs)
680 {
681 switch(value) {
682 case 0:
683 *sel = V_SQ_ALU_SRC_0;
684 break;
685 case 1:
686 *sel = V_SQ_ALU_SRC_1_INT;
687 break;
688 case -1:
689 *sel = V_SQ_ALU_SRC_M_1_INT;
690 break;
691 case 0x3F800000: /* 1.0f */
692 *sel = V_SQ_ALU_SRC_1;
693 break;
694 case 0x3F000000: /* 0.5f */
695 *sel = V_SQ_ALU_SRC_0_5;
696 break;
697 case 0xBF800000: /* -1.0f */
698 *sel = V_SQ_ALU_SRC_1;
699 *neg ^= !abs;
700 break;
701 case 0xBF000000: /* -0.5f */
702 *sel = V_SQ_ALU_SRC_0_5;
703 *neg ^= !abs;
704 break;
705 default:
706 *sel = V_SQ_ALU_SRC_LITERAL;
707 break;
708 }
709 }
710
711 /* compute how many literal are needed */
712 static int r600_bytecode_alu_nliterals(struct r600_bytecode_alu *alu,
713 uint32_t literal[4], unsigned *nliteral)
714 {
715 unsigned num_src = r600_bytecode_get_num_operands(alu);
716 unsigned i, j;
717
718 for (i = 0; i < num_src; ++i) {
719 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
720 uint32_t value = alu->src[i].value;
721 unsigned found = 0;
722 for (j = 0; j < *nliteral; ++j) {
723 if (literal[j] == value) {
724 found = 1;
725 break;
726 }
727 }
728 if (!found) {
729 if (*nliteral >= 4)
730 return -EINVAL;
731 literal[(*nliteral)++] = value;
732 }
733 }
734 }
735 return 0;
736 }
737
738 static void r600_bytecode_alu_adjust_literals(struct r600_bytecode_alu *alu,
739 uint32_t literal[4], unsigned nliteral)
740 {
741 unsigned num_src = r600_bytecode_get_num_operands(alu);
742 unsigned i, j;
743
744 for (i = 0; i < num_src; ++i) {
745 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
746 uint32_t value = alu->src[i].value;
747 for (j = 0; j < nliteral; ++j) {
748 if (literal[j] == value) {
749 alu->src[i].chan = j;
750 break;
751 }
752 }
753 }
754 }
755 }
756
757 static int merge_inst_groups(struct r600_bytecode *bc, struct r600_bytecode_alu *slots[5],
758 struct r600_bytecode_alu *alu_prev)
759 {
760 struct r600_bytecode_alu *prev[5];
761 struct r600_bytecode_alu *result[5] = { NULL };
762
763 uint32_t literal[4], prev_literal[4];
764 unsigned nliteral = 0, prev_nliteral = 0;
765
766 int i, j, r, src, num_src;
767 int num_once_inst = 0;
768 int have_mova = 0, have_rel = 0;
769 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
770
771 r = assign_alu_units(bc, alu_prev, prev);
772 if (r)
773 return r;
774
775 for (i = 0; i < max_slots; ++i) {
776 if (prev[i]) {
777 if (prev[i]->pred_sel)
778 return 0;
779 if (is_alu_once_inst(prev[i]))
780 return 0;
781 }
782 if (slots[i]) {
783 if (slots[i]->pred_sel)
784 return 0;
785 if (is_alu_once_inst(slots[i]))
786 return 0;
787 }
788 }
789
790 for (i = 0; i < max_slots; ++i) {
791 struct r600_bytecode_alu *alu;
792
793 if (num_once_inst > 0)
794 return 0;
795
796 /* check number of literals */
797 if (prev[i]) {
798 if (r600_bytecode_alu_nliterals(prev[i], literal, &nliteral))
799 return 0;
800 if (r600_bytecode_alu_nliterals(prev[i], prev_literal, &prev_nliteral))
801 return 0;
802 if (is_alu_mova_inst(prev[i])) {
803 if (have_rel)
804 return 0;
805 have_mova = 1;
806 }
807
808 if (alu_uses_rel(prev[i])) {
809 if (have_mova) {
810 return 0;
811 }
812 have_rel = 1;
813 }
814 if (alu_uses_lds(prev[i]))
815 return 0;
816
817 num_once_inst += is_alu_once_inst(prev[i]);
818 }
819 if (slots[i] && r600_bytecode_alu_nliterals(slots[i], literal, &nliteral))
820 return 0;
821
822 /* Let's check used slots. */
823 if (prev[i] && !slots[i]) {
824 result[i] = prev[i];
825 continue;
826 } else if (prev[i] && slots[i]) {
827 if (max_slots == 5 && result[4] == NULL && prev[4] == NULL && slots[4] == NULL) {
828 /* Trans unit is still free try to use it. */
829 if (is_alu_any_unit_inst(bc, slots[i]) && !alu_uses_lds(slots[i])) {
830 result[i] = prev[i];
831 result[4] = slots[i];
832 } else if (is_alu_any_unit_inst(bc, prev[i])) {
833 if (slots[i]->dst.sel == prev[i]->dst.sel &&
834 alu_writes(slots[i]) &&
835 alu_writes(prev[i]))
836 return 0;
837
838 result[i] = slots[i];
839 result[4] = prev[i];
840 } else
841 return 0;
842 } else
843 return 0;
844 } else if(!slots[i]) {
845 continue;
846 } else {
847 if (max_slots == 5 && slots[i] && prev[4] &&
848 slots[i]->dst.sel == prev[4]->dst.sel &&
849 slots[i]->dst.chan == prev[4]->dst.chan &&
850 alu_writes(slots[i]) &&
851 alu_writes(prev[4]))
852 return 0;
853
854 result[i] = slots[i];
855 }
856
857 alu = slots[i];
858 num_once_inst += is_alu_once_inst(alu);
859
860 /* don't reschedule NOPs */
861 if (is_nop_inst(alu))
862 return 0;
863
864 if (is_alu_mova_inst(alu)) {
865 if (have_rel) {
866 return 0;
867 }
868 have_mova = 1;
869 }
870
871 if (alu_uses_rel(alu)) {
872 if (have_mova) {
873 return 0;
874 }
875 have_rel = 1;
876 }
877
878 if (alu->op == ALU_OP0_SET_CF_IDX0 ||
879 alu->op == ALU_OP0_SET_CF_IDX1)
880 return 0; /* data hazard with MOVA */
881
882 /* Let's check source gprs */
883 num_src = r600_bytecode_get_num_operands(alu);
884 for (src = 0; src < num_src; ++src) {
885
886 /* Constants don't matter. */
887 if (!is_gpr(alu->src[src].sel))
888 continue;
889
890 for (j = 0; j < max_slots; ++j) {
891 if (!prev[j] || !alu_writes(prev[j]))
892 continue;
893
894 /* If it's relative then we can't determin which gpr is really used. */
895 if (prev[j]->dst.chan == alu->src[src].chan &&
896 (prev[j]->dst.sel == alu->src[src].sel ||
897 prev[j]->dst.rel || alu->src[src].rel))
898 return 0;
899 }
900 }
901 }
902
903 /* more than one PRED_ or KILL_ ? */
904 if (num_once_inst > 1)
905 return 0;
906
907 /* check if the result can still be swizzlet */
908 r = check_and_set_bank_swizzle(bc, result);
909 if (r)
910 return 0;
911
912 /* looks like everything worked out right, apply the changes */
913
914 /* undo adding previus literals */
915 bc->cf_last->ndw -= align(prev_nliteral, 2);
916
917 /* sort instructions */
918 for (i = 0; i < max_slots; ++i) {
919 slots[i] = result[i];
920 if (result[i]) {
921 LIST_DEL(&result[i]->list);
922 result[i]->last = 0;
923 LIST_ADDTAIL(&result[i]->list, &bc->cf_last->alu);
924 }
925 }
926
927 /* determine new last instruction */
928 LIST_ENTRY(struct r600_bytecode_alu, bc->cf_last->alu.prev, list)->last = 1;
929
930 /* determine new first instruction */
931 for (i = 0; i < max_slots; ++i) {
932 if (result[i]) {
933 bc->cf_last->curr_bs_head = result[i];
934 break;
935 }
936 }
937
938 bc->cf_last->prev_bs_head = bc->cf_last->prev2_bs_head;
939 bc->cf_last->prev2_bs_head = NULL;
940
941 return 0;
942 }
943
944 /* we'll keep kcache sets sorted by bank & addr */
945 static int r600_bytecode_alloc_kcache_line(struct r600_bytecode *bc,
946 struct r600_bytecode_kcache *kcache,
947 unsigned bank, unsigned line, unsigned index_mode)
948 {
949 int i, kcache_banks = bc->chip_class >= EVERGREEN ? 4 : 2;
950
951 for (i = 0; i < kcache_banks; i++) {
952 if (kcache[i].mode) {
953 int d;
954
955 if (kcache[i].bank < bank)
956 continue;
957
958 if ((kcache[i].bank == bank && kcache[i].addr > line+1) ||
959 kcache[i].bank > bank) {
960 /* try to insert new line */
961 if (kcache[kcache_banks-1].mode) {
962 /* all sets are in use */
963 return -ENOMEM;
964 }
965
966 memmove(&kcache[i+1],&kcache[i], (kcache_banks-i-1)*sizeof(struct r600_bytecode_kcache));
967 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
968 kcache[i].bank = bank;
969 kcache[i].addr = line;
970 kcache[i].index_mode = index_mode;
971 return 0;
972 }
973
974 d = line - kcache[i].addr;
975
976 if (d == -1) {
977 kcache[i].addr--;
978 if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_2) {
979 /* we are prepending the line to the current set,
980 * discarding the existing second line,
981 * so we'll have to insert line+2 after it */
982 line += 2;
983 continue;
984 } else if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_1) {
985 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
986 return 0;
987 } else {
988 /* V_SQ_CF_KCACHE_LOCK_LOOP_INDEX is not supported */
989 return -ENOMEM;
990 }
991 } else if (d == 1) {
992 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
993 return 0;
994 } else if (d == 0)
995 return 0;
996 } else { /* free kcache set - use it */
997 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
998 kcache[i].bank = bank;
999 kcache[i].addr = line;
1000 kcache[i].index_mode = index_mode;
1001 return 0;
1002 }
1003 }
1004 return -ENOMEM;
1005 }
1006
1007 static int r600_bytecode_alloc_inst_kcache_lines(struct r600_bytecode *bc,
1008 struct r600_bytecode_kcache *kcache,
1009 struct r600_bytecode_alu *alu)
1010 {
1011 int i, r;
1012
1013 for (i = 0; i < 3; i++) {
1014 unsigned bank, line, sel = alu->src[i].sel, index_mode;
1015
1016 if (sel < 512)
1017 continue;
1018
1019 bank = alu->src[i].kc_bank;
1020 assert(bank < R600_MAX_HW_CONST_BUFFERS);
1021 line = (sel-512)>>4;
1022 index_mode = alu->src[i].kc_rel ? 1 : 0; // V_SQ_CF_INDEX_0 / V_SQ_CF_INDEX_NONE
1023
1024 if ((r = r600_bytecode_alloc_kcache_line(bc, kcache, bank, line, index_mode)))
1025 return r;
1026 }
1027 return 0;
1028 }
1029
1030 static int r600_bytecode_assign_kcache_banks(
1031 struct r600_bytecode_alu *alu,
1032 struct r600_bytecode_kcache * kcache)
1033 {
1034 int i, j;
1035
1036 /* Alter the src operands to refer to the kcache. */
1037 for (i = 0; i < 3; ++i) {
1038 static const unsigned int base[] = {128, 160, 256, 288};
1039 unsigned int line, sel = alu->src[i].sel, found = 0;
1040
1041 if (sel < 512)
1042 continue;
1043
1044 sel -= 512;
1045 line = sel>>4;
1046
1047 for (j = 0; j < 4 && !found; ++j) {
1048 switch (kcache[j].mode) {
1049 case V_SQ_CF_KCACHE_NOP:
1050 case V_SQ_CF_KCACHE_LOCK_LOOP_INDEX:
1051 R600_ERR("unexpected kcache line mode\n");
1052 return -ENOMEM;
1053 default:
1054 if (kcache[j].bank == alu->src[i].kc_bank &&
1055 kcache[j].addr <= line &&
1056 line < kcache[j].addr + kcache[j].mode) {
1057 alu->src[i].sel = sel - (kcache[j].addr<<4);
1058 alu->src[i].sel += base[j];
1059 found=1;
1060 }
1061 }
1062 }
1063 }
1064 return 0;
1065 }
1066
1067 static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode *bc,
1068 struct r600_bytecode_alu *alu,
1069 unsigned type)
1070 {
1071 struct r600_bytecode_kcache kcache_sets[4];
1072 struct r600_bytecode_kcache *kcache = kcache_sets;
1073 int r;
1074
1075 memcpy(kcache, bc->cf_last->kcache, 4 * sizeof(struct r600_bytecode_kcache));
1076
1077 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1078 /* can't alloc, need to start new clause */
1079 if ((r = r600_bytecode_add_cf(bc))) {
1080 return r;
1081 }
1082 bc->cf_last->op = type;
1083
1084 /* retry with the new clause */
1085 kcache = bc->cf_last->kcache;
1086 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1087 /* can't alloc again- should never happen */
1088 return r;
1089 }
1090 } else {
1091 /* update kcache sets */
1092 memcpy(bc->cf_last->kcache, kcache, 4 * sizeof(struct r600_bytecode_kcache));
1093 }
1094
1095 /* if we actually used more than 2 kcache sets, or have relative indexing - use ALU_EXTENDED on eg+ */
1096 if (kcache[2].mode != V_SQ_CF_KCACHE_NOP ||
1097 kcache[0].index_mode || kcache[1].index_mode || kcache[2].index_mode || kcache[3].index_mode) {
1098 if (bc->chip_class < EVERGREEN)
1099 return -ENOMEM;
1100 bc->cf_last->eg_alu_extended = 1;
1101 }
1102
1103 return 0;
1104 }
1105
1106 static int insert_nop_r6xx(struct r600_bytecode *bc)
1107 {
1108 struct r600_bytecode_alu alu;
1109 int r, i;
1110
1111 for (i = 0; i < 4; i++) {
1112 memset(&alu, 0, sizeof(alu));
1113 alu.op = ALU_OP0_NOP;
1114 alu.src[0].chan = i;
1115 alu.dst.chan = i;
1116 alu.last = (i == 3);
1117 r = r600_bytecode_add_alu(bc, &alu);
1118 if (r)
1119 return r;
1120 }
1121 return 0;
1122 }
1123
1124 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1125 static int load_ar_r6xx(struct r600_bytecode *bc)
1126 {
1127 struct r600_bytecode_alu alu;
1128 int r;
1129
1130 if (bc->ar_loaded)
1131 return 0;
1132
1133 /* hack to avoid making MOVA the last instruction in the clause */
1134 if ((bc->cf_last->ndw>>1) >= 110)
1135 bc->force_add_cf = 1;
1136
1137 memset(&alu, 0, sizeof(alu));
1138 alu.op = ALU_OP1_MOVA_GPR_INT;
1139 alu.src[0].sel = bc->ar_reg;
1140 alu.src[0].chan = bc->ar_chan;
1141 alu.last = 1;
1142 alu.index_mode = INDEX_MODE_LOOP;
1143 r = r600_bytecode_add_alu(bc, &alu);
1144 if (r)
1145 return r;
1146
1147 /* no requirement to set uses waterfall on MOVA_GPR_INT */
1148 bc->ar_loaded = 1;
1149 return 0;
1150 }
1151
1152 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1153 static int load_ar(struct r600_bytecode *bc)
1154 {
1155 struct r600_bytecode_alu alu;
1156 int r;
1157
1158 if (bc->ar_handling)
1159 return load_ar_r6xx(bc);
1160
1161 if (bc->ar_loaded)
1162 return 0;
1163
1164 /* hack to avoid making MOVA the last instruction in the clause */
1165 if ((bc->cf_last->ndw>>1) >= 110)
1166 bc->force_add_cf = 1;
1167
1168 memset(&alu, 0, sizeof(alu));
1169 alu.op = ALU_OP1_MOVA_INT;
1170 alu.src[0].sel = bc->ar_reg;
1171 alu.src[0].chan = bc->ar_chan;
1172 alu.last = 1;
1173 r = r600_bytecode_add_alu(bc, &alu);
1174 if (r)
1175 return r;
1176
1177 bc->cf_last->r6xx_uses_waterfall = 1;
1178 bc->ar_loaded = 1;
1179 return 0;
1180 }
1181
1182 int r600_bytecode_add_alu_type(struct r600_bytecode *bc,
1183 const struct r600_bytecode_alu *alu, unsigned type)
1184 {
1185 struct r600_bytecode_alu *nalu = r600_bytecode_alu();
1186 struct r600_bytecode_alu *lalu;
1187 int i, r;
1188
1189 if (!nalu)
1190 return -ENOMEM;
1191 memcpy(nalu, alu, sizeof(struct r600_bytecode_alu));
1192
1193 if (alu->is_op3) {
1194 /* will fail later since alu does not support it. */
1195 assert(!alu->src[0].abs && !alu->src[1].abs && !alu->src[2].abs);
1196 }
1197
1198 if (bc->cf_last != NULL && bc->cf_last->op != type) {
1199 /* check if we could add it anyway */
1200 if (bc->cf_last->op == CF_OP_ALU &&
1201 type == CF_OP_ALU_PUSH_BEFORE) {
1202 LIST_FOR_EACH_ENTRY(lalu, &bc->cf_last->alu, list) {
1203 if (lalu->execute_mask) {
1204 bc->force_add_cf = 1;
1205 break;
1206 }
1207 }
1208 } else
1209 bc->force_add_cf = 1;
1210 }
1211
1212 /* cf can contains only alu or only vtx or only tex */
1213 if (bc->cf_last == NULL || bc->force_add_cf) {
1214 r = r600_bytecode_add_cf(bc);
1215 if (r) {
1216 free(nalu);
1217 return r;
1218 }
1219 }
1220 bc->cf_last->op = type;
1221
1222 /* Load index register if required */
1223 if (bc->chip_class >= EVERGREEN) {
1224 for (i = 0; i < 3; i++)
1225 if (nalu->src[i].kc_bank && nalu->src[i].kc_rel)
1226 egcm_load_index_reg(bc, 0, true);
1227 }
1228
1229 /* Check AR usage and load it if required */
1230 for (i = 0; i < 3; i++)
1231 if (nalu->src[i].rel && !bc->ar_loaded)
1232 load_ar(bc);
1233
1234 if (nalu->dst.rel && !bc->ar_loaded)
1235 load_ar(bc);
1236
1237 /* Setup the kcache for this ALU instruction. This will start a new
1238 * ALU clause if needed. */
1239 if ((r = r600_bytecode_alloc_kcache_lines(bc, nalu, type))) {
1240 free(nalu);
1241 return r;
1242 }
1243
1244 if (!bc->cf_last->curr_bs_head) {
1245 bc->cf_last->curr_bs_head = nalu;
1246 }
1247 /* number of gpr == the last gpr used in any alu */
1248 for (i = 0; i < 3; i++) {
1249 if (nalu->src[i].sel >= bc->ngpr && nalu->src[i].sel < 128) {
1250 bc->ngpr = nalu->src[i].sel + 1;
1251 }
1252 if (nalu->src[i].sel == V_SQ_ALU_SRC_LITERAL)
1253 r600_bytecode_special_constants(nalu->src[i].value,
1254 &nalu->src[i].sel, &nalu->src[i].neg, nalu->src[i].abs);
1255 }
1256 if (nalu->dst.sel >= bc->ngpr) {
1257 bc->ngpr = nalu->dst.sel + 1;
1258 }
1259 LIST_ADDTAIL(&nalu->list, &bc->cf_last->alu);
1260 /* each alu use 2 dwords */
1261 bc->cf_last->ndw += 2;
1262 bc->ndw += 2;
1263
1264 /* process cur ALU instructions for bank swizzle */
1265 if (nalu->last) {
1266 uint32_t literal[4];
1267 unsigned nliteral;
1268 struct r600_bytecode_alu *slots[5];
1269 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
1270 r = assign_alu_units(bc, bc->cf_last->curr_bs_head, slots);
1271 if (r)
1272 return r;
1273
1274 if (bc->cf_last->prev_bs_head) {
1275 r = merge_inst_groups(bc, slots, bc->cf_last->prev_bs_head);
1276 if (r)
1277 return r;
1278 }
1279
1280 if (bc->cf_last->prev_bs_head) {
1281 r = replace_gpr_with_pv_ps(bc, slots, bc->cf_last->prev_bs_head);
1282 if (r)
1283 return r;
1284 }
1285
1286 r = check_and_set_bank_swizzle(bc, slots);
1287 if (r)
1288 return r;
1289
1290 for (i = 0, nliteral = 0; i < max_slots; i++) {
1291 if (slots[i]) {
1292 r = r600_bytecode_alu_nliterals(slots[i], literal, &nliteral);
1293 if (r)
1294 return r;
1295 }
1296 }
1297 bc->cf_last->ndw += align(nliteral, 2);
1298
1299 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1300 * worst case */
1301 if ((bc->cf_last->ndw >> 1) >= 120) {
1302 bc->force_add_cf = 1;
1303 }
1304
1305 bc->cf_last->prev2_bs_head = bc->cf_last->prev_bs_head;
1306 bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head;
1307 bc->cf_last->curr_bs_head = NULL;
1308 }
1309
1310 if (nalu->dst.rel && bc->r6xx_nop_after_rel_dst)
1311 insert_nop_r6xx(bc);
1312
1313 /* Might need to insert spill write ops after current clause */
1314 if (nalu->last && bc->n_pending_outputs) {
1315 while (bc->n_pending_outputs) {
1316 r = r600_bytecode_add_output(bc, &bc->pending_outputs[--bc->n_pending_outputs]);
1317 if (r)
1318 return r;
1319 }
1320 }
1321
1322 return 0;
1323 }
1324
1325 int r600_bytecode_add_alu(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu)
1326 {
1327 return r600_bytecode_add_alu_type(bc, alu, CF_OP_ALU);
1328 }
1329
1330 static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode *bc)
1331 {
1332 switch (bc->chip_class) {
1333 case R600:
1334 return 8;
1335
1336 case R700:
1337 case EVERGREEN:
1338 case CAYMAN:
1339 return 16;
1340
1341 default:
1342 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1343 return 8;
1344 }
1345 }
1346
1347 static inline boolean last_inst_was_not_vtx_fetch(struct r600_bytecode *bc)
1348 {
1349 return !((r600_isa_cf(bc->cf_last->op)->flags & CF_FETCH) &&
1350 bc->cf_last->op != CF_OP_GDS &&
1351 (bc->chip_class == CAYMAN ||
1352 bc->cf_last->op != CF_OP_TEX));
1353 }
1354
1355 static int r600_bytecode_add_vtx_internal(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx,
1356 bool use_tc)
1357 {
1358 struct r600_bytecode_vtx *nvtx = r600_bytecode_vtx();
1359 int r;
1360
1361 if (!nvtx)
1362 return -ENOMEM;
1363 memcpy(nvtx, vtx, sizeof(struct r600_bytecode_vtx));
1364
1365 /* Load index register if required */
1366 if (bc->chip_class >= EVERGREEN) {
1367 if (vtx->buffer_index_mode)
1368 egcm_load_index_reg(bc, vtx->buffer_index_mode - 1, false);
1369 }
1370
1371 /* cf can contains only alu or only vtx or only tex */
1372 if (bc->cf_last == NULL ||
1373 last_inst_was_not_vtx_fetch(bc) ||
1374 bc->force_add_cf) {
1375 r = r600_bytecode_add_cf(bc);
1376 if (r) {
1377 free(nvtx);
1378 return r;
1379 }
1380 switch (bc->chip_class) {
1381 case R600:
1382 case R700:
1383 bc->cf_last->op = CF_OP_VTX;
1384 break;
1385 case EVERGREEN:
1386 if (use_tc)
1387 bc->cf_last->op = CF_OP_TEX;
1388 else
1389 bc->cf_last->op = CF_OP_VTX;
1390 break;
1391 case CAYMAN:
1392 bc->cf_last->op = CF_OP_TEX;
1393 break;
1394 default:
1395 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1396 free(nvtx);
1397 return -EINVAL;
1398 }
1399 }
1400 LIST_ADDTAIL(&nvtx->list, &bc->cf_last->vtx);
1401 /* each fetch use 4 dwords */
1402 bc->cf_last->ndw += 4;
1403 bc->ndw += 4;
1404 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1405 bc->force_add_cf = 1;
1406
1407 bc->ngpr = MAX2(bc->ngpr, vtx->src_gpr + 1);
1408 bc->ngpr = MAX2(bc->ngpr, vtx->dst_gpr + 1);
1409
1410 return 0;
1411 }
1412
1413 int r600_bytecode_add_vtx(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx)
1414 {
1415 return r600_bytecode_add_vtx_internal(bc, vtx, false);
1416 }
1417
1418 int r600_bytecode_add_vtx_tc(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx)
1419 {
1420 return r600_bytecode_add_vtx_internal(bc, vtx, true);
1421 }
1422
1423 int r600_bytecode_add_tex(struct r600_bytecode *bc, const struct r600_bytecode_tex *tex)
1424 {
1425 struct r600_bytecode_tex *ntex = r600_bytecode_tex();
1426 int r;
1427
1428 if (!ntex)
1429 return -ENOMEM;
1430 memcpy(ntex, tex, sizeof(struct r600_bytecode_tex));
1431
1432 /* Load index register if required */
1433 if (bc->chip_class >= EVERGREEN) {
1434 if (tex->sampler_index_mode || tex->resource_index_mode)
1435 egcm_load_index_reg(bc, 1, false);
1436 }
1437
1438 /* we can't fetch data und use it as texture lookup address in the same TEX clause */
1439 if (bc->cf_last != NULL &&
1440 bc->cf_last->op == CF_OP_TEX) {
1441 struct r600_bytecode_tex *ttex;
1442 LIST_FOR_EACH_ENTRY(ttex, &bc->cf_last->tex, list) {
1443 if (ttex->dst_gpr == ntex->src_gpr) {
1444 bc->force_add_cf = 1;
1445 break;
1446 }
1447 }
1448 /* slight hack to make gradients always go into same cf */
1449 if (ntex->op == FETCH_OP_SET_GRADIENTS_H)
1450 bc->force_add_cf = 1;
1451 }
1452
1453 /* cf can contains only alu or only vtx or only tex */
1454 if (bc->cf_last == NULL ||
1455 bc->cf_last->op != CF_OP_TEX ||
1456 bc->force_add_cf) {
1457 r = r600_bytecode_add_cf(bc);
1458 if (r) {
1459 free(ntex);
1460 return r;
1461 }
1462 bc->cf_last->op = CF_OP_TEX;
1463 }
1464 if (ntex->src_gpr >= bc->ngpr) {
1465 bc->ngpr = ntex->src_gpr + 1;
1466 }
1467 if (ntex->dst_gpr >= bc->ngpr) {
1468 bc->ngpr = ntex->dst_gpr + 1;
1469 }
1470 LIST_ADDTAIL(&ntex->list, &bc->cf_last->tex);
1471 /* each texture fetch use 4 dwords */
1472 bc->cf_last->ndw += 4;
1473 bc->ndw += 4;
1474 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1475 bc->force_add_cf = 1;
1476 return 0;
1477 }
1478
1479 int r600_bytecode_add_gds(struct r600_bytecode *bc, const struct r600_bytecode_gds *gds)
1480 {
1481 struct r600_bytecode_gds *ngds = r600_bytecode_gds();
1482 int r;
1483
1484 if (ngds == NULL)
1485 return -ENOMEM;
1486 memcpy(ngds, gds, sizeof(struct r600_bytecode_gds));
1487
1488 if (bc->chip_class >= EVERGREEN) {
1489 if (gds->uav_index_mode)
1490 egcm_load_index_reg(bc, gds->uav_index_mode - 1, false);
1491 }
1492
1493 if (bc->cf_last == NULL ||
1494 bc->cf_last->op != CF_OP_GDS ||
1495 bc->force_add_cf) {
1496 r = r600_bytecode_add_cf(bc);
1497 if (r) {
1498 free(ngds);
1499 return r;
1500 }
1501 bc->cf_last->op = CF_OP_GDS;
1502 }
1503
1504 LIST_ADDTAIL(&ngds->list, &bc->cf_last->gds);
1505 bc->cf_last->ndw += 4; /* each GDS uses 4 dwords */
1506 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1507 bc->force_add_cf = 1;
1508 return 0;
1509 }
1510
1511 int r600_bytecode_add_cfinst(struct r600_bytecode *bc, unsigned op)
1512 {
1513 int r;
1514 r = r600_bytecode_add_cf(bc);
1515 if (r)
1516 return r;
1517
1518 bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
1519 bc->cf_last->op = op;
1520 return 0;
1521 }
1522
1523 int cm_bytecode_add_cf_end(struct r600_bytecode *bc)
1524 {
1525 return r600_bytecode_add_cfinst(bc, CF_OP_CF_END);
1526 }
1527
1528 /* common to all 3 families */
1529 static int r600_bytecode_vtx_build(struct r600_bytecode *bc, struct r600_bytecode_vtx *vtx, unsigned id)
1530 {
1531 if (r600_isa_fetch(vtx->op)->flags & FF_MEM)
1532 return r700_bytecode_fetch_mem_build(bc, vtx, id);
1533 bc->bytecode[id] = S_SQ_VTX_WORD0_VTX_INST(r600_isa_fetch_opcode(bc->isa->hw_class, vtx->op)) |
1534 S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) |
1535 S_SQ_VTX_WORD0_FETCH_TYPE(vtx->fetch_type) |
1536 S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
1537 S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x);
1538 if (bc->chip_class < CAYMAN)
1539 bc->bytecode[id] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
1540 id++;
1541 bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
1542 S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
1543 S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
1544 S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
1545 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) |
1546 S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) |
1547 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) |
1548 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) |
1549 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
1550 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
1551 bc->bytecode[id] = S_SQ_VTX_WORD2_OFFSET(vtx->offset)|
1552 S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx->endian);
1553 if (bc->chip_class >= EVERGREEN)
1554 bc->bytecode[id] |= ((vtx->buffer_index_mode & 0x3) << 21); // S_SQ_VTX_WORD2_BIM(vtx->buffer_index_mode);
1555 if (bc->chip_class < CAYMAN)
1556 bc->bytecode[id] |= S_SQ_VTX_WORD2_MEGA_FETCH(1);
1557 id++;
1558 bc->bytecode[id++] = 0;
1559 return 0;
1560 }
1561
1562 /* common to all 3 families */
1563 static int r600_bytecode_tex_build(struct r600_bytecode *bc, struct r600_bytecode_tex *tex, unsigned id)
1564 {
1565 bc->bytecode[id] = S_SQ_TEX_WORD0_TEX_INST(
1566 r600_isa_fetch_opcode(bc->isa->hw_class, tex->op)) |
1567 EG_S_SQ_TEX_WORD0_INST_MOD(tex->inst_mod) |
1568 S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
1569 S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
1570 S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
1571 if (bc->chip_class >= EVERGREEN)
1572 bc->bytecode[id] |= ((tex->sampler_index_mode & 0x3) << 27) | // S_SQ_TEX_WORD0_SIM(tex->sampler_index_mode);
1573 ((tex->resource_index_mode & 0x3) << 25); // S_SQ_TEX_WORD0_RIM(tex->resource_index_mode)
1574 id++;
1575 bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
1576 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
1577 S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
1578 S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
1579 S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
1580 S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
1581 S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
1582 S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
1583 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
1584 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
1585 S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
1586 bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
1587 S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
1588 S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
1589 S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
1590 S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
1591 S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
1592 S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
1593 S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
1594 bc->bytecode[id++] = 0;
1595 return 0;
1596 }
1597
1598 /* r600 only, r700/eg bits in r700_asm.c */
1599 static int r600_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id)
1600 {
1601 unsigned opcode = r600_isa_alu_opcode(bc->isa->hw_class, alu->op);
1602
1603 /* don't replace gpr by pv or ps for destination register */
1604 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
1605 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
1606 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
1607 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
1608 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
1609 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
1610 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
1611 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
1612 S_SQ_ALU_WORD0_INDEX_MODE(alu->index_mode) |
1613 S_SQ_ALU_WORD0_PRED_SEL(alu->pred_sel) |
1614 S_SQ_ALU_WORD0_LAST(alu->last);
1615
1616 if (alu->is_op3) {
1617 assert(!alu->src[0].abs && !alu->src[1].abs && !alu->src[2].abs);
1618 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1619 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1620 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1621 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1622 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
1623 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
1624 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
1625 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
1626 S_SQ_ALU_WORD1_OP3_ALU_INST(opcode) |
1627 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
1628 } else {
1629 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1630 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1631 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1632 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1633 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
1634 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
1635 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
1636 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
1637 S_SQ_ALU_WORD1_OP2_ALU_INST(opcode) |
1638 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
1639 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->execute_mask) |
1640 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->update_pred);
1641 }
1642 return 0;
1643 }
1644
1645 static void r600_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_cf *cf)
1646 {
1647 *bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
1648 *bytecode++ = S_SQ_CF_WORD1_CF_INST(r600_isa_cf_opcode(ISA_CC_R600, cf->op)) |
1649 S_SQ_CF_WORD1_BARRIER(1) |
1650 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1)|
1651 S_SQ_CF_WORD1_END_OF_PROGRAM(cf->end_of_program);
1652 }
1653
1654 /* common for r600/r700 - eg in eg_asm.c */
1655 static int r600_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf)
1656 {
1657 unsigned id = cf->id;
1658 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
1659 unsigned opcode = r600_isa_cf_opcode(bc->isa->hw_class, cf->op);
1660
1661
1662 if (cf->op == CF_NATIVE) {
1663 bc->bytecode[id++] = cf->isa[0];
1664 bc->bytecode[id++] = cf->isa[1];
1665 } else if (cfop->flags & CF_ALU) {
1666 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
1667 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
1668 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
1669 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank);
1670
1671 bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(opcode) |
1672 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) |
1673 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
1674 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
1675 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1676 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chip_class == R600 ? cf->r6xx_uses_waterfall : 0) |
1677 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
1678 } else if (cfop->flags & CF_FETCH) {
1679 if (bc->chip_class == R700)
1680 r700_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1681 else
1682 r600_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1683 } else if (cfop->flags & CF_EXP) {
1684 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1685 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1686 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1687 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type) |
1688 S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(cf->output.index_gpr);
1689 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1690 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
1691 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
1692 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
1693 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
1694 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->barrier) |
1695 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) |
1696 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->end_of_program);
1697 } else if (cfop->flags & CF_MEM) {
1698 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1699 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1700 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1701 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type) |
1702 S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(cf->output.index_gpr);
1703 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1704 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->barrier) |
1705 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) |
1706 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->end_of_program) |
1707 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf->output.array_size) |
1708 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf->output.comp_mask);
1709 } else {
1710 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
1711 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(opcode) |
1712 S_SQ_CF_WORD1_BARRIER(1) |
1713 S_SQ_CF_WORD1_COND(cf->cond) |
1714 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count) |
1715 S_SQ_CF_WORD1_END_OF_PROGRAM(cf->end_of_program);
1716 }
1717 return 0;
1718 }
1719
1720 int r600_bytecode_build(struct r600_bytecode *bc)
1721 {
1722 struct r600_bytecode_cf *cf;
1723 struct r600_bytecode_alu *alu;
1724 struct r600_bytecode_vtx *vtx;
1725 struct r600_bytecode_tex *tex;
1726 struct r600_bytecode_gds *gds;
1727 uint32_t literal[4];
1728 unsigned nliteral;
1729 unsigned addr;
1730 int i, r;
1731
1732 if (!bc->nstack) { // If not 0, Stack_size already provided by llvm
1733 if (bc->stack.max_entries)
1734 bc->nstack = bc->stack.max_entries;
1735 else if (bc->type == PIPE_SHADER_VERTEX ||
1736 bc->type == PIPE_SHADER_TESS_EVAL ||
1737 bc->type == PIPE_SHADER_TESS_CTRL)
1738 bc->nstack = 1;
1739 }
1740
1741 /* first path compute addr of each CF block */
1742 /* addr start after all the CF instructions */
1743 addr = bc->cf_last->id + 2;
1744 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1745 if (r600_isa_cf(cf->op)->flags & CF_FETCH) {
1746 addr += 3;
1747 addr &= 0xFFFFFFFCUL;
1748 }
1749 cf->addr = addr;
1750 addr += cf->ndw;
1751 bc->ndw = cf->addr + cf->ndw;
1752 }
1753 free(bc->bytecode);
1754 bc->bytecode = calloc(4, bc->ndw);
1755 if (bc->bytecode == NULL)
1756 return -ENOMEM;
1757 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1758 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
1759 addr = cf->addr;
1760 if (bc->chip_class >= EVERGREEN)
1761 r = eg_bytecode_cf_build(bc, cf);
1762 else
1763 r = r600_bytecode_cf_build(bc, cf);
1764 if (r)
1765 return r;
1766 if (cfop->flags & CF_ALU) {
1767 nliteral = 0;
1768 memset(literal, 0, sizeof(literal));
1769 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1770 r = r600_bytecode_alu_nliterals(alu, literal, &nliteral);
1771 if (r)
1772 return r;
1773 r600_bytecode_alu_adjust_literals(alu, literal, nliteral);
1774 r600_bytecode_assign_kcache_banks(alu, cf->kcache);
1775
1776 switch(bc->chip_class) {
1777 case R600:
1778 r = r600_bytecode_alu_build(bc, alu, addr);
1779 break;
1780 case R700:
1781 r = r700_bytecode_alu_build(bc, alu, addr);
1782 break;
1783 case EVERGREEN:
1784 case CAYMAN:
1785 r = eg_bytecode_alu_build(bc, alu, addr);
1786 break;
1787 default:
1788 R600_ERR("unknown chip class %d.\n", bc->chip_class);
1789 return -EINVAL;
1790 }
1791 if (r)
1792 return r;
1793 addr += 2;
1794 if (alu->last) {
1795 for (i = 0; i < align(nliteral, 2); ++i) {
1796 bc->bytecode[addr++] = literal[i];
1797 }
1798 nliteral = 0;
1799 memset(literal, 0, sizeof(literal));
1800 }
1801 }
1802 } else if (cf->op == CF_OP_VTX) {
1803 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1804 r = r600_bytecode_vtx_build(bc, vtx, addr);
1805 if (r)
1806 return r;
1807 addr += 4;
1808 }
1809 } else if (cf->op == CF_OP_GDS) {
1810 assert(bc->chip_class >= EVERGREEN);
1811 LIST_FOR_EACH_ENTRY(gds, &cf->gds, list) {
1812 r = eg_bytecode_gds_build(bc, gds, addr);
1813 if (r)
1814 return r;
1815 addr += 4;
1816 }
1817 } else if (cf->op == CF_OP_TEX) {
1818 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1819 assert(bc->chip_class >= EVERGREEN);
1820 r = r600_bytecode_vtx_build(bc, vtx, addr);
1821 if (r)
1822 return r;
1823 addr += 4;
1824 }
1825 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
1826 r = r600_bytecode_tex_build(bc, tex, addr);
1827 if (r)
1828 return r;
1829 addr += 4;
1830 }
1831 }
1832 }
1833 return 0;
1834 }
1835
1836 void r600_bytecode_clear(struct r600_bytecode *bc)
1837 {
1838 struct r600_bytecode_cf *cf = NULL, *next_cf;
1839
1840 free(bc->bytecode);
1841 bc->bytecode = NULL;
1842
1843 LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
1844 struct r600_bytecode_alu *alu = NULL, *next_alu;
1845 struct r600_bytecode_tex *tex = NULL, *next_tex;
1846 struct r600_bytecode_tex *vtx = NULL, *next_vtx;
1847 struct r600_bytecode_gds *gds = NULL, *next_gds;
1848
1849 LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
1850 free(alu);
1851 }
1852
1853 LIST_INITHEAD(&cf->alu);
1854
1855 LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) {
1856 free(tex);
1857 }
1858
1859 LIST_INITHEAD(&cf->tex);
1860
1861 LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) {
1862 free(vtx);
1863 }
1864
1865 LIST_INITHEAD(&cf->vtx);
1866
1867 LIST_FOR_EACH_ENTRY_SAFE(gds, next_gds, &cf->gds, list) {
1868 free(gds);
1869 }
1870
1871 LIST_INITHEAD(&cf->gds);
1872
1873 free(cf);
1874 }
1875
1876 LIST_INITHEAD(&cf->list);
1877 }
1878
1879 static int print_swizzle(unsigned swz)
1880 {
1881 const char * swzchars = "xyzw01?_";
1882 assert(swz<8 && swz != 6);
1883 return fprintf(stderr, "%c", swzchars[swz]);
1884 }
1885
1886 static int print_sel(unsigned sel, unsigned rel, unsigned index_mode,
1887 unsigned need_brackets)
1888 {
1889 int o = 0;
1890 if (rel && index_mode >= 5 && sel < 128)
1891 o += fprintf(stderr, "G");
1892 if (rel || need_brackets) {
1893 o += fprintf(stderr, "[");
1894 }
1895 o += fprintf(stderr, "%d", sel);
1896 if (rel) {
1897 if (index_mode == 0 || index_mode == 6)
1898 o += fprintf(stderr, "+AR");
1899 else if (index_mode == 4)
1900 o += fprintf(stderr, "+AL");
1901 }
1902 if (rel || need_brackets) {
1903 o += fprintf(stderr, "]");
1904 }
1905 return o;
1906 }
1907
1908 static int print_dst(struct r600_bytecode_alu *alu)
1909 {
1910 int o = 0;
1911 unsigned sel = alu->dst.sel;
1912 char reg_char = 'R';
1913 if (sel > 128 - 4) { /* clause temporary gpr */
1914 sel -= 128 - 4;
1915 reg_char = 'T';
1916 }
1917
1918 if (alu_writes(alu)) {
1919 o += fprintf(stderr, "%c", reg_char);
1920 o += print_sel(alu->dst.sel, alu->dst.rel, alu->index_mode, 0);
1921 } else {
1922 o += fprintf(stderr, "__");
1923 }
1924 o += fprintf(stderr, ".");
1925 o += print_swizzle(alu->dst.chan);
1926 return o;
1927 }
1928
1929 static int print_src(struct r600_bytecode_alu *alu, unsigned idx)
1930 {
1931 int o = 0;
1932 struct r600_bytecode_alu_src *src = &alu->src[idx];
1933 unsigned sel = src->sel, need_sel = 1, need_chan = 1, need_brackets = 0;
1934
1935 if (src->neg)
1936 o += fprintf(stderr,"-");
1937 if (src->abs)
1938 o += fprintf(stderr,"|");
1939
1940 if (sel < 128 - 4) {
1941 o += fprintf(stderr, "R");
1942 } else if (sel < 128) {
1943 o += fprintf(stderr, "T");
1944 sel -= 128 - 4;
1945 } else if (sel < 160) {
1946 o += fprintf(stderr, "KC0");
1947 need_brackets = 1;
1948 sel -= 128;
1949 } else if (sel < 192) {
1950 o += fprintf(stderr, "KC1");
1951 need_brackets = 1;
1952 sel -= 160;
1953 } else if (sel >= 512) {
1954 o += fprintf(stderr, "C%d", src->kc_bank);
1955 need_brackets = 1;
1956 sel -= 512;
1957 } else if (sel >= 448) {
1958 o += fprintf(stderr, "Param");
1959 sel -= 448;
1960 need_chan = 0;
1961 } else if (sel >= 288) {
1962 o += fprintf(stderr, "KC3");
1963 need_brackets = 1;
1964 sel -= 288;
1965 } else if (sel >= 256) {
1966 o += fprintf(stderr, "KC2");
1967 need_brackets = 1;
1968 sel -= 256;
1969 } else {
1970 need_sel = 0;
1971 need_chan = 0;
1972 switch (sel) {
1973 case EG_V_SQ_ALU_SRC_LDS_DIRECT_A:
1974 o += fprintf(stderr, "LDS_A[0x%08X]", src->value);
1975 break;
1976 case EG_V_SQ_ALU_SRC_LDS_DIRECT_B:
1977 o += fprintf(stderr, "LDS_B[0x%08X]", src->value);
1978 break;
1979 case EG_V_SQ_ALU_SRC_LDS_OQ_A:
1980 o += fprintf(stderr, "LDS_OQ_A");
1981 need_chan = 1;
1982 break;
1983 case EG_V_SQ_ALU_SRC_LDS_OQ_B:
1984 o += fprintf(stderr, "LDS_OQ_B");
1985 need_chan = 1;
1986 break;
1987 case EG_V_SQ_ALU_SRC_LDS_OQ_A_POP:
1988 o += fprintf(stderr, "LDS_OQ_A_POP");
1989 need_chan = 1;
1990 break;
1991 case EG_V_SQ_ALU_SRC_LDS_OQ_B_POP:
1992 o += fprintf(stderr, "LDS_OQ_B_POP");
1993 need_chan = 1;
1994 break;
1995 case EG_V_SQ_ALU_SRC_SE_ID:
1996 o += fprintf(stderr, "SE_ID");
1997 break;
1998 case EG_V_SQ_ALU_SRC_SIMD_ID:
1999 o += fprintf(stderr, "SIMD_ID");
2000 break;
2001 case EG_V_SQ_ALU_SRC_HW_WAVE_ID:
2002 o += fprintf(stderr, "HW_WAVE_ID");
2003 break;
2004 case V_SQ_ALU_SRC_PS:
2005 o += fprintf(stderr, "PS");
2006 break;
2007 case V_SQ_ALU_SRC_PV:
2008 o += fprintf(stderr, "PV");
2009 need_chan = 1;
2010 break;
2011 case V_SQ_ALU_SRC_LITERAL:
2012 o += fprintf(stderr, "[0x%08X %f]", src->value, u_bitcast_u2f(src->value));
2013 break;
2014 case V_SQ_ALU_SRC_0_5:
2015 o += fprintf(stderr, "0.5");
2016 break;
2017 case V_SQ_ALU_SRC_M_1_INT:
2018 o += fprintf(stderr, "-1");
2019 break;
2020 case V_SQ_ALU_SRC_1_INT:
2021 o += fprintf(stderr, "1");
2022 break;
2023 case V_SQ_ALU_SRC_1:
2024 o += fprintf(stderr, "1.0");
2025 break;
2026 case V_SQ_ALU_SRC_0:
2027 o += fprintf(stderr, "0");
2028 break;
2029 default:
2030 o += fprintf(stderr, "??IMM_%d", sel);
2031 break;
2032 }
2033 }
2034
2035 if (need_sel)
2036 o += print_sel(sel, src->rel, alu->index_mode, need_brackets);
2037
2038 if (need_chan) {
2039 o += fprintf(stderr, ".");
2040 o += print_swizzle(src->chan);
2041 }
2042
2043 if (src->abs)
2044 o += fprintf(stderr,"|");
2045
2046 return o;
2047 }
2048
2049 static int print_indent(int p, int c)
2050 {
2051 int o = 0;
2052 while (p++ < c)
2053 o += fprintf(stderr, " ");
2054 return o;
2055 }
2056
2057 void r600_bytecode_disasm(struct r600_bytecode *bc)
2058 {
2059 const char *index_mode[] = {"CF_INDEX_NONE", "CF_INDEX_0", "CF_INDEX_1"};
2060 static int index = 0;
2061 struct r600_bytecode_cf *cf = NULL;
2062 struct r600_bytecode_alu *alu = NULL;
2063 struct r600_bytecode_vtx *vtx = NULL;
2064 struct r600_bytecode_tex *tex = NULL;
2065 struct r600_bytecode_gds *gds = NULL;
2066
2067 unsigned i, id, ngr = 0, last;
2068 uint32_t literal[4];
2069 unsigned nliteral;
2070 char chip = '6';
2071
2072 switch (bc->chip_class) {
2073 case R700:
2074 chip = '7';
2075 break;
2076 case EVERGREEN:
2077 chip = 'E';
2078 break;
2079 case CAYMAN:
2080 chip = 'C';
2081 break;
2082 case R600:
2083 default:
2084 chip = '6';
2085 break;
2086 }
2087 fprintf(stderr, "bytecode %d dw -- %d gprs -- %d nstack -------------\n",
2088 bc->ndw, bc->ngpr, bc->nstack);
2089 fprintf(stderr, "shader %d -- %c\n", index++, chip);
2090
2091 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
2092 id = cf->id;
2093 if (cf->op == CF_NATIVE) {
2094 fprintf(stderr, "%04d %08X %08X CF_NATIVE\n", id, bc->bytecode[id],
2095 bc->bytecode[id + 1]);
2096 } else {
2097 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
2098 if (cfop->flags & CF_ALU) {
2099 if (cf->eg_alu_extended) {
2100 fprintf(stderr, "%04d %08X %08X %s\n", id, bc->bytecode[id],
2101 bc->bytecode[id + 1], "ALU_EXT");
2102 id += 2;
2103 }
2104 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
2105 bc->bytecode[id + 1], cfop->name);
2106 fprintf(stderr, "%d @%d ", cf->ndw / 2, cf->addr);
2107 for (i = 0; i < 4; ++i) {
2108 if (cf->kcache[i].mode) {
2109 int c_start = (cf->kcache[i].addr << 4);
2110 int c_end = c_start + (cf->kcache[i].mode << 4);
2111 fprintf(stderr, "KC%d[CB%d:%d-%d%s%s] ",
2112 i, cf->kcache[i].bank, c_start, c_end,
2113 cf->kcache[i].index_mode ? " " : "",
2114 cf->kcache[i].index_mode ? index_mode[cf->kcache[i].index_mode] : "");
2115 }
2116 }
2117 fprintf(stderr, "\n");
2118 } else if (cfop->flags & CF_FETCH) {
2119 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
2120 bc->bytecode[id + 1], cfop->name);
2121 fprintf(stderr, "%d @%d ", cf->ndw / 4, cf->addr);
2122 if (cf->vpm)
2123 fprintf(stderr, "VPM ");
2124 if (cf->end_of_program)
2125 fprintf(stderr, "EOP ");
2126 fprintf(stderr, "\n");
2127
2128 } else if (cfop->flags & CF_EXP) {
2129 int o = 0;
2130 const char *exp_type[] = {"PIXEL", "POS ", "PARAM"};
2131 o += fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
2132 bc->bytecode[id + 1], cfop->name);
2133 o += print_indent(o, 43);
2134 o += fprintf(stderr, "%s ", exp_type[cf->output.type]);
2135 if (cf->output.burst_count > 1) {
2136 o += fprintf(stderr, "%d-%d ", cf->output.array_base,
2137 cf->output.array_base + cf->output.burst_count - 1);
2138
2139 o += print_indent(o, 55);
2140 o += fprintf(stderr, "R%d-%d.", cf->output.gpr,
2141 cf->output.gpr + cf->output.burst_count - 1);
2142 } else {
2143 o += fprintf(stderr, "%d ", cf->output.array_base);
2144 o += print_indent(o, 55);
2145 o += fprintf(stderr, "R%d.", cf->output.gpr);
2146 }
2147
2148 o += print_swizzle(cf->output.swizzle_x);
2149 o += print_swizzle(cf->output.swizzle_y);
2150 o += print_swizzle(cf->output.swizzle_z);
2151 o += print_swizzle(cf->output.swizzle_w);
2152
2153 print_indent(o, 67);
2154
2155 fprintf(stderr, " ES:%X ", cf->output.elem_size);
2156 if (cf->mark)
2157 fprintf(stderr, "MARK ");
2158 if (!cf->barrier)
2159 fprintf(stderr, "NO_BARRIER ");
2160 if (cf->end_of_program)
2161 fprintf(stderr, "EOP ");
2162 fprintf(stderr, "\n");
2163 } else if (r600_isa_cf(cf->op)->flags & CF_MEM) {
2164 int o = 0;
2165 const char *exp_type[] = {"WRITE", "WRITE_IND", "WRITE_ACK",
2166 "WRITE_IND_ACK"};
2167 o += fprintf(stderr, "%04d %08X %08X %s ", id,
2168 bc->bytecode[id], bc->bytecode[id + 1], cfop->name);
2169 o += print_indent(o, 43);
2170 o += fprintf(stderr, "%s ", exp_type[cf->output.type]);
2171
2172 if (r600_isa_cf(cf->op)->flags & CF_RAT) {
2173 o += fprintf(stderr, "RAT%d", cf->rat.id);
2174 if (cf->rat.index_mode) {
2175 o += fprintf(stderr, "[IDX%d]", cf->rat.index_mode - 1);
2176 }
2177 o += fprintf(stderr, " INST: %d ", cf->rat.inst);
2178 }
2179
2180 if (cf->output.burst_count > 1) {
2181 o += fprintf(stderr, "%d-%d ", cf->output.array_base,
2182 cf->output.array_base + cf->output.burst_count - 1);
2183 o += print_indent(o, 55);
2184 o += fprintf(stderr, "R%d-%d.", cf->output.gpr,
2185 cf->output.gpr + cf->output.burst_count - 1);
2186 } else {
2187 o += fprintf(stderr, "%d ", cf->output.array_base);
2188 o += print_indent(o, 55);
2189 o += fprintf(stderr, "R%d.", cf->output.gpr);
2190 }
2191 for (i = 0; i < 4; ++i) {
2192 if (cf->output.comp_mask & (1 << i))
2193 o += print_swizzle(i);
2194 else
2195 o += print_swizzle(7);
2196 }
2197
2198 if (cf->output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND ||
2199 cf->output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND)
2200 o += fprintf(stderr, " R%d", cf->output.index_gpr);
2201
2202 o += print_indent(o, 67);
2203
2204 fprintf(stderr, " ES:%i ", cf->output.elem_size);
2205 if (cf->output.array_size != 0xFFF)
2206 fprintf(stderr, "AS:%i ", cf->output.array_size);
2207 if (cf->mark)
2208 fprintf(stderr, "MARK ");
2209 if (!cf->barrier)
2210 fprintf(stderr, "NO_BARRIER ");
2211 if (cf->end_of_program)
2212 fprintf(stderr, "EOP ");
2213
2214 if (cf->output.mark)
2215 fprintf(stderr, "MARK ");
2216
2217 fprintf(stderr, "\n");
2218 } else {
2219 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
2220 bc->bytecode[id + 1], cfop->name);
2221 fprintf(stderr, "@%d ", cf->cf_addr);
2222 if (cf->cond)
2223 fprintf(stderr, "CND:%X ", cf->cond);
2224 if (cf->pop_count)
2225 fprintf(stderr, "POP:%X ", cf->pop_count);
2226 if (cf->count && (cfop->flags & CF_EMIT))
2227 fprintf(stderr, "STREAM%d ", cf->count);
2228 if (cf->vpm)
2229 fprintf(stderr, "VPM ");
2230 if (cf->end_of_program)
2231 fprintf(stderr, "EOP ");
2232 fprintf(stderr, "\n");
2233 }
2234 }
2235
2236 id = cf->addr;
2237 nliteral = 0;
2238 last = 1;
2239 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
2240 const char *omod_str[] = {"","*2","*4","/2"};
2241 const struct alu_op_info *aop = r600_isa_alu(alu->op);
2242 int o = 0;
2243
2244 r600_bytecode_alu_nliterals(alu, literal, &nliteral);
2245 o += fprintf(stderr, " %04d %08X %08X ", id, bc->bytecode[id], bc->bytecode[id+1]);
2246 if (last)
2247 o += fprintf(stderr, "%4d ", ++ngr);
2248 else
2249 o += fprintf(stderr, " ");
2250 o += fprintf(stderr, "%c%c %c ", alu->execute_mask ? 'M':' ',
2251 alu->update_pred ? 'P':' ',
2252 alu->pred_sel ? alu->pred_sel==2 ? '0':'1':' ');
2253
2254 o += fprintf(stderr, "%s%s%s ", aop->name,
2255 omod_str[alu->omod], alu->dst.clamp ? "_sat":"");
2256
2257 o += print_indent(o,60);
2258 o += print_dst(alu);
2259 for (i = 0; i < aop->src_count; ++i) {
2260 o += fprintf(stderr, i == 0 ? ", ": ", ");
2261 o += print_src(alu, i);
2262 }
2263
2264 if (alu->bank_swizzle) {
2265 o += print_indent(o,75);
2266 o += fprintf(stderr, " BS:%d", alu->bank_swizzle);
2267 }
2268
2269 fprintf(stderr, "\n");
2270 id += 2;
2271
2272 if (alu->last) {
2273 for (i = 0; i < nliteral; i++, id++) {
2274 float *f = (float*)(bc->bytecode + id);
2275 o = fprintf(stderr, " %04d %08X", id, bc->bytecode[id]);
2276 print_indent(o, 60);
2277 fprintf(stderr, " %f (%d)\n", *f, *(bc->bytecode + id));
2278 }
2279 id += nliteral & 1;
2280 nliteral = 0;
2281 }
2282 last = alu->last;
2283 }
2284
2285 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2286 int o = 0;
2287 o += fprintf(stderr, " %04d %08X %08X %08X ", id, bc->bytecode[id],
2288 bc->bytecode[id + 1], bc->bytecode[id + 2]);
2289
2290 o += fprintf(stderr, "%s ", r600_isa_fetch(tex->op)->name);
2291
2292 o += print_indent(o, 50);
2293
2294 o += fprintf(stderr, "R%d.", tex->dst_gpr);
2295 o += print_swizzle(tex->dst_sel_x);
2296 o += print_swizzle(tex->dst_sel_y);
2297 o += print_swizzle(tex->dst_sel_z);
2298 o += print_swizzle(tex->dst_sel_w);
2299
2300 o += fprintf(stderr, ", R%d.", tex->src_gpr);
2301 o += print_swizzle(tex->src_sel_x);
2302 o += print_swizzle(tex->src_sel_y);
2303 o += print_swizzle(tex->src_sel_z);
2304 o += print_swizzle(tex->src_sel_w);
2305
2306 o += fprintf(stderr, ", RID:%d", tex->resource_id);
2307 o += fprintf(stderr, ", SID:%d ", tex->sampler_id);
2308
2309 if (tex->sampler_index_mode)
2310 fprintf(stderr, "SQ_%s ", index_mode[tex->sampler_index_mode]);
2311
2312 if (tex->lod_bias)
2313 fprintf(stderr, "LB:%d ", tex->lod_bias);
2314
2315 fprintf(stderr, "CT:%c%c%c%c ",
2316 tex->coord_type_x ? 'N' : 'U',
2317 tex->coord_type_y ? 'N' : 'U',
2318 tex->coord_type_z ? 'N' : 'U',
2319 tex->coord_type_w ? 'N' : 'U');
2320
2321 if (tex->offset_x)
2322 fprintf(stderr, "OX:%d ", tex->offset_x);
2323 if (tex->offset_y)
2324 fprintf(stderr, "OY:%d ", tex->offset_y);
2325 if (tex->offset_z)
2326 fprintf(stderr, "OZ:%d ", tex->offset_z);
2327
2328 id += 4;
2329 fprintf(stderr, "\n");
2330 }
2331
2332 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2333 int o = 0;
2334 const char * fetch_type[] = {"VERTEX", "INSTANCE", ""};
2335 o += fprintf(stderr, " %04d %08X %08X %08X ", id, bc->bytecode[id],
2336 bc->bytecode[id + 1], bc->bytecode[id + 2]);
2337
2338 o += fprintf(stderr, "%s ", r600_isa_fetch(vtx->op)->name);
2339
2340 o += print_indent(o, 50);
2341
2342 o += fprintf(stderr, "R%d.", vtx->dst_gpr);
2343 o += print_swizzle(vtx->dst_sel_x);
2344 o += print_swizzle(vtx->dst_sel_y);
2345 o += print_swizzle(vtx->dst_sel_z);
2346 o += print_swizzle(vtx->dst_sel_w);
2347
2348 o += fprintf(stderr, ", R%d.", vtx->src_gpr);
2349 o += print_swizzle(vtx->src_sel_x);
2350 if (r600_isa_fetch(vtx->op)->flags & FF_MEM)
2351 o += print_swizzle(vtx->src_sel_y);
2352
2353 if (vtx->offset)
2354 fprintf(stderr, " +%db", vtx->offset);
2355
2356 o += print_indent(o, 55);
2357
2358 fprintf(stderr, ", RID:%d ", vtx->buffer_id);
2359
2360 fprintf(stderr, "%s ", fetch_type[vtx->fetch_type]);
2361
2362 if (bc->chip_class < CAYMAN && vtx->mega_fetch_count)
2363 fprintf(stderr, "MFC:%d ", vtx->mega_fetch_count);
2364
2365 if (bc->chip_class >= EVERGREEN && vtx->buffer_index_mode)
2366 fprintf(stderr, "SQ_%s ", index_mode[vtx->buffer_index_mode]);
2367
2368 if (r600_isa_fetch(vtx->op)->flags & FF_MEM) {
2369 if (vtx->uncached)
2370 fprintf(stderr, "UNCACHED ");
2371 if (vtx->indexed)
2372 fprintf(stderr, "INDEXED:%d ", vtx->indexed);
2373
2374 fprintf(stderr, "ELEM_SIZE:%d ", vtx->elem_size);
2375 if (vtx->burst_count)
2376 fprintf(stderr, "BURST_COUNT:%d ", vtx->burst_count);
2377 fprintf(stderr, "ARRAY_BASE:%d ", vtx->array_base);
2378 fprintf(stderr, "ARRAY_SIZE:%d ", vtx->array_size);
2379 }
2380
2381 fprintf(stderr, "UCF:%d ", vtx->use_const_fields);
2382 fprintf(stderr, "FMT(DTA:%d ", vtx->data_format);
2383 fprintf(stderr, "NUM:%d ", vtx->num_format_all);
2384 fprintf(stderr, "COMP:%d ", vtx->format_comp_all);
2385 fprintf(stderr, "MODE:%d)\n", vtx->srf_mode_all);
2386
2387 id += 4;
2388 }
2389
2390 LIST_FOR_EACH_ENTRY(gds, &cf->gds, list) {
2391 int o = 0;
2392 o += fprintf(stderr, " %04d %08X %08X %08X ", id, bc->bytecode[id],
2393 bc->bytecode[id + 1], bc->bytecode[id + 2]);
2394
2395 o += fprintf(stderr, "%s ", r600_isa_fetch(gds->op)->name);
2396
2397 if (gds->op != FETCH_OP_TF_WRITE) {
2398 o += fprintf(stderr, "R%d.", gds->dst_gpr);
2399 o += print_swizzle(gds->dst_sel_x);
2400 o += print_swizzle(gds->dst_sel_y);
2401 o += print_swizzle(gds->dst_sel_z);
2402 o += print_swizzle(gds->dst_sel_w);
2403 }
2404
2405 o += fprintf(stderr, ", R%d.", gds->src_gpr);
2406 o += print_swizzle(gds->src_sel_x);
2407 o += print_swizzle(gds->src_sel_y);
2408 o += print_swizzle(gds->src_sel_z);
2409
2410 if (gds->op != FETCH_OP_TF_WRITE) {
2411 o += fprintf(stderr, ", R%d.", gds->src_gpr2);
2412 }
2413 if (gds->alloc_consume) {
2414 o += fprintf(stderr, " UAV: %d", gds->uav_id);
2415 if (gds->uav_index_mode)
2416 o += fprintf(stderr, "[%s]", index_mode[gds->uav_index_mode]);
2417 }
2418 fprintf(stderr, "\n");
2419 id += 4;
2420 }
2421 }
2422
2423 fprintf(stderr, "--------------------------------------\n");
2424 }
2425
2426 void r600_vertex_data_type(enum pipe_format pformat,
2427 unsigned *format,
2428 unsigned *num_format, unsigned *format_comp, unsigned *endian)
2429 {
2430 const struct util_format_description *desc;
2431 unsigned i;
2432
2433 *format = 0;
2434 *num_format = 0;
2435 *format_comp = 0;
2436 *endian = ENDIAN_NONE;
2437
2438 if (pformat == PIPE_FORMAT_R11G11B10_FLOAT) {
2439 *format = FMT_10_11_11_FLOAT;
2440 *endian = r600_endian_swap(32);
2441 return;
2442 }
2443
2444 if (pformat == PIPE_FORMAT_B5G6R5_UNORM) {
2445 *format = FMT_5_6_5;
2446 *endian = r600_endian_swap(16);
2447 return;
2448 }
2449
2450 if (pformat == PIPE_FORMAT_B5G5R5A1_UNORM) {
2451 *format = FMT_1_5_5_5;
2452 *endian = r600_endian_swap(16);
2453 return;
2454 }
2455
2456 desc = util_format_description(pformat);
2457 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
2458 goto out_unknown;
2459 }
2460
2461 /* Find the first non-VOID channel. */
2462 for (i = 0; i < 4; i++) {
2463 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2464 break;
2465 }
2466 }
2467
2468 *endian = r600_endian_swap(desc->channel[i].size);
2469
2470 switch (desc->channel[i].type) {
2471 /* Half-floats, floats, ints */
2472 case UTIL_FORMAT_TYPE_FLOAT:
2473 switch (desc->channel[i].size) {
2474 case 16:
2475 switch (desc->nr_channels) {
2476 case 1:
2477 *format = FMT_16_FLOAT;
2478 break;
2479 case 2:
2480 *format = FMT_16_16_FLOAT;
2481 break;
2482 case 3:
2483 case 4:
2484 *format = FMT_16_16_16_16_FLOAT;
2485 break;
2486 }
2487 break;
2488 case 32:
2489 switch (desc->nr_channels) {
2490 case 1:
2491 *format = FMT_32_FLOAT;
2492 break;
2493 case 2:
2494 *format = FMT_32_32_FLOAT;
2495 break;
2496 case 3:
2497 *format = FMT_32_32_32_FLOAT;
2498 break;
2499 case 4:
2500 *format = FMT_32_32_32_32_FLOAT;
2501 break;
2502 }
2503 break;
2504 default:
2505 goto out_unknown;
2506 }
2507 break;
2508 /* Unsigned ints */
2509 case UTIL_FORMAT_TYPE_UNSIGNED:
2510 /* Signed ints */
2511 case UTIL_FORMAT_TYPE_SIGNED:
2512 switch (desc->channel[i].size) {
2513 case 8:
2514 switch (desc->nr_channels) {
2515 case 1:
2516 *format = FMT_8;
2517 break;
2518 case 2:
2519 *format = FMT_8_8;
2520 break;
2521 case 3:
2522 case 4:
2523 *format = FMT_8_8_8_8;
2524 break;
2525 }
2526 break;
2527 case 10:
2528 if (desc->nr_channels != 4)
2529 goto out_unknown;
2530
2531 *format = FMT_2_10_10_10;
2532 break;
2533 case 16:
2534 switch (desc->nr_channels) {
2535 case 1:
2536 *format = FMT_16;
2537 break;
2538 case 2:
2539 *format = FMT_16_16;
2540 break;
2541 case 3:
2542 case 4:
2543 *format = FMT_16_16_16_16;
2544 break;
2545 }
2546 break;
2547 case 32:
2548 switch (desc->nr_channels) {
2549 case 1:
2550 *format = FMT_32;
2551 break;
2552 case 2:
2553 *format = FMT_32_32;
2554 break;
2555 case 3:
2556 *format = FMT_32_32_32;
2557 break;
2558 case 4:
2559 *format = FMT_32_32_32_32;
2560 break;
2561 }
2562 break;
2563 default:
2564 goto out_unknown;
2565 }
2566 break;
2567 default:
2568 goto out_unknown;
2569 }
2570
2571 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2572 *format_comp = 1;
2573 }
2574
2575 *num_format = 0;
2576 if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED ||
2577 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2578 if (!desc->channel[i].normalized) {
2579 if (desc->channel[i].pure_integer)
2580 *num_format = 1;
2581 else
2582 *num_format = 2;
2583 }
2584 }
2585 return;
2586 out_unknown:
2587 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
2588 }
2589
2590 void *r600_create_vertex_fetch_shader(struct pipe_context *ctx,
2591 unsigned count,
2592 const struct pipe_vertex_element *elements)
2593 {
2594 struct r600_context *rctx = (struct r600_context *)ctx;
2595 struct r600_bytecode bc;
2596 struct r600_bytecode_vtx vtx;
2597 const struct util_format_description *desc;
2598 unsigned fetch_resource_start = rctx->b.chip_class >= EVERGREEN ? 0 : 160;
2599 unsigned format, num_format, format_comp, endian;
2600 uint32_t *bytecode;
2601 int i, j, r, fs_size;
2602 struct r600_fetch_shader *shader;
2603 unsigned no_sb = rctx->screen->b.debug_flags & DBG_NO_SB;
2604 unsigned sb_disasm = !no_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
2605
2606 assert(count < 32);
2607
2608 memset(&bc, 0, sizeof(bc));
2609 r600_bytecode_init(&bc, rctx->b.chip_class, rctx->b.family,
2610 rctx->screen->has_compressed_msaa_texturing);
2611
2612 bc.isa = rctx->isa;
2613
2614 for (i = 0; i < count; i++) {
2615 if (elements[i].instance_divisor > 1) {
2616 if (rctx->b.chip_class == CAYMAN) {
2617 for (j = 0; j < 4; j++) {
2618 struct r600_bytecode_alu alu;
2619 memset(&alu, 0, sizeof(alu));
2620 alu.op = ALU_OP2_MULHI_UINT;
2621 alu.src[0].sel = 0;
2622 alu.src[0].chan = 3;
2623 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2624 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2625 alu.dst.sel = i + 1;
2626 alu.dst.chan = j;
2627 alu.dst.write = j == 3;
2628 alu.last = j == 3;
2629 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2630 r600_bytecode_clear(&bc);
2631 return NULL;
2632 }
2633 }
2634 } else {
2635 struct r600_bytecode_alu alu;
2636 memset(&alu, 0, sizeof(alu));
2637 alu.op = ALU_OP2_MULHI_UINT;
2638 alu.src[0].sel = 0;
2639 alu.src[0].chan = 3;
2640 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2641 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2642 alu.dst.sel = i + 1;
2643 alu.dst.chan = 3;
2644 alu.dst.write = 1;
2645 alu.last = 1;
2646 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2647 r600_bytecode_clear(&bc);
2648 return NULL;
2649 }
2650 }
2651 }
2652 }
2653
2654 for (i = 0; i < count; i++) {
2655 r600_vertex_data_type(elements[i].src_format,
2656 &format, &num_format, &format_comp, &endian);
2657
2658 desc = util_format_description(elements[i].src_format);
2659 if (!desc) {
2660 r600_bytecode_clear(&bc);
2661 R600_ERR("unknown format %d\n", elements[i].src_format);
2662 return NULL;
2663 }
2664
2665 if (elements[i].src_offset > 65535) {
2666 r600_bytecode_clear(&bc);
2667 R600_ERR("too big src_offset: %u\n", elements[i].src_offset);
2668 return NULL;
2669 }
2670
2671 memset(&vtx, 0, sizeof(vtx));
2672 vtx.buffer_id = elements[i].vertex_buffer_index + fetch_resource_start;
2673 vtx.fetch_type = elements[i].instance_divisor ? SQ_VTX_FETCH_INSTANCE_DATA : SQ_VTX_FETCH_VERTEX_DATA;
2674 vtx.src_gpr = elements[i].instance_divisor > 1 ? i + 1 : 0;
2675 vtx.src_sel_x = elements[i].instance_divisor ? 3 : 0;
2676 vtx.mega_fetch_count = 0x1F;
2677 vtx.dst_gpr = i + 1;
2678 vtx.dst_sel_x = desc->swizzle[0];
2679 vtx.dst_sel_y = desc->swizzle[1];
2680 vtx.dst_sel_z = desc->swizzle[2];
2681 vtx.dst_sel_w = desc->swizzle[3];
2682 vtx.data_format = format;
2683 vtx.num_format_all = num_format;
2684 vtx.format_comp_all = format_comp;
2685 vtx.offset = elements[i].src_offset;
2686 vtx.endian = endian;
2687
2688 if ((r = r600_bytecode_add_vtx(&bc, &vtx))) {
2689 r600_bytecode_clear(&bc);
2690 return NULL;
2691 }
2692 }
2693
2694 r600_bytecode_add_cfinst(&bc, CF_OP_RET);
2695
2696 if ((r = r600_bytecode_build(&bc))) {
2697 r600_bytecode_clear(&bc);
2698 return NULL;
2699 }
2700
2701 if (rctx->screen->b.debug_flags & DBG_FS) {
2702 fprintf(stderr, "--------------------------------------------------------------\n");
2703 fprintf(stderr, "Vertex elements state:\n");
2704 for (i = 0; i < count; i++) {
2705 fprintf(stderr, " ");
2706 util_dump_vertex_element(stderr, elements+i);
2707 fprintf(stderr, "\n");
2708 }
2709
2710 if (!sb_disasm) {
2711 r600_bytecode_disasm(&bc);
2712
2713 fprintf(stderr, "______________________________________________________________\n");
2714 } else {
2715 r600_sb_bytecode_process(rctx, &bc, NULL, 1 /*dump*/, 0 /*optimize*/);
2716 }
2717 }
2718
2719 fs_size = bc.ndw*4;
2720
2721 /* Allocate the CSO. */
2722 shader = CALLOC_STRUCT(r600_fetch_shader);
2723 if (!shader) {
2724 r600_bytecode_clear(&bc);
2725 return NULL;
2726 }
2727
2728 u_suballocator_alloc(rctx->allocator_fetch_shader, fs_size, 256,
2729 &shader->offset,
2730 (struct pipe_resource**)&shader->buffer);
2731 if (!shader->buffer) {
2732 r600_bytecode_clear(&bc);
2733 FREE(shader);
2734 return NULL;
2735 }
2736
2737 bytecode = r600_buffer_map_sync_with_rings(&rctx->b, shader->buffer, PIPE_TRANSFER_WRITE | PIPE_TRANSFER_UNSYNCHRONIZED);
2738 bytecode += shader->offset / 4;
2739
2740 if (R600_BIG_ENDIAN) {
2741 for (i = 0; i < fs_size / 4; ++i) {
2742 bytecode[i] = util_cpu_to_le32(bc.bytecode[i]);
2743 }
2744 } else {
2745 memcpy(bytecode, bc.bytecode, fs_size);
2746 }
2747 rctx->b.ws->buffer_unmap(shader->buffer->buf);
2748
2749 r600_bytecode_clear(&bc);
2750 return shader;
2751 }
2752
2753 void r600_bytecode_alu_read(struct r600_bytecode *bc,
2754 struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1)
2755 {
2756 /* WORD0 */
2757 alu->src[0].sel = G_SQ_ALU_WORD0_SRC0_SEL(word0);
2758 alu->src[0].rel = G_SQ_ALU_WORD0_SRC0_REL(word0);
2759 alu->src[0].chan = G_SQ_ALU_WORD0_SRC0_CHAN(word0);
2760 alu->src[0].neg = G_SQ_ALU_WORD0_SRC0_NEG(word0);
2761 alu->src[1].sel = G_SQ_ALU_WORD0_SRC1_SEL(word0);
2762 alu->src[1].rel = G_SQ_ALU_WORD0_SRC1_REL(word0);
2763 alu->src[1].chan = G_SQ_ALU_WORD0_SRC1_CHAN(word0);
2764 alu->src[1].neg = G_SQ_ALU_WORD0_SRC1_NEG(word0);
2765 alu->index_mode = G_SQ_ALU_WORD0_INDEX_MODE(word0);
2766 alu->pred_sel = G_SQ_ALU_WORD0_PRED_SEL(word0);
2767 alu->last = G_SQ_ALU_WORD0_LAST(word0);
2768
2769 /* WORD1 */
2770 alu->bank_swizzle = G_SQ_ALU_WORD1_BANK_SWIZZLE(word1);
2771 if (alu->bank_swizzle)
2772 alu->bank_swizzle_force = alu->bank_swizzle;
2773 alu->dst.sel = G_SQ_ALU_WORD1_DST_GPR(word1);
2774 alu->dst.rel = G_SQ_ALU_WORD1_DST_REL(word1);
2775 alu->dst.chan = G_SQ_ALU_WORD1_DST_CHAN(word1);
2776 alu->dst.clamp = G_SQ_ALU_WORD1_CLAMP(word1);
2777 if (G_SQ_ALU_WORD1_ENCODING(word1)) /*ALU_DWORD1_OP3*/
2778 {
2779 alu->is_op3 = 1;
2780 alu->src[2].sel = G_SQ_ALU_WORD1_OP3_SRC2_SEL(word1);
2781 alu->src[2].rel = G_SQ_ALU_WORD1_OP3_SRC2_REL(word1);
2782 alu->src[2].chan = G_SQ_ALU_WORD1_OP3_SRC2_CHAN(word1);
2783 alu->src[2].neg = G_SQ_ALU_WORD1_OP3_SRC2_NEG(word1);
2784 alu->op = r600_isa_alu_by_opcode(bc->isa,
2785 G_SQ_ALU_WORD1_OP3_ALU_INST(word1), /* is_op3 = */ 1);
2786
2787 }
2788 else /*ALU_DWORD1_OP2*/
2789 {
2790 alu->src[0].abs = G_SQ_ALU_WORD1_OP2_SRC0_ABS(word1);
2791 alu->src[1].abs = G_SQ_ALU_WORD1_OP2_SRC1_ABS(word1);
2792 alu->op = r600_isa_alu_by_opcode(bc->isa,
2793 G_SQ_ALU_WORD1_OP2_ALU_INST(word1), /* is_op3 = */ 0);
2794 alu->omod = G_SQ_ALU_WORD1_OP2_OMOD(word1);
2795 alu->dst.write = G_SQ_ALU_WORD1_OP2_WRITE_MASK(word1);
2796 alu->update_pred = G_SQ_ALU_WORD1_OP2_UPDATE_PRED(word1);
2797 alu->execute_mask =
2798 G_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(word1);
2799 }
2800 }
2801
2802 #if 0
2803 void r600_bytecode_export_read(struct r600_bytecode *bc,
2804 struct r600_bytecode_output *output, uint32_t word0, uint32_t word1)
2805 {
2806 output->array_base = G_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(word0);
2807 output->type = G_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(word0);
2808 output->gpr = G_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(word0);
2809 output->elem_size = G_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(word0);
2810
2811 output->swizzle_x = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(word1);
2812 output->swizzle_y = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(word1);
2813 output->swizzle_z = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(word1);
2814 output->swizzle_w = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(word1);
2815 output->burst_count = G_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(word1);
2816 output->end_of_program = G_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(word1);
2817 output->op = r600_isa_cf_by_opcode(bc->isa,
2818 G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(word1), 0);
2819 output->barrier = G_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(word1);
2820 output->array_size = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(word1);
2821 output->comp_mask = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(word1);
2822 }
2823 #endif