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r600g: Print integer values of literal constants in shader dumps
[mesa.git] / src / gallium / drivers / r600 / r600_asm.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_opcodes.h"
25 #include "r600_formats.h"
26 #include "r600d.h"
27
28 #include <errno.h>
29 #include <byteswap.h>
30 #include "util/u_memory.h"
31 #include "pipe/p_shader_tokens.h"
32
33 #define NUM_OF_CYCLES 3
34 #define NUM_OF_COMPONENTS 4
35
36 static inline unsigned int r600_bytecode_get_num_operands(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
37 {
38 if(alu->is_op3)
39 return 3;
40
41 switch (bc->chip_class) {
42 case R600:
43 case R700:
44 switch (alu->inst) {
45 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
46 return 0;
47 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
48 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT:
49 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT:
50 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT:
51 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT:
52 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
53 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
54 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
55 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
56 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
57 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT:
58 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT:
59 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT:
60 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT:
61 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
62 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
63 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT:
64 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT:
65 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT:
66 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT:
67 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
68 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT:
69 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
70 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT:
71 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
72 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT:
73 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT:
74 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
75 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT:
76 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT:
77 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
78 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
79 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
80 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
81 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT:
82 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
83 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
84 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
85 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT:
86 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT:
87 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT:
88 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT:
89 return 2;
90
91 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
92 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA:
93 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR:
94 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT:
95 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
96 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
97 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
98 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
99 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
100 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
101 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
102 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
103 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
104 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT:
105 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
106 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
107 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
108 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT:
109 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT:
110 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT:
111 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
112 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
113 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE:
114 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT:
115 return 1;
116 default: R600_ERR(
117 "Need instruction operand number for 0x%x.\n", alu->inst);
118 }
119 break;
120 case EVERGREEN:
121 case CAYMAN:
122 switch (alu->inst) {
123 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
124 return 0;
125 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
126 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT:
127 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT:
128 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT:
129 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT:
130 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
131 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
132 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
133 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
134 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
135 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT:
136 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT:
137 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT:
138 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT:
139 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
140 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
141 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT:
142 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT:
143 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT:
144 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT:
145 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
146 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT:
147 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
148 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT:
149 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
150 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT:
151 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT:
152 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
153 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT:
154 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT:
155 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
156 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT:
157 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
158 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
159 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
160 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT:
161 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
162 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
163 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
164 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_XY:
165 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_ZW:
166 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT:
167 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT:
168 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT:
169 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT:
170 return 2;
171
172 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
173 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
174 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
175 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
176 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
177 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
178 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
179 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
180 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
181 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
182 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
183 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
184 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
185 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR:
186 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT:
187 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT:
188 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT:
189 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
190 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
191 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE:
192 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT:
193 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_LOAD_P0:
194 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT:
195 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT:
196 return 1;
197 default: R600_ERR(
198 "Need instruction operand number for 0x%x.\n", alu->inst);
199 }
200 break;
201 }
202
203 return 3;
204 }
205
206 int r700_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id);
207
208 static struct r600_bytecode_cf *r600_bytecode_cf(void)
209 {
210 struct r600_bytecode_cf *cf = CALLOC_STRUCT(r600_bytecode_cf);
211
212 if (cf == NULL)
213 return NULL;
214 LIST_INITHEAD(&cf->list);
215 LIST_INITHEAD(&cf->alu);
216 LIST_INITHEAD(&cf->vtx);
217 LIST_INITHEAD(&cf->tex);
218 return cf;
219 }
220
221 static struct r600_bytecode_alu *r600_bytecode_alu(void)
222 {
223 struct r600_bytecode_alu *alu = CALLOC_STRUCT(r600_bytecode_alu);
224
225 if (alu == NULL)
226 return NULL;
227 LIST_INITHEAD(&alu->list);
228 return alu;
229 }
230
231 static struct r600_bytecode_vtx *r600_bytecode_vtx(void)
232 {
233 struct r600_bytecode_vtx *vtx = CALLOC_STRUCT(r600_bytecode_vtx);
234
235 if (vtx == NULL)
236 return NULL;
237 LIST_INITHEAD(&vtx->list);
238 return vtx;
239 }
240
241 static struct r600_bytecode_tex *r600_bytecode_tex(void)
242 {
243 struct r600_bytecode_tex *tex = CALLOC_STRUCT(r600_bytecode_tex);
244
245 if (tex == NULL)
246 return NULL;
247 LIST_INITHEAD(&tex->list);
248 return tex;
249 }
250
251 void r600_bytecode_init(struct r600_bytecode *bc, enum chip_class chip_class, enum radeon_family family)
252 {
253 if ((chip_class == R600) && (family != CHIP_RV670))
254 bc->ar_handling = AR_HANDLE_RV6XX;
255 else
256 bc->ar_handling = AR_HANDLE_NORMAL;
257
258 if ((chip_class == R600) && (family != CHIP_RV670 && family != CHIP_RS780 &&
259 family != CHIP_RS880))
260 bc->r6xx_nop_after_rel_dst = 1;
261 else
262 bc->r6xx_nop_after_rel_dst = 0;
263 LIST_INITHEAD(&bc->cf);
264 bc->chip_class = chip_class;
265 }
266
267 static int r600_bytecode_add_cf(struct r600_bytecode *bc)
268 {
269 struct r600_bytecode_cf *cf = r600_bytecode_cf();
270
271 if (cf == NULL)
272 return -ENOMEM;
273 LIST_ADDTAIL(&cf->list, &bc->cf);
274 if (bc->cf_last) {
275 cf->id = bc->cf_last->id + 2;
276 if (bc->cf_last->eg_alu_extended) {
277 /* take into account extended alu size */
278 cf->id += 2;
279 bc->ndw += 2;
280 }
281 }
282 bc->cf_last = cf;
283 bc->ncf++;
284 bc->ndw += 2;
285 bc->force_add_cf = 0;
286 bc->ar_loaded = 0;
287 return 0;
288 }
289
290 int r600_bytecode_add_output(struct r600_bytecode *bc, const struct r600_bytecode_output *output)
291 {
292 int r;
293
294 if (output->gpr >= bc->ngpr)
295 bc->ngpr = output->gpr + 1;
296
297 if (bc->cf_last && (bc->cf_last->inst == output->inst ||
298 (bc->cf_last->inst == BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT) &&
299 output->inst == BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE))) &&
300 output->type == bc->cf_last->output.type &&
301 output->elem_size == bc->cf_last->output.elem_size &&
302 output->swizzle_x == bc->cf_last->output.swizzle_x &&
303 output->swizzle_y == bc->cf_last->output.swizzle_y &&
304 output->swizzle_z == bc->cf_last->output.swizzle_z &&
305 output->swizzle_w == bc->cf_last->output.swizzle_w &&
306 (output->burst_count + bc->cf_last->output.burst_count) <= 16) {
307
308 if ((output->gpr + output->burst_count) == bc->cf_last->output.gpr &&
309 (output->array_base + output->burst_count) == bc->cf_last->output.array_base) {
310
311 bc->cf_last->output.end_of_program |= output->end_of_program;
312 bc->cf_last->output.inst = output->inst;
313 bc->cf_last->output.gpr = output->gpr;
314 bc->cf_last->output.array_base = output->array_base;
315 bc->cf_last->output.burst_count += output->burst_count;
316 return 0;
317
318 } else if (output->gpr == (bc->cf_last->output.gpr + bc->cf_last->output.burst_count) &&
319 output->array_base == (bc->cf_last->output.array_base + bc->cf_last->output.burst_count)) {
320
321 bc->cf_last->output.end_of_program |= output->end_of_program;
322 bc->cf_last->output.inst = output->inst;
323 bc->cf_last->output.burst_count += output->burst_count;
324 return 0;
325 }
326 }
327
328 r = r600_bytecode_add_cf(bc);
329 if (r)
330 return r;
331 bc->cf_last->inst = output->inst;
332 memcpy(&bc->cf_last->output, output, sizeof(struct r600_bytecode_output));
333 return 0;
334 }
335
336 /* alu instructions that can ony exits once per group */
337 static int is_alu_once_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
338 {
339 switch (bc->chip_class) {
340 case R600:
341 case R700:
342 return !alu->is_op3 && (
343 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
344 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
345 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
346 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
347 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
348 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
349 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
350 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
351 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
352 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
353 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
354 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
355 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
356 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
357 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
358 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
359 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
360 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
361 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
362 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
363 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
364 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
365 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
366 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
367 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
368 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
369 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
370 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
371 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
372 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
373 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
374 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
375 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
376 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
377 case EVERGREEN:
378 case CAYMAN:
379 default:
380 return !alu->is_op3 && (
381 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
382 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
383 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
384 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
385 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
386 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
387 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
388 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
389 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
390 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
391 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
392 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
393 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
394 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
395 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
396 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
397 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
398 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
399 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
400 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
401 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
402 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
403 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
404 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
405 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
406 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
407 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
408 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
409 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
410 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
411 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
412 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
413 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
414 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
415 }
416 }
417
418 static int is_alu_reduction_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
419 {
420 switch (bc->chip_class) {
421 case R600:
422 case R700:
423 return !alu->is_op3 && (
424 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
425 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
426 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
427 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
428 case EVERGREEN:
429 case CAYMAN:
430 default:
431 return !alu->is_op3 && (
432 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
433 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
434 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
435 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
436 }
437 }
438
439 static int is_alu_cube_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
440 {
441 switch (bc->chip_class) {
442 case R600:
443 case R700:
444 return !alu->is_op3 &&
445 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
446 case EVERGREEN:
447 case CAYMAN:
448 default:
449 return !alu->is_op3 &&
450 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
451 }
452 }
453
454 static int is_alu_mova_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
455 {
456 switch (bc->chip_class) {
457 case R600:
458 case R700:
459 return !alu->is_op3 && (
460 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA ||
461 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR ||
462 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT ||
463 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT);
464 case EVERGREEN:
465 case CAYMAN:
466 default:
467 return !alu->is_op3 && (
468 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
469 }
470 }
471
472 static int is_opcode_in_range(unsigned opcode, unsigned min, unsigned max)
473 {
474 return min <= opcode && opcode <= max;
475 }
476
477 /* ALU instructions that can only execute on the vector unit:
478 *
479 * opcode ranges:
480 * R6xx/R7xx:
481 * op3 : [0x08 - 0x0B]
482 * op2 : 0x07, [0x15 - 0x18], [0x1B - 0x1D], [0x50 - 0x53], [0x7A - 0x7E]
483 *
484 * EVERGREEN:
485 * op3: [0x04 - 0x11]
486 * op2: [0xA0 - 0xE2]
487 */
488 static int is_alu_vec_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
489 {
490 switch (bc->chip_class) {
491 case R600:
492 case R700:
493 if (alu->is_op3)
494 return is_opcode_in_range(alu->inst,
495 V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_64,
496 V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_64_D2);
497 else
498 return (alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FREXP_64) ||
499 is_opcode_in_range(alu->inst,
500 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA,
501 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT) ||
502 is_opcode_in_range(alu->inst,
503 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_64,
504 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT32_TO_FLT64) ||
505 is_opcode_in_range(alu->inst,
506 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4,
507 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4) ||
508 is_opcode_in_range(alu->inst,
509 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LDEXP_64,
510 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_64);
511
512 case EVERGREEN:
513 if (alu->is_op3)
514 return is_opcode_in_range(alu->inst,
515 EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_BFE_UINT,
516 EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_LDS_IDX_OP);
517 else
518 return is_opcode_in_range(alu->inst,
519 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_BFM_INT,
520 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_LOAD_P20);
521 case CAYMAN:
522 default:
523 assert(0);
524 return 0;
525 }
526 }
527
528 /* ALU instructions that can only execute on the trans unit:
529 *
530 * opcode ranges:
531 * R600:
532 * op3: 0x0C
533 * op2: [0x60 - 0x79]
534 *
535 * R700:
536 * op3: 0x0C
537 * op2: [0x60 - 0x6F], [0x73 - 0x79]
538 *
539 * EVERGREEN:
540 * op3: 0x1F
541 * op2: [0x81 - 0x9C]
542 */
543 static int is_alu_trans_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
544 {
545
546 switch (bc->chip_class) {
547 case R600:
548 if (alu->is_op3)
549 return alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
550 else
551 return is_opcode_in_range(alu->inst,
552 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT,
553 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT);
554 case R700:
555 if (alu->is_op3)
556 return alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
557 else
558 return is_opcode_in_range(alu->inst,
559 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT,
560 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS) ||
561 is_opcode_in_range(alu->inst,
562 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT,
563 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT);
564 case EVERGREEN:
565 if (alu->is_op3)
566 return alu->inst == EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
567 else
568 return is_opcode_in_range(alu->inst,
569 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE,
570 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT);
571 case CAYMAN:
572 default:
573 assert(0);
574 return 0;
575 }
576 }
577
578 /* alu instructions that can execute on any unit */
579 static int is_alu_any_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
580 {
581 return !is_alu_vec_unit_inst(bc, alu) &&
582 !is_alu_trans_unit_inst(bc, alu);
583 }
584
585 static int is_nop_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
586 {
587 switch (bc->chip_class) {
588 case R600:
589 case R700:
590 return (!alu->is_op3 && alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
591 case EVERGREEN:
592 case CAYMAN:
593 default:
594 return (!alu->is_op3 && alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
595 }
596 }
597
598 static int assign_alu_units(struct r600_bytecode *bc, struct r600_bytecode_alu *alu_first,
599 struct r600_bytecode_alu *assignment[5])
600 {
601 struct r600_bytecode_alu *alu;
602 unsigned i, chan, trans;
603 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
604
605 for (i = 0; i < max_slots; i++)
606 assignment[i] = NULL;
607
608 for (alu = alu_first; alu; alu = LIST_ENTRY(struct r600_bytecode_alu, alu->list.next, list)) {
609 chan = alu->dst.chan;
610 if (max_slots == 4)
611 trans = 0;
612 else if (is_alu_trans_unit_inst(bc, alu))
613 trans = 1;
614 else if (is_alu_vec_unit_inst(bc, alu))
615 trans = 0;
616 else if (assignment[chan])
617 trans = 1; /* Assume ALU_INST_PREFER_VECTOR. */
618 else
619 trans = 0;
620
621 if (trans) {
622 if (assignment[4]) {
623 assert(0); /* ALU.Trans has already been allocated. */
624 return -1;
625 }
626 assignment[4] = alu;
627 } else {
628 if (assignment[chan]) {
629 assert(0); /* ALU.chan has already been allocated. */
630 return -1;
631 }
632 assignment[chan] = alu;
633 }
634
635 if (alu->last)
636 break;
637 }
638 return 0;
639 }
640
641 struct alu_bank_swizzle {
642 int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
643 int hw_cfile_addr[4];
644 int hw_cfile_elem[4];
645 };
646
647 static const unsigned cycle_for_bank_swizzle_vec[][3] = {
648 [SQ_ALU_VEC_012] = { 0, 1, 2 },
649 [SQ_ALU_VEC_021] = { 0, 2, 1 },
650 [SQ_ALU_VEC_120] = { 1, 2, 0 },
651 [SQ_ALU_VEC_102] = { 1, 0, 2 },
652 [SQ_ALU_VEC_201] = { 2, 0, 1 },
653 [SQ_ALU_VEC_210] = { 2, 1, 0 }
654 };
655
656 static const unsigned cycle_for_bank_swizzle_scl[][3] = {
657 [SQ_ALU_SCL_210] = { 2, 1, 0 },
658 [SQ_ALU_SCL_122] = { 1, 2, 2 },
659 [SQ_ALU_SCL_212] = { 2, 1, 2 },
660 [SQ_ALU_SCL_221] = { 2, 2, 1 }
661 };
662
663 static void init_bank_swizzle(struct alu_bank_swizzle *bs)
664 {
665 int i, cycle, component;
666 /* set up gpr use */
667 for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
668 for (component = 0; component < NUM_OF_COMPONENTS; component++)
669 bs->hw_gpr[cycle][component] = -1;
670 for (i = 0; i < 4; i++)
671 bs->hw_cfile_addr[i] = -1;
672 for (i = 0; i < 4; i++)
673 bs->hw_cfile_elem[i] = -1;
674 }
675
676 static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan, unsigned cycle)
677 {
678 if (bs->hw_gpr[cycle][chan] == -1)
679 bs->hw_gpr[cycle][chan] = sel;
680 else if (bs->hw_gpr[cycle][chan] != (int)sel) {
681 /* Another scalar operation has already used the GPR read port for the channel. */
682 return -1;
683 }
684 return 0;
685 }
686
687 static int reserve_cfile(struct r600_bytecode *bc, struct alu_bank_swizzle *bs, unsigned sel, unsigned chan)
688 {
689 int res, num_res = 4;
690 if (bc->chip_class >= R700) {
691 num_res = 2;
692 chan /= 2;
693 }
694 for (res = 0; res < num_res; ++res) {
695 if (bs->hw_cfile_addr[res] == -1) {
696 bs->hw_cfile_addr[res] = sel;
697 bs->hw_cfile_elem[res] = chan;
698 return 0;
699 } else if (bs->hw_cfile_addr[res] == sel &&
700 bs->hw_cfile_elem[res] == chan)
701 return 0; /* Read for this scalar element already reserved, nothing to do here. */
702 }
703 /* All cfile read ports are used, cannot reference vector element. */
704 return -1;
705 }
706
707 static int is_gpr(unsigned sel)
708 {
709 return (sel >= 0 && sel <= 127);
710 }
711
712 /* CB constants start at 512, and get translated to a kcache index when ALU
713 * clauses are constructed. Note that we handle kcache constants the same way
714 * as (the now gone) cfile constants, is that really required? */
715 static int is_cfile(unsigned sel)
716 {
717 return (sel > 255 && sel < 512) ||
718 (sel > 511 && sel < 4607) || /* Kcache before translation. */
719 (sel > 127 && sel < 192); /* Kcache after translation. */
720 }
721
722 static int is_const(int sel)
723 {
724 return is_cfile(sel) ||
725 (sel >= V_SQ_ALU_SRC_0 &&
726 sel <= V_SQ_ALU_SRC_LITERAL);
727 }
728
729 static int check_vector(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
730 struct alu_bank_swizzle *bs, int bank_swizzle)
731 {
732 int r, src, num_src, sel, elem, cycle;
733
734 num_src = r600_bytecode_get_num_operands(bc, alu);
735 for (src = 0; src < num_src; src++) {
736 sel = alu->src[src].sel;
737 elem = alu->src[src].chan;
738 if (is_gpr(sel)) {
739 cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src];
740 if (src == 1 && sel == alu->src[0].sel && elem == alu->src[0].chan)
741 /* Nothing to do; special-case optimization,
742 * second source uses first source’s reservation. */
743 continue;
744 else {
745 r = reserve_gpr(bs, sel, elem, cycle);
746 if (r)
747 return r;
748 }
749 } else if (is_cfile(sel)) {
750 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
751 if (r)
752 return r;
753 }
754 /* No restrictions on PV, PS, literal or special constants. */
755 }
756 return 0;
757 }
758
759 static int check_scalar(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
760 struct alu_bank_swizzle *bs, int bank_swizzle)
761 {
762 int r, src, num_src, const_count, sel, elem, cycle;
763
764 num_src = r600_bytecode_get_num_operands(bc, alu);
765 for (const_count = 0, src = 0; src < num_src; ++src) {
766 sel = alu->src[src].sel;
767 elem = alu->src[src].chan;
768 if (is_const(sel)) { /* Any constant, including literal and inline constants. */
769 if (const_count >= 2)
770 /* More than two references to a constant in
771 * transcendental operation. */
772 return -1;
773 else
774 const_count++;
775 }
776 if (is_cfile(sel)) {
777 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
778 if (r)
779 return r;
780 }
781 }
782 for (src = 0; src < num_src; ++src) {
783 sel = alu->src[src].sel;
784 elem = alu->src[src].chan;
785 if (is_gpr(sel)) {
786 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
787 if (cycle < const_count)
788 /* Cycle for GPR load conflicts with
789 * constant load in transcendental operation. */
790 return -1;
791 r = reserve_gpr(bs, sel, elem, cycle);
792 if (r)
793 return r;
794 }
795 /* PV PS restrictions */
796 if (const_count && (sel == 254 || sel == 255)) {
797 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
798 if (cycle < const_count)
799 return -1;
800 }
801 }
802 return 0;
803 }
804
805 static int check_and_set_bank_swizzle(struct r600_bytecode *bc,
806 struct r600_bytecode_alu *slots[5])
807 {
808 struct alu_bank_swizzle bs;
809 int bank_swizzle[5];
810 int i, r = 0, forced = 1;
811 boolean scalar_only = bc->chip_class == CAYMAN ? false : true;
812 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
813
814 for (i = 0; i < max_slots; i++) {
815 if (slots[i]) {
816 if (slots[i]->bank_swizzle_force) {
817 slots[i]->bank_swizzle = slots[i]->bank_swizzle_force;
818 } else {
819 forced = 0;
820 }
821 }
822
823 if (i < 4 && slots[i])
824 scalar_only = false;
825 }
826 if (forced)
827 return 0;
828
829 /* Just check every possible combination of bank swizzle.
830 * Not very efficent, but works on the first try in most of the cases. */
831 for (i = 0; i < 4; i++)
832 if (!slots[i] || !slots[i]->bank_swizzle_force)
833 bank_swizzle[i] = SQ_ALU_VEC_012;
834 else
835 bank_swizzle[i] = slots[i]->bank_swizzle;
836
837 bank_swizzle[4] = SQ_ALU_SCL_210;
838 while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
839
840 if (max_slots == 4) {
841 for (i = 0; i < max_slots; i++) {
842 if (bank_swizzle[i] == SQ_ALU_VEC_210)
843 return -1;
844 }
845 }
846 init_bank_swizzle(&bs);
847 if (scalar_only == false) {
848 for (i = 0; i < 4; i++) {
849 if (slots[i]) {
850 r = check_vector(bc, slots[i], &bs, bank_swizzle[i]);
851 if (r)
852 break;
853 }
854 }
855 } else
856 r = 0;
857
858 if (!r && slots[4] && max_slots == 5) {
859 r = check_scalar(bc, slots[4], &bs, bank_swizzle[4]);
860 }
861 if (!r) {
862 for (i = 0; i < max_slots; i++) {
863 if (slots[i])
864 slots[i]->bank_swizzle = bank_swizzle[i];
865 }
866 return 0;
867 }
868
869 if (scalar_only) {
870 bank_swizzle[4]++;
871 } else {
872 for (i = 0; i < max_slots; i++) {
873 if (!slots[i] || !slots[i]->bank_swizzle_force) {
874 bank_swizzle[i]++;
875 if (bank_swizzle[i] <= SQ_ALU_VEC_210)
876 break;
877 else
878 bank_swizzle[i] = SQ_ALU_VEC_012;
879 }
880 }
881 }
882 }
883
884 /* Couldn't find a working swizzle. */
885 return -1;
886 }
887
888 static int replace_gpr_with_pv_ps(struct r600_bytecode *bc,
889 struct r600_bytecode_alu *slots[5], struct r600_bytecode_alu *alu_prev)
890 {
891 struct r600_bytecode_alu *prev[5];
892 int gpr[5], chan[5];
893 int i, j, r, src, num_src;
894 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
895
896 r = assign_alu_units(bc, alu_prev, prev);
897 if (r)
898 return r;
899
900 for (i = 0; i < max_slots; ++i) {
901 if (prev[i] && (prev[i]->dst.write || prev[i]->is_op3) && !prev[i]->dst.rel) {
902 gpr[i] = prev[i]->dst.sel;
903 /* cube writes more than PV.X */
904 if (!is_alu_cube_inst(bc, prev[i]) && is_alu_reduction_inst(bc, prev[i]))
905 chan[i] = 0;
906 else
907 chan[i] = prev[i]->dst.chan;
908 } else
909 gpr[i] = -1;
910 }
911
912 for (i = 0; i < max_slots; ++i) {
913 struct r600_bytecode_alu *alu = slots[i];
914 if(!alu)
915 continue;
916
917 num_src = r600_bytecode_get_num_operands(bc, alu);
918 for (src = 0; src < num_src; ++src) {
919 if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
920 continue;
921
922 if (bc->chip_class < CAYMAN) {
923 if (alu->src[src].sel == gpr[4] &&
924 alu->src[src].chan == chan[4]) {
925 alu->src[src].sel = V_SQ_ALU_SRC_PS;
926 alu->src[src].chan = 0;
927 continue;
928 }
929 }
930
931 for (j = 0; j < 4; ++j) {
932 if (alu->src[src].sel == gpr[j] &&
933 alu->src[src].chan == j) {
934 alu->src[src].sel = V_SQ_ALU_SRC_PV;
935 alu->src[src].chan = chan[j];
936 break;
937 }
938 }
939 }
940 }
941
942 return 0;
943 }
944
945 void r600_bytecode_special_constants(uint32_t value, unsigned *sel, unsigned *neg)
946 {
947 switch(value) {
948 case 0:
949 *sel = V_SQ_ALU_SRC_0;
950 break;
951 case 1:
952 *sel = V_SQ_ALU_SRC_1_INT;
953 break;
954 case -1:
955 *sel = V_SQ_ALU_SRC_M_1_INT;
956 break;
957 case 0x3F800000: /* 1.0f */
958 *sel = V_SQ_ALU_SRC_1;
959 break;
960 case 0x3F000000: /* 0.5f */
961 *sel = V_SQ_ALU_SRC_0_5;
962 break;
963 case 0xBF800000: /* -1.0f */
964 *sel = V_SQ_ALU_SRC_1;
965 *neg ^= 1;
966 break;
967 case 0xBF000000: /* -0.5f */
968 *sel = V_SQ_ALU_SRC_0_5;
969 *neg ^= 1;
970 break;
971 default:
972 *sel = V_SQ_ALU_SRC_LITERAL;
973 break;
974 }
975 }
976
977 /* compute how many literal are needed */
978 static int r600_bytecode_alu_nliterals(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
979 uint32_t literal[4], unsigned *nliteral)
980 {
981 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
982 unsigned i, j;
983
984 for (i = 0; i < num_src; ++i) {
985 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
986 uint32_t value = alu->src[i].value;
987 unsigned found = 0;
988 for (j = 0; j < *nliteral; ++j) {
989 if (literal[j] == value) {
990 found = 1;
991 break;
992 }
993 }
994 if (!found) {
995 if (*nliteral >= 4)
996 return -EINVAL;
997 literal[(*nliteral)++] = value;
998 }
999 }
1000 }
1001 return 0;
1002 }
1003
1004 static void r600_bytecode_alu_adjust_literals(struct r600_bytecode *bc,
1005 struct r600_bytecode_alu *alu,
1006 uint32_t literal[4], unsigned nliteral)
1007 {
1008 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
1009 unsigned i, j;
1010
1011 for (i = 0; i < num_src; ++i) {
1012 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1013 uint32_t value = alu->src[i].value;
1014 for (j = 0; j < nliteral; ++j) {
1015 if (literal[j] == value) {
1016 alu->src[i].chan = j;
1017 break;
1018 }
1019 }
1020 }
1021 }
1022 }
1023
1024 static int merge_inst_groups(struct r600_bytecode *bc, struct r600_bytecode_alu *slots[5],
1025 struct r600_bytecode_alu *alu_prev)
1026 {
1027 struct r600_bytecode_alu *prev[5];
1028 struct r600_bytecode_alu *result[5] = { NULL };
1029
1030 uint32_t literal[4], prev_literal[4];
1031 unsigned nliteral = 0, prev_nliteral = 0;
1032
1033 int i, j, r, src, num_src;
1034 int num_once_inst = 0;
1035 int have_mova = 0, have_rel = 0;
1036 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
1037
1038 r = assign_alu_units(bc, alu_prev, prev);
1039 if (r)
1040 return r;
1041
1042 for (i = 0; i < max_slots; ++i) {
1043 struct r600_bytecode_alu *alu;
1044
1045 /* check number of literals */
1046 if (prev[i]) {
1047 if (r600_bytecode_alu_nliterals(bc, prev[i], literal, &nliteral))
1048 return 0;
1049 if (r600_bytecode_alu_nliterals(bc, prev[i], prev_literal, &prev_nliteral))
1050 return 0;
1051 if (is_alu_mova_inst(bc, prev[i])) {
1052 if (have_rel)
1053 return 0;
1054 have_mova = 1;
1055 }
1056 num_once_inst += is_alu_once_inst(bc, prev[i]);
1057 }
1058 if (slots[i] && r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral))
1059 return 0;
1060
1061 /* Let's check used slots. */
1062 if (prev[i] && !slots[i]) {
1063 result[i] = prev[i];
1064 continue;
1065 } else if (prev[i] && slots[i]) {
1066 if (max_slots == 5 && result[4] == NULL && prev[4] == NULL && slots[4] == NULL) {
1067 /* Trans unit is still free try to use it. */
1068 if (is_alu_any_unit_inst(bc, slots[i])) {
1069 result[i] = prev[i];
1070 result[4] = slots[i];
1071 } else if (is_alu_any_unit_inst(bc, prev[i])) {
1072 if (slots[i]->dst.sel == prev[i]->dst.sel &&
1073 (slots[i]->dst.write == 1 || slots[i]->is_op3) &&
1074 (prev[i]->dst.write == 1 || prev[i]->is_op3))
1075 return 0;
1076
1077 result[i] = slots[i];
1078 result[4] = prev[i];
1079 } else
1080 return 0;
1081 } else
1082 return 0;
1083 } else if(!slots[i]) {
1084 continue;
1085 } else {
1086 if (max_slots == 5 && slots[i] && prev[4] &&
1087 slots[i]->dst.sel == prev[4]->dst.sel &&
1088 slots[i]->dst.chan == prev[4]->dst.chan &&
1089 (slots[i]->dst.write == 1 || slots[i]->is_op3) &&
1090 (prev[4]->dst.write == 1 || prev[4]->is_op3))
1091 return 0;
1092
1093 result[i] = slots[i];
1094 }
1095
1096 alu = slots[i];
1097 num_once_inst += is_alu_once_inst(bc, alu);
1098
1099 /* don't reschedule NOPs */
1100 if (is_nop_inst(bc, alu))
1101 return 0;
1102
1103 /* Let's check dst gpr. */
1104 if (alu->dst.rel) {
1105 if (have_mova)
1106 return 0;
1107 have_rel = 1;
1108 }
1109
1110 /* Let's check source gprs */
1111 num_src = r600_bytecode_get_num_operands(bc, alu);
1112 for (src = 0; src < num_src; ++src) {
1113 if (alu->src[src].rel) {
1114 if (have_mova)
1115 return 0;
1116 have_rel = 1;
1117 }
1118
1119 /* Constants don't matter. */
1120 if (!is_gpr(alu->src[src].sel))
1121 continue;
1122
1123 for (j = 0; j < max_slots; ++j) {
1124 if (!prev[j] || !(prev[j]->dst.write || prev[j]->is_op3))
1125 continue;
1126
1127 /* If it's relative then we can't determin which gpr is really used. */
1128 if (prev[j]->dst.chan == alu->src[src].chan &&
1129 (prev[j]->dst.sel == alu->src[src].sel ||
1130 prev[j]->dst.rel || alu->src[src].rel))
1131 return 0;
1132 }
1133 }
1134 }
1135
1136 /* more than one PRED_ or KILL_ ? */
1137 if (num_once_inst > 1)
1138 return 0;
1139
1140 /* check if the result can still be swizzlet */
1141 r = check_and_set_bank_swizzle(bc, result);
1142 if (r)
1143 return 0;
1144
1145 /* looks like everything worked out right, apply the changes */
1146
1147 /* undo adding previus literals */
1148 bc->cf_last->ndw -= align(prev_nliteral, 2);
1149
1150 /* sort instructions */
1151 for (i = 0; i < max_slots; ++i) {
1152 slots[i] = result[i];
1153 if (result[i]) {
1154 LIST_DEL(&result[i]->list);
1155 result[i]->last = 0;
1156 LIST_ADDTAIL(&result[i]->list, &bc->cf_last->alu);
1157 }
1158 }
1159
1160 /* determine new last instruction */
1161 LIST_ENTRY(struct r600_bytecode_alu, bc->cf_last->alu.prev, list)->last = 1;
1162
1163 /* determine new first instruction */
1164 for (i = 0; i < max_slots; ++i) {
1165 if (result[i]) {
1166 bc->cf_last->curr_bs_head = result[i];
1167 break;
1168 }
1169 }
1170
1171 bc->cf_last->prev_bs_head = bc->cf_last->prev2_bs_head;
1172 bc->cf_last->prev2_bs_head = NULL;
1173
1174 return 0;
1175 }
1176
1177 /* we'll keep kcache sets sorted by bank & addr */
1178 static int r600_bytecode_alloc_kcache_line(struct r600_bytecode *bc,
1179 struct r600_bytecode_kcache *kcache,
1180 unsigned bank, unsigned line)
1181 {
1182 int i, kcache_banks = bc->chip_class >= EVERGREEN ? 4 : 2;
1183
1184 for (i = 0; i < kcache_banks; i++) {
1185 if (kcache[i].mode) {
1186 int d;
1187
1188 if (kcache[i].bank < bank)
1189 continue;
1190
1191 if ((kcache[i].bank == bank && kcache[i].addr > line+1) ||
1192 kcache[i].bank > bank) {
1193 /* try to insert new line */
1194 if (kcache[kcache_banks-1].mode) {
1195 /* all sets are in use */
1196 return -ENOMEM;
1197 }
1198
1199 memmove(&kcache[i+1],&kcache[i], (kcache_banks-i-1)*sizeof(struct r600_bytecode_kcache));
1200 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
1201 kcache[i].bank = bank;
1202 kcache[i].addr = line;
1203 return 0;
1204 }
1205
1206 d = line - kcache[i].addr;
1207
1208 if (d == -1) {
1209 kcache[i].addr--;
1210 if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_2) {
1211 /* we are prepending the line to the current set,
1212 * discarding the existing second line,
1213 * so we'll have to insert line+2 after it */
1214 line += 2;
1215 continue;
1216 } else if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_1) {
1217 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
1218 return 0;
1219 } else {
1220 /* V_SQ_CF_KCACHE_LOCK_LOOP_INDEX is not supported */
1221 return -ENOMEM;
1222 }
1223 } else if (d == 1) {
1224 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
1225 return 0;
1226 } else if (d == 0)
1227 return 0;
1228 } else { /* free kcache set - use it */
1229 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
1230 kcache[i].bank = bank;
1231 kcache[i].addr = line;
1232 return 0;
1233 }
1234 }
1235 return -ENOMEM;
1236 }
1237
1238 static int r600_bytecode_alloc_inst_kcache_lines(struct r600_bytecode *bc,
1239 struct r600_bytecode_kcache *kcache,
1240 struct r600_bytecode_alu *alu)
1241 {
1242 int i, r;
1243
1244 for (i = 0; i < 3; i++) {
1245 unsigned bank, line, sel = alu->src[i].sel;
1246
1247 if (sel < 512)
1248 continue;
1249
1250 bank = alu->src[i].kc_bank;
1251 line = (sel-512)>>4;
1252
1253 if ((r = r600_bytecode_alloc_kcache_line(bc, kcache, bank, line)))
1254 return r;
1255 }
1256 return 0;
1257 }
1258
1259 static int r600_bytecode_assign_kcache_banks(struct r600_bytecode *bc,
1260 struct r600_bytecode_alu *alu,
1261 struct r600_bytecode_kcache * kcache)
1262 {
1263 int i, j;
1264
1265 /* Alter the src operands to refer to the kcache. */
1266 for (i = 0; i < 3; ++i) {
1267 static const unsigned int base[] = {128, 160, 256, 288};
1268 unsigned int line, sel = alu->src[i].sel, found = 0;
1269
1270 if (sel < 512)
1271 continue;
1272
1273 sel -= 512;
1274 line = sel>>4;
1275
1276 for (j = 0; j < 4 && !found; ++j) {
1277 switch (kcache[j].mode) {
1278 case V_SQ_CF_KCACHE_NOP:
1279 case V_SQ_CF_KCACHE_LOCK_LOOP_INDEX:
1280 R600_ERR("unexpected kcache line mode\n");
1281 return -ENOMEM;
1282 default:
1283 if (kcache[j].bank == alu->src[i].kc_bank &&
1284 kcache[j].addr <= line &&
1285 line < kcache[j].addr + kcache[j].mode) {
1286 alu->src[i].sel = sel - (kcache[j].addr<<4);
1287 alu->src[i].sel += base[j];
1288 found=1;
1289 }
1290 }
1291 }
1292 }
1293 return 0;
1294 }
1295
1296 static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, int type)
1297 {
1298 struct r600_bytecode_kcache kcache_sets[4];
1299 struct r600_bytecode_kcache *kcache = kcache_sets;
1300 int r;
1301
1302 memcpy(kcache, bc->cf_last->kcache, 4 * sizeof(struct r600_bytecode_kcache));
1303
1304 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1305 /* can't alloc, need to start new clause */
1306 if ((r = r600_bytecode_add_cf(bc))) {
1307 return r;
1308 }
1309 bc->cf_last->inst = type;
1310
1311 /* retry with the new clause */
1312 kcache = bc->cf_last->kcache;
1313 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1314 /* can't alloc again- should never happen */
1315 return r;
1316 }
1317 } else {
1318 /* update kcache sets */
1319 memcpy(bc->cf_last->kcache, kcache, 4 * sizeof(struct r600_bytecode_kcache));
1320 }
1321
1322 /* if we actually used more than 2 kcache sets - use ALU_EXTENDED on eg+ */
1323 if (kcache[2].mode != V_SQ_CF_KCACHE_NOP) {
1324 if (bc->chip_class < EVERGREEN)
1325 return -ENOMEM;
1326 bc->cf_last->eg_alu_extended = 1;
1327 }
1328
1329 return 0;
1330 }
1331
1332 static int insert_nop_r6xx(struct r600_bytecode *bc)
1333 {
1334 struct r600_bytecode_alu alu;
1335 int r, i;
1336
1337 for (i = 0; i < 4; i++) {
1338 memset(&alu, 0, sizeof(alu));
1339 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP;
1340 alu.src[0].chan = i;
1341 alu.dst.chan = i;
1342 alu.last = (i == 3);
1343 r = r600_bytecode_add_alu(bc, &alu);
1344 if (r)
1345 return r;
1346 }
1347 return 0;
1348 }
1349
1350 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1351 static int load_ar_r6xx(struct r600_bytecode *bc)
1352 {
1353 struct r600_bytecode_alu alu;
1354 int r;
1355
1356 if (bc->ar_loaded)
1357 return 0;
1358
1359 /* hack to avoid making MOVA the last instruction in the clause */
1360 if ((bc->cf_last->ndw>>1) >= 110)
1361 bc->force_add_cf = 1;
1362
1363 memset(&alu, 0, sizeof(alu));
1364 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT;
1365 alu.src[0].sel = bc->ar_reg;
1366 alu.last = 1;
1367 alu.index_mode = INDEX_MODE_LOOP;
1368 r = r600_bytecode_add_alu(bc, &alu);
1369 if (r)
1370 return r;
1371
1372 /* no requirement to set uses waterfall on MOVA_GPR_INT */
1373 bc->ar_loaded = 1;
1374 return 0;
1375 }
1376
1377 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1378 static int load_ar(struct r600_bytecode *bc)
1379 {
1380 struct r600_bytecode_alu alu;
1381 int r;
1382
1383 if (bc->ar_handling)
1384 return load_ar_r6xx(bc);
1385
1386 if (bc->ar_loaded)
1387 return 0;
1388
1389 /* hack to avoid making MOVA the last instruction in the clause */
1390 if ((bc->cf_last->ndw>>1) >= 110)
1391 bc->force_add_cf = 1;
1392
1393 memset(&alu, 0, sizeof(alu));
1394 alu.inst = BC_INST(bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
1395 alu.src[0].sel = bc->ar_reg;
1396 alu.last = 1;
1397 r = r600_bytecode_add_alu(bc, &alu);
1398 if (r)
1399 return r;
1400
1401 bc->cf_last->r6xx_uses_waterfall = 1;
1402 bc->ar_loaded = 1;
1403 return 0;
1404 }
1405
1406 int r600_bytecode_add_alu_type(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu, int type)
1407 {
1408 struct r600_bytecode_alu *nalu = r600_bytecode_alu();
1409 struct r600_bytecode_alu *lalu;
1410 int i, r;
1411
1412 if (nalu == NULL)
1413 return -ENOMEM;
1414 memcpy(nalu, alu, sizeof(struct r600_bytecode_alu));
1415
1416 if (bc->cf_last != NULL && bc->cf_last->inst != type) {
1417 /* check if we could add it anyway */
1418 if (bc->cf_last->inst == BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU) &&
1419 type == BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE)) {
1420 LIST_FOR_EACH_ENTRY(lalu, &bc->cf_last->alu, list) {
1421 if (lalu->predicate) {
1422 bc->force_add_cf = 1;
1423 break;
1424 }
1425 }
1426 } else
1427 bc->force_add_cf = 1;
1428 }
1429
1430 /* cf can contains only alu or only vtx or only tex */
1431 if (bc->cf_last == NULL || bc->force_add_cf) {
1432 r = r600_bytecode_add_cf(bc);
1433 if (r) {
1434 free(nalu);
1435 return r;
1436 }
1437 }
1438 bc->cf_last->inst = type;
1439
1440 /* Check AR usage and load it if required */
1441 for (i = 0; i < 3; i++)
1442 if (nalu->src[i].rel && !bc->ar_loaded)
1443 load_ar(bc);
1444
1445 if (nalu->dst.rel && !bc->ar_loaded)
1446 load_ar(bc);
1447
1448 /* Setup the kcache for this ALU instruction. This will start a new
1449 * ALU clause if needed. */
1450 if ((r = r600_bytecode_alloc_kcache_lines(bc, nalu, type))) {
1451 free(nalu);
1452 return r;
1453 }
1454
1455 if (!bc->cf_last->curr_bs_head) {
1456 bc->cf_last->curr_bs_head = nalu;
1457 }
1458 /* number of gpr == the last gpr used in any alu */
1459 for (i = 0; i < 3; i++) {
1460 if (nalu->src[i].sel >= bc->ngpr && nalu->src[i].sel < 128) {
1461 bc->ngpr = nalu->src[i].sel + 1;
1462 }
1463 if (nalu->src[i].sel == V_SQ_ALU_SRC_LITERAL)
1464 r600_bytecode_special_constants(nalu->src[i].value,
1465 &nalu->src[i].sel, &nalu->src[i].neg);
1466 }
1467 if (nalu->dst.sel >= bc->ngpr) {
1468 bc->ngpr = nalu->dst.sel + 1;
1469 }
1470 LIST_ADDTAIL(&nalu->list, &bc->cf_last->alu);
1471 /* each alu use 2 dwords */
1472 bc->cf_last->ndw += 2;
1473 bc->ndw += 2;
1474
1475 /* process cur ALU instructions for bank swizzle */
1476 if (nalu->last) {
1477 uint32_t literal[4];
1478 unsigned nliteral;
1479 struct r600_bytecode_alu *slots[5];
1480 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
1481 r = assign_alu_units(bc, bc->cf_last->curr_bs_head, slots);
1482 if (r)
1483 return r;
1484
1485 if (bc->cf_last->prev_bs_head) {
1486 r = merge_inst_groups(bc, slots, bc->cf_last->prev_bs_head);
1487 if (r)
1488 return r;
1489 }
1490
1491 if (bc->cf_last->prev_bs_head) {
1492 r = replace_gpr_with_pv_ps(bc, slots, bc->cf_last->prev_bs_head);
1493 if (r)
1494 return r;
1495 }
1496
1497 r = check_and_set_bank_swizzle(bc, slots);
1498 if (r)
1499 return r;
1500
1501 for (i = 0, nliteral = 0; i < max_slots; i++) {
1502 if (slots[i]) {
1503 r = r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral);
1504 if (r)
1505 return r;
1506 }
1507 }
1508 bc->cf_last->ndw += align(nliteral, 2);
1509
1510 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1511 * worst case */
1512 if ((bc->cf_last->ndw >> 1) >= 120) {
1513 bc->force_add_cf = 1;
1514 }
1515
1516 bc->cf_last->prev2_bs_head = bc->cf_last->prev_bs_head;
1517 bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head;
1518 bc->cf_last->curr_bs_head = NULL;
1519 }
1520
1521 if (nalu->dst.rel && bc->r6xx_nop_after_rel_dst)
1522 insert_nop_r6xx(bc);
1523
1524 return 0;
1525 }
1526
1527 int r600_bytecode_add_alu(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu)
1528 {
1529 return r600_bytecode_add_alu_type(bc, alu, BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
1530 }
1531
1532 static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode *bc)
1533 {
1534 switch (bc->chip_class) {
1535 case R600:
1536 return 8;
1537
1538 case R700:
1539 case EVERGREEN:
1540 case CAYMAN:
1541 return 16;
1542
1543 default:
1544 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1545 return 8;
1546 }
1547 }
1548
1549 static inline boolean last_inst_was_not_vtx_fetch(struct r600_bytecode *bc)
1550 {
1551 switch (bc->chip_class) {
1552 case R700:
1553 case R600:
1554 return bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX &&
1555 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC;
1556 case EVERGREEN:
1557 return bc->cf_last->inst != EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1558 case CAYMAN:
1559 return bc->cf_last->inst != CM_V_SQ_CF_WORD1_SQ_CF_INST_TC;
1560 default:
1561 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1562 return FALSE;
1563 }
1564 }
1565
1566 int r600_bytecode_add_vtx(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx)
1567 {
1568 struct r600_bytecode_vtx *nvtx = r600_bytecode_vtx();
1569 int r;
1570
1571 if (nvtx == NULL)
1572 return -ENOMEM;
1573 memcpy(nvtx, vtx, sizeof(struct r600_bytecode_vtx));
1574
1575 /* cf can contains only alu or only vtx or only tex */
1576 if (bc->cf_last == NULL ||
1577 last_inst_was_not_vtx_fetch(bc) ||
1578 bc->force_add_cf) {
1579 r = r600_bytecode_add_cf(bc);
1580 if (r) {
1581 free(nvtx);
1582 return r;
1583 }
1584 switch (bc->chip_class) {
1585 case R600:
1586 case R700:
1587 bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1588 break;
1589 case EVERGREEN:
1590 bc->cf_last->inst = EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1591 break;
1592 case CAYMAN:
1593 bc->cf_last->inst = CM_V_SQ_CF_WORD1_SQ_CF_INST_TC;
1594 break;
1595 default:
1596 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1597 return -EINVAL;
1598 }
1599 }
1600 LIST_ADDTAIL(&nvtx->list, &bc->cf_last->vtx);
1601 /* each fetch use 4 dwords */
1602 bc->cf_last->ndw += 4;
1603 bc->ndw += 4;
1604 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1605 bc->force_add_cf = 1;
1606 return 0;
1607 }
1608
1609 int r600_bytecode_add_tex(struct r600_bytecode *bc, const struct r600_bytecode_tex *tex)
1610 {
1611 struct r600_bytecode_tex *ntex = r600_bytecode_tex();
1612 int r;
1613
1614 if (ntex == NULL)
1615 return -ENOMEM;
1616 memcpy(ntex, tex, sizeof(struct r600_bytecode_tex));
1617
1618 /* we can't fetch data und use it as texture lookup address in the same TEX clause */
1619 if (bc->cf_last != NULL &&
1620 bc->cf_last->inst == BC_INST(bc, V_SQ_CF_WORD1_SQ_CF_INST_TEX)) {
1621 struct r600_bytecode_tex *ttex;
1622 LIST_FOR_EACH_ENTRY(ttex, &bc->cf_last->tex, list) {
1623 if (ttex->dst_gpr == ntex->src_gpr) {
1624 bc->force_add_cf = 1;
1625 break;
1626 }
1627 }
1628 /* slight hack to make gradients always go into same cf */
1629 if (ntex->inst == SQ_TEX_INST_SET_GRADIENTS_H)
1630 bc->force_add_cf = 1;
1631 }
1632
1633 /* cf can contains only alu or only vtx or only tex */
1634 if (bc->cf_last == NULL ||
1635 bc->cf_last->inst != BC_INST(bc, V_SQ_CF_WORD1_SQ_CF_INST_TEX) ||
1636 bc->force_add_cf) {
1637 r = r600_bytecode_add_cf(bc);
1638 if (r) {
1639 free(ntex);
1640 return r;
1641 }
1642 bc->cf_last->inst = BC_INST(bc, V_SQ_CF_WORD1_SQ_CF_INST_TEX);
1643 }
1644 if (ntex->src_gpr >= bc->ngpr) {
1645 bc->ngpr = ntex->src_gpr + 1;
1646 }
1647 if (ntex->dst_gpr >= bc->ngpr) {
1648 bc->ngpr = ntex->dst_gpr + 1;
1649 }
1650 LIST_ADDTAIL(&ntex->list, &bc->cf_last->tex);
1651 /* each texture fetch use 4 dwords */
1652 bc->cf_last->ndw += 4;
1653 bc->ndw += 4;
1654 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1655 bc->force_add_cf = 1;
1656 return 0;
1657 }
1658
1659 int r600_bytecode_add_cfinst(struct r600_bytecode *bc, int inst)
1660 {
1661 int r;
1662 r = r600_bytecode_add_cf(bc);
1663 if (r)
1664 return r;
1665
1666 bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
1667 bc->cf_last->inst = inst;
1668 return 0;
1669 }
1670
1671 int cm_bytecode_add_cf_end(struct r600_bytecode *bc)
1672 {
1673 return r600_bytecode_add_cfinst(bc, CM_V_SQ_CF_WORD1_SQ_CF_INST_END);
1674 }
1675
1676 /* common to all 3 families */
1677 static int r600_bytecode_vtx_build(struct r600_bytecode *bc, struct r600_bytecode_vtx *vtx, unsigned id)
1678 {
1679 bc->bytecode[id] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) |
1680 S_SQ_VTX_WORD0_FETCH_TYPE(vtx->fetch_type) |
1681 S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
1682 S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x);
1683 if (bc->chip_class < CAYMAN)
1684 bc->bytecode[id] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
1685 id++;
1686 bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
1687 S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
1688 S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
1689 S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
1690 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) |
1691 S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) |
1692 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) |
1693 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) |
1694 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
1695 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
1696 bc->bytecode[id] = S_SQ_VTX_WORD2_OFFSET(vtx->offset)|
1697 S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx->endian);
1698 if (bc->chip_class < CAYMAN)
1699 bc->bytecode[id] |= S_SQ_VTX_WORD2_MEGA_FETCH(1);
1700 id++;
1701 bc->bytecode[id++] = 0;
1702 return 0;
1703 }
1704
1705 /* common to all 3 families */
1706 static int r600_bytecode_tex_build(struct r600_bytecode *bc, struct r600_bytecode_tex *tex, unsigned id)
1707 {
1708 bc->bytecode[id++] = S_SQ_TEX_WORD0_TEX_INST(tex->inst) |
1709 S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
1710 S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
1711 S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
1712 bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
1713 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
1714 S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
1715 S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
1716 S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
1717 S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
1718 S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
1719 S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
1720 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
1721 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
1722 S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
1723 bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
1724 S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
1725 S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
1726 S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
1727 S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
1728 S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
1729 S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
1730 S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
1731 bc->bytecode[id++] = 0;
1732 return 0;
1733 }
1734
1735 /* r600 only, r700/eg bits in r700_asm.c */
1736 static int r600_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id)
1737 {
1738 /* don't replace gpr by pv or ps for destination register */
1739 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
1740 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
1741 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
1742 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
1743 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
1744 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
1745 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
1746 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
1747 S_SQ_ALU_WORD0_INDEX_MODE(alu->index_mode) |
1748 S_SQ_ALU_WORD0_LAST(alu->last);
1749
1750 if (alu->is_op3) {
1751 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1752 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1753 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1754 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1755 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
1756 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
1757 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
1758 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
1759 S_SQ_ALU_WORD1_OP3_ALU_INST(alu->inst) |
1760 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
1761 } else {
1762 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1763 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1764 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1765 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1766 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
1767 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
1768 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
1769 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
1770 S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
1771 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
1772 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->predicate) |
1773 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->predicate);
1774 }
1775 return 0;
1776 }
1777
1778 static void r600_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_cf *cf)
1779 {
1780 *bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
1781 *bytecode++ = cf->inst |
1782 S_SQ_CF_WORD1_BARRIER(1) |
1783 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
1784 }
1785
1786 /* common for r600/r700 - eg in eg_asm.c */
1787 static int r600_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf)
1788 {
1789 unsigned id = cf->id;
1790
1791 switch (cf->inst) {
1792 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
1793 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
1794 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
1795 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
1796 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
1797 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
1798 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
1799 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank);
1800
1801 bc->bytecode[id++] = cf->inst |
1802 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) |
1803 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
1804 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
1805 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1806 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chip_class == R600 ? cf->r6xx_uses_waterfall : 0) |
1807 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
1808 break;
1809 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1810 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1811 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1812 if (bc->chip_class == R700)
1813 r700_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1814 else
1815 r600_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1816 break;
1817 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1818 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1819 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1820 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1821 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1822 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
1823 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1824 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
1825 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
1826 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
1827 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
1828 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
1829 cf->output.inst |
1830 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program);
1831 break;
1832 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
1833 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
1834 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
1835 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
1836 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1837 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1838 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1839 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
1840 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1841 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
1842 cf->output.inst |
1843 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program) |
1844 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf->output.array_size) |
1845 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf->output.comp_mask);
1846 break;
1847 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1848 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1849 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1850 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1851 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1852 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1853 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1854 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1855 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1856 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
1857 bc->bytecode[id++] = cf->inst |
1858 S_SQ_CF_WORD1_BARRIER(1) |
1859 S_SQ_CF_WORD1_COND(cf->cond) |
1860 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count);
1861
1862 break;
1863 default:
1864 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1865 return -EINVAL;
1866 }
1867 return 0;
1868 }
1869
1870 int r600_bytecode_build(struct r600_bytecode *bc)
1871 {
1872 struct r600_bytecode_cf *cf;
1873 struct r600_bytecode_alu *alu;
1874 struct r600_bytecode_vtx *vtx;
1875 struct r600_bytecode_tex *tex;
1876 uint32_t literal[4];
1877 unsigned nliteral;
1878 unsigned addr;
1879 int i, r;
1880
1881 if (bc->callstack[0].max > 0)
1882 bc->nstack = ((bc->callstack[0].max + 3) >> 2) + 2;
1883 if (bc->type == TGSI_PROCESSOR_VERTEX && !bc->nstack) {
1884 bc->nstack = 1;
1885 }
1886
1887 /* first path compute addr of each CF block */
1888 /* addr start after all the CF instructions */
1889 addr = bc->cf_last->id + 2;
1890 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1891 if (bc->chip_class >= EVERGREEN) {
1892 switch (cf->inst) {
1893 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1894 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1895 /* fetch node need to be 16 bytes aligned*/
1896 addr += 3;
1897 addr &= 0xFFFFFFFCUL;
1898 break;
1899 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
1900 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
1901 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
1902 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
1903 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1904 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1905 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0:
1906 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1:
1907 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2:
1908 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3:
1909 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0:
1910 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1:
1911 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2:
1912 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3:
1913 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0:
1914 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1:
1915 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2:
1916 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3:
1917 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0:
1918 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1:
1919 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2:
1920 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3:
1921 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1922 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1923 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
1924 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1925 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1926 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1927 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1928 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1929 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1930 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
1931 case CF_NATIVE:
1932 break;
1933 default:
1934 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1935 return -EINVAL;
1936 }
1937 } else {
1938 switch (cf->inst) {
1939 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1940 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1941 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1942 /* fetch node need to be 16 bytes aligned*/
1943 addr += 3;
1944 addr &= 0xFFFFFFFCUL;
1945 break;
1946 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
1947 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
1948 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
1949 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
1950 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1951 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1952 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
1953 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
1954 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
1955 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
1956 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1957 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1958 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1959 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1960 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1961 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1962 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1963 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1964 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1965 break;
1966 default:
1967 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1968 return -EINVAL;
1969 }
1970 }
1971 cf->addr = addr;
1972 addr += cf->ndw;
1973 bc->ndw = cf->addr + cf->ndw;
1974 }
1975 free(bc->bytecode);
1976 bc->bytecode = calloc(1, bc->ndw * 4);
1977 if (bc->bytecode == NULL)
1978 return -ENOMEM;
1979 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1980 addr = cf->addr;
1981 if (bc->chip_class >= EVERGREEN) {
1982 r = eg_bytecode_cf_build(bc, cf);
1983 if (r)
1984 return r;
1985
1986 switch (cf->inst) {
1987 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
1988 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
1989 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
1990 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
1991 nliteral = 0;
1992 memset(literal, 0, sizeof(literal));
1993 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1994 r = r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
1995 if (r)
1996 return r;
1997 r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral);
1998 r600_bytecode_assign_kcache_banks(bc, alu, cf->kcache);
1999
2000 switch(bc->chip_class) {
2001 case EVERGREEN: /* eg alu is same encoding as r700 */
2002 case CAYMAN:
2003 r = r700_bytecode_alu_build(bc, alu, addr);
2004 break;
2005 default:
2006 R600_ERR("unknown chip class %d.\n", bc->chip_class);
2007 return -EINVAL;
2008 }
2009 if (r)
2010 return r;
2011 addr += 2;
2012 if (alu->last) {
2013 for (i = 0; i < align(nliteral, 2); ++i) {
2014 bc->bytecode[addr++] = literal[i];
2015 }
2016 nliteral = 0;
2017 memset(literal, 0, sizeof(literal));
2018 }
2019 }
2020 break;
2021 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2022 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2023 r = r600_bytecode_vtx_build(bc, vtx, addr);
2024 if (r)
2025 return r;
2026 addr += 4;
2027 }
2028 break;
2029 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2030 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2031 assert(bc->chip_class >= EVERGREEN);
2032 r = r600_bytecode_vtx_build(bc, vtx, addr);
2033 if (r)
2034 return r;
2035 addr += 4;
2036 }
2037 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2038 r = r600_bytecode_tex_build(bc, tex, addr);
2039 if (r)
2040 return r;
2041 addr += 4;
2042 }
2043 break;
2044 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2045 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2046 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0:
2047 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1:
2048 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2:
2049 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3:
2050 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0:
2051 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1:
2052 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2:
2053 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3:
2054 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0:
2055 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1:
2056 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2:
2057 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3:
2058 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0:
2059 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1:
2060 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2:
2061 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3:
2062 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
2063 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2064 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2065 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2066 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2067 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2068 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
2069 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2070 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2071 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
2072 break;
2073 case CF_NATIVE:
2074 break;
2075 default:
2076 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
2077 return -EINVAL;
2078 }
2079 } else {
2080 r = r600_bytecode_cf_build(bc, cf);
2081 if (r)
2082 return r;
2083
2084 switch (cf->inst) {
2085 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
2086 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
2087 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
2088 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
2089 nliteral = 0;
2090 memset(literal, 0, sizeof(literal));
2091 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
2092 r = r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
2093 if (r)
2094 return r;
2095 r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral);
2096 r600_bytecode_assign_kcache_banks(bc, alu, cf->kcache);
2097
2098 switch(bc->chip_class) {
2099 case R600:
2100 r = r600_bytecode_alu_build(bc, alu, addr);
2101 break;
2102 case R700:
2103 r = r700_bytecode_alu_build(bc, alu, addr);
2104 break;
2105 default:
2106 R600_ERR("unknown chip class %d.\n", bc->chip_class);
2107 return -EINVAL;
2108 }
2109 if (r)
2110 return r;
2111 addr += 2;
2112 if (alu->last) {
2113 for (i = 0; i < align(nliteral, 2); ++i) {
2114 bc->bytecode[addr++] = literal[i];
2115 }
2116 nliteral = 0;
2117 memset(literal, 0, sizeof(literal));
2118 }
2119 }
2120 break;
2121 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2122 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
2123 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2124 r = r600_bytecode_vtx_build(bc, vtx, addr);
2125 if (r)
2126 return r;
2127 addr += 4;
2128 }
2129 break;
2130 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2131 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2132 r = r600_bytecode_tex_build(bc, tex, addr);
2133 if (r)
2134 return r;
2135 addr += 4;
2136 }
2137 break;
2138 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2139 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2140 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
2141 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
2142 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
2143 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
2144 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
2145 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2146 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2147 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2148 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2149 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2150 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
2151 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2152 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2153 break;
2154 default:
2155 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
2156 return -EINVAL;
2157 }
2158 }
2159 }
2160 return 0;
2161 }
2162
2163 void r600_bytecode_clear(struct r600_bytecode *bc)
2164 {
2165 struct r600_bytecode_cf *cf = NULL, *next_cf;
2166
2167 free(bc->bytecode);
2168 bc->bytecode = NULL;
2169
2170 LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
2171 struct r600_bytecode_alu *alu = NULL, *next_alu;
2172 struct r600_bytecode_tex *tex = NULL, *next_tex;
2173 struct r600_bytecode_tex *vtx = NULL, *next_vtx;
2174
2175 LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
2176 free(alu);
2177 }
2178
2179 LIST_INITHEAD(&cf->alu);
2180
2181 LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) {
2182 free(tex);
2183 }
2184
2185 LIST_INITHEAD(&cf->tex);
2186
2187 LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) {
2188 free(vtx);
2189 }
2190
2191 LIST_INITHEAD(&cf->vtx);
2192
2193 free(cf);
2194 }
2195
2196 LIST_INITHEAD(&cf->list);
2197 }
2198
2199 void r600_bytecode_dump(struct r600_bytecode *bc)
2200 {
2201 struct r600_bytecode_cf *cf = NULL;
2202 struct r600_bytecode_alu *alu = NULL;
2203 struct r600_bytecode_vtx *vtx = NULL;
2204 struct r600_bytecode_tex *tex = NULL;
2205
2206 unsigned i, id;
2207 uint32_t literal[4];
2208 unsigned nliteral;
2209 char chip = '6';
2210
2211 switch (bc->chip_class) {
2212 case R700:
2213 chip = '7';
2214 break;
2215 case EVERGREEN:
2216 chip = 'E';
2217 break;
2218 case CAYMAN:
2219 chip = 'C';
2220 break;
2221 case R600:
2222 default:
2223 chip = '6';
2224 break;
2225 }
2226 fprintf(stderr, "bytecode %d dw -- %d gprs ---------------------\n", bc->ndw, bc->ngpr);
2227 fprintf(stderr, " %c\n", chip);
2228
2229 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
2230 id = cf->id;
2231
2232 if (bc->chip_class >= EVERGREEN) {
2233 switch (cf->inst) {
2234 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
2235 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
2236 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
2237 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
2238 if (cf->eg_alu_extended) {
2239 fprintf(stderr, "%04d %08X ALU_EXT0 ", id, bc->bytecode[id]);
2240 fprintf(stderr, "KCACHE_BANK2:%X ", cf->kcache[2].bank);
2241 fprintf(stderr, "KCACHE_BANK3:%X ", cf->kcache[3].bank);
2242 fprintf(stderr, "KCACHE_MODE2:%X\n", cf->kcache[2].mode);
2243 id++;
2244 fprintf(stderr, "%04d %08X ALU_EXT1 ", id, bc->bytecode[id]);
2245 fprintf(stderr, "KCACHE_MODE3:%X ", cf->kcache[3].mode);
2246 fprintf(stderr, "KCACHE_ADDR2:%X ", cf->kcache[2].addr);
2247 fprintf(stderr, "KCACHE_ADDR3:%X\n", cf->kcache[3].addr);
2248 id++;
2249 }
2250
2251 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2252 fprintf(stderr, "ADDR:%d ", cf->addr);
2253 fprintf(stderr, "KCACHE_MODE0:%X ", cf->kcache[0].mode);
2254 fprintf(stderr, "KCACHE_BANK0:%X ", cf->kcache[0].bank);
2255 fprintf(stderr, "KCACHE_BANK1:%X\n", cf->kcache[1].bank);
2256 id++;
2257 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2258 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_ALU_WORD1_CF_INST(cf->inst));
2259 fprintf(stderr, "KCACHE_MODE1:%X ", cf->kcache[1].mode);
2260 fprintf(stderr, "KCACHE_ADDR0:%X ", cf->kcache[0].addr);
2261 fprintf(stderr, "KCACHE_ADDR1:%X ", cf->kcache[1].addr);
2262 fprintf(stderr, "COUNT:%d\n", cf->ndw / 2);
2263 break;
2264 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2265 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2266 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2267 fprintf(stderr, "ADDR:%d\n", cf->addr);
2268 id++;
2269 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2270 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_WORD1_CF_INST(cf->inst));
2271 fprintf(stderr, "COUNT:%d\n", cf->ndw / 4);
2272 break;
2273 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2274 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2275 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2276 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2277 fprintf(stderr, "ELEM_SIZE:%X ", cf->output.elem_size);
2278 fprintf(stderr, "ARRAY_BASE:%X ", cf->output.array_base);
2279 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2280 id++;
2281 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2282 fprintf(stderr, "SWIZ_X:%X ", cf->output.swizzle_x);
2283 fprintf(stderr, "SWIZ_Y:%X ", cf->output.swizzle_y);
2284 fprintf(stderr, "SWIZ_Z:%X ", cf->output.swizzle_z);
2285 fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
2286 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2287 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst));
2288 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2289 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2290 break;
2291 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0:
2292 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1:
2293 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2:
2294 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3:
2295 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0:
2296 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1:
2297 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2:
2298 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3:
2299 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0:
2300 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1:
2301 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2:
2302 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3:
2303 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0:
2304 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1:
2305 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2:
2306 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3:
2307 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i_BUF%i ", id, bc->bytecode[id],
2308 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2309 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) / 4,
2310 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2311 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) % 4);
2312 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2313 fprintf(stderr, "ELEM_SIZE:%i ", cf->output.elem_size);
2314 fprintf(stderr, "ARRAY_BASE:%i ", cf->output.array_base);
2315 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2316 id++;
2317 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i_BUF%i ", id, bc->bytecode[id],
2318 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2319 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) / 4,
2320 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2321 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) % 4);
2322 fprintf(stderr, "ARRAY_SIZE:%i ", cf->output.array_size);
2323 fprintf(stderr, "COMP_MASK:%X ", cf->output.comp_mask);
2324 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2325 fprintf(stderr, "INST:%d ", cf->output.inst);
2326 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2327 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2328 break;
2329 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2330 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2331 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
2332 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
2333 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2334 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2335 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2336 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2337 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2338 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
2339 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2340 fprintf(stderr, "ADDR:%d\n", cf->cf_addr);
2341 id++;
2342 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2343 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_WORD1_CF_INST(cf->inst));
2344 fprintf(stderr, "COND:%X ", cf->cond);
2345 fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
2346 break;
2347 case CF_NATIVE:
2348 fprintf(stderr, "%04d %08X CF NATIVE\n", id, bc->bytecode[id]);
2349 fprintf(stderr, "%04d %08X CF NATIVE\n", id + 1, bc->bytecode[id + 1]);
2350 break;
2351 default:
2352 R600_ERR("Unknown instruction %0x\n", cf->inst);
2353 }
2354 } else {
2355 switch (cf->inst) {
2356 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
2357 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
2358 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
2359 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
2360 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2361 fprintf(stderr, "ADDR:%d ", cf->addr);
2362 fprintf(stderr, "KCACHE_MODE0:%X ", cf->kcache[0].mode);
2363 fprintf(stderr, "KCACHE_BANK0:%X ", cf->kcache[0].bank);
2364 fprintf(stderr, "KCACHE_BANK1:%X\n", cf->kcache[1].bank);
2365 id++;
2366 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2367 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_ALU_WORD1_CF_INST(cf->inst));
2368 fprintf(stderr, "KCACHE_MODE1:%X ", cf->kcache[1].mode);
2369 fprintf(stderr, "KCACHE_ADDR0:%X ", cf->kcache[0].addr);
2370 fprintf(stderr, "KCACHE_ADDR1:%X ", cf->kcache[1].addr);
2371 fprintf(stderr, "COUNT:%d\n", cf->ndw / 2);
2372 break;
2373 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2374 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2375 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
2376 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2377 fprintf(stderr, "ADDR:%d\n", cf->addr);
2378 id++;
2379 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2380 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_WORD1_CF_INST(cf->inst));
2381 fprintf(stderr, "COUNT:%d\n", cf->ndw / 4);
2382 break;
2383 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2384 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2385 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2386 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2387 fprintf(stderr, "ELEM_SIZE:%X ", cf->output.elem_size);
2388 fprintf(stderr, "ARRAY_BASE:%X ", cf->output.array_base);
2389 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2390 id++;
2391 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2392 fprintf(stderr, "SWIZ_X:%X ", cf->output.swizzle_x);
2393 fprintf(stderr, "SWIZ_Y:%X ", cf->output.swizzle_y);
2394 fprintf(stderr, "SWIZ_Z:%X ", cf->output.swizzle_z);
2395 fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
2396 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2397 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst));
2398 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2399 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2400 break;
2401 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
2402 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
2403 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
2404 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
2405 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i ", id, bc->bytecode[id],
2406 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2407 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0));
2408 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2409 fprintf(stderr, "ELEM_SIZE:%i ", cf->output.elem_size);
2410 fprintf(stderr, "ARRAY_BASE:%i ", cf->output.array_base);
2411 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2412 id++;
2413 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i ", id, bc->bytecode[id],
2414 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2415 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0));
2416 fprintf(stderr, "ARRAY_SIZE:%i ", cf->output.array_size);
2417 fprintf(stderr, "COMP_MASK:%X ", cf->output.comp_mask);
2418 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2419 fprintf(stderr, "INST:%d ", cf->output.inst);
2420 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2421 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2422 break;
2423 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2424 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2425 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
2426 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
2427 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2428 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2429 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2430 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2431 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2432 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2433 fprintf(stderr, "ADDR:%d\n", cf->cf_addr);
2434 id++;
2435 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2436 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_WORD1_CF_INST(cf->inst));
2437 fprintf(stderr, "COND:%X ", cf->cond);
2438 fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
2439 break;
2440 default:
2441 R600_ERR("Unknown instruction %0x\n", cf->inst);
2442 }
2443 }
2444
2445 id = cf->addr;
2446 nliteral = 0;
2447 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
2448 r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
2449
2450 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2451 fprintf(stderr, "SRC0(SEL:%d ", alu->src[0].sel);
2452 fprintf(stderr, "REL:%d ", alu->src[0].rel);
2453 fprintf(stderr, "CHAN:%d ", alu->src[0].chan);
2454 fprintf(stderr, "NEG:%d) ", alu->src[0].neg);
2455 fprintf(stderr, "SRC1(SEL:%d ", alu->src[1].sel);
2456 fprintf(stderr, "REL:%d ", alu->src[1].rel);
2457 fprintf(stderr, "CHAN:%d ", alu->src[1].chan);
2458 fprintf(stderr, "NEG:%d ", alu->src[1].neg);
2459 fprintf(stderr, "IM:%d) ", alu->index_mode);
2460 fprintf(stderr, "LAST:%d)\n", alu->last);
2461 id++;
2462 fprintf(stderr, "%04d %08X %c ", id, bc->bytecode[id], alu->last ? '*' : ' ');
2463 fprintf(stderr, "INST:0x%x ", alu->inst);
2464 fprintf(stderr, "DST(SEL:%d ", alu->dst.sel);
2465 fprintf(stderr, "CHAN:%d ", alu->dst.chan);
2466 fprintf(stderr, "REL:%d ", alu->dst.rel);
2467 fprintf(stderr, "CLAMP:%d) ", alu->dst.clamp);
2468 fprintf(stderr, "BANK_SWIZZLE:%d ", alu->bank_swizzle);
2469 if (alu->is_op3) {
2470 fprintf(stderr, "SRC2(SEL:%d ", alu->src[2].sel);
2471 fprintf(stderr, "REL:%d ", alu->src[2].rel);
2472 fprintf(stderr, "CHAN:%d ", alu->src[2].chan);
2473 fprintf(stderr, "NEG:%d)\n", alu->src[2].neg);
2474 } else {
2475 fprintf(stderr, "SRC0_ABS:%d ", alu->src[0].abs);
2476 fprintf(stderr, "SRC1_ABS:%d ", alu->src[1].abs);
2477 fprintf(stderr, "WRITE_MASK:%d ", alu->dst.write);
2478 fprintf(stderr, "OMOD:%d ", alu->omod);
2479 fprintf(stderr, "EXECUTE_MASK:%d ", alu->predicate);
2480 fprintf(stderr, "UPDATE_PRED:%d\n", alu->predicate);
2481 }
2482
2483 id++;
2484 if (alu->last) {
2485 for (i = 0; i < nliteral; i++, id++) {
2486 float *f = (float*)(bc->bytecode + id);
2487 fprintf(stderr, "%04d %08X\t%f (%d)\n", id, bc->bytecode[id], *f,
2488 *(bc->bytecode + id));
2489 }
2490 id += nliteral & 1;
2491 nliteral = 0;
2492 }
2493 }
2494
2495 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2496 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2497 fprintf(stderr, "INST:0x%x ", tex->inst);
2498 fprintf(stderr, "RESOURCE_ID:%d ", tex->resource_id);
2499 fprintf(stderr, "SRC(GPR:%d ", tex->src_gpr);
2500 fprintf(stderr, "REL:%d)\n", tex->src_rel);
2501 id++;
2502 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2503 fprintf(stderr, "DST(GPR:%d ", tex->dst_gpr);
2504 fprintf(stderr, "REL:%d ", tex->dst_rel);
2505 fprintf(stderr, "SEL_X:%d ", tex->dst_sel_x);
2506 fprintf(stderr, "SEL_Y:%d ", tex->dst_sel_y);
2507 fprintf(stderr, "SEL_Z:%d ", tex->dst_sel_z);
2508 fprintf(stderr, "SEL_W:%d) ", tex->dst_sel_w);
2509 fprintf(stderr, "LOD_BIAS:%d ", tex->lod_bias);
2510 fprintf(stderr, "COORD_TYPE_X:%d ", tex->coord_type_x);
2511 fprintf(stderr, "COORD_TYPE_Y:%d ", tex->coord_type_y);
2512 fprintf(stderr, "COORD_TYPE_Z:%d ", tex->coord_type_z);
2513 fprintf(stderr, "COORD_TYPE_W:%d\n", tex->coord_type_w);
2514 id++;
2515 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2516 fprintf(stderr, "OFFSET_X:%d ", tex->offset_x);
2517 fprintf(stderr, "OFFSET_Y:%d ", tex->offset_y);
2518 fprintf(stderr, "OFFSET_Z:%d ", tex->offset_z);
2519 fprintf(stderr, "SAMPLER_ID:%d ", tex->sampler_id);
2520 fprintf(stderr, "SRC(SEL_X:%d ", tex->src_sel_x);
2521 fprintf(stderr, "SEL_Y:%d ", tex->src_sel_y);
2522 fprintf(stderr, "SEL_Z:%d ", tex->src_sel_z);
2523 fprintf(stderr, "SEL_W:%d)\n", tex->src_sel_w);
2524 id++;
2525 fprintf(stderr, "%04d %08X \n", id, bc->bytecode[id]);
2526 id++;
2527 }
2528
2529 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2530 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2531 fprintf(stderr, "INST:%d ", vtx->inst);
2532 fprintf(stderr, "FETCH_TYPE:%d ", vtx->fetch_type);
2533 fprintf(stderr, "BUFFER_ID:%d\n", vtx->buffer_id);
2534 id++;
2535 /* This assumes that no semantic fetches exist */
2536 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2537 fprintf(stderr, "SRC(GPR:%d ", vtx->src_gpr);
2538 fprintf(stderr, "SEL_X:%d) ", vtx->src_sel_x);
2539 if (bc->chip_class < CAYMAN)
2540 fprintf(stderr, "MEGA_FETCH_COUNT:%d ", vtx->mega_fetch_count);
2541 else
2542 fprintf(stderr, "SEL_Y:%d) ", 0);
2543 fprintf(stderr, "DST(GPR:%d ", vtx->dst_gpr);
2544 fprintf(stderr, "SEL_X:%d ", vtx->dst_sel_x);
2545 fprintf(stderr, "SEL_Y:%d ", vtx->dst_sel_y);
2546 fprintf(stderr, "SEL_Z:%d ", vtx->dst_sel_z);
2547 fprintf(stderr, "SEL_W:%d) ", vtx->dst_sel_w);
2548 fprintf(stderr, "USE_CONST_FIELDS:%d ", vtx->use_const_fields);
2549 fprintf(stderr, "FORMAT(DATA:%d ", vtx->data_format);
2550 fprintf(stderr, "NUM:%d ", vtx->num_format_all);
2551 fprintf(stderr, "COMP:%d ", vtx->format_comp_all);
2552 fprintf(stderr, "MODE:%d)\n", vtx->srf_mode_all);
2553 id++;
2554 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2555 fprintf(stderr, "ENDIAN:%d ", vtx->endian);
2556 fprintf(stderr, "OFFSET:%d\n", vtx->offset);
2557 /* XXX */
2558 id++;
2559 fprintf(stderr, "%04d %08X \n", id, bc->bytecode[id]);
2560 id++;
2561 }
2562 }
2563
2564 fprintf(stderr, "--------------------------------------\n");
2565 }
2566
2567 static void r600_vertex_data_type(enum pipe_format pformat,
2568 unsigned *format,
2569 unsigned *num_format, unsigned *format_comp, unsigned *endian)
2570 {
2571 const struct util_format_description *desc;
2572 unsigned i;
2573
2574 *format = 0;
2575 *num_format = 0;
2576 *format_comp = 0;
2577 *endian = ENDIAN_NONE;
2578
2579 desc = util_format_description(pformat);
2580 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
2581 goto out_unknown;
2582 }
2583
2584 /* Find the first non-VOID channel. */
2585 for (i = 0; i < 4; i++) {
2586 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2587 break;
2588 }
2589 }
2590
2591 *endian = r600_endian_swap(desc->channel[i].size);
2592
2593 switch (desc->channel[i].type) {
2594 /* Half-floats, floats, ints */
2595 case UTIL_FORMAT_TYPE_FLOAT:
2596 switch (desc->channel[i].size) {
2597 case 16:
2598 switch (desc->nr_channels) {
2599 case 1:
2600 *format = FMT_16_FLOAT;
2601 break;
2602 case 2:
2603 *format = FMT_16_16_FLOAT;
2604 break;
2605 case 3:
2606 case 4:
2607 *format = FMT_16_16_16_16_FLOAT;
2608 break;
2609 }
2610 break;
2611 case 32:
2612 switch (desc->nr_channels) {
2613 case 1:
2614 *format = FMT_32_FLOAT;
2615 break;
2616 case 2:
2617 *format = FMT_32_32_FLOAT;
2618 break;
2619 case 3:
2620 *format = FMT_32_32_32_FLOAT;
2621 break;
2622 case 4:
2623 *format = FMT_32_32_32_32_FLOAT;
2624 break;
2625 }
2626 break;
2627 default:
2628 goto out_unknown;
2629 }
2630 break;
2631 /* Unsigned ints */
2632 case UTIL_FORMAT_TYPE_UNSIGNED:
2633 /* Signed ints */
2634 case UTIL_FORMAT_TYPE_SIGNED:
2635 switch (desc->channel[i].size) {
2636 case 8:
2637 switch (desc->nr_channels) {
2638 case 1:
2639 *format = FMT_8;
2640 break;
2641 case 2:
2642 *format = FMT_8_8;
2643 break;
2644 case 3:
2645 case 4:
2646 *format = FMT_8_8_8_8;
2647 break;
2648 }
2649 break;
2650 case 10:
2651 if (desc->nr_channels != 4)
2652 goto out_unknown;
2653
2654 *format = FMT_2_10_10_10;
2655 break;
2656 case 16:
2657 switch (desc->nr_channels) {
2658 case 1:
2659 *format = FMT_16;
2660 break;
2661 case 2:
2662 *format = FMT_16_16;
2663 break;
2664 case 3:
2665 case 4:
2666 *format = FMT_16_16_16_16;
2667 break;
2668 }
2669 break;
2670 case 32:
2671 switch (desc->nr_channels) {
2672 case 1:
2673 *format = FMT_32;
2674 break;
2675 case 2:
2676 *format = FMT_32_32;
2677 break;
2678 case 3:
2679 *format = FMT_32_32_32;
2680 break;
2681 case 4:
2682 *format = FMT_32_32_32_32;
2683 break;
2684 }
2685 break;
2686 default:
2687 goto out_unknown;
2688 }
2689 break;
2690 default:
2691 goto out_unknown;
2692 }
2693
2694 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2695 *format_comp = 1;
2696 }
2697
2698 *num_format = 0;
2699 if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED ||
2700 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2701 if (!desc->channel[i].normalized) {
2702 if (desc->channel[i].pure_integer)
2703 *num_format = 1;
2704 else
2705 *num_format = 2;
2706 }
2707 }
2708 return;
2709 out_unknown:
2710 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
2711 }
2712
2713 int r600_vertex_elements_build_fetch_shader(struct r600_context *rctx, struct r600_vertex_element *ve)
2714 {
2715 static int dump_shaders = -1;
2716
2717 struct r600_bytecode bc;
2718 struct r600_bytecode_vtx vtx;
2719 struct pipe_vertex_element *elements = ve->elements;
2720 const struct util_format_description *desc;
2721 unsigned fetch_resource_start = rctx->chip_class >= EVERGREEN ? 0 : 160;
2722 unsigned format, num_format, format_comp, endian;
2723 uint32_t *bytecode;
2724 int i, r;
2725
2726 memset(&bc, 0, sizeof(bc));
2727 r600_bytecode_init(&bc, rctx->chip_class, rctx->family);
2728
2729 for (i = 0; i < ve->count; i++) {
2730 if (elements[i].instance_divisor > 1) {
2731 struct r600_bytecode_alu alu;
2732
2733 memset(&alu, 0, sizeof(alu));
2734 alu.inst = BC_INST(&bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
2735 alu.src[0].sel = 0;
2736 alu.src[0].chan = 3;
2737
2738 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2739 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2740
2741 alu.dst.sel = i + 1;
2742 alu.dst.chan = 3;
2743 alu.dst.write = 1;
2744 alu.last = 1;
2745
2746 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2747 r600_bytecode_clear(&bc);
2748 return r;
2749 }
2750 }
2751 }
2752
2753 for (i = 0; i < ve->count; i++) {
2754 r600_vertex_data_type(ve->elements[i].src_format,
2755 &format, &num_format, &format_comp, &endian);
2756
2757 desc = util_format_description(ve->elements[i].src_format);
2758 if (desc == NULL) {
2759 r600_bytecode_clear(&bc);
2760 R600_ERR("unknown format %d\n", ve->elements[i].src_format);
2761 return -EINVAL;
2762 }
2763
2764 if (elements[i].src_offset > 65535) {
2765 r600_bytecode_clear(&bc);
2766 R600_ERR("too big src_offset: %u\n", elements[i].src_offset);
2767 return -EINVAL;
2768 }
2769
2770 memset(&vtx, 0, sizeof(vtx));
2771 vtx.buffer_id = elements[i].vertex_buffer_index + fetch_resource_start;
2772 vtx.fetch_type = elements[i].instance_divisor ? 1 : 0;
2773 vtx.src_gpr = elements[i].instance_divisor > 1 ? i + 1 : 0;
2774 vtx.src_sel_x = elements[i].instance_divisor ? 3 : 0;
2775 vtx.mega_fetch_count = 0x1F;
2776 vtx.dst_gpr = i + 1;
2777 vtx.dst_sel_x = desc->swizzle[0];
2778 vtx.dst_sel_y = desc->swizzle[1];
2779 vtx.dst_sel_z = desc->swizzle[2];
2780 vtx.dst_sel_w = desc->swizzle[3];
2781 vtx.data_format = format;
2782 vtx.num_format_all = num_format;
2783 vtx.format_comp_all = format_comp;
2784 vtx.srf_mode_all = 1;
2785 vtx.offset = elements[i].src_offset;
2786 vtx.endian = endian;
2787
2788 if ((r = r600_bytecode_add_vtx(&bc, &vtx))) {
2789 r600_bytecode_clear(&bc);
2790 return r;
2791 }
2792 }
2793
2794 r600_bytecode_add_cfinst(&bc, BC_INST(&bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN));
2795
2796 if ((r = r600_bytecode_build(&bc))) {
2797 r600_bytecode_clear(&bc);
2798 return r;
2799 }
2800
2801 if (dump_shaders == -1)
2802 dump_shaders = debug_get_bool_option("R600_DUMP_SHADERS", FALSE);
2803
2804 if (dump_shaders) {
2805 fprintf(stderr, "--------------------------------------------------------------\n");
2806 r600_bytecode_dump(&bc);
2807 fprintf(stderr, "______________________________________________________________\n");
2808 }
2809
2810 ve->fs_size = bc.ndw*4;
2811
2812 ve->fetch_shader = (struct r600_resource*)
2813 pipe_buffer_create(rctx->context.screen,
2814 PIPE_BIND_CUSTOM,
2815 PIPE_USAGE_IMMUTABLE, ve->fs_size);
2816 if (ve->fetch_shader == NULL) {
2817 r600_bytecode_clear(&bc);
2818 return -ENOMEM;
2819 }
2820
2821 bytecode = rctx->ws->buffer_map(ve->fetch_shader->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
2822 if (bytecode == NULL) {
2823 r600_bytecode_clear(&bc);
2824 pipe_resource_reference((struct pipe_resource**)&ve->fetch_shader, NULL);
2825 return -ENOMEM;
2826 }
2827
2828 if (R600_BIG_ENDIAN) {
2829 for (i = 0; i < ve->fs_size / 4; ++i) {
2830 bytecode[i] = bswap_32(bc.bytecode[i]);
2831 }
2832 } else {
2833 memcpy(bytecode, bc.bytecode, ve->fs_size);
2834 }
2835
2836 rctx->ws->buffer_unmap(ve->fetch_shader->cs_buf);
2837 r600_bytecode_clear(&bc);
2838
2839 if (rctx->chip_class >= EVERGREEN)
2840 evergreen_fetch_shader(&rctx->context, ve);
2841 else
2842 r600_fetch_shader(&rctx->context, ve);
2843
2844 return 0;
2845 }