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r600: add support for vertex fetches via texture cache
[mesa.git] / src / gallium / drivers / r600 / r600_asm.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_opcodes.h"
25 #include "r600_formats.h"
26 #include "r600_shader.h"
27 #include "r600d.h"
28
29 #include <errno.h>
30 #include "util/u_bitcast.h"
31 #include "util/u_dump.h"
32 #include "util/u_memory.h"
33 #include "util/u_math.h"
34 #include "pipe/p_shader_tokens.h"
35
36 #include "sb/sb_public.h"
37
38 #define NUM_OF_CYCLES 3
39 #define NUM_OF_COMPONENTS 4
40
41 static inline bool alu_writes(struct r600_bytecode_alu *alu)
42 {
43 return alu->dst.write || alu->is_op3;
44 }
45
46 static inline unsigned int r600_bytecode_get_num_operands(
47 struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
48 {
49 return r600_isa_alu(alu->op)->src_count;
50 }
51
52 int r700_bytecode_alu_build(struct r600_bytecode *bc,
53 struct r600_bytecode_alu *alu, unsigned id);
54
55 static struct r600_bytecode_cf *r600_bytecode_cf(void)
56 {
57 struct r600_bytecode_cf *cf = CALLOC_STRUCT(r600_bytecode_cf);
58
59 if (!cf)
60 return NULL;
61 LIST_INITHEAD(&cf->list);
62 LIST_INITHEAD(&cf->alu);
63 LIST_INITHEAD(&cf->vtx);
64 LIST_INITHEAD(&cf->tex);
65 LIST_INITHEAD(&cf->gds);
66 return cf;
67 }
68
69 static struct r600_bytecode_alu *r600_bytecode_alu(void)
70 {
71 struct r600_bytecode_alu *alu = CALLOC_STRUCT(r600_bytecode_alu);
72
73 if (!alu)
74 return NULL;
75 LIST_INITHEAD(&alu->list);
76 return alu;
77 }
78
79 static struct r600_bytecode_vtx *r600_bytecode_vtx(void)
80 {
81 struct r600_bytecode_vtx *vtx = CALLOC_STRUCT(r600_bytecode_vtx);
82
83 if (!vtx)
84 return NULL;
85 LIST_INITHEAD(&vtx->list);
86 return vtx;
87 }
88
89 static struct r600_bytecode_tex *r600_bytecode_tex(void)
90 {
91 struct r600_bytecode_tex *tex = CALLOC_STRUCT(r600_bytecode_tex);
92
93 if (!tex)
94 return NULL;
95 LIST_INITHEAD(&tex->list);
96 return tex;
97 }
98
99 static struct r600_bytecode_gds *r600_bytecode_gds(void)
100 {
101 struct r600_bytecode_gds *gds = CALLOC_STRUCT(r600_bytecode_gds);
102
103 if (gds == NULL)
104 return NULL;
105 LIST_INITHEAD(&gds->list);
106 return gds;
107 }
108
109 static unsigned stack_entry_size(enum radeon_family chip) {
110 /* Wavefront size:
111 * 64: R600/RV670/RV770/Cypress/R740/Barts/Turks/Caicos/
112 * Aruba/Sumo/Sumo2/redwood/juniper
113 * 32: R630/R730/R710/Palm/Cedar
114 * 16: R610/Rs780
115 *
116 * Stack row size:
117 * Wavefront Size 16 32 48 64
118 * Columns per Row (R6xx/R7xx/R8xx only) 8 8 4 4
119 * Columns per Row (R9xx+) 8 4 4 4 */
120
121 switch (chip) {
122 /* FIXME: are some chips missing here? */
123 /* wavefront size 16 */
124 case CHIP_RV610:
125 case CHIP_RS780:
126 case CHIP_RV620:
127 case CHIP_RS880:
128 /* wavefront size 32 */
129 case CHIP_RV630:
130 case CHIP_RV635:
131 case CHIP_RV730:
132 case CHIP_RV710:
133 case CHIP_PALM:
134 case CHIP_CEDAR:
135 return 8;
136
137 /* wavefront size 64 */
138 default:
139 return 4;
140 }
141 }
142
143 void r600_bytecode_init(struct r600_bytecode *bc,
144 enum chip_class chip_class,
145 enum radeon_family family,
146 bool has_compressed_msaa_texturing)
147 {
148 static unsigned next_shader_id = 0;
149
150 bc->debug_id = ++next_shader_id;
151
152 if ((chip_class == R600) &&
153 (family != CHIP_RV670 && family != CHIP_RS780 && family != CHIP_RS880)) {
154 bc->ar_handling = AR_HANDLE_RV6XX;
155 bc->r6xx_nop_after_rel_dst = 1;
156 } else {
157 bc->ar_handling = AR_HANDLE_NORMAL;
158 bc->r6xx_nop_after_rel_dst = 0;
159 }
160
161 LIST_INITHEAD(&bc->cf);
162 bc->chip_class = chip_class;
163 bc->family = family;
164 bc->has_compressed_msaa_texturing = has_compressed_msaa_texturing;
165 bc->stack.entry_size = stack_entry_size(family);
166 }
167
168 int r600_bytecode_add_cf(struct r600_bytecode *bc)
169 {
170 struct r600_bytecode_cf *cf = r600_bytecode_cf();
171
172 if (!cf)
173 return -ENOMEM;
174 LIST_ADDTAIL(&cf->list, &bc->cf);
175 if (bc->cf_last) {
176 cf->id = bc->cf_last->id + 2;
177 if (bc->cf_last->eg_alu_extended) {
178 /* take into account extended alu size */
179 cf->id += 2;
180 bc->ndw += 2;
181 }
182 }
183 bc->cf_last = cf;
184 bc->ncf++;
185 bc->ndw += 2;
186 bc->force_add_cf = 0;
187 bc->ar_loaded = 0;
188 return 0;
189 }
190
191 int r600_bytecode_add_output(struct r600_bytecode *bc,
192 const struct r600_bytecode_output *output)
193 {
194 int r;
195
196 if (output->gpr >= bc->ngpr)
197 bc->ngpr = output->gpr + 1;
198
199 if (bc->cf_last && (bc->cf_last->op == output->op ||
200 (bc->cf_last->op == CF_OP_EXPORT &&
201 output->op == CF_OP_EXPORT_DONE)) &&
202 output->type == bc->cf_last->output.type &&
203 output->elem_size == bc->cf_last->output.elem_size &&
204 output->swizzle_x == bc->cf_last->output.swizzle_x &&
205 output->swizzle_y == bc->cf_last->output.swizzle_y &&
206 output->swizzle_z == bc->cf_last->output.swizzle_z &&
207 output->swizzle_w == bc->cf_last->output.swizzle_w &&
208 output->comp_mask == bc->cf_last->output.comp_mask &&
209 (output->burst_count + bc->cf_last->output.burst_count) <= 16) {
210
211 if ((output->gpr + output->burst_count) == bc->cf_last->output.gpr &&
212 (output->array_base + output->burst_count) == bc->cf_last->output.array_base) {
213
214 bc->cf_last->op = bc->cf_last->output.op = output->op;
215 bc->cf_last->output.gpr = output->gpr;
216 bc->cf_last->output.array_base = output->array_base;
217 bc->cf_last->output.burst_count += output->burst_count;
218 return 0;
219
220 } else if (output->gpr == (bc->cf_last->output.gpr + bc->cf_last->output.burst_count) &&
221 output->array_base == (bc->cf_last->output.array_base + bc->cf_last->output.burst_count)) {
222
223 bc->cf_last->op = bc->cf_last->output.op = output->op;
224 bc->cf_last->output.burst_count += output->burst_count;
225 return 0;
226 }
227 }
228
229 r = r600_bytecode_add_cf(bc);
230 if (r)
231 return r;
232 bc->cf_last->op = output->op;
233 memcpy(&bc->cf_last->output, output, sizeof(struct r600_bytecode_output));
234 bc->cf_last->barrier = 1;
235 return 0;
236 }
237
238 /* alu instructions that can ony exits once per group */
239 static int is_alu_once_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
240 {
241 return r600_isa_alu(alu->op)->flags & (AF_KILL | AF_PRED) || alu->is_lds_idx_op || alu->op == ALU_OP0_GROUP_BARRIER;
242 }
243
244 static int is_alu_reduction_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
245 {
246 return (r600_isa_alu(alu->op)->flags & AF_REPL) &&
247 (r600_isa_alu_slots(bc->isa->hw_class, alu->op) == AF_4V);
248 }
249
250 static int is_alu_mova_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
251 {
252 return r600_isa_alu(alu->op)->flags & AF_MOVA;
253 }
254
255 static int alu_uses_rel(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
256 {
257 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
258 unsigned src;
259
260 if (alu->dst.rel) {
261 return 1;
262 }
263
264 for (src = 0; src < num_src; ++src) {
265 if (alu->src[src].rel) {
266 return 1;
267 }
268 }
269 return 0;
270 }
271
272 static int is_lds_read(int sel)
273 {
274 return sel == EG_V_SQ_ALU_SRC_LDS_OQ_A_POP || sel == EG_V_SQ_ALU_SRC_LDS_OQ_B_POP;
275 }
276
277 static int alu_uses_lds(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
278 {
279 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
280 unsigned src;
281
282 for (src = 0; src < num_src; ++src) {
283 if (is_lds_read(alu->src[src].sel)) {
284 return 1;
285 }
286 }
287 return 0;
288 }
289
290 static int is_alu_64bit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
291 {
292 const struct alu_op_info *op = r600_isa_alu(alu->op);
293 return (op->flags & AF_64);
294 }
295
296 static int is_alu_vec_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
297 {
298 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
299 return !(slots & AF_S);
300 }
301
302 static int is_alu_trans_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
303 {
304 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
305 return !(slots & AF_V);
306 }
307
308 /* alu instructions that can execute on any unit */
309 static int is_alu_any_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
310 {
311 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
312 return slots == AF_VS;
313 }
314
315 static int is_nop_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
316 {
317 return alu->op == ALU_OP0_NOP;
318 }
319
320 static int assign_alu_units(struct r600_bytecode *bc, struct r600_bytecode_alu *alu_first,
321 struct r600_bytecode_alu *assignment[5])
322 {
323 struct r600_bytecode_alu *alu;
324 unsigned i, chan, trans;
325 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
326
327 for (i = 0; i < max_slots; i++)
328 assignment[i] = NULL;
329
330 for (alu = alu_first; alu; alu = LIST_ENTRY(struct r600_bytecode_alu, alu->list.next, list)) {
331 chan = alu->dst.chan;
332 if (max_slots == 4)
333 trans = 0;
334 else if (is_alu_trans_unit_inst(bc, alu))
335 trans = 1;
336 else if (is_alu_vec_unit_inst(bc, alu))
337 trans = 0;
338 else if (assignment[chan])
339 trans = 1; /* Assume ALU_INST_PREFER_VECTOR. */
340 else
341 trans = 0;
342
343 if (trans) {
344 if (assignment[4]) {
345 assert(0); /* ALU.Trans has already been allocated. */
346 return -1;
347 }
348 assignment[4] = alu;
349 } else {
350 if (assignment[chan]) {
351 assert(0); /* ALU.chan has already been allocated. */
352 return -1;
353 }
354 assignment[chan] = alu;
355 }
356
357 if (alu->last)
358 break;
359 }
360 return 0;
361 }
362
363 struct alu_bank_swizzle {
364 int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
365 int hw_cfile_addr[4];
366 int hw_cfile_elem[4];
367 };
368
369 static const unsigned cycle_for_bank_swizzle_vec[][3] = {
370 [SQ_ALU_VEC_012] = { 0, 1, 2 },
371 [SQ_ALU_VEC_021] = { 0, 2, 1 },
372 [SQ_ALU_VEC_120] = { 1, 2, 0 },
373 [SQ_ALU_VEC_102] = { 1, 0, 2 },
374 [SQ_ALU_VEC_201] = { 2, 0, 1 },
375 [SQ_ALU_VEC_210] = { 2, 1, 0 }
376 };
377
378 static const unsigned cycle_for_bank_swizzle_scl[][3] = {
379 [SQ_ALU_SCL_210] = { 2, 1, 0 },
380 [SQ_ALU_SCL_122] = { 1, 2, 2 },
381 [SQ_ALU_SCL_212] = { 2, 1, 2 },
382 [SQ_ALU_SCL_221] = { 2, 2, 1 }
383 };
384
385 static void init_bank_swizzle(struct alu_bank_swizzle *bs)
386 {
387 int i, cycle, component;
388 /* set up gpr use */
389 for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
390 for (component = 0; component < NUM_OF_COMPONENTS; component++)
391 bs->hw_gpr[cycle][component] = -1;
392 for (i = 0; i < 4; i++)
393 bs->hw_cfile_addr[i] = -1;
394 for (i = 0; i < 4; i++)
395 bs->hw_cfile_elem[i] = -1;
396 }
397
398 static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan, unsigned cycle)
399 {
400 if (bs->hw_gpr[cycle][chan] == -1)
401 bs->hw_gpr[cycle][chan] = sel;
402 else if (bs->hw_gpr[cycle][chan] != (int)sel) {
403 /* Another scalar operation has already used the GPR read port for the channel. */
404 return -1;
405 }
406 return 0;
407 }
408
409 static int reserve_cfile(struct r600_bytecode *bc, struct alu_bank_swizzle *bs, unsigned sel, unsigned chan)
410 {
411 int res, num_res = 4;
412 if (bc->chip_class >= R700) {
413 num_res = 2;
414 chan /= 2;
415 }
416 for (res = 0; res < num_res; ++res) {
417 if (bs->hw_cfile_addr[res] == -1) {
418 bs->hw_cfile_addr[res] = sel;
419 bs->hw_cfile_elem[res] = chan;
420 return 0;
421 } else if (bs->hw_cfile_addr[res] == sel &&
422 bs->hw_cfile_elem[res] == chan)
423 return 0; /* Read for this scalar element already reserved, nothing to do here. */
424 }
425 /* All cfile read ports are used, cannot reference vector element. */
426 return -1;
427 }
428
429 static int is_gpr(unsigned sel)
430 {
431 return (sel <= 127);
432 }
433
434 /* CB constants start at 512, and get translated to a kcache index when ALU
435 * clauses are constructed. Note that we handle kcache constants the same way
436 * as (the now gone) cfile constants, is that really required? */
437 static int is_cfile(unsigned sel)
438 {
439 return (sel > 255 && sel < 512) ||
440 (sel > 511 && sel < 4607) || /* Kcache before translation. */
441 (sel > 127 && sel < 192); /* Kcache after translation. */
442 }
443
444 static int is_const(int sel)
445 {
446 return is_cfile(sel) ||
447 (sel >= V_SQ_ALU_SRC_0 &&
448 sel <= V_SQ_ALU_SRC_LITERAL);
449 }
450
451 static int check_vector(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
452 struct alu_bank_swizzle *bs, int bank_swizzle)
453 {
454 int r, src, num_src, sel, elem, cycle;
455
456 num_src = r600_bytecode_get_num_operands(bc, alu);
457 for (src = 0; src < num_src; src++) {
458 sel = alu->src[src].sel;
459 elem = alu->src[src].chan;
460 if (is_gpr(sel)) {
461 cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src];
462 if (src == 1 && sel == alu->src[0].sel && elem == alu->src[0].chan)
463 /* Nothing to do; special-case optimization,
464 * second source uses first source’s reservation. */
465 continue;
466 else {
467 r = reserve_gpr(bs, sel, elem, cycle);
468 if (r)
469 return r;
470 }
471 } else if (is_cfile(sel)) {
472 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
473 if (r)
474 return r;
475 }
476 /* No restrictions on PV, PS, literal or special constants. */
477 }
478 return 0;
479 }
480
481 static int check_scalar(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
482 struct alu_bank_swizzle *bs, int bank_swizzle)
483 {
484 int r, src, num_src, const_count, sel, elem, cycle;
485
486 num_src = r600_bytecode_get_num_operands(bc, alu);
487 for (const_count = 0, src = 0; src < num_src; ++src) {
488 sel = alu->src[src].sel;
489 elem = alu->src[src].chan;
490 if (is_const(sel)) { /* Any constant, including literal and inline constants. */
491 if (const_count >= 2)
492 /* More than two references to a constant in
493 * transcendental operation. */
494 return -1;
495 else
496 const_count++;
497 }
498 if (is_cfile(sel)) {
499 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
500 if (r)
501 return r;
502 }
503 }
504 for (src = 0; src < num_src; ++src) {
505 sel = alu->src[src].sel;
506 elem = alu->src[src].chan;
507 if (is_gpr(sel)) {
508 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
509 if (cycle < const_count)
510 /* Cycle for GPR load conflicts with
511 * constant load in transcendental operation. */
512 return -1;
513 r = reserve_gpr(bs, sel, elem, cycle);
514 if (r)
515 return r;
516 }
517 /* PV PS restrictions */
518 if (const_count && (sel == 254 || sel == 255)) {
519 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
520 if (cycle < const_count)
521 return -1;
522 }
523 }
524 return 0;
525 }
526
527 static int check_and_set_bank_swizzle(struct r600_bytecode *bc,
528 struct r600_bytecode_alu *slots[5])
529 {
530 struct alu_bank_swizzle bs;
531 int bank_swizzle[5];
532 int i, r = 0, forced = 1;
533 boolean scalar_only = bc->chip_class == CAYMAN ? false : true;
534 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
535
536 for (i = 0; i < max_slots; i++) {
537 if (slots[i]) {
538 if (slots[i]->bank_swizzle_force) {
539 slots[i]->bank_swizzle = slots[i]->bank_swizzle_force;
540 } else {
541 forced = 0;
542 }
543 }
544
545 if (i < 4 && slots[i])
546 scalar_only = false;
547 }
548 if (forced)
549 return 0;
550
551 /* Just check every possible combination of bank swizzle.
552 * Not very efficent, but works on the first try in most of the cases. */
553 for (i = 0; i < 4; i++)
554 if (!slots[i] || !slots[i]->bank_swizzle_force)
555 bank_swizzle[i] = SQ_ALU_VEC_012;
556 else
557 bank_swizzle[i] = slots[i]->bank_swizzle;
558
559 bank_swizzle[4] = SQ_ALU_SCL_210;
560 while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
561
562 init_bank_swizzle(&bs);
563 if (scalar_only == false) {
564 for (i = 0; i < 4; i++) {
565 if (slots[i]) {
566 r = check_vector(bc, slots[i], &bs, bank_swizzle[i]);
567 if (r)
568 break;
569 }
570 }
571 } else
572 r = 0;
573
574 if (!r && max_slots == 5 && slots[4]) {
575 r = check_scalar(bc, slots[4], &bs, bank_swizzle[4]);
576 }
577 if (!r) {
578 for (i = 0; i < max_slots; i++) {
579 if (slots[i])
580 slots[i]->bank_swizzle = bank_swizzle[i];
581 }
582 return 0;
583 }
584
585 if (scalar_only) {
586 bank_swizzle[4]++;
587 } else {
588 for (i = 0; i < max_slots; i++) {
589 if (!slots[i] || !slots[i]->bank_swizzle_force) {
590 bank_swizzle[i]++;
591 if (bank_swizzle[i] <= SQ_ALU_VEC_210)
592 break;
593 else if (i < max_slots - 1)
594 bank_swizzle[i] = SQ_ALU_VEC_012;
595 else
596 return -1;
597 }
598 }
599 }
600 }
601
602 /* Couldn't find a working swizzle. */
603 return -1;
604 }
605
606 static int replace_gpr_with_pv_ps(struct r600_bytecode *bc,
607 struct r600_bytecode_alu *slots[5], struct r600_bytecode_alu *alu_prev)
608 {
609 struct r600_bytecode_alu *prev[5];
610 int gpr[5], chan[5];
611 int i, j, r, src, num_src;
612 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
613
614 r = assign_alu_units(bc, alu_prev, prev);
615 if (r)
616 return r;
617
618 for (i = 0; i < max_slots; ++i) {
619 if (prev[i] && alu_writes(prev[i]) && !prev[i]->dst.rel) {
620
621 if (is_alu_64bit_inst(bc, prev[i])) {
622 gpr[i] = -1;
623 continue;
624 }
625
626 gpr[i] = prev[i]->dst.sel;
627 /* cube writes more than PV.X */
628 if (is_alu_reduction_inst(bc, prev[i]))
629 chan[i] = 0;
630 else
631 chan[i] = prev[i]->dst.chan;
632 } else
633 gpr[i] = -1;
634 }
635
636 for (i = 0; i < max_slots; ++i) {
637 struct r600_bytecode_alu *alu = slots[i];
638 if (!alu)
639 continue;
640
641 if (is_alu_64bit_inst(bc, alu))
642 continue;
643 num_src = r600_bytecode_get_num_operands(bc, alu);
644 for (src = 0; src < num_src; ++src) {
645 if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
646 continue;
647
648 if (bc->chip_class < CAYMAN) {
649 if (alu->src[src].sel == gpr[4] &&
650 alu->src[src].chan == chan[4] &&
651 alu_prev->pred_sel == alu->pred_sel) {
652 alu->src[src].sel = V_SQ_ALU_SRC_PS;
653 alu->src[src].chan = 0;
654 continue;
655 }
656 }
657
658 for (j = 0; j < 4; ++j) {
659 if (alu->src[src].sel == gpr[j] &&
660 alu->src[src].chan == j &&
661 alu_prev->pred_sel == alu->pred_sel) {
662 alu->src[src].sel = V_SQ_ALU_SRC_PV;
663 alu->src[src].chan = chan[j];
664 break;
665 }
666 }
667 }
668 }
669
670 return 0;
671 }
672
673 void r600_bytecode_special_constants(uint32_t value, unsigned *sel, unsigned *neg, unsigned abs)
674 {
675 switch(value) {
676 case 0:
677 *sel = V_SQ_ALU_SRC_0;
678 break;
679 case 1:
680 *sel = V_SQ_ALU_SRC_1_INT;
681 break;
682 case -1:
683 *sel = V_SQ_ALU_SRC_M_1_INT;
684 break;
685 case 0x3F800000: /* 1.0f */
686 *sel = V_SQ_ALU_SRC_1;
687 break;
688 case 0x3F000000: /* 0.5f */
689 *sel = V_SQ_ALU_SRC_0_5;
690 break;
691 case 0xBF800000: /* -1.0f */
692 *sel = V_SQ_ALU_SRC_1;
693 *neg ^= !abs;
694 break;
695 case 0xBF000000: /* -0.5f */
696 *sel = V_SQ_ALU_SRC_0_5;
697 *neg ^= !abs;
698 break;
699 default:
700 *sel = V_SQ_ALU_SRC_LITERAL;
701 break;
702 }
703 }
704
705 /* compute how many literal are needed */
706 static int r600_bytecode_alu_nliterals(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
707 uint32_t literal[4], unsigned *nliteral)
708 {
709 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
710 unsigned i, j;
711
712 for (i = 0; i < num_src; ++i) {
713 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
714 uint32_t value = alu->src[i].value;
715 unsigned found = 0;
716 for (j = 0; j < *nliteral; ++j) {
717 if (literal[j] == value) {
718 found = 1;
719 break;
720 }
721 }
722 if (!found) {
723 if (*nliteral >= 4)
724 return -EINVAL;
725 literal[(*nliteral)++] = value;
726 }
727 }
728 }
729 return 0;
730 }
731
732 static void r600_bytecode_alu_adjust_literals(struct r600_bytecode *bc,
733 struct r600_bytecode_alu *alu,
734 uint32_t literal[4], unsigned nliteral)
735 {
736 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
737 unsigned i, j;
738
739 for (i = 0; i < num_src; ++i) {
740 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
741 uint32_t value = alu->src[i].value;
742 for (j = 0; j < nliteral; ++j) {
743 if (literal[j] == value) {
744 alu->src[i].chan = j;
745 break;
746 }
747 }
748 }
749 }
750 }
751
752 static int merge_inst_groups(struct r600_bytecode *bc, struct r600_bytecode_alu *slots[5],
753 struct r600_bytecode_alu *alu_prev)
754 {
755 struct r600_bytecode_alu *prev[5];
756 struct r600_bytecode_alu *result[5] = { NULL };
757
758 uint32_t literal[4], prev_literal[4];
759 unsigned nliteral = 0, prev_nliteral = 0;
760
761 int i, j, r, src, num_src;
762 int num_once_inst = 0;
763 int have_mova = 0, have_rel = 0;
764 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
765
766 r = assign_alu_units(bc, alu_prev, prev);
767 if (r)
768 return r;
769
770 for (i = 0; i < max_slots; ++i) {
771 if (prev[i]) {
772 if (prev[i]->pred_sel)
773 return 0;
774 if (is_alu_once_inst(bc, prev[i]))
775 return 0;
776 }
777 if (slots[i]) {
778 if (slots[i]->pred_sel)
779 return 0;
780 if (is_alu_once_inst(bc, slots[i]))
781 return 0;
782 }
783 }
784
785 for (i = 0; i < max_slots; ++i) {
786 struct r600_bytecode_alu *alu;
787
788 if (num_once_inst > 0)
789 return 0;
790
791 /* check number of literals */
792 if (prev[i]) {
793 if (r600_bytecode_alu_nliterals(bc, prev[i], literal, &nliteral))
794 return 0;
795 if (r600_bytecode_alu_nliterals(bc, prev[i], prev_literal, &prev_nliteral))
796 return 0;
797 if (is_alu_mova_inst(bc, prev[i])) {
798 if (have_rel)
799 return 0;
800 have_mova = 1;
801 }
802
803 if (alu_uses_rel(bc, prev[i])) {
804 if (have_mova) {
805 return 0;
806 }
807 have_rel = 1;
808 }
809 if (alu_uses_lds(bc, prev[i]))
810 return 0;
811
812 num_once_inst += is_alu_once_inst(bc, prev[i]);
813 }
814 if (slots[i] && r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral))
815 return 0;
816
817 /* Let's check used slots. */
818 if (prev[i] && !slots[i]) {
819 result[i] = prev[i];
820 continue;
821 } else if (prev[i] && slots[i]) {
822 if (max_slots == 5 && result[4] == NULL && prev[4] == NULL && slots[4] == NULL) {
823 /* Trans unit is still free try to use it. */
824 if (is_alu_any_unit_inst(bc, slots[i]) && !alu_uses_lds(bc, slots[i])) {
825 result[i] = prev[i];
826 result[4] = slots[i];
827 } else if (is_alu_any_unit_inst(bc, prev[i])) {
828 if (slots[i]->dst.sel == prev[i]->dst.sel &&
829 alu_writes(slots[i]) &&
830 alu_writes(prev[i]))
831 return 0;
832
833 result[i] = slots[i];
834 result[4] = prev[i];
835 } else
836 return 0;
837 } else
838 return 0;
839 } else if(!slots[i]) {
840 continue;
841 } else {
842 if (max_slots == 5 && slots[i] && prev[4] &&
843 slots[i]->dst.sel == prev[4]->dst.sel &&
844 slots[i]->dst.chan == prev[4]->dst.chan &&
845 alu_writes(slots[i]) &&
846 alu_writes(prev[4]))
847 return 0;
848
849 result[i] = slots[i];
850 }
851
852 alu = slots[i];
853 num_once_inst += is_alu_once_inst(bc, alu);
854
855 /* don't reschedule NOPs */
856 if (is_nop_inst(bc, alu))
857 return 0;
858
859 if (is_alu_mova_inst(bc, alu)) {
860 if (have_rel) {
861 return 0;
862 }
863 have_mova = 1;
864 }
865
866 if (alu_uses_rel(bc, alu)) {
867 if (have_mova) {
868 return 0;
869 }
870 have_rel = 1;
871 }
872
873 if (alu->op == ALU_OP0_SET_CF_IDX0 ||
874 alu->op == ALU_OP0_SET_CF_IDX1)
875 return 0; /* data hazard with MOVA */
876
877 /* Let's check source gprs */
878 num_src = r600_bytecode_get_num_operands(bc, alu);
879 for (src = 0; src < num_src; ++src) {
880
881 /* Constants don't matter. */
882 if (!is_gpr(alu->src[src].sel))
883 continue;
884
885 for (j = 0; j < max_slots; ++j) {
886 if (!prev[j] || !alu_writes(prev[j]))
887 continue;
888
889 /* If it's relative then we can't determin which gpr is really used. */
890 if (prev[j]->dst.chan == alu->src[src].chan &&
891 (prev[j]->dst.sel == alu->src[src].sel ||
892 prev[j]->dst.rel || alu->src[src].rel))
893 return 0;
894 }
895 }
896 }
897
898 /* more than one PRED_ or KILL_ ? */
899 if (num_once_inst > 1)
900 return 0;
901
902 /* check if the result can still be swizzlet */
903 r = check_and_set_bank_swizzle(bc, result);
904 if (r)
905 return 0;
906
907 /* looks like everything worked out right, apply the changes */
908
909 /* undo adding previus literals */
910 bc->cf_last->ndw -= align(prev_nliteral, 2);
911
912 /* sort instructions */
913 for (i = 0; i < max_slots; ++i) {
914 slots[i] = result[i];
915 if (result[i]) {
916 LIST_DEL(&result[i]->list);
917 result[i]->last = 0;
918 LIST_ADDTAIL(&result[i]->list, &bc->cf_last->alu);
919 }
920 }
921
922 /* determine new last instruction */
923 LIST_ENTRY(struct r600_bytecode_alu, bc->cf_last->alu.prev, list)->last = 1;
924
925 /* determine new first instruction */
926 for (i = 0; i < max_slots; ++i) {
927 if (result[i]) {
928 bc->cf_last->curr_bs_head = result[i];
929 break;
930 }
931 }
932
933 bc->cf_last->prev_bs_head = bc->cf_last->prev2_bs_head;
934 bc->cf_last->prev2_bs_head = NULL;
935
936 return 0;
937 }
938
939 /* we'll keep kcache sets sorted by bank & addr */
940 static int r600_bytecode_alloc_kcache_line(struct r600_bytecode *bc,
941 struct r600_bytecode_kcache *kcache,
942 unsigned bank, unsigned line, unsigned index_mode)
943 {
944 int i, kcache_banks = bc->chip_class >= EVERGREEN ? 4 : 2;
945
946 for (i = 0; i < kcache_banks; i++) {
947 if (kcache[i].mode) {
948 int d;
949
950 if (kcache[i].bank < bank)
951 continue;
952
953 if ((kcache[i].bank == bank && kcache[i].addr > line+1) ||
954 kcache[i].bank > bank) {
955 /* try to insert new line */
956 if (kcache[kcache_banks-1].mode) {
957 /* all sets are in use */
958 return -ENOMEM;
959 }
960
961 memmove(&kcache[i+1],&kcache[i], (kcache_banks-i-1)*sizeof(struct r600_bytecode_kcache));
962 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
963 kcache[i].bank = bank;
964 kcache[i].addr = line;
965 kcache[i].index_mode = index_mode;
966 return 0;
967 }
968
969 d = line - kcache[i].addr;
970
971 if (d == -1) {
972 kcache[i].addr--;
973 if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_2) {
974 /* we are prepending the line to the current set,
975 * discarding the existing second line,
976 * so we'll have to insert line+2 after it */
977 line += 2;
978 continue;
979 } else if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_1) {
980 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
981 return 0;
982 } else {
983 /* V_SQ_CF_KCACHE_LOCK_LOOP_INDEX is not supported */
984 return -ENOMEM;
985 }
986 } else if (d == 1) {
987 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
988 return 0;
989 } else if (d == 0)
990 return 0;
991 } else { /* free kcache set - use it */
992 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
993 kcache[i].bank = bank;
994 kcache[i].addr = line;
995 kcache[i].index_mode = index_mode;
996 return 0;
997 }
998 }
999 return -ENOMEM;
1000 }
1001
1002 static int r600_bytecode_alloc_inst_kcache_lines(struct r600_bytecode *bc,
1003 struct r600_bytecode_kcache *kcache,
1004 struct r600_bytecode_alu *alu)
1005 {
1006 int i, r;
1007
1008 for (i = 0; i < 3; i++) {
1009 unsigned bank, line, sel = alu->src[i].sel, index_mode;
1010
1011 if (sel < 512)
1012 continue;
1013
1014 bank = alu->src[i].kc_bank;
1015 line = (sel-512)>>4;
1016 index_mode = alu->src[i].kc_rel ? 1 : 0; // V_SQ_CF_INDEX_0 / V_SQ_CF_INDEX_NONE
1017
1018 if ((r = r600_bytecode_alloc_kcache_line(bc, kcache, bank, line, index_mode)))
1019 return r;
1020 }
1021 return 0;
1022 }
1023
1024 static int r600_bytecode_assign_kcache_banks(struct r600_bytecode *bc,
1025 struct r600_bytecode_alu *alu,
1026 struct r600_bytecode_kcache * kcache)
1027 {
1028 int i, j;
1029
1030 /* Alter the src operands to refer to the kcache. */
1031 for (i = 0; i < 3; ++i) {
1032 static const unsigned int base[] = {128, 160, 256, 288};
1033 unsigned int line, sel = alu->src[i].sel, found = 0;
1034
1035 if (sel < 512)
1036 continue;
1037
1038 sel -= 512;
1039 line = sel>>4;
1040
1041 for (j = 0; j < 4 && !found; ++j) {
1042 switch (kcache[j].mode) {
1043 case V_SQ_CF_KCACHE_NOP:
1044 case V_SQ_CF_KCACHE_LOCK_LOOP_INDEX:
1045 R600_ERR("unexpected kcache line mode\n");
1046 return -ENOMEM;
1047 default:
1048 if (kcache[j].bank == alu->src[i].kc_bank &&
1049 kcache[j].addr <= line &&
1050 line < kcache[j].addr + kcache[j].mode) {
1051 alu->src[i].sel = sel - (kcache[j].addr<<4);
1052 alu->src[i].sel += base[j];
1053 found=1;
1054 }
1055 }
1056 }
1057 }
1058 return 0;
1059 }
1060
1061 static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode *bc,
1062 struct r600_bytecode_alu *alu,
1063 unsigned type)
1064 {
1065 struct r600_bytecode_kcache kcache_sets[4];
1066 struct r600_bytecode_kcache *kcache = kcache_sets;
1067 int r;
1068
1069 memcpy(kcache, bc->cf_last->kcache, 4 * sizeof(struct r600_bytecode_kcache));
1070
1071 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1072 /* can't alloc, need to start new clause */
1073 if ((r = r600_bytecode_add_cf(bc))) {
1074 return r;
1075 }
1076 bc->cf_last->op = type;
1077
1078 /* retry with the new clause */
1079 kcache = bc->cf_last->kcache;
1080 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1081 /* can't alloc again- should never happen */
1082 return r;
1083 }
1084 } else {
1085 /* update kcache sets */
1086 memcpy(bc->cf_last->kcache, kcache, 4 * sizeof(struct r600_bytecode_kcache));
1087 }
1088
1089 /* if we actually used more than 2 kcache sets, or have relative indexing - use ALU_EXTENDED on eg+ */
1090 if (kcache[2].mode != V_SQ_CF_KCACHE_NOP ||
1091 kcache[0].index_mode || kcache[1].index_mode || kcache[2].index_mode || kcache[3].index_mode) {
1092 if (bc->chip_class < EVERGREEN)
1093 return -ENOMEM;
1094 bc->cf_last->eg_alu_extended = 1;
1095 }
1096
1097 return 0;
1098 }
1099
1100 static int insert_nop_r6xx(struct r600_bytecode *bc)
1101 {
1102 struct r600_bytecode_alu alu;
1103 int r, i;
1104
1105 for (i = 0; i < 4; i++) {
1106 memset(&alu, 0, sizeof(alu));
1107 alu.op = ALU_OP0_NOP;
1108 alu.src[0].chan = i;
1109 alu.dst.chan = i;
1110 alu.last = (i == 3);
1111 r = r600_bytecode_add_alu(bc, &alu);
1112 if (r)
1113 return r;
1114 }
1115 return 0;
1116 }
1117
1118 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1119 static int load_ar_r6xx(struct r600_bytecode *bc)
1120 {
1121 struct r600_bytecode_alu alu;
1122 int r;
1123
1124 if (bc->ar_loaded)
1125 return 0;
1126
1127 /* hack to avoid making MOVA the last instruction in the clause */
1128 if ((bc->cf_last->ndw>>1) >= 110)
1129 bc->force_add_cf = 1;
1130
1131 memset(&alu, 0, sizeof(alu));
1132 alu.op = ALU_OP1_MOVA_GPR_INT;
1133 alu.src[0].sel = bc->ar_reg;
1134 alu.src[0].chan = bc->ar_chan;
1135 alu.last = 1;
1136 alu.index_mode = INDEX_MODE_LOOP;
1137 r = r600_bytecode_add_alu(bc, &alu);
1138 if (r)
1139 return r;
1140
1141 /* no requirement to set uses waterfall on MOVA_GPR_INT */
1142 bc->ar_loaded = 1;
1143 return 0;
1144 }
1145
1146 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1147 static int load_ar(struct r600_bytecode *bc)
1148 {
1149 struct r600_bytecode_alu alu;
1150 int r;
1151
1152 if (bc->ar_handling)
1153 return load_ar_r6xx(bc);
1154
1155 if (bc->ar_loaded)
1156 return 0;
1157
1158 /* hack to avoid making MOVA the last instruction in the clause */
1159 if ((bc->cf_last->ndw>>1) >= 110)
1160 bc->force_add_cf = 1;
1161
1162 memset(&alu, 0, sizeof(alu));
1163 alu.op = ALU_OP1_MOVA_INT;
1164 alu.src[0].sel = bc->ar_reg;
1165 alu.src[0].chan = bc->ar_chan;
1166 alu.last = 1;
1167 r = r600_bytecode_add_alu(bc, &alu);
1168 if (r)
1169 return r;
1170
1171 bc->cf_last->r6xx_uses_waterfall = 1;
1172 bc->ar_loaded = 1;
1173 return 0;
1174 }
1175
1176 int r600_bytecode_add_alu_type(struct r600_bytecode *bc,
1177 const struct r600_bytecode_alu *alu, unsigned type)
1178 {
1179 struct r600_bytecode_alu *nalu = r600_bytecode_alu();
1180 struct r600_bytecode_alu *lalu;
1181 int i, r;
1182
1183 if (!nalu)
1184 return -ENOMEM;
1185 memcpy(nalu, alu, sizeof(struct r600_bytecode_alu));
1186
1187 if (alu->is_op3) {
1188 /* will fail later since alu does not support it. */
1189 assert(!alu->src[0].abs && !alu->src[1].abs && !alu->src[2].abs);
1190 }
1191
1192 if (bc->cf_last != NULL && bc->cf_last->op != type) {
1193 /* check if we could add it anyway */
1194 if (bc->cf_last->op == CF_OP_ALU &&
1195 type == CF_OP_ALU_PUSH_BEFORE) {
1196 LIST_FOR_EACH_ENTRY(lalu, &bc->cf_last->alu, list) {
1197 if (lalu->execute_mask) {
1198 bc->force_add_cf = 1;
1199 break;
1200 }
1201 }
1202 } else
1203 bc->force_add_cf = 1;
1204 }
1205
1206 /* cf can contains only alu or only vtx or only tex */
1207 if (bc->cf_last == NULL || bc->force_add_cf) {
1208 r = r600_bytecode_add_cf(bc);
1209 if (r) {
1210 free(nalu);
1211 return r;
1212 }
1213 }
1214 bc->cf_last->op = type;
1215
1216 /* Load index register if required */
1217 if (bc->chip_class >= EVERGREEN) {
1218 for (i = 0; i < 3; i++)
1219 if (nalu->src[i].kc_bank && nalu->src[i].kc_rel)
1220 egcm_load_index_reg(bc, 0, true);
1221 }
1222
1223 /* Check AR usage and load it if required */
1224 for (i = 0; i < 3; i++)
1225 if (nalu->src[i].rel && !bc->ar_loaded)
1226 load_ar(bc);
1227
1228 if (nalu->dst.rel && !bc->ar_loaded)
1229 load_ar(bc);
1230
1231 /* Setup the kcache for this ALU instruction. This will start a new
1232 * ALU clause if needed. */
1233 if ((r = r600_bytecode_alloc_kcache_lines(bc, nalu, type))) {
1234 free(nalu);
1235 return r;
1236 }
1237
1238 if (!bc->cf_last->curr_bs_head) {
1239 bc->cf_last->curr_bs_head = nalu;
1240 }
1241 /* number of gpr == the last gpr used in any alu */
1242 for (i = 0; i < 3; i++) {
1243 if (nalu->src[i].sel >= bc->ngpr && nalu->src[i].sel < 128) {
1244 bc->ngpr = nalu->src[i].sel + 1;
1245 }
1246 if (nalu->src[i].sel == V_SQ_ALU_SRC_LITERAL)
1247 r600_bytecode_special_constants(nalu->src[i].value,
1248 &nalu->src[i].sel, &nalu->src[i].neg, nalu->src[i].abs);
1249 }
1250 if (nalu->dst.sel >= bc->ngpr) {
1251 bc->ngpr = nalu->dst.sel + 1;
1252 }
1253 LIST_ADDTAIL(&nalu->list, &bc->cf_last->alu);
1254 /* each alu use 2 dwords */
1255 bc->cf_last->ndw += 2;
1256 bc->ndw += 2;
1257
1258 /* process cur ALU instructions for bank swizzle */
1259 if (nalu->last) {
1260 uint32_t literal[4];
1261 unsigned nliteral;
1262 struct r600_bytecode_alu *slots[5];
1263 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
1264 r = assign_alu_units(bc, bc->cf_last->curr_bs_head, slots);
1265 if (r)
1266 return r;
1267
1268 if (bc->cf_last->prev_bs_head) {
1269 r = merge_inst_groups(bc, slots, bc->cf_last->prev_bs_head);
1270 if (r)
1271 return r;
1272 }
1273
1274 if (bc->cf_last->prev_bs_head) {
1275 r = replace_gpr_with_pv_ps(bc, slots, bc->cf_last->prev_bs_head);
1276 if (r)
1277 return r;
1278 }
1279
1280 r = check_and_set_bank_swizzle(bc, slots);
1281 if (r)
1282 return r;
1283
1284 for (i = 0, nliteral = 0; i < max_slots; i++) {
1285 if (slots[i]) {
1286 r = r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral);
1287 if (r)
1288 return r;
1289 }
1290 }
1291 bc->cf_last->ndw += align(nliteral, 2);
1292
1293 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1294 * worst case */
1295 if ((bc->cf_last->ndw >> 1) >= 120) {
1296 bc->force_add_cf = 1;
1297 }
1298
1299 bc->cf_last->prev2_bs_head = bc->cf_last->prev_bs_head;
1300 bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head;
1301 bc->cf_last->curr_bs_head = NULL;
1302 }
1303
1304 if (nalu->dst.rel && bc->r6xx_nop_after_rel_dst)
1305 insert_nop_r6xx(bc);
1306
1307 return 0;
1308 }
1309
1310 int r600_bytecode_add_alu(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu)
1311 {
1312 return r600_bytecode_add_alu_type(bc, alu, CF_OP_ALU);
1313 }
1314
1315 static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode *bc)
1316 {
1317 switch (bc->chip_class) {
1318 case R600:
1319 return 8;
1320
1321 case R700:
1322 case EVERGREEN:
1323 case CAYMAN:
1324 return 16;
1325
1326 default:
1327 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1328 return 8;
1329 }
1330 }
1331
1332 static inline boolean last_inst_was_not_vtx_fetch(struct r600_bytecode *bc)
1333 {
1334 return !((r600_isa_cf(bc->cf_last->op)->flags & CF_FETCH) &&
1335 (bc->chip_class == CAYMAN ||
1336 bc->cf_last->op != CF_OP_TEX));
1337 }
1338
1339 static int r600_bytecode_add_vtx_internal(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx,
1340 bool use_tc)
1341 {
1342 struct r600_bytecode_vtx *nvtx = r600_bytecode_vtx();
1343 int r;
1344
1345 if (!nvtx)
1346 return -ENOMEM;
1347 memcpy(nvtx, vtx, sizeof(struct r600_bytecode_vtx));
1348
1349 /* Load index register if required */
1350 if (bc->chip_class >= EVERGREEN) {
1351 if (vtx->buffer_index_mode)
1352 egcm_load_index_reg(bc, vtx->buffer_index_mode - 1, false);
1353 }
1354
1355 /* cf can contains only alu or only vtx or only tex */
1356 if (bc->cf_last == NULL ||
1357 last_inst_was_not_vtx_fetch(bc) ||
1358 bc->force_add_cf) {
1359 r = r600_bytecode_add_cf(bc);
1360 if (r) {
1361 free(nvtx);
1362 return r;
1363 }
1364 switch (bc->chip_class) {
1365 case R600:
1366 case R700:
1367 bc->cf_last->op = CF_OP_VTX;
1368 break;
1369 case EVERGREEN:
1370 if (use_tc)
1371 bc->cf_last->op = CF_OP_TEX;
1372 else
1373 bc->cf_last->op = CF_OP_VTX;
1374 break;
1375 case CAYMAN:
1376 bc->cf_last->op = CF_OP_TEX;
1377 break;
1378 default:
1379 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1380 free(nvtx);
1381 return -EINVAL;
1382 }
1383 }
1384 LIST_ADDTAIL(&nvtx->list, &bc->cf_last->vtx);
1385 /* each fetch use 4 dwords */
1386 bc->cf_last->ndw += 4;
1387 bc->ndw += 4;
1388 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1389 bc->force_add_cf = 1;
1390
1391 bc->ngpr = MAX2(bc->ngpr, vtx->src_gpr + 1);
1392 bc->ngpr = MAX2(bc->ngpr, vtx->dst_gpr + 1);
1393
1394 return 0;
1395 }
1396
1397 int r600_bytecode_add_vtx(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx)
1398 {
1399 return r600_bytecode_add_vtx_internal(bc, vtx, false);
1400 }
1401
1402 int r600_bytecode_add_vtx_tc(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx)
1403 {
1404 return r600_bytecode_add_vtx_internal(bc, vtx, true);
1405 }
1406
1407 int r600_bytecode_add_tex(struct r600_bytecode *bc, const struct r600_bytecode_tex *tex)
1408 {
1409 struct r600_bytecode_tex *ntex = r600_bytecode_tex();
1410 int r;
1411
1412 if (!ntex)
1413 return -ENOMEM;
1414 memcpy(ntex, tex, sizeof(struct r600_bytecode_tex));
1415
1416 /* Load index register if required */
1417 if (bc->chip_class >= EVERGREEN) {
1418 if (tex->sampler_index_mode || tex->resource_index_mode)
1419 egcm_load_index_reg(bc, 1, false);
1420 }
1421
1422 /* we can't fetch data und use it as texture lookup address in the same TEX clause */
1423 if (bc->cf_last != NULL &&
1424 bc->cf_last->op == CF_OP_TEX) {
1425 struct r600_bytecode_tex *ttex;
1426 LIST_FOR_EACH_ENTRY(ttex, &bc->cf_last->tex, list) {
1427 if (ttex->dst_gpr == ntex->src_gpr) {
1428 bc->force_add_cf = 1;
1429 break;
1430 }
1431 }
1432 /* slight hack to make gradients always go into same cf */
1433 if (ntex->op == FETCH_OP_SET_GRADIENTS_H)
1434 bc->force_add_cf = 1;
1435 }
1436
1437 /* cf can contains only alu or only vtx or only tex */
1438 if (bc->cf_last == NULL ||
1439 bc->cf_last->op != CF_OP_TEX ||
1440 bc->force_add_cf) {
1441 r = r600_bytecode_add_cf(bc);
1442 if (r) {
1443 free(ntex);
1444 return r;
1445 }
1446 bc->cf_last->op = CF_OP_TEX;
1447 }
1448 if (ntex->src_gpr >= bc->ngpr) {
1449 bc->ngpr = ntex->src_gpr + 1;
1450 }
1451 if (ntex->dst_gpr >= bc->ngpr) {
1452 bc->ngpr = ntex->dst_gpr + 1;
1453 }
1454 LIST_ADDTAIL(&ntex->list, &bc->cf_last->tex);
1455 /* each texture fetch use 4 dwords */
1456 bc->cf_last->ndw += 4;
1457 bc->ndw += 4;
1458 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1459 bc->force_add_cf = 1;
1460 return 0;
1461 }
1462
1463 int r600_bytecode_add_gds(struct r600_bytecode *bc, const struct r600_bytecode_gds *gds)
1464 {
1465 struct r600_bytecode_gds *ngds = r600_bytecode_gds();
1466 int r;
1467
1468 if (ngds == NULL)
1469 return -ENOMEM;
1470 memcpy(ngds, gds, sizeof(struct r600_bytecode_gds));
1471
1472 if (bc->cf_last == NULL ||
1473 bc->cf_last->op != CF_OP_GDS ||
1474 bc->force_add_cf) {
1475 r = r600_bytecode_add_cf(bc);
1476 if (r) {
1477 free(ngds);
1478 return r;
1479 }
1480 bc->cf_last->op = CF_OP_GDS;
1481 }
1482
1483 LIST_ADDTAIL(&ngds->list, &bc->cf_last->gds);
1484 bc->cf_last->ndw += 4; /* each GDS uses 4 dwords */
1485 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1486 bc->force_add_cf = 1;
1487 return 0;
1488 }
1489
1490 int r600_bytecode_add_cfinst(struct r600_bytecode *bc, unsigned op)
1491 {
1492 int r;
1493 r = r600_bytecode_add_cf(bc);
1494 if (r)
1495 return r;
1496
1497 bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
1498 bc->cf_last->op = op;
1499 return 0;
1500 }
1501
1502 int cm_bytecode_add_cf_end(struct r600_bytecode *bc)
1503 {
1504 return r600_bytecode_add_cfinst(bc, CF_OP_CF_END);
1505 }
1506
1507 /* common to all 3 families */
1508 static int r600_bytecode_vtx_build(struct r600_bytecode *bc, struct r600_bytecode_vtx *vtx, unsigned id)
1509 {
1510 bc->bytecode[id] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) |
1511 S_SQ_VTX_WORD0_FETCH_TYPE(vtx->fetch_type) |
1512 S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
1513 S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x);
1514 if (bc->chip_class < CAYMAN)
1515 bc->bytecode[id] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
1516 id++;
1517 bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
1518 S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
1519 S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
1520 S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
1521 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) |
1522 S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) |
1523 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) |
1524 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) |
1525 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
1526 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
1527 bc->bytecode[id] = S_SQ_VTX_WORD2_OFFSET(vtx->offset)|
1528 S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx->endian);
1529 if (bc->chip_class >= EVERGREEN)
1530 bc->bytecode[id] |= ((vtx->buffer_index_mode & 0x3) << 21); // S_SQ_VTX_WORD2_BIM(vtx->buffer_index_mode);
1531 if (bc->chip_class < CAYMAN)
1532 bc->bytecode[id] |= S_SQ_VTX_WORD2_MEGA_FETCH(1);
1533 id++;
1534 bc->bytecode[id++] = 0;
1535 return 0;
1536 }
1537
1538 /* common to all 3 families */
1539 static int r600_bytecode_tex_build(struct r600_bytecode *bc, struct r600_bytecode_tex *tex, unsigned id)
1540 {
1541 bc->bytecode[id] = S_SQ_TEX_WORD0_TEX_INST(
1542 r600_isa_fetch_opcode(bc->isa->hw_class, tex->op)) |
1543 EG_S_SQ_TEX_WORD0_INST_MOD(tex->inst_mod) |
1544 S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
1545 S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
1546 S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
1547 if (bc->chip_class >= EVERGREEN)
1548 bc->bytecode[id] |= ((tex->sampler_index_mode & 0x3) << 27) | // S_SQ_TEX_WORD0_SIM(tex->sampler_index_mode);
1549 ((tex->resource_index_mode & 0x3) << 25); // S_SQ_TEX_WORD0_RIM(tex->resource_index_mode)
1550 id++;
1551 bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
1552 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
1553 S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
1554 S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
1555 S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
1556 S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
1557 S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
1558 S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
1559 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
1560 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
1561 S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
1562 bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
1563 S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
1564 S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
1565 S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
1566 S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
1567 S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
1568 S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
1569 S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
1570 bc->bytecode[id++] = 0;
1571 return 0;
1572 }
1573
1574 /* r600 only, r700/eg bits in r700_asm.c */
1575 static int r600_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id)
1576 {
1577 unsigned opcode = r600_isa_alu_opcode(bc->isa->hw_class, alu->op);
1578
1579 /* don't replace gpr by pv or ps for destination register */
1580 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
1581 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
1582 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
1583 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
1584 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
1585 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
1586 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
1587 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
1588 S_SQ_ALU_WORD0_INDEX_MODE(alu->index_mode) |
1589 S_SQ_ALU_WORD0_PRED_SEL(alu->pred_sel) |
1590 S_SQ_ALU_WORD0_LAST(alu->last);
1591
1592 if (alu->is_op3) {
1593 assert(!alu->src[0].abs && !alu->src[1].abs && !alu->src[2].abs);
1594 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1595 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1596 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1597 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1598 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
1599 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
1600 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
1601 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
1602 S_SQ_ALU_WORD1_OP3_ALU_INST(opcode) |
1603 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
1604 } else {
1605 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1606 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1607 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1608 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1609 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
1610 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
1611 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
1612 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
1613 S_SQ_ALU_WORD1_OP2_ALU_INST(opcode) |
1614 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
1615 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->execute_mask) |
1616 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->update_pred);
1617 }
1618 return 0;
1619 }
1620
1621 static void r600_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_cf *cf)
1622 {
1623 *bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
1624 *bytecode++ = S_SQ_CF_WORD1_CF_INST(r600_isa_cf_opcode(ISA_CC_R600, cf->op)) |
1625 S_SQ_CF_WORD1_BARRIER(1) |
1626 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
1627 }
1628
1629 /* common for r600/r700 - eg in eg_asm.c */
1630 static int r600_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf)
1631 {
1632 unsigned id = cf->id;
1633 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
1634 unsigned opcode = r600_isa_cf_opcode(bc->isa->hw_class, cf->op);
1635
1636
1637 if (cf->op == CF_NATIVE) {
1638 bc->bytecode[id++] = cf->isa[0];
1639 bc->bytecode[id++] = cf->isa[1];
1640 } else if (cfop->flags & CF_ALU) {
1641 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
1642 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
1643 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
1644 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank);
1645
1646 bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(opcode) |
1647 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) |
1648 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
1649 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
1650 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1651 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chip_class == R600 ? cf->r6xx_uses_waterfall : 0) |
1652 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
1653 } else if (cfop->flags & CF_FETCH) {
1654 if (bc->chip_class == R700)
1655 r700_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1656 else
1657 r600_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1658 } else if (cfop->flags & CF_EXP) {
1659 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1660 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1661 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1662 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type) |
1663 S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(cf->output.index_gpr);
1664 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1665 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
1666 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
1667 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
1668 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
1669 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->barrier) |
1670 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) |
1671 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->end_of_program);
1672 } else if (cfop->flags & CF_MEM) {
1673 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1674 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1675 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1676 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type) |
1677 S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(cf->output.index_gpr);
1678 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1679 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->barrier) |
1680 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) |
1681 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->end_of_program) |
1682 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf->output.array_size) |
1683 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf->output.comp_mask);
1684 } else {
1685 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
1686 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(opcode) |
1687 S_SQ_CF_WORD1_BARRIER(1) |
1688 S_SQ_CF_WORD1_COND(cf->cond) |
1689 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count) |
1690 S_SQ_CF_WORD1_END_OF_PROGRAM(cf->end_of_program);
1691 }
1692 return 0;
1693 }
1694
1695 int r600_bytecode_build(struct r600_bytecode *bc)
1696 {
1697 struct r600_bytecode_cf *cf;
1698 struct r600_bytecode_alu *alu;
1699 struct r600_bytecode_vtx *vtx;
1700 struct r600_bytecode_tex *tex;
1701 struct r600_bytecode_gds *gds;
1702 uint32_t literal[4];
1703 unsigned nliteral;
1704 unsigned addr;
1705 int i, r;
1706
1707 if (!bc->nstack) { // If not 0, Stack_size already provided by llvm
1708 if (bc->stack.max_entries)
1709 bc->nstack = bc->stack.max_entries;
1710 else if (bc->type == PIPE_SHADER_VERTEX ||
1711 bc->type == PIPE_SHADER_TESS_EVAL ||
1712 bc->type == PIPE_SHADER_TESS_CTRL)
1713 bc->nstack = 1;
1714 }
1715
1716 /* first path compute addr of each CF block */
1717 /* addr start after all the CF instructions */
1718 addr = bc->cf_last->id + 2;
1719 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1720 if (r600_isa_cf(cf->op)->flags & CF_FETCH) {
1721 addr += 3;
1722 addr &= 0xFFFFFFFCUL;
1723 }
1724 cf->addr = addr;
1725 addr += cf->ndw;
1726 bc->ndw = cf->addr + cf->ndw;
1727 }
1728 free(bc->bytecode);
1729 bc->bytecode = calloc(4, bc->ndw);
1730 if (bc->bytecode == NULL)
1731 return -ENOMEM;
1732 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1733 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
1734 addr = cf->addr;
1735 if (bc->chip_class >= EVERGREEN)
1736 r = eg_bytecode_cf_build(bc, cf);
1737 else
1738 r = r600_bytecode_cf_build(bc, cf);
1739 if (r)
1740 return r;
1741 if (cfop->flags & CF_ALU) {
1742 nliteral = 0;
1743 memset(literal, 0, sizeof(literal));
1744 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1745 r = r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
1746 if (r)
1747 return r;
1748 r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral);
1749 r600_bytecode_assign_kcache_banks(bc, alu, cf->kcache);
1750
1751 switch(bc->chip_class) {
1752 case R600:
1753 r = r600_bytecode_alu_build(bc, alu, addr);
1754 break;
1755 case R700:
1756 r = r700_bytecode_alu_build(bc, alu, addr);
1757 break;
1758 case EVERGREEN:
1759 case CAYMAN:
1760 r = eg_bytecode_alu_build(bc, alu, addr);
1761 break;
1762 default:
1763 R600_ERR("unknown chip class %d.\n", bc->chip_class);
1764 return -EINVAL;
1765 }
1766 if (r)
1767 return r;
1768 addr += 2;
1769 if (alu->last) {
1770 for (i = 0; i < align(nliteral, 2); ++i) {
1771 bc->bytecode[addr++] = literal[i];
1772 }
1773 nliteral = 0;
1774 memset(literal, 0, sizeof(literal));
1775 }
1776 }
1777 } else if (cf->op == CF_OP_VTX) {
1778 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1779 r = r600_bytecode_vtx_build(bc, vtx, addr);
1780 if (r)
1781 return r;
1782 addr += 4;
1783 }
1784 } else if (cf->op == CF_OP_GDS) {
1785 assert(bc->chip_class >= EVERGREEN);
1786 LIST_FOR_EACH_ENTRY(gds, &cf->gds, list) {
1787 r = eg_bytecode_gds_build(bc, gds, addr);
1788 if (r)
1789 return r;
1790 addr += 4;
1791 }
1792 } else if (cf->op == CF_OP_TEX) {
1793 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1794 assert(bc->chip_class >= EVERGREEN);
1795 r = r600_bytecode_vtx_build(bc, vtx, addr);
1796 if (r)
1797 return r;
1798 addr += 4;
1799 }
1800 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
1801 r = r600_bytecode_tex_build(bc, tex, addr);
1802 if (r)
1803 return r;
1804 addr += 4;
1805 }
1806 }
1807 }
1808 return 0;
1809 }
1810
1811 void r600_bytecode_clear(struct r600_bytecode *bc)
1812 {
1813 struct r600_bytecode_cf *cf = NULL, *next_cf;
1814
1815 free(bc->bytecode);
1816 bc->bytecode = NULL;
1817
1818 LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
1819 struct r600_bytecode_alu *alu = NULL, *next_alu;
1820 struct r600_bytecode_tex *tex = NULL, *next_tex;
1821 struct r600_bytecode_tex *vtx = NULL, *next_vtx;
1822 struct r600_bytecode_gds *gds = NULL, *next_gds;
1823
1824 LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
1825 free(alu);
1826 }
1827
1828 LIST_INITHEAD(&cf->alu);
1829
1830 LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) {
1831 free(tex);
1832 }
1833
1834 LIST_INITHEAD(&cf->tex);
1835
1836 LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) {
1837 free(vtx);
1838 }
1839
1840 LIST_INITHEAD(&cf->vtx);
1841
1842 LIST_FOR_EACH_ENTRY_SAFE(gds, next_gds, &cf->gds, list) {
1843 free(gds);
1844 }
1845
1846 LIST_INITHEAD(&cf->gds);
1847
1848 free(cf);
1849 }
1850
1851 LIST_INITHEAD(&cf->list);
1852 }
1853
1854 static int print_swizzle(unsigned swz)
1855 {
1856 const char * swzchars = "xyzw01?_";
1857 assert(swz<8 && swz != 6);
1858 return fprintf(stderr, "%c", swzchars[swz]);
1859 }
1860
1861 static int print_sel(unsigned sel, unsigned rel, unsigned index_mode,
1862 unsigned need_brackets)
1863 {
1864 int o = 0;
1865 if (rel && index_mode >= 5 && sel < 128)
1866 o += fprintf(stderr, "G");
1867 if (rel || need_brackets) {
1868 o += fprintf(stderr, "[");
1869 }
1870 o += fprintf(stderr, "%d", sel);
1871 if (rel) {
1872 if (index_mode == 0 || index_mode == 6)
1873 o += fprintf(stderr, "+AR");
1874 else if (index_mode == 4)
1875 o += fprintf(stderr, "+AL");
1876 }
1877 if (rel || need_brackets) {
1878 o += fprintf(stderr, "]");
1879 }
1880 return o;
1881 }
1882
1883 static int print_dst(struct r600_bytecode_alu *alu)
1884 {
1885 int o = 0;
1886 unsigned sel = alu->dst.sel;
1887 char reg_char = 'R';
1888 if (sel > 128 - 4) { /* clause temporary gpr */
1889 sel -= 128 - 4;
1890 reg_char = 'T';
1891 }
1892
1893 if (alu_writes(alu)) {
1894 o += fprintf(stderr, "%c", reg_char);
1895 o += print_sel(alu->dst.sel, alu->dst.rel, alu->index_mode, 0);
1896 } else {
1897 o += fprintf(stderr, "__");
1898 }
1899 o += fprintf(stderr, ".");
1900 o += print_swizzle(alu->dst.chan);
1901 return o;
1902 }
1903
1904 static int print_src(struct r600_bytecode_alu *alu, unsigned idx)
1905 {
1906 int o = 0;
1907 struct r600_bytecode_alu_src *src = &alu->src[idx];
1908 unsigned sel = src->sel, need_sel = 1, need_chan = 1, need_brackets = 0;
1909
1910 if (src->neg)
1911 o += fprintf(stderr,"-");
1912 if (src->abs)
1913 o += fprintf(stderr,"|");
1914
1915 if (sel < 128 - 4) {
1916 o += fprintf(stderr, "R");
1917 } else if (sel < 128) {
1918 o += fprintf(stderr, "T");
1919 sel -= 128 - 4;
1920 } else if (sel < 160) {
1921 o += fprintf(stderr, "KC0");
1922 need_brackets = 1;
1923 sel -= 128;
1924 } else if (sel < 192) {
1925 o += fprintf(stderr, "KC1");
1926 need_brackets = 1;
1927 sel -= 160;
1928 } else if (sel >= 512) {
1929 o += fprintf(stderr, "C%d", src->kc_bank);
1930 need_brackets = 1;
1931 sel -= 512;
1932 } else if (sel >= 448) {
1933 o += fprintf(stderr, "Param");
1934 sel -= 448;
1935 need_chan = 0;
1936 } else if (sel >= 288) {
1937 o += fprintf(stderr, "KC3");
1938 need_brackets = 1;
1939 sel -= 288;
1940 } else if (sel >= 256) {
1941 o += fprintf(stderr, "KC2");
1942 need_brackets = 1;
1943 sel -= 256;
1944 } else {
1945 need_sel = 0;
1946 need_chan = 0;
1947 switch (sel) {
1948 case EG_V_SQ_ALU_SRC_LDS_DIRECT_A:
1949 o += fprintf(stderr, "LDS_A[0x%08X]", src->value);
1950 break;
1951 case EG_V_SQ_ALU_SRC_LDS_DIRECT_B:
1952 o += fprintf(stderr, "LDS_B[0x%08X]", src->value);
1953 break;
1954 case EG_V_SQ_ALU_SRC_LDS_OQ_A:
1955 o += fprintf(stderr, "LDS_OQ_A");
1956 need_chan = 1;
1957 break;
1958 case EG_V_SQ_ALU_SRC_LDS_OQ_B:
1959 o += fprintf(stderr, "LDS_OQ_B");
1960 need_chan = 1;
1961 break;
1962 case EG_V_SQ_ALU_SRC_LDS_OQ_A_POP:
1963 o += fprintf(stderr, "LDS_OQ_A_POP");
1964 need_chan = 1;
1965 break;
1966 case EG_V_SQ_ALU_SRC_LDS_OQ_B_POP:
1967 o += fprintf(stderr, "LDS_OQ_B_POP");
1968 need_chan = 1;
1969 break;
1970 case V_SQ_ALU_SRC_PS:
1971 o += fprintf(stderr, "PS");
1972 break;
1973 case V_SQ_ALU_SRC_PV:
1974 o += fprintf(stderr, "PV");
1975 need_chan = 1;
1976 break;
1977 case V_SQ_ALU_SRC_LITERAL:
1978 o += fprintf(stderr, "[0x%08X %f]", src->value, u_bitcast_u2f(src->value));
1979 break;
1980 case V_SQ_ALU_SRC_0_5:
1981 o += fprintf(stderr, "0.5");
1982 break;
1983 case V_SQ_ALU_SRC_M_1_INT:
1984 o += fprintf(stderr, "-1");
1985 break;
1986 case V_SQ_ALU_SRC_1_INT:
1987 o += fprintf(stderr, "1");
1988 break;
1989 case V_SQ_ALU_SRC_1:
1990 o += fprintf(stderr, "1.0");
1991 break;
1992 case V_SQ_ALU_SRC_0:
1993 o += fprintf(stderr, "0");
1994 break;
1995 default:
1996 o += fprintf(stderr, "??IMM_%d", sel);
1997 break;
1998 }
1999 }
2000
2001 if (need_sel)
2002 o += print_sel(sel, src->rel, alu->index_mode, need_brackets);
2003
2004 if (need_chan) {
2005 o += fprintf(stderr, ".");
2006 o += print_swizzle(src->chan);
2007 }
2008
2009 if (src->abs)
2010 o += fprintf(stderr,"|");
2011
2012 return o;
2013 }
2014
2015 static int print_indent(int p, int c)
2016 {
2017 int o = 0;
2018 while (p++ < c)
2019 o += fprintf(stderr, " ");
2020 return o;
2021 }
2022
2023 void r600_bytecode_disasm(struct r600_bytecode *bc)
2024 {
2025 const char *index_mode[] = {"CF_INDEX_NONE", "CF_INDEX_0", "CF_INDEX_1"};
2026 static int index = 0;
2027 struct r600_bytecode_cf *cf = NULL;
2028 struct r600_bytecode_alu *alu = NULL;
2029 struct r600_bytecode_vtx *vtx = NULL;
2030 struct r600_bytecode_tex *tex = NULL;
2031 struct r600_bytecode_gds *gds = NULL;
2032
2033 unsigned i, id, ngr = 0, last;
2034 uint32_t literal[4];
2035 unsigned nliteral;
2036 char chip = '6';
2037
2038 switch (bc->chip_class) {
2039 case R700:
2040 chip = '7';
2041 break;
2042 case EVERGREEN:
2043 chip = 'E';
2044 break;
2045 case CAYMAN:
2046 chip = 'C';
2047 break;
2048 case R600:
2049 default:
2050 chip = '6';
2051 break;
2052 }
2053 fprintf(stderr, "bytecode %d dw -- %d gprs -- %d nstack -------------\n",
2054 bc->ndw, bc->ngpr, bc->nstack);
2055 fprintf(stderr, "shader %d -- %c\n", index++, chip);
2056
2057 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
2058 id = cf->id;
2059 if (cf->op == CF_NATIVE) {
2060 fprintf(stderr, "%04d %08X %08X CF_NATIVE\n", id, bc->bytecode[id],
2061 bc->bytecode[id + 1]);
2062 } else {
2063 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
2064 if (cfop->flags & CF_ALU) {
2065 if (cf->eg_alu_extended) {
2066 fprintf(stderr, "%04d %08X %08X %s\n", id, bc->bytecode[id],
2067 bc->bytecode[id + 1], "ALU_EXT");
2068 id += 2;
2069 }
2070 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
2071 bc->bytecode[id + 1], cfop->name);
2072 fprintf(stderr, "%d @%d ", cf->ndw / 2, cf->addr);
2073 for (i = 0; i < 4; ++i) {
2074 if (cf->kcache[i].mode) {
2075 int c_start = (cf->kcache[i].addr << 4);
2076 int c_end = c_start + (cf->kcache[i].mode << 4);
2077 fprintf(stderr, "KC%d[CB%d:%d-%d%s%s] ",
2078 i, cf->kcache[i].bank, c_start, c_end,
2079 cf->kcache[i].index_mode ? " " : "",
2080 cf->kcache[i].index_mode ? index_mode[cf->kcache[i].index_mode] : "");
2081 }
2082 }
2083 fprintf(stderr, "\n");
2084 } else if (cfop->flags & CF_FETCH) {
2085 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
2086 bc->bytecode[id + 1], cfop->name);
2087 fprintf(stderr, "%d @%d ", cf->ndw / 4, cf->addr);
2088 fprintf(stderr, "\n");
2089 } else if (cfop->flags & CF_EXP) {
2090 int o = 0;
2091 const char *exp_type[] = {"PIXEL", "POS ", "PARAM"};
2092 o += fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
2093 bc->bytecode[id + 1], cfop->name);
2094 o += print_indent(o, 43);
2095 o += fprintf(stderr, "%s ", exp_type[cf->output.type]);
2096 if (cf->output.burst_count > 1) {
2097 o += fprintf(stderr, "%d-%d ", cf->output.array_base,
2098 cf->output.array_base + cf->output.burst_count - 1);
2099
2100 o += print_indent(o, 55);
2101 o += fprintf(stderr, "R%d-%d.", cf->output.gpr,
2102 cf->output.gpr + cf->output.burst_count - 1);
2103 } else {
2104 o += fprintf(stderr, "%d ", cf->output.array_base);
2105 o += print_indent(o, 55);
2106 o += fprintf(stderr, "R%d.", cf->output.gpr);
2107 }
2108
2109 o += print_swizzle(cf->output.swizzle_x);
2110 o += print_swizzle(cf->output.swizzle_y);
2111 o += print_swizzle(cf->output.swizzle_z);
2112 o += print_swizzle(cf->output.swizzle_w);
2113
2114 print_indent(o, 67);
2115
2116 fprintf(stderr, " ES:%X ", cf->output.elem_size);
2117 if (!cf->barrier)
2118 fprintf(stderr, "NO_BARRIER ");
2119 if (cf->end_of_program)
2120 fprintf(stderr, "EOP ");
2121 fprintf(stderr, "\n");
2122 } else if (r600_isa_cf(cf->op)->flags & CF_MEM) {
2123 int o = 0;
2124 const char *exp_type[] = {"WRITE", "WRITE_IND", "WRITE_ACK",
2125 "WRITE_IND_ACK"};
2126 o += fprintf(stderr, "%04d %08X %08X %s ", id,
2127 bc->bytecode[id], bc->bytecode[id + 1], cfop->name);
2128 o += print_indent(o, 43);
2129 o += fprintf(stderr, "%s ", exp_type[cf->output.type]);
2130 if (cf->output.burst_count > 1) {
2131 o += fprintf(stderr, "%d-%d ", cf->output.array_base,
2132 cf->output.array_base + cf->output.burst_count - 1);
2133 o += print_indent(o, 55);
2134 o += fprintf(stderr, "R%d-%d.", cf->output.gpr,
2135 cf->output.gpr + cf->output.burst_count - 1);
2136 } else {
2137 o += fprintf(stderr, "%d ", cf->output.array_base);
2138 o += print_indent(o, 55);
2139 o += fprintf(stderr, "R%d.", cf->output.gpr);
2140 }
2141 for (i = 0; i < 4; ++i) {
2142 if (cf->output.comp_mask & (1 << i))
2143 o += print_swizzle(i);
2144 else
2145 o += print_swizzle(7);
2146 }
2147
2148 if (cf->output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND)
2149 o += fprintf(stderr, " R%d", cf->output.index_gpr);
2150
2151 o += print_indent(o, 67);
2152
2153 fprintf(stderr, " ES:%i ", cf->output.elem_size);
2154 if (cf->output.array_size != 0xFFF)
2155 fprintf(stderr, "AS:%i ", cf->output.array_size);
2156 if (!cf->barrier)
2157 fprintf(stderr, "NO_BARRIER ");
2158 if (cf->end_of_program)
2159 fprintf(stderr, "EOP ");
2160 fprintf(stderr, "\n");
2161 } else {
2162 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
2163 bc->bytecode[id + 1], cfop->name);
2164 fprintf(stderr, "@%d ", cf->cf_addr);
2165 if (cf->cond)
2166 fprintf(stderr, "CND:%X ", cf->cond);
2167 if (cf->pop_count)
2168 fprintf(stderr, "POP:%X ", cf->pop_count);
2169 if (cf->count && (cfop->flags & CF_EMIT))
2170 fprintf(stderr, "STREAM%d ", cf->count);
2171 if (cf->end_of_program)
2172 fprintf(stderr, "EOP ");
2173 fprintf(stderr, "\n");
2174 }
2175 }
2176
2177 id = cf->addr;
2178 nliteral = 0;
2179 last = 1;
2180 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
2181 const char *omod_str[] = {"","*2","*4","/2"};
2182 const struct alu_op_info *aop = r600_isa_alu(alu->op);
2183 int o = 0;
2184
2185 r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
2186 o += fprintf(stderr, " %04d %08X %08X ", id, bc->bytecode[id], bc->bytecode[id+1]);
2187 if (last)
2188 o += fprintf(stderr, "%4d ", ++ngr);
2189 else
2190 o += fprintf(stderr, " ");
2191 o += fprintf(stderr, "%c%c %c ", alu->execute_mask ? 'M':' ',
2192 alu->update_pred ? 'P':' ',
2193 alu->pred_sel ? alu->pred_sel==2 ? '0':'1':' ');
2194
2195 o += fprintf(stderr, "%s%s%s ", aop->name,
2196 omod_str[alu->omod], alu->dst.clamp ? "_sat":"");
2197
2198 o += print_indent(o,60);
2199 o += print_dst(alu);
2200 for (i = 0; i < aop->src_count; ++i) {
2201 o += fprintf(stderr, i == 0 ? ", ": ", ");
2202 o += print_src(alu, i);
2203 }
2204
2205 if (alu->bank_swizzle) {
2206 o += print_indent(o,75);
2207 o += fprintf(stderr, " BS:%d", alu->bank_swizzle);
2208 }
2209
2210 fprintf(stderr, "\n");
2211 id += 2;
2212
2213 if (alu->last) {
2214 for (i = 0; i < nliteral; i++, id++) {
2215 float *f = (float*)(bc->bytecode + id);
2216 o = fprintf(stderr, " %04d %08X", id, bc->bytecode[id]);
2217 print_indent(o, 60);
2218 fprintf(stderr, " %f (%d)\n", *f, *(bc->bytecode + id));
2219 }
2220 id += nliteral & 1;
2221 nliteral = 0;
2222 }
2223 last = alu->last;
2224 }
2225
2226 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2227 int o = 0;
2228 o += fprintf(stderr, " %04d %08X %08X %08X ", id, bc->bytecode[id],
2229 bc->bytecode[id + 1], bc->bytecode[id + 2]);
2230
2231 o += fprintf(stderr, "%s ", r600_isa_fetch(tex->op)->name);
2232
2233 o += print_indent(o, 50);
2234
2235 o += fprintf(stderr, "R%d.", tex->dst_gpr);
2236 o += print_swizzle(tex->dst_sel_x);
2237 o += print_swizzle(tex->dst_sel_y);
2238 o += print_swizzle(tex->dst_sel_z);
2239 o += print_swizzle(tex->dst_sel_w);
2240
2241 o += fprintf(stderr, ", R%d.", tex->src_gpr);
2242 o += print_swizzle(tex->src_sel_x);
2243 o += print_swizzle(tex->src_sel_y);
2244 o += print_swizzle(tex->src_sel_z);
2245 o += print_swizzle(tex->src_sel_w);
2246
2247 o += fprintf(stderr, ", RID:%d", tex->resource_id);
2248 o += fprintf(stderr, ", SID:%d ", tex->sampler_id);
2249
2250 if (tex->sampler_index_mode)
2251 fprintf(stderr, "SQ_%s ", index_mode[tex->sampler_index_mode]);
2252
2253 if (tex->lod_bias)
2254 fprintf(stderr, "LB:%d ", tex->lod_bias);
2255
2256 fprintf(stderr, "CT:%c%c%c%c ",
2257 tex->coord_type_x ? 'N' : 'U',
2258 tex->coord_type_y ? 'N' : 'U',
2259 tex->coord_type_z ? 'N' : 'U',
2260 tex->coord_type_w ? 'N' : 'U');
2261
2262 if (tex->offset_x)
2263 fprintf(stderr, "OX:%d ", tex->offset_x);
2264 if (tex->offset_y)
2265 fprintf(stderr, "OY:%d ", tex->offset_y);
2266 if (tex->offset_z)
2267 fprintf(stderr, "OZ:%d ", tex->offset_z);
2268
2269 id += 4;
2270 fprintf(stderr, "\n");
2271 }
2272
2273 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2274 int o = 0;
2275 const char * fetch_type[] = {"VERTEX", "INSTANCE", ""};
2276 o += fprintf(stderr, " %04d %08X %08X %08X ", id, bc->bytecode[id],
2277 bc->bytecode[id + 1], bc->bytecode[id + 2]);
2278
2279 o += fprintf(stderr, "%s ", r600_isa_fetch(vtx->op)->name);
2280
2281 o += print_indent(o, 50);
2282
2283 o += fprintf(stderr, "R%d.", vtx->dst_gpr);
2284 o += print_swizzle(vtx->dst_sel_x);
2285 o += print_swizzle(vtx->dst_sel_y);
2286 o += print_swizzle(vtx->dst_sel_z);
2287 o += print_swizzle(vtx->dst_sel_w);
2288
2289 o += fprintf(stderr, ", R%d.", vtx->src_gpr);
2290 o += print_swizzle(vtx->src_sel_x);
2291
2292 if (vtx->offset)
2293 fprintf(stderr, " +%db", vtx->offset);
2294
2295 o += print_indent(o, 55);
2296
2297 fprintf(stderr, ", RID:%d ", vtx->buffer_id);
2298
2299 fprintf(stderr, "%s ", fetch_type[vtx->fetch_type]);
2300
2301 if (bc->chip_class < CAYMAN && vtx->mega_fetch_count)
2302 fprintf(stderr, "MFC:%d ", vtx->mega_fetch_count);
2303
2304 if (bc->chip_class >= EVERGREEN && vtx->buffer_index_mode)
2305 fprintf(stderr, "SQ_%s ", index_mode[vtx->buffer_index_mode]);
2306
2307 fprintf(stderr, "UCF:%d ", vtx->use_const_fields);
2308 fprintf(stderr, "FMT(DTA:%d ", vtx->data_format);
2309 fprintf(stderr, "NUM:%d ", vtx->num_format_all);
2310 fprintf(stderr, "COMP:%d ", vtx->format_comp_all);
2311 fprintf(stderr, "MODE:%d)\n", vtx->srf_mode_all);
2312
2313 id += 4;
2314 }
2315
2316 LIST_FOR_EACH_ENTRY(gds, &cf->gds, list) {
2317 int o = 0;
2318 o += fprintf(stderr, " %04d %08X %08X %08X ", id, bc->bytecode[id],
2319 bc->bytecode[id + 1], bc->bytecode[id + 2]);
2320
2321 o += fprintf(stderr, "%s ", r600_isa_fetch(gds->op)->name);
2322
2323 if (gds->op != FETCH_OP_TF_WRITE) {
2324 o += fprintf(stderr, "R%d.", gds->dst_gpr);
2325 o += print_swizzle(gds->dst_sel_x);
2326 o += print_swizzle(gds->dst_sel_y);
2327 o += print_swizzle(gds->dst_sel_z);
2328 o += print_swizzle(gds->dst_sel_w);
2329 }
2330
2331 o += fprintf(stderr, ", R%d.", gds->src_gpr);
2332 o += print_swizzle(gds->src_sel_x);
2333 o += print_swizzle(gds->src_sel_y);
2334 o += print_swizzle(gds->src_sel_z);
2335
2336 if (gds->op != FETCH_OP_TF_WRITE) {
2337 o += fprintf(stderr, ", R%d.", gds->src_gpr2);
2338 }
2339 fprintf(stderr, "\n");
2340 id += 4;
2341 }
2342 }
2343
2344 fprintf(stderr, "--------------------------------------\n");
2345 }
2346
2347 void r600_vertex_data_type(enum pipe_format pformat,
2348 unsigned *format,
2349 unsigned *num_format, unsigned *format_comp, unsigned *endian)
2350 {
2351 const struct util_format_description *desc;
2352 unsigned i;
2353
2354 *format = 0;
2355 *num_format = 0;
2356 *format_comp = 0;
2357 *endian = ENDIAN_NONE;
2358
2359 if (pformat == PIPE_FORMAT_R11G11B10_FLOAT) {
2360 *format = FMT_10_11_11_FLOAT;
2361 *endian = r600_endian_swap(32);
2362 return;
2363 }
2364
2365 if (pformat == PIPE_FORMAT_B5G6R5_UNORM) {
2366 *format = FMT_5_6_5;
2367 *endian = r600_endian_swap(16);
2368 return;
2369 }
2370
2371 desc = util_format_description(pformat);
2372 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
2373 goto out_unknown;
2374 }
2375
2376 /* Find the first non-VOID channel. */
2377 for (i = 0; i < 4; i++) {
2378 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2379 break;
2380 }
2381 }
2382
2383 *endian = r600_endian_swap(desc->channel[i].size);
2384
2385 switch (desc->channel[i].type) {
2386 /* Half-floats, floats, ints */
2387 case UTIL_FORMAT_TYPE_FLOAT:
2388 switch (desc->channel[i].size) {
2389 case 16:
2390 switch (desc->nr_channels) {
2391 case 1:
2392 *format = FMT_16_FLOAT;
2393 break;
2394 case 2:
2395 *format = FMT_16_16_FLOAT;
2396 break;
2397 case 3:
2398 case 4:
2399 *format = FMT_16_16_16_16_FLOAT;
2400 break;
2401 }
2402 break;
2403 case 32:
2404 switch (desc->nr_channels) {
2405 case 1:
2406 *format = FMT_32_FLOAT;
2407 break;
2408 case 2:
2409 *format = FMT_32_32_FLOAT;
2410 break;
2411 case 3:
2412 *format = FMT_32_32_32_FLOAT;
2413 break;
2414 case 4:
2415 *format = FMT_32_32_32_32_FLOAT;
2416 break;
2417 }
2418 break;
2419 default:
2420 goto out_unknown;
2421 }
2422 break;
2423 /* Unsigned ints */
2424 case UTIL_FORMAT_TYPE_UNSIGNED:
2425 /* Signed ints */
2426 case UTIL_FORMAT_TYPE_SIGNED:
2427 switch (desc->channel[i].size) {
2428 case 8:
2429 switch (desc->nr_channels) {
2430 case 1:
2431 *format = FMT_8;
2432 break;
2433 case 2:
2434 *format = FMT_8_8;
2435 break;
2436 case 3:
2437 case 4:
2438 *format = FMT_8_8_8_8;
2439 break;
2440 }
2441 break;
2442 case 10:
2443 if (desc->nr_channels != 4)
2444 goto out_unknown;
2445
2446 *format = FMT_2_10_10_10;
2447 break;
2448 case 16:
2449 switch (desc->nr_channels) {
2450 case 1:
2451 *format = FMT_16;
2452 break;
2453 case 2:
2454 *format = FMT_16_16;
2455 break;
2456 case 3:
2457 case 4:
2458 *format = FMT_16_16_16_16;
2459 break;
2460 }
2461 break;
2462 case 32:
2463 switch (desc->nr_channels) {
2464 case 1:
2465 *format = FMT_32;
2466 break;
2467 case 2:
2468 *format = FMT_32_32;
2469 break;
2470 case 3:
2471 *format = FMT_32_32_32;
2472 break;
2473 case 4:
2474 *format = FMT_32_32_32_32;
2475 break;
2476 }
2477 break;
2478 default:
2479 goto out_unknown;
2480 }
2481 break;
2482 default:
2483 goto out_unknown;
2484 }
2485
2486 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2487 *format_comp = 1;
2488 }
2489
2490 *num_format = 0;
2491 if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED ||
2492 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2493 if (!desc->channel[i].normalized) {
2494 if (desc->channel[i].pure_integer)
2495 *num_format = 1;
2496 else
2497 *num_format = 2;
2498 }
2499 }
2500 return;
2501 out_unknown:
2502 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
2503 }
2504
2505 void *r600_create_vertex_fetch_shader(struct pipe_context *ctx,
2506 unsigned count,
2507 const struct pipe_vertex_element *elements)
2508 {
2509 struct r600_context *rctx = (struct r600_context *)ctx;
2510 struct r600_bytecode bc;
2511 struct r600_bytecode_vtx vtx;
2512 const struct util_format_description *desc;
2513 unsigned fetch_resource_start = rctx->b.chip_class >= EVERGREEN ? 0 : 160;
2514 unsigned format, num_format, format_comp, endian;
2515 uint32_t *bytecode;
2516 int i, j, r, fs_size;
2517 struct r600_fetch_shader *shader;
2518 unsigned no_sb = rctx->screen->b.debug_flags & DBG_NO_SB;
2519 unsigned sb_disasm = !no_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
2520
2521 assert(count < 32);
2522
2523 memset(&bc, 0, sizeof(bc));
2524 r600_bytecode_init(&bc, rctx->b.chip_class, rctx->b.family,
2525 rctx->screen->has_compressed_msaa_texturing);
2526
2527 bc.isa = rctx->isa;
2528
2529 for (i = 0; i < count; i++) {
2530 if (elements[i].instance_divisor > 1) {
2531 if (rctx->b.chip_class == CAYMAN) {
2532 for (j = 0; j < 4; j++) {
2533 struct r600_bytecode_alu alu;
2534 memset(&alu, 0, sizeof(alu));
2535 alu.op = ALU_OP2_MULHI_UINT;
2536 alu.src[0].sel = 0;
2537 alu.src[0].chan = 3;
2538 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2539 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2540 alu.dst.sel = i + 1;
2541 alu.dst.chan = j;
2542 alu.dst.write = j == 3;
2543 alu.last = j == 3;
2544 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2545 r600_bytecode_clear(&bc);
2546 return NULL;
2547 }
2548 }
2549 } else {
2550 struct r600_bytecode_alu alu;
2551 memset(&alu, 0, sizeof(alu));
2552 alu.op = ALU_OP2_MULHI_UINT;
2553 alu.src[0].sel = 0;
2554 alu.src[0].chan = 3;
2555 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2556 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2557 alu.dst.sel = i + 1;
2558 alu.dst.chan = 3;
2559 alu.dst.write = 1;
2560 alu.last = 1;
2561 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2562 r600_bytecode_clear(&bc);
2563 return NULL;
2564 }
2565 }
2566 }
2567 }
2568
2569 for (i = 0; i < count; i++) {
2570 r600_vertex_data_type(elements[i].src_format,
2571 &format, &num_format, &format_comp, &endian);
2572
2573 desc = util_format_description(elements[i].src_format);
2574 if (!desc) {
2575 r600_bytecode_clear(&bc);
2576 R600_ERR("unknown format %d\n", elements[i].src_format);
2577 return NULL;
2578 }
2579
2580 if (elements[i].src_offset > 65535) {
2581 r600_bytecode_clear(&bc);
2582 R600_ERR("too big src_offset: %u\n", elements[i].src_offset);
2583 return NULL;
2584 }
2585
2586 memset(&vtx, 0, sizeof(vtx));
2587 vtx.buffer_id = elements[i].vertex_buffer_index + fetch_resource_start;
2588 vtx.fetch_type = elements[i].instance_divisor ? SQ_VTX_FETCH_INSTANCE_DATA : SQ_VTX_FETCH_VERTEX_DATA;
2589 vtx.src_gpr = elements[i].instance_divisor > 1 ? i + 1 : 0;
2590 vtx.src_sel_x = elements[i].instance_divisor ? 3 : 0;
2591 vtx.mega_fetch_count = 0x1F;
2592 vtx.dst_gpr = i + 1;
2593 vtx.dst_sel_x = desc->swizzle[0];
2594 vtx.dst_sel_y = desc->swizzle[1];
2595 vtx.dst_sel_z = desc->swizzle[2];
2596 vtx.dst_sel_w = desc->swizzle[3];
2597 vtx.data_format = format;
2598 vtx.num_format_all = num_format;
2599 vtx.format_comp_all = format_comp;
2600 vtx.offset = elements[i].src_offset;
2601 vtx.endian = endian;
2602
2603 if ((r = r600_bytecode_add_vtx(&bc, &vtx))) {
2604 r600_bytecode_clear(&bc);
2605 return NULL;
2606 }
2607 }
2608
2609 r600_bytecode_add_cfinst(&bc, CF_OP_RET);
2610
2611 if ((r = r600_bytecode_build(&bc))) {
2612 r600_bytecode_clear(&bc);
2613 return NULL;
2614 }
2615
2616 if (rctx->screen->b.debug_flags & DBG_FS) {
2617 fprintf(stderr, "--------------------------------------------------------------\n");
2618 fprintf(stderr, "Vertex elements state:\n");
2619 for (i = 0; i < count; i++) {
2620 fprintf(stderr, " ");
2621 util_dump_vertex_element(stderr, elements+i);
2622 fprintf(stderr, "\n");
2623 }
2624
2625 if (!sb_disasm) {
2626 r600_bytecode_disasm(&bc);
2627
2628 fprintf(stderr, "______________________________________________________________\n");
2629 } else {
2630 r600_sb_bytecode_process(rctx, &bc, NULL, 1 /*dump*/, 0 /*optimize*/);
2631 }
2632 }
2633
2634 fs_size = bc.ndw*4;
2635
2636 /* Allocate the CSO. */
2637 shader = CALLOC_STRUCT(r600_fetch_shader);
2638 if (!shader) {
2639 r600_bytecode_clear(&bc);
2640 return NULL;
2641 }
2642
2643 u_suballocator_alloc(rctx->allocator_fetch_shader, fs_size, 256,
2644 &shader->offset,
2645 (struct pipe_resource**)&shader->buffer);
2646 if (!shader->buffer) {
2647 r600_bytecode_clear(&bc);
2648 FREE(shader);
2649 return NULL;
2650 }
2651
2652 bytecode = r600_buffer_map_sync_with_rings(&rctx->b, shader->buffer, PIPE_TRANSFER_WRITE | PIPE_TRANSFER_UNSYNCHRONIZED);
2653 bytecode += shader->offset / 4;
2654
2655 if (R600_BIG_ENDIAN) {
2656 for (i = 0; i < fs_size / 4; ++i) {
2657 bytecode[i] = util_cpu_to_le32(bc.bytecode[i]);
2658 }
2659 } else {
2660 memcpy(bytecode, bc.bytecode, fs_size);
2661 }
2662 rctx->b.ws->buffer_unmap(shader->buffer->buf);
2663
2664 r600_bytecode_clear(&bc);
2665 return shader;
2666 }
2667
2668 void r600_bytecode_alu_read(struct r600_bytecode *bc,
2669 struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1)
2670 {
2671 /* WORD0 */
2672 alu->src[0].sel = G_SQ_ALU_WORD0_SRC0_SEL(word0);
2673 alu->src[0].rel = G_SQ_ALU_WORD0_SRC0_REL(word0);
2674 alu->src[0].chan = G_SQ_ALU_WORD0_SRC0_CHAN(word0);
2675 alu->src[0].neg = G_SQ_ALU_WORD0_SRC0_NEG(word0);
2676 alu->src[1].sel = G_SQ_ALU_WORD0_SRC1_SEL(word0);
2677 alu->src[1].rel = G_SQ_ALU_WORD0_SRC1_REL(word0);
2678 alu->src[1].chan = G_SQ_ALU_WORD0_SRC1_CHAN(word0);
2679 alu->src[1].neg = G_SQ_ALU_WORD0_SRC1_NEG(word0);
2680 alu->index_mode = G_SQ_ALU_WORD0_INDEX_MODE(word0);
2681 alu->pred_sel = G_SQ_ALU_WORD0_PRED_SEL(word0);
2682 alu->last = G_SQ_ALU_WORD0_LAST(word0);
2683
2684 /* WORD1 */
2685 alu->bank_swizzle = G_SQ_ALU_WORD1_BANK_SWIZZLE(word1);
2686 if (alu->bank_swizzle)
2687 alu->bank_swizzle_force = alu->bank_swizzle;
2688 alu->dst.sel = G_SQ_ALU_WORD1_DST_GPR(word1);
2689 alu->dst.rel = G_SQ_ALU_WORD1_DST_REL(word1);
2690 alu->dst.chan = G_SQ_ALU_WORD1_DST_CHAN(word1);
2691 alu->dst.clamp = G_SQ_ALU_WORD1_CLAMP(word1);
2692 if (G_SQ_ALU_WORD1_ENCODING(word1)) /*ALU_DWORD1_OP3*/
2693 {
2694 alu->is_op3 = 1;
2695 alu->src[2].sel = G_SQ_ALU_WORD1_OP3_SRC2_SEL(word1);
2696 alu->src[2].rel = G_SQ_ALU_WORD1_OP3_SRC2_REL(word1);
2697 alu->src[2].chan = G_SQ_ALU_WORD1_OP3_SRC2_CHAN(word1);
2698 alu->src[2].neg = G_SQ_ALU_WORD1_OP3_SRC2_NEG(word1);
2699 alu->op = r600_isa_alu_by_opcode(bc->isa,
2700 G_SQ_ALU_WORD1_OP3_ALU_INST(word1), /* is_op3 = */ 1);
2701
2702 }
2703 else /*ALU_DWORD1_OP2*/
2704 {
2705 alu->src[0].abs = G_SQ_ALU_WORD1_OP2_SRC0_ABS(word1);
2706 alu->src[1].abs = G_SQ_ALU_WORD1_OP2_SRC1_ABS(word1);
2707 alu->op = r600_isa_alu_by_opcode(bc->isa,
2708 G_SQ_ALU_WORD1_OP2_ALU_INST(word1), /* is_op3 = */ 0);
2709 alu->omod = G_SQ_ALU_WORD1_OP2_OMOD(word1);
2710 alu->dst.write = G_SQ_ALU_WORD1_OP2_WRITE_MASK(word1);
2711 alu->update_pred = G_SQ_ALU_WORD1_OP2_UPDATE_PRED(word1);
2712 alu->execute_mask =
2713 G_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(word1);
2714 }
2715 }
2716
2717 #if 0
2718 void r600_bytecode_export_read(struct r600_bytecode *bc,
2719 struct r600_bytecode_output *output, uint32_t word0, uint32_t word1)
2720 {
2721 output->array_base = G_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(word0);
2722 output->type = G_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(word0);
2723 output->gpr = G_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(word0);
2724 output->elem_size = G_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(word0);
2725
2726 output->swizzle_x = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(word1);
2727 output->swizzle_y = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(word1);
2728 output->swizzle_z = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(word1);
2729 output->swizzle_w = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(word1);
2730 output->burst_count = G_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(word1);
2731 output->end_of_program = G_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(word1);
2732 output->op = r600_isa_cf_by_opcode(bc->isa,
2733 G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(word1), 0);
2734 output->barrier = G_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(word1);
2735 output->array_size = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(word1);
2736 output->comp_mask = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(word1);
2737 }
2738 #endif