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r600g/llvm: Add support for cf_alu native encode
[mesa.git] / src / gallium / drivers / r600 / r600_asm.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_opcodes.h"
25 #include "r600_formats.h"
26 #include "r600_shader.h"
27 #include "r600d.h"
28
29 #include <errno.h>
30 #include <byteswap.h>
31 #include "util/u_dump.h"
32 #include "util/u_memory.h"
33 #include "pipe/p_shader_tokens.h"
34
35 #define NUM_OF_CYCLES 3
36 #define NUM_OF_COMPONENTS 4
37
38 static inline unsigned int r600_bytecode_get_num_operands(
39 struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
40 {
41 return r600_isa_alu(alu->op)->src_count;
42 }
43
44 int r700_bytecode_alu_build(struct r600_bytecode *bc,
45 struct r600_bytecode_alu *alu, unsigned id);
46
47 static struct r600_bytecode_cf *r600_bytecode_cf(void)
48 {
49 struct r600_bytecode_cf *cf = CALLOC_STRUCT(r600_bytecode_cf);
50
51 if (cf == NULL)
52 return NULL;
53 LIST_INITHEAD(&cf->list);
54 LIST_INITHEAD(&cf->alu);
55 LIST_INITHEAD(&cf->vtx);
56 LIST_INITHEAD(&cf->tex);
57 return cf;
58 }
59
60 static struct r600_bytecode_alu *r600_bytecode_alu(void)
61 {
62 struct r600_bytecode_alu *alu = CALLOC_STRUCT(r600_bytecode_alu);
63
64 if (alu == NULL)
65 return NULL;
66 LIST_INITHEAD(&alu->list);
67 return alu;
68 }
69
70 static struct r600_bytecode_vtx *r600_bytecode_vtx(void)
71 {
72 struct r600_bytecode_vtx *vtx = CALLOC_STRUCT(r600_bytecode_vtx);
73
74 if (vtx == NULL)
75 return NULL;
76 LIST_INITHEAD(&vtx->list);
77 return vtx;
78 }
79
80 static struct r600_bytecode_tex *r600_bytecode_tex(void)
81 {
82 struct r600_bytecode_tex *tex = CALLOC_STRUCT(r600_bytecode_tex);
83
84 if (tex == NULL)
85 return NULL;
86 LIST_INITHEAD(&tex->list);
87 return tex;
88 }
89
90 void r600_bytecode_init(struct r600_bytecode *bc,
91 enum chip_class chip_class,
92 enum radeon_family family,
93 enum r600_msaa_texture_mode msaa_texture_mode)
94 {
95 if ((chip_class == R600) &&
96 (family != CHIP_RV670 && family != CHIP_RS780 && family != CHIP_RS880)) {
97 bc->ar_handling = AR_HANDLE_RV6XX;
98 bc->r6xx_nop_after_rel_dst = 1;
99 } else {
100 bc->ar_handling = AR_HANDLE_NORMAL;
101 bc->r6xx_nop_after_rel_dst = 0;
102 }
103
104 LIST_INITHEAD(&bc->cf);
105 bc->chip_class = chip_class;
106 bc->msaa_texture_mode = msaa_texture_mode;
107 }
108
109 int r600_bytecode_add_cf(struct r600_bytecode *bc)
110 {
111 struct r600_bytecode_cf *cf = r600_bytecode_cf();
112
113 if (cf == NULL)
114 return -ENOMEM;
115 LIST_ADDTAIL(&cf->list, &bc->cf);
116 if (bc->cf_last) {
117 cf->id = bc->cf_last->id + 2;
118 if (bc->cf_last->eg_alu_extended) {
119 /* take into account extended alu size */
120 cf->id += 2;
121 bc->ndw += 2;
122 }
123 }
124 bc->cf_last = cf;
125 bc->ncf++;
126 bc->ndw += 2;
127 bc->force_add_cf = 0;
128 bc->ar_loaded = 0;
129 return 0;
130 }
131
132 int r600_bytecode_add_output(struct r600_bytecode *bc,
133 const struct r600_bytecode_output *output)
134 {
135 int r;
136
137 if (output->gpr >= bc->ngpr)
138 bc->ngpr = output->gpr + 1;
139
140 if (bc->cf_last && (bc->cf_last->op == output->op ||
141 (bc->cf_last->op == CF_OP_EXPORT &&
142 output->op == CF_OP_EXPORT_DONE)) &&
143 output->type == bc->cf_last->output.type &&
144 output->elem_size == bc->cf_last->output.elem_size &&
145 output->swizzle_x == bc->cf_last->output.swizzle_x &&
146 output->swizzle_y == bc->cf_last->output.swizzle_y &&
147 output->swizzle_z == bc->cf_last->output.swizzle_z &&
148 output->swizzle_w == bc->cf_last->output.swizzle_w &&
149 output->comp_mask == bc->cf_last->output.comp_mask &&
150 (output->burst_count + bc->cf_last->output.burst_count) <= 16) {
151
152 if ((output->gpr + output->burst_count) == bc->cf_last->output.gpr &&
153 (output->array_base + output->burst_count) == bc->cf_last->output.array_base) {
154
155 bc->cf_last->output.end_of_program |= output->end_of_program;
156 bc->cf_last->op = bc->cf_last->output.op = output->op;
157 bc->cf_last->output.gpr = output->gpr;
158 bc->cf_last->output.array_base = output->array_base;
159 bc->cf_last->output.burst_count += output->burst_count;
160 return 0;
161
162 } else if (output->gpr == (bc->cf_last->output.gpr + bc->cf_last->output.burst_count) &&
163 output->array_base == (bc->cf_last->output.array_base + bc->cf_last->output.burst_count)) {
164
165 bc->cf_last->output.end_of_program |= output->end_of_program;
166 bc->cf_last->op = bc->cf_last->output.op = output->op;
167 bc->cf_last->output.burst_count += output->burst_count;
168 return 0;
169 }
170 }
171
172 r = r600_bytecode_add_cf(bc);
173 if (r)
174 return r;
175 bc->cf_last->op = output->op;
176 memcpy(&bc->cf_last->output, output, sizeof(struct r600_bytecode_output));
177 return 0;
178 }
179
180 /* alu instructions that can ony exits once per group */
181 static int is_alu_once_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
182 {
183 return r600_isa_alu(alu->op)->flags & (AF_KILL | AF_PRED);
184 }
185
186 static int is_alu_reduction_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
187 {
188 return (r600_isa_alu(alu->op)->flags & AF_REPL) &&
189 (r600_isa_alu_slots(bc->isa->hw_class, alu->op) == AF_4V);
190 }
191
192 static int is_alu_mova_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
193 {
194 return r600_isa_alu(alu->op)->flags & AF_MOVA;
195 }
196
197 static int alu_uses_rel(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
198 {
199 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
200 unsigned src;
201
202 if (alu->dst.rel) {
203 return 1;
204 }
205
206 for (src = 0; src < num_src; ++src) {
207 if (alu->src[src].rel) {
208 return 1;
209 }
210 }
211 return 0;
212 }
213
214 static int is_alu_vec_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
215 {
216 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
217 return !(slots & AF_S);
218 }
219
220 static int is_alu_trans_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
221 {
222 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
223 return !(slots & AF_V);
224 }
225
226 /* alu instructions that can execute on any unit */
227 static int is_alu_any_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
228 {
229 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
230 return slots == AF_VS;
231 }
232
233 static int is_nop_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
234 {
235 return alu->op == ALU_OP0_NOP;
236 }
237
238 static int assign_alu_units(struct r600_bytecode *bc, struct r600_bytecode_alu *alu_first,
239 struct r600_bytecode_alu *assignment[5])
240 {
241 struct r600_bytecode_alu *alu;
242 unsigned i, chan, trans;
243 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
244
245 for (i = 0; i < max_slots; i++)
246 assignment[i] = NULL;
247
248 for (alu = alu_first; alu; alu = LIST_ENTRY(struct r600_bytecode_alu, alu->list.next, list)) {
249 chan = alu->dst.chan;
250 if (max_slots == 4)
251 trans = 0;
252 else if (is_alu_trans_unit_inst(bc, alu))
253 trans = 1;
254 else if (is_alu_vec_unit_inst(bc, alu))
255 trans = 0;
256 else if (assignment[chan])
257 trans = 1; /* Assume ALU_INST_PREFER_VECTOR. */
258 else
259 trans = 0;
260
261 if (trans) {
262 if (assignment[4]) {
263 assert(0); /* ALU.Trans has already been allocated. */
264 return -1;
265 }
266 assignment[4] = alu;
267 } else {
268 if (assignment[chan]) {
269 assert(0); /* ALU.chan has already been allocated. */
270 return -1;
271 }
272 assignment[chan] = alu;
273 }
274
275 if (alu->last)
276 break;
277 }
278 return 0;
279 }
280
281 struct alu_bank_swizzle {
282 int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
283 int hw_cfile_addr[4];
284 int hw_cfile_elem[4];
285 };
286
287 static const unsigned cycle_for_bank_swizzle_vec[][3] = {
288 [SQ_ALU_VEC_012] = { 0, 1, 2 },
289 [SQ_ALU_VEC_021] = { 0, 2, 1 },
290 [SQ_ALU_VEC_120] = { 1, 2, 0 },
291 [SQ_ALU_VEC_102] = { 1, 0, 2 },
292 [SQ_ALU_VEC_201] = { 2, 0, 1 },
293 [SQ_ALU_VEC_210] = { 2, 1, 0 }
294 };
295
296 static const unsigned cycle_for_bank_swizzle_scl[][3] = {
297 [SQ_ALU_SCL_210] = { 2, 1, 0 },
298 [SQ_ALU_SCL_122] = { 1, 2, 2 },
299 [SQ_ALU_SCL_212] = { 2, 1, 2 },
300 [SQ_ALU_SCL_221] = { 2, 2, 1 }
301 };
302
303 static void init_bank_swizzle(struct alu_bank_swizzle *bs)
304 {
305 int i, cycle, component;
306 /* set up gpr use */
307 for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
308 for (component = 0; component < NUM_OF_COMPONENTS; component++)
309 bs->hw_gpr[cycle][component] = -1;
310 for (i = 0; i < 4; i++)
311 bs->hw_cfile_addr[i] = -1;
312 for (i = 0; i < 4; i++)
313 bs->hw_cfile_elem[i] = -1;
314 }
315
316 static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan, unsigned cycle)
317 {
318 if (bs->hw_gpr[cycle][chan] == -1)
319 bs->hw_gpr[cycle][chan] = sel;
320 else if (bs->hw_gpr[cycle][chan] != (int)sel) {
321 /* Another scalar operation has already used the GPR read port for the channel. */
322 return -1;
323 }
324 return 0;
325 }
326
327 static int reserve_cfile(struct r600_bytecode *bc, struct alu_bank_swizzle *bs, unsigned sel, unsigned chan)
328 {
329 int res, num_res = 4;
330 if (bc->chip_class >= R700) {
331 num_res = 2;
332 chan /= 2;
333 }
334 for (res = 0; res < num_res; ++res) {
335 if (bs->hw_cfile_addr[res] == -1) {
336 bs->hw_cfile_addr[res] = sel;
337 bs->hw_cfile_elem[res] = chan;
338 return 0;
339 } else if (bs->hw_cfile_addr[res] == sel &&
340 bs->hw_cfile_elem[res] == chan)
341 return 0; /* Read for this scalar element already reserved, nothing to do here. */
342 }
343 /* All cfile read ports are used, cannot reference vector element. */
344 return -1;
345 }
346
347 static int is_gpr(unsigned sel)
348 {
349 return (sel >= 0 && sel <= 127);
350 }
351
352 /* CB constants start at 512, and get translated to a kcache index when ALU
353 * clauses are constructed. Note that we handle kcache constants the same way
354 * as (the now gone) cfile constants, is that really required? */
355 static int is_cfile(unsigned sel)
356 {
357 return (sel > 255 && sel < 512) ||
358 (sel > 511 && sel < 4607) || /* Kcache before translation. */
359 (sel > 127 && sel < 192); /* Kcache after translation. */
360 }
361
362 static int is_const(int sel)
363 {
364 return is_cfile(sel) ||
365 (sel >= V_SQ_ALU_SRC_0 &&
366 sel <= V_SQ_ALU_SRC_LITERAL);
367 }
368
369 static int check_vector(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
370 struct alu_bank_swizzle *bs, int bank_swizzle)
371 {
372 int r, src, num_src, sel, elem, cycle;
373
374 num_src = r600_bytecode_get_num_operands(bc, alu);
375 for (src = 0; src < num_src; src++) {
376 sel = alu->src[src].sel;
377 elem = alu->src[src].chan;
378 if (is_gpr(sel)) {
379 cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src];
380 if (src == 1 && sel == alu->src[0].sel && elem == alu->src[0].chan)
381 /* Nothing to do; special-case optimization,
382 * second source uses first source’s reservation. */
383 continue;
384 else {
385 r = reserve_gpr(bs, sel, elem, cycle);
386 if (r)
387 return r;
388 }
389 } else if (is_cfile(sel)) {
390 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
391 if (r)
392 return r;
393 }
394 /* No restrictions on PV, PS, literal or special constants. */
395 }
396 return 0;
397 }
398
399 static int check_scalar(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
400 struct alu_bank_swizzle *bs, int bank_swizzle)
401 {
402 int r, src, num_src, const_count, sel, elem, cycle;
403
404 num_src = r600_bytecode_get_num_operands(bc, alu);
405 for (const_count = 0, src = 0; src < num_src; ++src) {
406 sel = alu->src[src].sel;
407 elem = alu->src[src].chan;
408 if (is_const(sel)) { /* Any constant, including literal and inline constants. */
409 if (const_count >= 2)
410 /* More than two references to a constant in
411 * transcendental operation. */
412 return -1;
413 else
414 const_count++;
415 }
416 if (is_cfile(sel)) {
417 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
418 if (r)
419 return r;
420 }
421 }
422 for (src = 0; src < num_src; ++src) {
423 sel = alu->src[src].sel;
424 elem = alu->src[src].chan;
425 if (is_gpr(sel)) {
426 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
427 if (cycle < const_count)
428 /* Cycle for GPR load conflicts with
429 * constant load in transcendental operation. */
430 return -1;
431 r = reserve_gpr(bs, sel, elem, cycle);
432 if (r)
433 return r;
434 }
435 /* PV PS restrictions */
436 if (const_count && (sel == 254 || sel == 255)) {
437 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
438 if (cycle < const_count)
439 return -1;
440 }
441 }
442 return 0;
443 }
444
445 static int check_and_set_bank_swizzle(struct r600_bytecode *bc,
446 struct r600_bytecode_alu *slots[5])
447 {
448 struct alu_bank_swizzle bs;
449 int bank_swizzle[5];
450 int i, r = 0, forced = 1;
451 boolean scalar_only = bc->chip_class == CAYMAN ? false : true;
452 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
453
454 for (i = 0; i < max_slots; i++) {
455 if (slots[i]) {
456 if (slots[i]->bank_swizzle_force) {
457 slots[i]->bank_swizzle = slots[i]->bank_swizzle_force;
458 } else {
459 forced = 0;
460 }
461 }
462
463 if (i < 4 && slots[i])
464 scalar_only = false;
465 }
466 if (forced)
467 return 0;
468
469 /* Just check every possible combination of bank swizzle.
470 * Not very efficent, but works on the first try in most of the cases. */
471 for (i = 0; i < 4; i++)
472 if (!slots[i] || !slots[i]->bank_swizzle_force)
473 bank_swizzle[i] = SQ_ALU_VEC_012;
474 else
475 bank_swizzle[i] = slots[i]->bank_swizzle;
476
477 bank_swizzle[4] = SQ_ALU_SCL_210;
478 while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
479
480 init_bank_swizzle(&bs);
481 if (scalar_only == false) {
482 for (i = 0; i < 4; i++) {
483 if (slots[i]) {
484 r = check_vector(bc, slots[i], &bs, bank_swizzle[i]);
485 if (r)
486 break;
487 }
488 }
489 } else
490 r = 0;
491
492 if (!r && slots[4] && max_slots == 5) {
493 r = check_scalar(bc, slots[4], &bs, bank_swizzle[4]);
494 }
495 if (!r) {
496 for (i = 0; i < max_slots; i++) {
497 if (slots[i])
498 slots[i]->bank_swizzle = bank_swizzle[i];
499 }
500 return 0;
501 }
502
503 if (scalar_only) {
504 bank_swizzle[4]++;
505 } else {
506 for (i = 0; i < max_slots; i++) {
507 if (!slots[i] || !slots[i]->bank_swizzle_force) {
508 bank_swizzle[i]++;
509 if (bank_swizzle[i] <= SQ_ALU_VEC_210)
510 break;
511 else if (i < max_slots - 1)
512 bank_swizzle[i] = SQ_ALU_VEC_012;
513 else
514 return -1;
515 }
516 }
517 }
518 }
519
520 /* Couldn't find a working swizzle. */
521 return -1;
522 }
523
524 static int replace_gpr_with_pv_ps(struct r600_bytecode *bc,
525 struct r600_bytecode_alu *slots[5], struct r600_bytecode_alu *alu_prev)
526 {
527 struct r600_bytecode_alu *prev[5];
528 int gpr[5], chan[5];
529 int i, j, r, src, num_src;
530 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
531
532 r = assign_alu_units(bc, alu_prev, prev);
533 if (r)
534 return r;
535
536 for (i = 0; i < max_slots; ++i) {
537 if (prev[i] && (prev[i]->dst.write || prev[i]->is_op3) && !prev[i]->dst.rel) {
538 gpr[i] = prev[i]->dst.sel;
539 /* cube writes more than PV.X */
540 if (is_alu_reduction_inst(bc, prev[i]))
541 chan[i] = 0;
542 else
543 chan[i] = prev[i]->dst.chan;
544 } else
545 gpr[i] = -1;
546 }
547
548 for (i = 0; i < max_slots; ++i) {
549 struct r600_bytecode_alu *alu = slots[i];
550 if(!alu)
551 continue;
552
553 num_src = r600_bytecode_get_num_operands(bc, alu);
554 for (src = 0; src < num_src; ++src) {
555 if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
556 continue;
557
558 if (bc->chip_class < CAYMAN) {
559 if (alu->src[src].sel == gpr[4] &&
560 alu->src[src].chan == chan[4] &&
561 alu_prev->pred_sel == alu->pred_sel) {
562 alu->src[src].sel = V_SQ_ALU_SRC_PS;
563 alu->src[src].chan = 0;
564 continue;
565 }
566 }
567
568 for (j = 0; j < 4; ++j) {
569 if (alu->src[src].sel == gpr[j] &&
570 alu->src[src].chan == j &&
571 alu_prev->pred_sel == alu->pred_sel) {
572 alu->src[src].sel = V_SQ_ALU_SRC_PV;
573 alu->src[src].chan = chan[j];
574 break;
575 }
576 }
577 }
578 }
579
580 return 0;
581 }
582
583 void r600_bytecode_special_constants(uint32_t value, unsigned *sel, unsigned *neg)
584 {
585 switch(value) {
586 case 0:
587 *sel = V_SQ_ALU_SRC_0;
588 break;
589 case 1:
590 *sel = V_SQ_ALU_SRC_1_INT;
591 break;
592 case -1:
593 *sel = V_SQ_ALU_SRC_M_1_INT;
594 break;
595 case 0x3F800000: /* 1.0f */
596 *sel = V_SQ_ALU_SRC_1;
597 break;
598 case 0x3F000000: /* 0.5f */
599 *sel = V_SQ_ALU_SRC_0_5;
600 break;
601 case 0xBF800000: /* -1.0f */
602 *sel = V_SQ_ALU_SRC_1;
603 *neg ^= 1;
604 break;
605 case 0xBF000000: /* -0.5f */
606 *sel = V_SQ_ALU_SRC_0_5;
607 *neg ^= 1;
608 break;
609 default:
610 *sel = V_SQ_ALU_SRC_LITERAL;
611 break;
612 }
613 }
614
615 /* compute how many literal are needed */
616 static int r600_bytecode_alu_nliterals(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
617 uint32_t literal[4], unsigned *nliteral)
618 {
619 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
620 unsigned i, j;
621
622 for (i = 0; i < num_src; ++i) {
623 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
624 uint32_t value = alu->src[i].value;
625 unsigned found = 0;
626 for (j = 0; j < *nliteral; ++j) {
627 if (literal[j] == value) {
628 found = 1;
629 break;
630 }
631 }
632 if (!found) {
633 if (*nliteral >= 4)
634 return -EINVAL;
635 literal[(*nliteral)++] = value;
636 }
637 }
638 }
639 return 0;
640 }
641
642 static void r600_bytecode_alu_adjust_literals(struct r600_bytecode *bc,
643 struct r600_bytecode_alu *alu,
644 uint32_t literal[4], unsigned nliteral)
645 {
646 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
647 unsigned i, j;
648
649 for (i = 0; i < num_src; ++i) {
650 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
651 uint32_t value = alu->src[i].value;
652 for (j = 0; j < nliteral; ++j) {
653 if (literal[j] == value) {
654 alu->src[i].chan = j;
655 break;
656 }
657 }
658 }
659 }
660 }
661
662 static int merge_inst_groups(struct r600_bytecode *bc, struct r600_bytecode_alu *slots[5],
663 struct r600_bytecode_alu *alu_prev)
664 {
665 struct r600_bytecode_alu *prev[5];
666 struct r600_bytecode_alu *result[5] = { NULL };
667
668 uint32_t literal[4], prev_literal[4];
669 unsigned nliteral = 0, prev_nliteral = 0;
670
671 int i, j, r, src, num_src;
672 int num_once_inst = 0;
673 int have_mova = 0, have_rel = 0;
674 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
675
676 r = assign_alu_units(bc, alu_prev, prev);
677 if (r)
678 return r;
679
680 for (i = 0; i < max_slots; ++i) {
681 if (prev[i]) {
682 if (prev[i]->pred_sel)
683 return 0;
684 if (is_alu_once_inst(bc, prev[i]))
685 return 0;
686 }
687 if (slots[i]) {
688 if (slots[i]->pred_sel)
689 return 0;
690 if (is_alu_once_inst(bc, slots[i]))
691 return 0;
692 }
693 }
694
695 for (i = 0; i < max_slots; ++i) {
696 struct r600_bytecode_alu *alu;
697
698 if (num_once_inst > 0)
699 return 0;
700
701 /* check number of literals */
702 if (prev[i]) {
703 if (r600_bytecode_alu_nliterals(bc, prev[i], literal, &nliteral))
704 return 0;
705 if (r600_bytecode_alu_nliterals(bc, prev[i], prev_literal, &prev_nliteral))
706 return 0;
707 if (is_alu_mova_inst(bc, prev[i])) {
708 if (have_rel)
709 return 0;
710 have_mova = 1;
711 }
712
713 if (alu_uses_rel(bc, prev[i])) {
714 if (have_mova) {
715 return 0;
716 }
717 have_rel = 1;
718 }
719
720 num_once_inst += is_alu_once_inst(bc, prev[i]);
721 }
722 if (slots[i] && r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral))
723 return 0;
724
725 /* Let's check used slots. */
726 if (prev[i] && !slots[i]) {
727 result[i] = prev[i];
728 continue;
729 } else if (prev[i] && slots[i]) {
730 if (max_slots == 5 && result[4] == NULL && prev[4] == NULL && slots[4] == NULL) {
731 /* Trans unit is still free try to use it. */
732 if (is_alu_any_unit_inst(bc, slots[i])) {
733 result[i] = prev[i];
734 result[4] = slots[i];
735 } else if (is_alu_any_unit_inst(bc, prev[i])) {
736 if (slots[i]->dst.sel == prev[i]->dst.sel &&
737 (slots[i]->dst.write == 1 || slots[i]->is_op3) &&
738 (prev[i]->dst.write == 1 || prev[i]->is_op3))
739 return 0;
740
741 result[i] = slots[i];
742 result[4] = prev[i];
743 } else
744 return 0;
745 } else
746 return 0;
747 } else if(!slots[i]) {
748 continue;
749 } else {
750 if (max_slots == 5 && slots[i] && prev[4] &&
751 slots[i]->dst.sel == prev[4]->dst.sel &&
752 slots[i]->dst.chan == prev[4]->dst.chan &&
753 (slots[i]->dst.write == 1 || slots[i]->is_op3) &&
754 (prev[4]->dst.write == 1 || prev[4]->is_op3))
755 return 0;
756
757 result[i] = slots[i];
758 }
759
760 alu = slots[i];
761 num_once_inst += is_alu_once_inst(bc, alu);
762
763 /* don't reschedule NOPs */
764 if (is_nop_inst(bc, alu))
765 return 0;
766
767 if (is_alu_mova_inst(bc, alu)) {
768 if (have_rel) {
769 return 0;
770 }
771 have_mova = 1;
772 }
773
774 if (alu_uses_rel(bc, alu)) {
775 if (have_mova) {
776 return 0;
777 }
778 have_rel = 1;
779 }
780
781 /* Let's check source gprs */
782 num_src = r600_bytecode_get_num_operands(bc, alu);
783 for (src = 0; src < num_src; ++src) {
784
785 /* Constants don't matter. */
786 if (!is_gpr(alu->src[src].sel))
787 continue;
788
789 for (j = 0; j < max_slots; ++j) {
790 if (!prev[j] || !(prev[j]->dst.write || prev[j]->is_op3))
791 continue;
792
793 /* If it's relative then we can't determin which gpr is really used. */
794 if (prev[j]->dst.chan == alu->src[src].chan &&
795 (prev[j]->dst.sel == alu->src[src].sel ||
796 prev[j]->dst.rel || alu->src[src].rel))
797 return 0;
798 }
799 }
800 }
801
802 /* more than one PRED_ or KILL_ ? */
803 if (num_once_inst > 1)
804 return 0;
805
806 /* check if the result can still be swizzlet */
807 r = check_and_set_bank_swizzle(bc, result);
808 if (r)
809 return 0;
810
811 /* looks like everything worked out right, apply the changes */
812
813 /* undo adding previus literals */
814 bc->cf_last->ndw -= align(prev_nliteral, 2);
815
816 /* sort instructions */
817 for (i = 0; i < max_slots; ++i) {
818 slots[i] = result[i];
819 if (result[i]) {
820 LIST_DEL(&result[i]->list);
821 result[i]->last = 0;
822 LIST_ADDTAIL(&result[i]->list, &bc->cf_last->alu);
823 }
824 }
825
826 /* determine new last instruction */
827 LIST_ENTRY(struct r600_bytecode_alu, bc->cf_last->alu.prev, list)->last = 1;
828
829 /* determine new first instruction */
830 for (i = 0; i < max_slots; ++i) {
831 if (result[i]) {
832 bc->cf_last->curr_bs_head = result[i];
833 break;
834 }
835 }
836
837 bc->cf_last->prev_bs_head = bc->cf_last->prev2_bs_head;
838 bc->cf_last->prev2_bs_head = NULL;
839
840 return 0;
841 }
842
843 /* we'll keep kcache sets sorted by bank & addr */
844 static int r600_bytecode_alloc_kcache_line(struct r600_bytecode *bc,
845 struct r600_bytecode_kcache *kcache,
846 unsigned bank, unsigned line)
847 {
848 int i, kcache_banks = bc->chip_class >= EVERGREEN ? 4 : 2;
849
850 for (i = 0; i < kcache_banks; i++) {
851 if (kcache[i].mode) {
852 int d;
853
854 if (kcache[i].bank < bank)
855 continue;
856
857 if ((kcache[i].bank == bank && kcache[i].addr > line+1) ||
858 kcache[i].bank > bank) {
859 /* try to insert new line */
860 if (kcache[kcache_banks-1].mode) {
861 /* all sets are in use */
862 return -ENOMEM;
863 }
864
865 memmove(&kcache[i+1],&kcache[i], (kcache_banks-i-1)*sizeof(struct r600_bytecode_kcache));
866 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
867 kcache[i].bank = bank;
868 kcache[i].addr = line;
869 return 0;
870 }
871
872 d = line - kcache[i].addr;
873
874 if (d == -1) {
875 kcache[i].addr--;
876 if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_2) {
877 /* we are prepending the line to the current set,
878 * discarding the existing second line,
879 * so we'll have to insert line+2 after it */
880 line += 2;
881 continue;
882 } else if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_1) {
883 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
884 return 0;
885 } else {
886 /* V_SQ_CF_KCACHE_LOCK_LOOP_INDEX is not supported */
887 return -ENOMEM;
888 }
889 } else if (d == 1) {
890 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
891 return 0;
892 } else if (d == 0)
893 return 0;
894 } else { /* free kcache set - use it */
895 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
896 kcache[i].bank = bank;
897 kcache[i].addr = line;
898 return 0;
899 }
900 }
901 return -ENOMEM;
902 }
903
904 static int r600_bytecode_alloc_inst_kcache_lines(struct r600_bytecode *bc,
905 struct r600_bytecode_kcache *kcache,
906 struct r600_bytecode_alu *alu)
907 {
908 int i, r;
909
910 for (i = 0; i < 3; i++) {
911 unsigned bank, line, sel = alu->src[i].sel;
912
913 if (sel < 512)
914 continue;
915
916 bank = alu->src[i].kc_bank;
917 line = (sel-512)>>4;
918
919 if ((r = r600_bytecode_alloc_kcache_line(bc, kcache, bank, line)))
920 return r;
921 }
922 return 0;
923 }
924
925 static int r600_bytecode_assign_kcache_banks(struct r600_bytecode *bc,
926 struct r600_bytecode_alu *alu,
927 struct r600_bytecode_kcache * kcache)
928 {
929 int i, j;
930
931 /* Alter the src operands to refer to the kcache. */
932 for (i = 0; i < 3; ++i) {
933 static const unsigned int base[] = {128, 160, 256, 288};
934 unsigned int line, sel = alu->src[i].sel, found = 0;
935
936 if (sel < 512)
937 continue;
938
939 sel -= 512;
940 line = sel>>4;
941
942 for (j = 0; j < 4 && !found; ++j) {
943 switch (kcache[j].mode) {
944 case V_SQ_CF_KCACHE_NOP:
945 case V_SQ_CF_KCACHE_LOCK_LOOP_INDEX:
946 R600_ERR("unexpected kcache line mode\n");
947 return -ENOMEM;
948 default:
949 if (kcache[j].bank == alu->src[i].kc_bank &&
950 kcache[j].addr <= line &&
951 line < kcache[j].addr + kcache[j].mode) {
952 alu->src[i].sel = sel - (kcache[j].addr<<4);
953 alu->src[i].sel += base[j];
954 found=1;
955 }
956 }
957 }
958 }
959 return 0;
960 }
961
962 static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode *bc,
963 struct r600_bytecode_alu *alu,
964 unsigned type)
965 {
966 struct r600_bytecode_kcache kcache_sets[4];
967 struct r600_bytecode_kcache *kcache = kcache_sets;
968 int r;
969
970 memcpy(kcache, bc->cf_last->kcache, 4 * sizeof(struct r600_bytecode_kcache));
971
972 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
973 /* can't alloc, need to start new clause */
974 if ((r = r600_bytecode_add_cf(bc))) {
975 return r;
976 }
977 bc->cf_last->op = type;
978
979 /* retry with the new clause */
980 kcache = bc->cf_last->kcache;
981 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
982 /* can't alloc again- should never happen */
983 return r;
984 }
985 } else {
986 /* update kcache sets */
987 memcpy(bc->cf_last->kcache, kcache, 4 * sizeof(struct r600_bytecode_kcache));
988 }
989
990 /* if we actually used more than 2 kcache sets - use ALU_EXTENDED on eg+ */
991 if (kcache[2].mode != V_SQ_CF_KCACHE_NOP) {
992 if (bc->chip_class < EVERGREEN)
993 return -ENOMEM;
994 bc->cf_last->eg_alu_extended = 1;
995 }
996
997 return 0;
998 }
999
1000 static int insert_nop_r6xx(struct r600_bytecode *bc)
1001 {
1002 struct r600_bytecode_alu alu;
1003 int r, i;
1004
1005 for (i = 0; i < 4; i++) {
1006 memset(&alu, 0, sizeof(alu));
1007 alu.op = ALU_OP0_NOP;
1008 alu.src[0].chan = i;
1009 alu.dst.chan = i;
1010 alu.last = (i == 3);
1011 r = r600_bytecode_add_alu(bc, &alu);
1012 if (r)
1013 return r;
1014 }
1015 return 0;
1016 }
1017
1018 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1019 static int load_ar_r6xx(struct r600_bytecode *bc)
1020 {
1021 struct r600_bytecode_alu alu;
1022 int r;
1023
1024 if (bc->ar_loaded)
1025 return 0;
1026
1027 /* hack to avoid making MOVA the last instruction in the clause */
1028 if ((bc->cf_last->ndw>>1) >= 110)
1029 bc->force_add_cf = 1;
1030
1031 memset(&alu, 0, sizeof(alu));
1032 alu.op = ALU_OP1_MOVA_GPR_INT;
1033 alu.src[0].sel = bc->ar_reg;
1034 alu.src[0].chan = bc->ar_chan;
1035 alu.last = 1;
1036 alu.index_mode = INDEX_MODE_LOOP;
1037 r = r600_bytecode_add_alu(bc, &alu);
1038 if (r)
1039 return r;
1040
1041 /* no requirement to set uses waterfall on MOVA_GPR_INT */
1042 bc->ar_loaded = 1;
1043 return 0;
1044 }
1045
1046 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1047 static int load_ar(struct r600_bytecode *bc)
1048 {
1049 struct r600_bytecode_alu alu;
1050 int r;
1051
1052 if (bc->ar_handling)
1053 return load_ar_r6xx(bc);
1054
1055 if (bc->ar_loaded)
1056 return 0;
1057
1058 /* hack to avoid making MOVA the last instruction in the clause */
1059 if ((bc->cf_last->ndw>>1) >= 110)
1060 bc->force_add_cf = 1;
1061
1062 memset(&alu, 0, sizeof(alu));
1063 alu.op = ALU_OP1_MOVA_INT;
1064 alu.src[0].sel = bc->ar_reg;
1065 alu.src[0].chan = bc->ar_chan;
1066 alu.last = 1;
1067 r = r600_bytecode_add_alu(bc, &alu);
1068 if (r)
1069 return r;
1070
1071 bc->cf_last->r6xx_uses_waterfall = 1;
1072 bc->ar_loaded = 1;
1073 return 0;
1074 }
1075
1076 int r600_bytecode_add_alu_type(struct r600_bytecode *bc,
1077 const struct r600_bytecode_alu *alu, unsigned type)
1078 {
1079 struct r600_bytecode_alu *nalu = r600_bytecode_alu();
1080 struct r600_bytecode_alu *lalu;
1081 int i, r;
1082
1083 if (nalu == NULL)
1084 return -ENOMEM;
1085 memcpy(nalu, alu, sizeof(struct r600_bytecode_alu));
1086
1087 if (bc->cf_last != NULL && bc->cf_last->op != type) {
1088 /* check if we could add it anyway */
1089 if (bc->cf_last->op == CF_OP_ALU &&
1090 type == CF_OP_ALU_PUSH_BEFORE) {
1091 LIST_FOR_EACH_ENTRY(lalu, &bc->cf_last->alu, list) {
1092 if (lalu->execute_mask) {
1093 bc->force_add_cf = 1;
1094 break;
1095 }
1096 }
1097 } else
1098 bc->force_add_cf = 1;
1099 }
1100
1101 /* cf can contains only alu or only vtx or only tex */
1102 if (bc->cf_last == NULL || bc->force_add_cf) {
1103 r = r600_bytecode_add_cf(bc);
1104 if (r) {
1105 free(nalu);
1106 return r;
1107 }
1108 }
1109 bc->cf_last->op = type;
1110
1111 /* Check AR usage and load it if required */
1112 for (i = 0; i < 3; i++)
1113 if (nalu->src[i].rel && !bc->ar_loaded)
1114 load_ar(bc);
1115
1116 if (nalu->dst.rel && !bc->ar_loaded)
1117 load_ar(bc);
1118
1119 /* Setup the kcache for this ALU instruction. This will start a new
1120 * ALU clause if needed. */
1121 if ((r = r600_bytecode_alloc_kcache_lines(bc, nalu, type))) {
1122 free(nalu);
1123 return r;
1124 }
1125
1126 if (!bc->cf_last->curr_bs_head) {
1127 bc->cf_last->curr_bs_head = nalu;
1128 }
1129 /* number of gpr == the last gpr used in any alu */
1130 for (i = 0; i < 3; i++) {
1131 if (nalu->src[i].sel >= bc->ngpr && nalu->src[i].sel < 128) {
1132 bc->ngpr = nalu->src[i].sel + 1;
1133 }
1134 if (nalu->src[i].sel == V_SQ_ALU_SRC_LITERAL)
1135 r600_bytecode_special_constants(nalu->src[i].value,
1136 &nalu->src[i].sel, &nalu->src[i].neg);
1137 }
1138 if (nalu->dst.sel >= bc->ngpr) {
1139 bc->ngpr = nalu->dst.sel + 1;
1140 }
1141 LIST_ADDTAIL(&nalu->list, &bc->cf_last->alu);
1142 /* each alu use 2 dwords */
1143 bc->cf_last->ndw += 2;
1144 bc->ndw += 2;
1145
1146 /* process cur ALU instructions for bank swizzle */
1147 if (nalu->last) {
1148 uint32_t literal[4];
1149 unsigned nliteral;
1150 struct r600_bytecode_alu *slots[5];
1151 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
1152 r = assign_alu_units(bc, bc->cf_last->curr_bs_head, slots);
1153 if (r)
1154 return r;
1155
1156 if (bc->cf_last->prev_bs_head) {
1157 r = merge_inst_groups(bc, slots, bc->cf_last->prev_bs_head);
1158 if (r)
1159 return r;
1160 }
1161
1162 if (bc->cf_last->prev_bs_head) {
1163 r = replace_gpr_with_pv_ps(bc, slots, bc->cf_last->prev_bs_head);
1164 if (r)
1165 return r;
1166 }
1167
1168 r = check_and_set_bank_swizzle(bc, slots);
1169 if (r)
1170 return r;
1171
1172 for (i = 0, nliteral = 0; i < max_slots; i++) {
1173 if (slots[i]) {
1174 r = r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral);
1175 if (r)
1176 return r;
1177 }
1178 }
1179 bc->cf_last->ndw += align(nliteral, 2);
1180
1181 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1182 * worst case */
1183 if ((bc->cf_last->ndw >> 1) >= 120) {
1184 bc->force_add_cf = 1;
1185 }
1186
1187 bc->cf_last->prev2_bs_head = bc->cf_last->prev_bs_head;
1188 bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head;
1189 bc->cf_last->curr_bs_head = NULL;
1190 }
1191
1192 if (nalu->dst.rel && bc->r6xx_nop_after_rel_dst)
1193 insert_nop_r6xx(bc);
1194
1195 return 0;
1196 }
1197
1198 int r600_bytecode_add_alu(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu)
1199 {
1200 return r600_bytecode_add_alu_type(bc, alu, CF_OP_ALU);
1201 }
1202
1203 static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode *bc)
1204 {
1205 switch (bc->chip_class) {
1206 case R600:
1207 return 8;
1208
1209 case R700:
1210 case EVERGREEN:
1211 case CAYMAN:
1212 return 16;
1213
1214 default:
1215 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1216 return 8;
1217 }
1218 }
1219
1220 static inline boolean last_inst_was_not_vtx_fetch(struct r600_bytecode *bc)
1221 {
1222 return !((r600_isa_cf(bc->cf_last->op)->flags & CF_FETCH) &&
1223 (bc->chip_class == CAYMAN ||
1224 bc->cf_last->op != CF_OP_TEX));
1225 }
1226
1227 int r600_bytecode_add_vtx(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx)
1228 {
1229 struct r600_bytecode_vtx *nvtx = r600_bytecode_vtx();
1230 int r;
1231
1232 if (nvtx == NULL)
1233 return -ENOMEM;
1234 memcpy(nvtx, vtx, sizeof(struct r600_bytecode_vtx));
1235
1236 /* cf can contains only alu or only vtx or only tex */
1237 if (bc->cf_last == NULL ||
1238 last_inst_was_not_vtx_fetch(bc) ||
1239 bc->force_add_cf) {
1240 r = r600_bytecode_add_cf(bc);
1241 if (r) {
1242 free(nvtx);
1243 return r;
1244 }
1245 switch (bc->chip_class) {
1246 case R600:
1247 case R700:
1248 case EVERGREEN:
1249 bc->cf_last->op = CF_OP_VTX;
1250 break;
1251 case CAYMAN:
1252 bc->cf_last->op = CF_OP_TEX;
1253 break;
1254 default:
1255 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1256 free(nvtx);
1257 return -EINVAL;
1258 }
1259 }
1260 LIST_ADDTAIL(&nvtx->list, &bc->cf_last->vtx);
1261 /* each fetch use 4 dwords */
1262 bc->cf_last->ndw += 4;
1263 bc->ndw += 4;
1264 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1265 bc->force_add_cf = 1;
1266
1267 bc->ngpr = MAX2(bc->ngpr, vtx->src_gpr + 1);
1268 bc->ngpr = MAX2(bc->ngpr, vtx->dst_gpr + 1);
1269
1270 return 0;
1271 }
1272
1273 int r600_bytecode_add_tex(struct r600_bytecode *bc, const struct r600_bytecode_tex *tex)
1274 {
1275 struct r600_bytecode_tex *ntex = r600_bytecode_tex();
1276 int r;
1277
1278 if (ntex == NULL)
1279 return -ENOMEM;
1280 memcpy(ntex, tex, sizeof(struct r600_bytecode_tex));
1281
1282 /* we can't fetch data und use it as texture lookup address in the same TEX clause */
1283 if (bc->cf_last != NULL &&
1284 bc->cf_last->op == CF_OP_TEX) {
1285 struct r600_bytecode_tex *ttex;
1286 LIST_FOR_EACH_ENTRY(ttex, &bc->cf_last->tex, list) {
1287 if (ttex->dst_gpr == ntex->src_gpr) {
1288 bc->force_add_cf = 1;
1289 break;
1290 }
1291 }
1292 /* slight hack to make gradients always go into same cf */
1293 if (ntex->op == FETCH_OP_SET_GRADIENTS_H)
1294 bc->force_add_cf = 1;
1295 }
1296
1297 /* cf can contains only alu or only vtx or only tex */
1298 if (bc->cf_last == NULL ||
1299 bc->cf_last->op != CF_OP_TEX ||
1300 bc->force_add_cf) {
1301 r = r600_bytecode_add_cf(bc);
1302 if (r) {
1303 free(ntex);
1304 return r;
1305 }
1306 bc->cf_last->op = CF_OP_TEX;
1307 }
1308 if (ntex->src_gpr >= bc->ngpr) {
1309 bc->ngpr = ntex->src_gpr + 1;
1310 }
1311 if (ntex->dst_gpr >= bc->ngpr) {
1312 bc->ngpr = ntex->dst_gpr + 1;
1313 }
1314 LIST_ADDTAIL(&ntex->list, &bc->cf_last->tex);
1315 /* each texture fetch use 4 dwords */
1316 bc->cf_last->ndw += 4;
1317 bc->ndw += 4;
1318 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1319 bc->force_add_cf = 1;
1320 return 0;
1321 }
1322
1323 int r600_bytecode_add_cfinst(struct r600_bytecode *bc, unsigned op)
1324 {
1325 int r;
1326 r = r600_bytecode_add_cf(bc);
1327 if (r)
1328 return r;
1329
1330 bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
1331 bc->cf_last->op = op;
1332 return 0;
1333 }
1334
1335 int cm_bytecode_add_cf_end(struct r600_bytecode *bc)
1336 {
1337 return r600_bytecode_add_cfinst(bc, CF_OP_CF_END);
1338 }
1339
1340 /* common to all 3 families */
1341 static int r600_bytecode_vtx_build(struct r600_bytecode *bc, struct r600_bytecode_vtx *vtx, unsigned id)
1342 {
1343 bc->bytecode[id] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) |
1344 S_SQ_VTX_WORD0_FETCH_TYPE(vtx->fetch_type) |
1345 S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
1346 S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x);
1347 if (bc->chip_class < CAYMAN)
1348 bc->bytecode[id] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
1349 id++;
1350 bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
1351 S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
1352 S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
1353 S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
1354 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) |
1355 S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) |
1356 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) |
1357 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) |
1358 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
1359 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
1360 bc->bytecode[id] = S_SQ_VTX_WORD2_OFFSET(vtx->offset)|
1361 S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx->endian);
1362 if (bc->chip_class < CAYMAN)
1363 bc->bytecode[id] |= S_SQ_VTX_WORD2_MEGA_FETCH(1);
1364 id++;
1365 bc->bytecode[id++] = 0;
1366 return 0;
1367 }
1368
1369 /* common to all 3 families */
1370 static int r600_bytecode_tex_build(struct r600_bytecode *bc, struct r600_bytecode_tex *tex, unsigned id)
1371 {
1372 bc->bytecode[id++] = S_SQ_TEX_WORD0_TEX_INST(
1373 r600_isa_fetch_opcode(bc->isa->hw_class, tex->op)) |
1374 EG_S_SQ_TEX_WORD0_INST_MOD(tex->inst_mod) |
1375 S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
1376 S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
1377 S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
1378 bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
1379 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
1380 S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
1381 S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
1382 S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
1383 S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
1384 S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
1385 S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
1386 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
1387 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
1388 S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
1389 bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
1390 S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
1391 S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
1392 S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
1393 S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
1394 S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
1395 S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
1396 S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
1397 bc->bytecode[id++] = 0;
1398 return 0;
1399 }
1400
1401 /* r600 only, r700/eg bits in r700_asm.c */
1402 static int r600_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id)
1403 {
1404 unsigned opcode = r600_isa_alu_opcode(bc->isa->hw_class, alu->op);
1405
1406 /* don't replace gpr by pv or ps for destination register */
1407 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
1408 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
1409 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
1410 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
1411 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
1412 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
1413 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
1414 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
1415 S_SQ_ALU_WORD0_INDEX_MODE(alu->index_mode) |
1416 S_SQ_ALU_WORD0_PRED_SEL(alu->pred_sel) |
1417 S_SQ_ALU_WORD0_LAST(alu->last);
1418
1419 if (alu->is_op3) {
1420 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1421 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1422 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1423 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1424 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
1425 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
1426 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
1427 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
1428 S_SQ_ALU_WORD1_OP3_ALU_INST(opcode) |
1429 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
1430 } else {
1431 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1432 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1433 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1434 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1435 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
1436 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
1437 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
1438 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
1439 S_SQ_ALU_WORD1_OP2_ALU_INST(opcode) |
1440 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
1441 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->execute_mask) |
1442 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->update_pred);
1443 }
1444 return 0;
1445 }
1446
1447 static void r600_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_cf *cf)
1448 {
1449 *bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
1450 *bytecode++ = S_SQ_CF_WORD1_CF_INST(r600_isa_cf_opcode(ISA_CC_R600, cf->op)) |
1451 S_SQ_CF_WORD1_BARRIER(1) |
1452 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
1453 }
1454
1455 /* common for r600/r700 - eg in eg_asm.c */
1456 static int r600_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf)
1457 {
1458 unsigned id = cf->id;
1459 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
1460 unsigned opcode = r600_isa_cf_opcode(bc->isa->hw_class, cf->op);
1461
1462 if (cfop->flags & CF_ALU) {
1463 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
1464 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
1465 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
1466 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank);
1467
1468 bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(opcode) |
1469 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) |
1470 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
1471 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
1472 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1473 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chip_class == R600 ? cf->r6xx_uses_waterfall : 0) |
1474 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
1475 } else if (cfop->flags & CF_FETCH) {
1476 if (bc->chip_class == R700)
1477 r700_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1478 else
1479 r600_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1480 } else if (cfop->flags & CF_EXP) {
1481 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1482 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1483 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1484 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
1485 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1486 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
1487 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
1488 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
1489 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
1490 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
1491 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) |
1492 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program);
1493 } else if (cfop->flags & CF_STRM) {
1494 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1495 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1496 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1497 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
1498 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1499 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
1500 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) |
1501 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program) |
1502 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf->output.array_size) |
1503 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf->output.comp_mask);
1504 } else {
1505 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
1506 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(opcode) |
1507 S_SQ_CF_WORD1_BARRIER(1) |
1508 S_SQ_CF_WORD1_COND(cf->cond) |
1509 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count);
1510 }
1511 return 0;
1512 }
1513
1514 int r600_bytecode_build(struct r600_bytecode *bc)
1515 {
1516 struct r600_bytecode_cf *cf;
1517 struct r600_bytecode_alu *alu;
1518 struct r600_bytecode_vtx *vtx;
1519 struct r600_bytecode_tex *tex;
1520 uint32_t literal[4];
1521 unsigned nliteral;
1522 unsigned addr;
1523 int i, r;
1524
1525 if (bc->callstack[0].max > 0)
1526 bc->nstack = ((bc->callstack[0].max + 3) >> 2) + 2;
1527 if (bc->type == TGSI_PROCESSOR_VERTEX && !bc->nstack) {
1528 bc->nstack = 1;
1529 }
1530
1531 /* first path compute addr of each CF block */
1532 /* addr start after all the CF instructions */
1533 addr = bc->cf_last->id + 2;
1534 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1535 if (r600_isa_cf(cf->op)->flags & CF_FETCH) {
1536 addr += 3;
1537 addr &= 0xFFFFFFFCUL;
1538 }
1539 cf->addr = addr;
1540 addr += cf->ndw;
1541 bc->ndw = cf->addr + cf->ndw;
1542 }
1543 free(bc->bytecode);
1544 bc->bytecode = calloc(1, bc->ndw * 4);
1545 if (bc->bytecode == NULL)
1546 return -ENOMEM;
1547 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1548 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
1549 addr = cf->addr;
1550 if (bc->chip_class >= EVERGREEN)
1551 r = eg_bytecode_cf_build(bc, cf);
1552 else
1553 r = r600_bytecode_cf_build(bc, cf);
1554 if (r)
1555 return r;
1556 if (cfop->flags & CF_ALU) {
1557 nliteral = 0;
1558 memset(literal, 0, sizeof(literal));
1559 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1560 r = r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
1561 if (r)
1562 return r;
1563 r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral);
1564 r600_bytecode_assign_kcache_banks(bc, alu, cf->kcache);
1565
1566 switch(bc->chip_class) {
1567 case R600:
1568 r = r600_bytecode_alu_build(bc, alu, addr);
1569 break;
1570 case R700:
1571 case EVERGREEN: /* eg alu is same encoding as r700 */
1572 case CAYMAN:
1573 r = r700_bytecode_alu_build(bc, alu, addr);
1574 break;
1575 default:
1576 R600_ERR("unknown chip class %d.\n", bc->chip_class);
1577 return -EINVAL;
1578 }
1579 if (r)
1580 return r;
1581 addr += 2;
1582 if (alu->last) {
1583 for (i = 0; i < align(nliteral, 2); ++i) {
1584 bc->bytecode[addr++] = literal[i];
1585 }
1586 nliteral = 0;
1587 memset(literal, 0, sizeof(literal));
1588 }
1589 }
1590 } else if (cf->op == CF_OP_VTX) {
1591 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1592 r = r600_bytecode_vtx_build(bc, vtx, addr);
1593 if (r)
1594 return r;
1595 addr += 4;
1596 }
1597 } else if (cf->op == CF_OP_TEX) {
1598 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1599 assert(bc->chip_class >= EVERGREEN);
1600 r = r600_bytecode_vtx_build(bc, vtx, addr);
1601 if (r)
1602 return r;
1603 addr += 4;
1604 }
1605 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
1606 r = r600_bytecode_tex_build(bc, tex, addr);
1607 if (r)
1608 return r;
1609 addr += 4;
1610 }
1611 }
1612 }
1613 return 0;
1614 }
1615
1616 void r600_bytecode_clear(struct r600_bytecode *bc)
1617 {
1618 struct r600_bytecode_cf *cf = NULL, *next_cf;
1619
1620 free(bc->bytecode);
1621 bc->bytecode = NULL;
1622
1623 LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
1624 struct r600_bytecode_alu *alu = NULL, *next_alu;
1625 struct r600_bytecode_tex *tex = NULL, *next_tex;
1626 struct r600_bytecode_tex *vtx = NULL, *next_vtx;
1627
1628 LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
1629 free(alu);
1630 }
1631
1632 LIST_INITHEAD(&cf->alu);
1633
1634 LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) {
1635 free(tex);
1636 }
1637
1638 LIST_INITHEAD(&cf->tex);
1639
1640 LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) {
1641 free(vtx);
1642 }
1643
1644 LIST_INITHEAD(&cf->vtx);
1645
1646 free(cf);
1647 }
1648
1649 LIST_INITHEAD(&cf->list);
1650 }
1651
1652 static int print_swizzle(unsigned swz)
1653 {
1654 const char * swzchars = "xyzw01?_";
1655 assert(swz<8 && swz != 6);
1656 return fprintf(stderr, "%c", swzchars[swz]);
1657 }
1658
1659 static int print_sel(unsigned sel, unsigned rel, unsigned index_mode,
1660 unsigned need_brackets)
1661 {
1662 int o = 0;
1663 if (rel && index_mode >= 5 && sel < 128)
1664 o += fprintf(stderr, "G");
1665 if (rel || need_brackets) {
1666 o += fprintf(stderr, "[");
1667 }
1668 o += fprintf(stderr, "%d", sel);
1669 if (rel) {
1670 if (index_mode == 0 || index_mode == 6)
1671 o += fprintf(stderr, "+AR");
1672 else if (index_mode == 4)
1673 o += fprintf(stderr, "+AL");
1674 }
1675 if (rel || need_brackets) {
1676 o += fprintf(stderr, "]");
1677 }
1678 return o;
1679 }
1680
1681 static int print_dst(struct r600_bytecode_alu *alu)
1682 {
1683 int o = 0;
1684 unsigned sel = alu->dst.sel;
1685 char reg_char = 'R';
1686 if (sel > 128 - 4) { /* clause temporary gpr */
1687 sel -= 128 - 4;
1688 reg_char = 'T';
1689 }
1690
1691 if (alu->dst.write || alu->is_op3) {
1692 o += fprintf(stderr, "%c", reg_char);
1693 o += print_sel(alu->dst.sel, alu->dst.rel, alu->index_mode, 0);
1694 } else {
1695 o += fprintf(stderr, "__");
1696 }
1697 o += fprintf(stderr, ".");
1698 o += print_swizzle(alu->dst.chan);
1699 return o;
1700 }
1701
1702 static int print_src(struct r600_bytecode_alu *alu, unsigned idx)
1703 {
1704 int o = 0;
1705 struct r600_bytecode_alu_src *src = &alu->src[idx];
1706 unsigned sel = src->sel, need_sel = 1, need_chan = 1, need_brackets = 0;
1707
1708 if (src->neg)
1709 o += fprintf(stderr,"-");
1710 if (src->abs)
1711 o += fprintf(stderr,"|");
1712
1713 if (sel < 128 - 4) {
1714 o += fprintf(stderr, "R");
1715 } else if (sel < 128) {
1716 o += fprintf(stderr, "T");
1717 sel -= 128 - 4;
1718 } else if (sel < 160) {
1719 o += fprintf(stderr, "KC0");
1720 need_brackets = 1;
1721 sel -= 128;
1722 } else if (sel < 192) {
1723 o += fprintf(stderr, "KC1");
1724 need_brackets = 1;
1725 sel -= 160;
1726 } else if (sel >= 512) {
1727 o += fprintf(stderr, "C%d", src->kc_bank);
1728 need_brackets = 1;
1729 sel -= 512;
1730 } else if (sel >= 448) {
1731 o += fprintf(stderr, "Param");
1732 sel -= 448;
1733 need_chan = 0;
1734 } else if (sel >= 288) {
1735 o += fprintf(stderr, "KC3");
1736 need_brackets = 1;
1737 sel -= 288;
1738 } else if (sel >= 256) {
1739 o += fprintf(stderr, "KC2");
1740 need_brackets = 1;
1741 sel -= 256;
1742 } else {
1743 need_sel = 0;
1744 need_chan = 0;
1745 switch (sel) {
1746 case V_SQ_ALU_SRC_PS:
1747 o += fprintf(stderr, "PS");
1748 break;
1749 case V_SQ_ALU_SRC_PV:
1750 o += fprintf(stderr, "PV");
1751 need_chan = 1;
1752 break;
1753 case V_SQ_ALU_SRC_LITERAL:
1754 o += fprintf(stderr, "[0x%08X %f]", src->value, *(float*)&src->value);
1755 break;
1756 case V_SQ_ALU_SRC_0_5:
1757 o += fprintf(stderr, "0.5");
1758 break;
1759 case V_SQ_ALU_SRC_M_1_INT:
1760 o += fprintf(stderr, "-1");
1761 break;
1762 case V_SQ_ALU_SRC_1_INT:
1763 o += fprintf(stderr, "1");
1764 break;
1765 case V_SQ_ALU_SRC_1:
1766 o += fprintf(stderr, "1.0");
1767 break;
1768 case V_SQ_ALU_SRC_0:
1769 o += fprintf(stderr, "0");
1770 break;
1771 default:
1772 o += fprintf(stderr, "??IMM_%d", sel);
1773 break;
1774 }
1775 }
1776
1777 if (need_sel)
1778 o += print_sel(sel, src->rel, alu->index_mode, need_brackets);
1779
1780 if (need_chan) {
1781 o += fprintf(stderr, ".");
1782 o += print_swizzle(src->chan);
1783 }
1784
1785 if (src->abs)
1786 o += fprintf(stderr,"|");
1787
1788 return o;
1789 }
1790
1791 static int print_indent(int p, int c)
1792 {
1793 int o = 0;
1794 while (p++ < c)
1795 o += fprintf(stderr, " ");
1796 return o;
1797 }
1798
1799 void r600_bytecode_disasm(struct r600_bytecode *bc)
1800 {
1801 static int index = 0;
1802 struct r600_bytecode_cf *cf = NULL;
1803 struct r600_bytecode_alu *alu = NULL;
1804 struct r600_bytecode_vtx *vtx = NULL;
1805 struct r600_bytecode_tex *tex = NULL;
1806
1807 unsigned i, id, ngr = 0, last;
1808 uint32_t literal[4];
1809 unsigned nliteral;
1810 char chip = '6';
1811
1812 switch (bc->chip_class) {
1813 case R700:
1814 chip = '7';
1815 break;
1816 case EVERGREEN:
1817 chip = 'E';
1818 break;
1819 case CAYMAN:
1820 chip = 'C';
1821 break;
1822 case R600:
1823 default:
1824 chip = '6';
1825 break;
1826 }
1827 fprintf(stderr, "bytecode %d dw -- %d gprs ---------------------\n",
1828 bc->ndw, bc->ngpr);
1829 fprintf(stderr, "shader %d -- %c\n", index++, chip);
1830
1831 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1832 id = cf->id;
1833 if (cf->op == CF_NATIVE) {
1834 fprintf(stderr, "%04d %08X %08X CF_NATIVE\n", id, bc->bytecode[id],
1835 bc->bytecode[id + 1]);
1836 } else {
1837 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
1838 if (cfop->flags & CF_ALU) {
1839 if (cf->eg_alu_extended) {
1840 fprintf(stderr, "%04d %08X %08X %s\n", id, bc->bytecode[id],
1841 bc->bytecode[id + 1], "ALU_EXT");
1842 id += 2;
1843 }
1844 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
1845 bc->bytecode[id + 1], cfop->name);
1846 fprintf(stderr, "%d @%d ", cf->ndw / 2, cf->addr);
1847 for (i = 0; i < 4; ++i) {
1848 if (cf->kcache[i].mode) {
1849 int c_start = (cf->kcache[i].addr << 4);
1850 int c_end = c_start + (cf->kcache[i].mode << 4);
1851 fprintf(stderr, "KC%d[CB%d:%d-%d] ",
1852 i, cf->kcache[i].bank, c_start, c_end);
1853 }
1854 }
1855 fprintf(stderr, "\n");
1856 } else if (cfop->flags & CF_FETCH) {
1857 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
1858 bc->bytecode[id + 1], cfop->name);
1859 fprintf(stderr, "%d @%d ", cf->ndw / 4, cf->addr);
1860 fprintf(stderr, "\n");
1861 } else if (cfop->flags & CF_EXP) {
1862 int o = 0;
1863 const char *exp_type[] = {"PIXEL", "POS ", "PARAM"};
1864 o += fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
1865 bc->bytecode[id + 1], cfop->name);
1866 o += print_indent(o, 43);
1867 o += fprintf(stderr, "%s ", exp_type[cf->output.type]);
1868 if (cf->output.burst_count > 1) {
1869 o += fprintf(stderr, "%d-%d ", cf->output.array_base,
1870 cf->output.array_base + cf->output.burst_count - 1);
1871
1872 o += print_indent(o, 55);
1873 o += fprintf(stderr, "R%d-%d.", cf->output.gpr,
1874 cf->output.gpr + cf->output.burst_count - 1);
1875 } else {
1876 o += fprintf(stderr, "%d ", cf->output.array_base);
1877 o += print_indent(o, 55);
1878 o += fprintf(stderr, "R%d.", cf->output.gpr);
1879 }
1880
1881 o += print_swizzle(cf->output.swizzle_x);
1882 o += print_swizzle(cf->output.swizzle_y);
1883 o += print_swizzle(cf->output.swizzle_z);
1884 o += print_swizzle(cf->output.swizzle_w);
1885
1886 print_indent(o, 67);
1887
1888 fprintf(stderr, " ES:%X ", cf->output.elem_size);
1889 if (!cf->output.barrier)
1890 fprintf(stderr, "NO_BARRIER ");
1891 if (cf->output.end_of_program)
1892 fprintf(stderr, "EOP ");
1893 fprintf(stderr, "\n");
1894 } else if (r600_isa_cf(cf->op)->flags & CF_STRM) {
1895 int o = 0;
1896 const char *exp_type[] = {"WRITE", "WRITE_IND", "WRITE_ACK",
1897 "WRITE_IND_ACK"};
1898 o += fprintf(stderr, "%04d %08X %08X %s ", id,
1899 bc->bytecode[id], bc->bytecode[id + 1], cfop->name);
1900 o += print_indent(o, 43);
1901 o += fprintf(stderr, "%s ", exp_type[cf->output.type]);
1902 if (cf->output.burst_count > 1) {
1903 o += fprintf(stderr, "%d-%d ", cf->output.array_base,
1904 cf->output.array_base + cf->output.burst_count - 1);
1905 o += print_indent(o, 55);
1906 o += fprintf(stderr, "R%d-%d.", cf->output.gpr,
1907 cf->output.gpr + cf->output.burst_count - 1);
1908 } else {
1909 o += fprintf(stderr, "%d ", cf->output.array_base);
1910 o += print_indent(o, 55);
1911 o += fprintf(stderr, "R%d.", cf->output.gpr);
1912 }
1913 for (i = 0; i < 4; ++i) {
1914 if (cf->output.comp_mask & (1 << i))
1915 o += print_swizzle(i);
1916 else
1917 o += print_swizzle(7);
1918 }
1919
1920 o += print_indent(o, 67);
1921
1922 fprintf(stderr, " ES:%i ", cf->output.elem_size);
1923 if (cf->output.array_size != 0xFFF)
1924 fprintf(stderr, "AS:%i ", cf->output.array_size);
1925 if (!cf->output.barrier)
1926 fprintf(stderr, "NO_BARRIER ");
1927 if (cf->output.end_of_program)
1928 fprintf(stderr, "EOP ");
1929 fprintf(stderr, "\n");
1930 } else {
1931 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
1932 bc->bytecode[id + 1], cfop->name);
1933 fprintf(stderr, "@%d ", cf->cf_addr);
1934 if (cf->cond)
1935 fprintf(stderr, "CND:%X ", cf->cond);
1936 if (cf->pop_count)
1937 fprintf(stderr, "POP:%X ", cf->pop_count);
1938 fprintf(stderr, "\n");
1939 }
1940 }
1941
1942 id = cf->addr;
1943 nliteral = 0;
1944 last = 1;
1945 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1946 const char *omod_str[] = {"","*2","*4","/2"};
1947 const struct alu_op_info *aop = r600_isa_alu(alu->op);
1948 int o = 0;
1949
1950 r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
1951 o += fprintf(stderr, " %04d %08X %08X ", id, bc->bytecode[id], bc->bytecode[id+1]);
1952 if (last)
1953 o += fprintf(stderr, "%4d ", ++ngr);
1954 else
1955 o += fprintf(stderr, " ");
1956 o += fprintf(stderr, "%c%c %c ", alu->execute_mask ? 'M':' ',
1957 alu->update_pred ? 'P':' ',
1958 alu->pred_sel ? alu->pred_sel==2 ? '0':'1':' ');
1959
1960 o += fprintf(stderr, "%s%s%s ", aop->name,
1961 omod_str[alu->omod], alu->dst.clamp ? "_sat":"");
1962
1963 o += print_indent(o,60);
1964 o += print_dst(alu);
1965 for (i = 0; i < aop->src_count; ++i) {
1966 o += fprintf(stderr, i == 0 ? ", ": ", ");
1967 o += print_src(alu, i);
1968 }
1969
1970 if (alu->bank_swizzle) {
1971 o += print_indent(o,75);
1972 o += fprintf(stderr, " BS:%d", alu->bank_swizzle);
1973 }
1974
1975 fprintf(stderr, "\n");
1976 id += 2;
1977
1978 if (alu->last) {
1979 for (i = 0; i < nliteral; i++, id++) {
1980 float *f = (float*)(bc->bytecode + id);
1981 o = fprintf(stderr, " %04d %08X", id, bc->bytecode[id]);
1982 print_indent(o, 60);
1983 fprintf(stderr, " %f (%d)\n", *f, *(bc->bytecode + id));
1984 }
1985 id += nliteral & 1;
1986 nliteral = 0;
1987 }
1988 last = alu->last;
1989 }
1990
1991 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
1992 int o = 0;
1993 o += fprintf(stderr, " %04d %08X %08X %08X ", id, bc->bytecode[id],
1994 bc->bytecode[id + 1], bc->bytecode[id + 2]);
1995
1996 o += fprintf(stderr, "%s ", r600_isa_fetch(tex->op)->name);
1997
1998 o += print_indent(o, 50);
1999
2000 o += fprintf(stderr, "R%d.", tex->dst_gpr);
2001 o += print_swizzle(tex->dst_sel_x);
2002 o += print_swizzle(tex->dst_sel_y);
2003 o += print_swizzle(tex->dst_sel_z);
2004 o += print_swizzle(tex->dst_sel_w);
2005
2006 o += fprintf(stderr, ", R%d.", tex->src_gpr);
2007 o += print_swizzle(tex->src_sel_x);
2008 o += print_swizzle(tex->src_sel_y);
2009 o += print_swizzle(tex->src_sel_z);
2010 o += print_swizzle(tex->src_sel_w);
2011
2012 o += fprintf(stderr, ", RID:%d", tex->resource_id);
2013 o += fprintf(stderr, ", SID:%d ", tex->sampler_id);
2014
2015 if (tex->lod_bias)
2016 fprintf(stderr, "LB:%d ", tex->lod_bias);
2017
2018 fprintf(stderr, "CT:%c%c%c%c ",
2019 tex->coord_type_x ? 'N' : 'U',
2020 tex->coord_type_y ? 'N' : 'U',
2021 tex->coord_type_z ? 'N' : 'U',
2022 tex->coord_type_w ? 'N' : 'U');
2023
2024 if (tex->offset_x)
2025 fprintf(stderr, "OX:%d ", tex->offset_x);
2026 if (tex->offset_y)
2027 fprintf(stderr, "OY:%d ", tex->offset_y);
2028 if (tex->offset_z)
2029 fprintf(stderr, "OZ:%d ", tex->offset_z);
2030
2031 id += 4;
2032 fprintf(stderr, "\n");
2033 }
2034
2035 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2036 int o = 0;
2037 const char * fetch_type[] = {"VERTEX", "INSTANCE", ""};
2038 o += fprintf(stderr, " %04d %08X %08X %08X ", id, bc->bytecode[id],
2039 bc->bytecode[id + 1], bc->bytecode[id + 2]);
2040
2041 o += fprintf(stderr, "%s ", r600_isa_fetch(vtx->op)->name);
2042
2043 o += print_indent(o, 50);
2044
2045 o += fprintf(stderr, "R%d.", vtx->dst_gpr);
2046 o += print_swizzle(vtx->dst_sel_x);
2047 o += print_swizzle(vtx->dst_sel_y);
2048 o += print_swizzle(vtx->dst_sel_z);
2049 o += print_swizzle(vtx->dst_sel_w);
2050
2051 o += fprintf(stderr, ", R%d.", vtx->src_gpr);
2052 o += print_swizzle(vtx->src_sel_x);
2053
2054 if (vtx->offset)
2055 fprintf(stderr, " +%db", vtx->offset);
2056
2057 o += print_indent(o, 55);
2058
2059 fprintf(stderr, ", RID:%d ", vtx->buffer_id);
2060
2061 fprintf(stderr, "%s ", fetch_type[vtx->fetch_type]);
2062
2063 if (bc->chip_class < CAYMAN && vtx->mega_fetch_count)
2064 fprintf(stderr, "MFC:%d ", vtx->mega_fetch_count);
2065
2066 fprintf(stderr, "UCF:%d ", vtx->use_const_fields);
2067 fprintf(stderr, "FMT(DTA:%d ", vtx->data_format);
2068 fprintf(stderr, "NUM:%d ", vtx->num_format_all);
2069 fprintf(stderr, "COMP:%d ", vtx->format_comp_all);
2070 fprintf(stderr, "MODE:%d)\n", vtx->srf_mode_all);
2071
2072 id += 4;
2073 }
2074 }
2075
2076 fprintf(stderr, "--------------------------------------\n");
2077 }
2078
2079 void r600_vertex_data_type(enum pipe_format pformat,
2080 unsigned *format,
2081 unsigned *num_format, unsigned *format_comp, unsigned *endian)
2082 {
2083 const struct util_format_description *desc;
2084 unsigned i;
2085
2086 *format = 0;
2087 *num_format = 0;
2088 *format_comp = 0;
2089 *endian = ENDIAN_NONE;
2090
2091 desc = util_format_description(pformat);
2092 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
2093 goto out_unknown;
2094 }
2095
2096 /* Find the first non-VOID channel. */
2097 for (i = 0; i < 4; i++) {
2098 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2099 break;
2100 }
2101 }
2102
2103 *endian = r600_endian_swap(desc->channel[i].size);
2104
2105 switch (desc->channel[i].type) {
2106 /* Half-floats, floats, ints */
2107 case UTIL_FORMAT_TYPE_FLOAT:
2108 switch (desc->channel[i].size) {
2109 case 16:
2110 switch (desc->nr_channels) {
2111 case 1:
2112 *format = FMT_16_FLOAT;
2113 break;
2114 case 2:
2115 *format = FMT_16_16_FLOAT;
2116 break;
2117 case 3:
2118 case 4:
2119 *format = FMT_16_16_16_16_FLOAT;
2120 break;
2121 }
2122 break;
2123 case 32:
2124 switch (desc->nr_channels) {
2125 case 1:
2126 *format = FMT_32_FLOAT;
2127 break;
2128 case 2:
2129 *format = FMT_32_32_FLOAT;
2130 break;
2131 case 3:
2132 *format = FMT_32_32_32_FLOAT;
2133 break;
2134 case 4:
2135 *format = FMT_32_32_32_32_FLOAT;
2136 break;
2137 }
2138 break;
2139 default:
2140 goto out_unknown;
2141 }
2142 break;
2143 /* Unsigned ints */
2144 case UTIL_FORMAT_TYPE_UNSIGNED:
2145 /* Signed ints */
2146 case UTIL_FORMAT_TYPE_SIGNED:
2147 switch (desc->channel[i].size) {
2148 case 8:
2149 switch (desc->nr_channels) {
2150 case 1:
2151 *format = FMT_8;
2152 break;
2153 case 2:
2154 *format = FMT_8_8;
2155 break;
2156 case 3:
2157 case 4:
2158 *format = FMT_8_8_8_8;
2159 break;
2160 }
2161 break;
2162 case 10:
2163 if (desc->nr_channels != 4)
2164 goto out_unknown;
2165
2166 *format = FMT_2_10_10_10;
2167 break;
2168 case 16:
2169 switch (desc->nr_channels) {
2170 case 1:
2171 *format = FMT_16;
2172 break;
2173 case 2:
2174 *format = FMT_16_16;
2175 break;
2176 case 3:
2177 case 4:
2178 *format = FMT_16_16_16_16;
2179 break;
2180 }
2181 break;
2182 case 32:
2183 switch (desc->nr_channels) {
2184 case 1:
2185 *format = FMT_32;
2186 break;
2187 case 2:
2188 *format = FMT_32_32;
2189 break;
2190 case 3:
2191 *format = FMT_32_32_32;
2192 break;
2193 case 4:
2194 *format = FMT_32_32_32_32;
2195 break;
2196 }
2197 break;
2198 default:
2199 goto out_unknown;
2200 }
2201 break;
2202 default:
2203 goto out_unknown;
2204 }
2205
2206 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2207 *format_comp = 1;
2208 }
2209
2210 *num_format = 0;
2211 if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED ||
2212 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2213 if (!desc->channel[i].normalized) {
2214 if (desc->channel[i].pure_integer)
2215 *num_format = 1;
2216 else
2217 *num_format = 2;
2218 }
2219 }
2220 return;
2221 out_unknown:
2222 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
2223 }
2224
2225 void *r600_create_vertex_fetch_shader(struct pipe_context *ctx,
2226 unsigned count,
2227 const struct pipe_vertex_element *elements)
2228 {
2229 struct r600_context *rctx = (struct r600_context *)ctx;
2230 struct r600_bytecode bc;
2231 struct r600_bytecode_vtx vtx;
2232 const struct util_format_description *desc;
2233 unsigned fetch_resource_start = rctx->chip_class >= EVERGREEN ? 0 : 160;
2234 unsigned format, num_format, format_comp, endian;
2235 uint32_t *bytecode;
2236 int i, j, r, fs_size;
2237 struct r600_fetch_shader *shader;
2238
2239 assert(count < 32);
2240
2241 memset(&bc, 0, sizeof(bc));
2242 r600_bytecode_init(&bc, rctx->chip_class, rctx->family,
2243 rctx->screen->msaa_texture_support);
2244
2245 bc.isa = rctx->isa;
2246
2247 for (i = 0; i < count; i++) {
2248 if (elements[i].instance_divisor > 1) {
2249 if (rctx->chip_class == CAYMAN) {
2250 for (j = 0; j < 4; j++) {
2251 struct r600_bytecode_alu alu;
2252 memset(&alu, 0, sizeof(alu));
2253 alu.op = ALU_OP2_MULHI_UINT;
2254 alu.src[0].sel = 0;
2255 alu.src[0].chan = 3;
2256 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2257 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2258 alu.dst.sel = i + 1;
2259 alu.dst.chan = j;
2260 alu.dst.write = j == 3;
2261 alu.last = j == 3;
2262 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2263 r600_bytecode_clear(&bc);
2264 return NULL;
2265 }
2266 }
2267 } else {
2268 struct r600_bytecode_alu alu;
2269 memset(&alu, 0, sizeof(alu));
2270 alu.op = ALU_OP2_MULHI_UINT;
2271 alu.src[0].sel = 0;
2272 alu.src[0].chan = 3;
2273 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2274 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2275 alu.dst.sel = i + 1;
2276 alu.dst.chan = 3;
2277 alu.dst.write = 1;
2278 alu.last = 1;
2279 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2280 r600_bytecode_clear(&bc);
2281 return NULL;
2282 }
2283 }
2284 }
2285 }
2286
2287 for (i = 0; i < count; i++) {
2288 r600_vertex_data_type(elements[i].src_format,
2289 &format, &num_format, &format_comp, &endian);
2290
2291 desc = util_format_description(elements[i].src_format);
2292 if (desc == NULL) {
2293 r600_bytecode_clear(&bc);
2294 R600_ERR("unknown format %d\n", elements[i].src_format);
2295 return NULL;
2296 }
2297
2298 if (elements[i].src_offset > 65535) {
2299 r600_bytecode_clear(&bc);
2300 R600_ERR("too big src_offset: %u\n", elements[i].src_offset);
2301 return NULL;
2302 }
2303
2304 memset(&vtx, 0, sizeof(vtx));
2305 vtx.buffer_id = elements[i].vertex_buffer_index + fetch_resource_start;
2306 vtx.fetch_type = elements[i].instance_divisor ? 1 : 0;
2307 vtx.src_gpr = elements[i].instance_divisor > 1 ? i + 1 : 0;
2308 vtx.src_sel_x = elements[i].instance_divisor ? 3 : 0;
2309 vtx.mega_fetch_count = 0x1F;
2310 vtx.dst_gpr = i + 1;
2311 vtx.dst_sel_x = desc->swizzle[0];
2312 vtx.dst_sel_y = desc->swizzle[1];
2313 vtx.dst_sel_z = desc->swizzle[2];
2314 vtx.dst_sel_w = desc->swizzle[3];
2315 vtx.data_format = format;
2316 vtx.num_format_all = num_format;
2317 vtx.format_comp_all = format_comp;
2318 vtx.srf_mode_all = 1;
2319 vtx.offset = elements[i].src_offset;
2320 vtx.endian = endian;
2321
2322 if ((r = r600_bytecode_add_vtx(&bc, &vtx))) {
2323 r600_bytecode_clear(&bc);
2324 return NULL;
2325 }
2326 }
2327
2328 r600_bytecode_add_cfinst(&bc, CF_OP_RET);
2329
2330 if ((r = r600_bytecode_build(&bc))) {
2331 r600_bytecode_clear(&bc);
2332 return NULL;
2333 }
2334
2335 if (rctx->screen->debug_flags & DBG_FS) {
2336 fprintf(stderr, "--------------------------------------------------------------\n");
2337 fprintf(stderr, "Vertex elements state:\n");
2338 for (i = 0; i < count; i++) {
2339 fprintf(stderr, " ");
2340 util_dump_vertex_element(stderr, elements+i);
2341 fprintf(stderr, "\n");
2342 }
2343
2344 r600_bytecode_disasm(&bc);
2345 fprintf(stderr, "______________________________________________________________\n");
2346 }
2347
2348 fs_size = bc.ndw*4;
2349
2350 /* Allocate the CSO. */
2351 shader = CALLOC_STRUCT(r600_fetch_shader);
2352 if (!shader) {
2353 r600_bytecode_clear(&bc);
2354 return NULL;
2355 }
2356
2357 u_suballocator_alloc(rctx->allocator_fetch_shader, fs_size, &shader->offset,
2358 (struct pipe_resource**)&shader->buffer);
2359 if (!shader->buffer) {
2360 r600_bytecode_clear(&bc);
2361 FREE(shader);
2362 return NULL;
2363 }
2364
2365 bytecode = r600_buffer_mmap_sync_with_rings(rctx, shader->buffer, PIPE_TRANSFER_WRITE | PIPE_TRANSFER_UNSYNCHRONIZED);
2366 bytecode += shader->offset / 4;
2367
2368 if (R600_BIG_ENDIAN) {
2369 for (i = 0; i < fs_size / 4; ++i) {
2370 bytecode[i] = bswap_32(bc.bytecode[i]);
2371 }
2372 } else {
2373 memcpy(bytecode, bc.bytecode, fs_size);
2374 }
2375 rctx->ws->buffer_unmap(shader->buffer->cs_buf);
2376
2377 r600_bytecode_clear(&bc);
2378 return shader;
2379 }
2380
2381 void r600_bytecode_alu_read(struct r600_bytecode *bc,
2382 struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1)
2383 {
2384 /* WORD0 */
2385 alu->src[0].sel = G_SQ_ALU_WORD0_SRC0_SEL(word0);
2386 alu->src[0].rel = G_SQ_ALU_WORD0_SRC0_REL(word0);
2387 alu->src[0].chan = G_SQ_ALU_WORD0_SRC0_CHAN(word0);
2388 alu->src[0].neg = G_SQ_ALU_WORD0_SRC0_NEG(word0);
2389 alu->src[1].sel = G_SQ_ALU_WORD0_SRC1_SEL(word0);
2390 alu->src[1].rel = G_SQ_ALU_WORD0_SRC1_REL(word0);
2391 alu->src[1].chan = G_SQ_ALU_WORD0_SRC1_CHAN(word0);
2392 alu->src[1].neg = G_SQ_ALU_WORD0_SRC1_NEG(word0);
2393 alu->index_mode = G_SQ_ALU_WORD0_INDEX_MODE(word0);
2394 alu->pred_sel = G_SQ_ALU_WORD0_PRED_SEL(word0);
2395 alu->last = G_SQ_ALU_WORD0_LAST(word0);
2396
2397 /* WORD1 */
2398 alu->bank_swizzle = G_SQ_ALU_WORD1_BANK_SWIZZLE(word1);
2399 if (alu->bank_swizzle)
2400 alu->bank_swizzle_force = alu->bank_swizzle;
2401 alu->dst.sel = G_SQ_ALU_WORD1_DST_GPR(word1);
2402 alu->dst.rel = G_SQ_ALU_WORD1_DST_REL(word1);
2403 alu->dst.chan = G_SQ_ALU_WORD1_DST_CHAN(word1);
2404 alu->dst.clamp = G_SQ_ALU_WORD1_CLAMP(word1);
2405 if (G_SQ_ALU_WORD1_ENCODING(word1)) /*ALU_DWORD1_OP3*/
2406 {
2407 alu->is_op3 = 1;
2408 alu->src[2].sel = G_SQ_ALU_WORD1_OP3_SRC2_SEL(word1);
2409 alu->src[2].rel = G_SQ_ALU_WORD1_OP3_SRC2_REL(word1);
2410 alu->src[2].chan = G_SQ_ALU_WORD1_OP3_SRC2_CHAN(word1);
2411 alu->src[2].neg = G_SQ_ALU_WORD1_OP3_SRC2_NEG(word1);
2412 alu->op = r600_isa_alu_by_opcode(bc->isa,
2413 G_SQ_ALU_WORD1_OP3_ALU_INST(word1), /* is_op3 = */ 1);
2414
2415 }
2416 else /*ALU_DWORD1_OP2*/
2417 {
2418 alu->src[0].abs = G_SQ_ALU_WORD1_OP2_SRC0_ABS(word1);
2419 alu->src[1].abs = G_SQ_ALU_WORD1_OP2_SRC1_ABS(word1);
2420 alu->op = r600_isa_alu_by_opcode(bc->isa,
2421 G_SQ_ALU_WORD1_OP2_ALU_INST(word1), /* is_op3 = */ 0);
2422 alu->omod = G_SQ_ALU_WORD1_OP2_OMOD(word1);
2423 alu->dst.write = G_SQ_ALU_WORD1_OP2_WRITE_MASK(word1);
2424 alu->update_pred = G_SQ_ALU_WORD1_OP2_UPDATE_PRED(word1);
2425 alu->execute_mask =
2426 G_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(word1);
2427 }
2428 }
2429
2430 void r600_bytecode_export_read(struct r600_bytecode *bc,
2431 struct r600_bytecode_output *output, uint32_t word0, uint32_t word1)
2432 {
2433 output->array_base = G_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(word0);
2434 output->type = G_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(word0);
2435 output->gpr = G_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(word0);
2436 output->elem_size = G_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(word0);
2437
2438 output->swizzle_x = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(word1);
2439 output->swizzle_y = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(word1);
2440 output->swizzle_z = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(word1);
2441 output->swizzle_w = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(word1);
2442 output->burst_count = G_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(word1);
2443 output->end_of_program = G_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(word1);
2444 output->op = r600_isa_cf_by_opcode(bc->isa,
2445 G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(word1), 0);
2446 output->barrier = G_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(word1);
2447 output->array_size = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(word1);
2448 output->comp_mask = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(word1);
2449 }