2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 #include "r600_opcodes.h"
25 #include "r600_formats.h"
26 #include "r600_shader.h"
30 #include "util/u_dump.h"
31 #include "util/u_memory.h"
32 #include "util/u_math.h"
33 #include "pipe/p_shader_tokens.h"
35 #include "sb/sb_public.h"
37 #define NUM_OF_CYCLES 3
38 #define NUM_OF_COMPONENTS 4
40 static inline bool alu_writes(struct r600_bytecode_alu
*alu
)
42 return alu
->dst
.write
|| alu
->is_op3
;
45 static inline unsigned int r600_bytecode_get_num_operands(
46 struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
48 return r600_isa_alu(alu
->op
)->src_count
;
51 int r700_bytecode_alu_build(struct r600_bytecode
*bc
,
52 struct r600_bytecode_alu
*alu
, unsigned id
);
54 static struct r600_bytecode_cf
*r600_bytecode_cf(void)
56 struct r600_bytecode_cf
*cf
= CALLOC_STRUCT(r600_bytecode_cf
);
60 LIST_INITHEAD(&cf
->list
);
61 LIST_INITHEAD(&cf
->alu
);
62 LIST_INITHEAD(&cf
->vtx
);
63 LIST_INITHEAD(&cf
->tex
);
64 LIST_INITHEAD(&cf
->gds
);
68 static struct r600_bytecode_alu
*r600_bytecode_alu(void)
70 struct r600_bytecode_alu
*alu
= CALLOC_STRUCT(r600_bytecode_alu
);
74 LIST_INITHEAD(&alu
->list
);
78 static struct r600_bytecode_vtx
*r600_bytecode_vtx(void)
80 struct r600_bytecode_vtx
*vtx
= CALLOC_STRUCT(r600_bytecode_vtx
);
84 LIST_INITHEAD(&vtx
->list
);
88 static struct r600_bytecode_tex
*r600_bytecode_tex(void)
90 struct r600_bytecode_tex
*tex
= CALLOC_STRUCT(r600_bytecode_tex
);
94 LIST_INITHEAD(&tex
->list
);
98 static struct r600_bytecode_gds
*r600_bytecode_gds(void)
100 struct r600_bytecode_gds
*gds
= CALLOC_STRUCT(r600_bytecode_gds
);
104 LIST_INITHEAD(&gds
->list
);
108 static unsigned stack_entry_size(enum radeon_family chip
) {
110 * 64: R600/RV670/RV770/Cypress/R740/Barts/Turks/Caicos/
111 * Aruba/Sumo/Sumo2/redwood/juniper
112 * 32: R630/R730/R710/Palm/Cedar
116 * Wavefront Size 16 32 48 64
117 * Columns per Row (R6xx/R7xx/R8xx only) 8 8 4 4
118 * Columns per Row (R9xx+) 8 4 4 4 */
121 /* FIXME: are some chips missing here? */
122 /* wavefront size 16 */
127 /* wavefront size 32 */
136 /* wavefront size 64 */
142 void r600_bytecode_init(struct r600_bytecode
*bc
,
143 enum chip_class chip_class
,
144 enum radeon_family family
,
145 bool has_compressed_msaa_texturing
)
147 static unsigned next_shader_id
= 0;
149 bc
->debug_id
= ++next_shader_id
;
151 if ((chip_class
== R600
) &&
152 (family
!= CHIP_RV670
&& family
!= CHIP_RS780
&& family
!= CHIP_RS880
)) {
153 bc
->ar_handling
= AR_HANDLE_RV6XX
;
154 bc
->r6xx_nop_after_rel_dst
= 1;
156 bc
->ar_handling
= AR_HANDLE_NORMAL
;
157 bc
->r6xx_nop_after_rel_dst
= 0;
160 LIST_INITHEAD(&bc
->cf
);
161 bc
->chip_class
= chip_class
;
163 bc
->has_compressed_msaa_texturing
= has_compressed_msaa_texturing
;
164 bc
->stack
.entry_size
= stack_entry_size(family
);
167 int r600_bytecode_add_cf(struct r600_bytecode
*bc
)
169 struct r600_bytecode_cf
*cf
= r600_bytecode_cf();
173 LIST_ADDTAIL(&cf
->list
, &bc
->cf
);
175 cf
->id
= bc
->cf_last
->id
+ 2;
176 if (bc
->cf_last
->eg_alu_extended
) {
177 /* take into account extended alu size */
185 bc
->force_add_cf
= 0;
190 int r600_bytecode_add_output(struct r600_bytecode
*bc
,
191 const struct r600_bytecode_output
*output
)
195 if (output
->gpr
>= bc
->ngpr
)
196 bc
->ngpr
= output
->gpr
+ 1;
198 if (bc
->cf_last
&& (bc
->cf_last
->op
== output
->op
||
199 (bc
->cf_last
->op
== CF_OP_EXPORT
&&
200 output
->op
== CF_OP_EXPORT_DONE
)) &&
201 output
->type
== bc
->cf_last
->output
.type
&&
202 output
->elem_size
== bc
->cf_last
->output
.elem_size
&&
203 output
->swizzle_x
== bc
->cf_last
->output
.swizzle_x
&&
204 output
->swizzle_y
== bc
->cf_last
->output
.swizzle_y
&&
205 output
->swizzle_z
== bc
->cf_last
->output
.swizzle_z
&&
206 output
->swizzle_w
== bc
->cf_last
->output
.swizzle_w
&&
207 output
->comp_mask
== bc
->cf_last
->output
.comp_mask
&&
208 (output
->burst_count
+ bc
->cf_last
->output
.burst_count
) <= 16) {
210 if ((output
->gpr
+ output
->burst_count
) == bc
->cf_last
->output
.gpr
&&
211 (output
->array_base
+ output
->burst_count
) == bc
->cf_last
->output
.array_base
) {
213 bc
->cf_last
->op
= bc
->cf_last
->output
.op
= output
->op
;
214 bc
->cf_last
->output
.gpr
= output
->gpr
;
215 bc
->cf_last
->output
.array_base
= output
->array_base
;
216 bc
->cf_last
->output
.burst_count
+= output
->burst_count
;
219 } else if (output
->gpr
== (bc
->cf_last
->output
.gpr
+ bc
->cf_last
->output
.burst_count
) &&
220 output
->array_base
== (bc
->cf_last
->output
.array_base
+ bc
->cf_last
->output
.burst_count
)) {
222 bc
->cf_last
->op
= bc
->cf_last
->output
.op
= output
->op
;
223 bc
->cf_last
->output
.burst_count
+= output
->burst_count
;
228 r
= r600_bytecode_add_cf(bc
);
231 bc
->cf_last
->op
= output
->op
;
232 memcpy(&bc
->cf_last
->output
, output
, sizeof(struct r600_bytecode_output
));
233 bc
->cf_last
->barrier
= 1;
237 /* alu instructions that can ony exits once per group */
238 static int is_alu_once_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
240 return r600_isa_alu(alu
->op
)->flags
& (AF_KILL
| AF_PRED
) || alu
->is_lds_idx_op
|| alu
->op
== ALU_OP0_GROUP_BARRIER
;
243 static int is_alu_reduction_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
245 return (r600_isa_alu(alu
->op
)->flags
& AF_REPL
) &&
246 (r600_isa_alu_slots(bc
->isa
->hw_class
, alu
->op
) == AF_4V
);
249 static int is_alu_mova_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
251 return r600_isa_alu(alu
->op
)->flags
& AF_MOVA
;
254 static int alu_uses_rel(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
256 unsigned num_src
= r600_bytecode_get_num_operands(bc
, alu
);
263 for (src
= 0; src
< num_src
; ++src
) {
264 if (alu
->src
[src
].rel
) {
271 static int is_lds_read(int sel
)
273 return sel
== EG_V_SQ_ALU_SRC_LDS_OQ_A_POP
|| sel
== EG_V_SQ_ALU_SRC_LDS_OQ_B_POP
;
276 static int alu_uses_lds(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
278 unsigned num_src
= r600_bytecode_get_num_operands(bc
, alu
);
281 for (src
= 0; src
< num_src
; ++src
) {
282 if (is_lds_read(alu
->src
[src
].sel
)) {
289 static int is_alu_64bit_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
291 const struct alu_op_info
*op
= r600_isa_alu(alu
->op
);
292 return (op
->flags
& AF_64
);
295 static int is_alu_vec_unit_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
297 unsigned slots
= r600_isa_alu_slots(bc
->isa
->hw_class
, alu
->op
);
298 return !(slots
& AF_S
);
301 static int is_alu_trans_unit_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
303 unsigned slots
= r600_isa_alu_slots(bc
->isa
->hw_class
, alu
->op
);
304 return !(slots
& AF_V
);
307 /* alu instructions that can execute on any unit */
308 static int is_alu_any_unit_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
310 unsigned slots
= r600_isa_alu_slots(bc
->isa
->hw_class
, alu
->op
);
311 return slots
== AF_VS
;
314 static int is_nop_inst(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
)
316 return alu
->op
== ALU_OP0_NOP
;
319 static int assign_alu_units(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu_first
,
320 struct r600_bytecode_alu
*assignment
[5])
322 struct r600_bytecode_alu
*alu
;
323 unsigned i
, chan
, trans
;
324 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
326 for (i
= 0; i
< max_slots
; i
++)
327 assignment
[i
] = NULL
;
329 for (alu
= alu_first
; alu
; alu
= LIST_ENTRY(struct r600_bytecode_alu
, alu
->list
.next
, list
)) {
330 chan
= alu
->dst
.chan
;
333 else if (is_alu_trans_unit_inst(bc
, alu
))
335 else if (is_alu_vec_unit_inst(bc
, alu
))
337 else if (assignment
[chan
])
338 trans
= 1; /* Assume ALU_INST_PREFER_VECTOR. */
344 assert(0); /* ALU.Trans has already been allocated. */
349 if (assignment
[chan
]) {
350 assert(0); /* ALU.chan has already been allocated. */
353 assignment
[chan
] = alu
;
362 struct alu_bank_swizzle
{
363 int hw_gpr
[NUM_OF_CYCLES
][NUM_OF_COMPONENTS
];
364 int hw_cfile_addr
[4];
365 int hw_cfile_elem
[4];
368 static const unsigned cycle_for_bank_swizzle_vec
[][3] = {
369 [SQ_ALU_VEC_012
] = { 0, 1, 2 },
370 [SQ_ALU_VEC_021
] = { 0, 2, 1 },
371 [SQ_ALU_VEC_120
] = { 1, 2, 0 },
372 [SQ_ALU_VEC_102
] = { 1, 0, 2 },
373 [SQ_ALU_VEC_201
] = { 2, 0, 1 },
374 [SQ_ALU_VEC_210
] = { 2, 1, 0 }
377 static const unsigned cycle_for_bank_swizzle_scl
[][3] = {
378 [SQ_ALU_SCL_210
] = { 2, 1, 0 },
379 [SQ_ALU_SCL_122
] = { 1, 2, 2 },
380 [SQ_ALU_SCL_212
] = { 2, 1, 2 },
381 [SQ_ALU_SCL_221
] = { 2, 2, 1 }
384 static void init_bank_swizzle(struct alu_bank_swizzle
*bs
)
386 int i
, cycle
, component
;
388 for (cycle
= 0; cycle
< NUM_OF_CYCLES
; cycle
++)
389 for (component
= 0; component
< NUM_OF_COMPONENTS
; component
++)
390 bs
->hw_gpr
[cycle
][component
] = -1;
391 for (i
= 0; i
< 4; i
++)
392 bs
->hw_cfile_addr
[i
] = -1;
393 for (i
= 0; i
< 4; i
++)
394 bs
->hw_cfile_elem
[i
] = -1;
397 static int reserve_gpr(struct alu_bank_swizzle
*bs
, unsigned sel
, unsigned chan
, unsigned cycle
)
399 if (bs
->hw_gpr
[cycle
][chan
] == -1)
400 bs
->hw_gpr
[cycle
][chan
] = sel
;
401 else if (bs
->hw_gpr
[cycle
][chan
] != (int)sel
) {
402 /* Another scalar operation has already used the GPR read port for the channel. */
408 static int reserve_cfile(struct r600_bytecode
*bc
, struct alu_bank_swizzle
*bs
, unsigned sel
, unsigned chan
)
410 int res
, num_res
= 4;
411 if (bc
->chip_class
>= R700
) {
415 for (res
= 0; res
< num_res
; ++res
) {
416 if (bs
->hw_cfile_addr
[res
] == -1) {
417 bs
->hw_cfile_addr
[res
] = sel
;
418 bs
->hw_cfile_elem
[res
] = chan
;
420 } else if (bs
->hw_cfile_addr
[res
] == sel
&&
421 bs
->hw_cfile_elem
[res
] == chan
)
422 return 0; /* Read for this scalar element already reserved, nothing to do here. */
424 /* All cfile read ports are used, cannot reference vector element. */
428 static int is_gpr(unsigned sel
)
433 /* CB constants start at 512, and get translated to a kcache index when ALU
434 * clauses are constructed. Note that we handle kcache constants the same way
435 * as (the now gone) cfile constants, is that really required? */
436 static int is_cfile(unsigned sel
)
438 return (sel
> 255 && sel
< 512) ||
439 (sel
> 511 && sel
< 4607) || /* Kcache before translation. */
440 (sel
> 127 && sel
< 192); /* Kcache after translation. */
443 static int is_const(int sel
)
445 return is_cfile(sel
) ||
446 (sel
>= V_SQ_ALU_SRC_0
&&
447 sel
<= V_SQ_ALU_SRC_LITERAL
);
450 static int check_vector(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
,
451 struct alu_bank_swizzle
*bs
, int bank_swizzle
)
453 int r
, src
, num_src
, sel
, elem
, cycle
;
455 num_src
= r600_bytecode_get_num_operands(bc
, alu
);
456 for (src
= 0; src
< num_src
; src
++) {
457 sel
= alu
->src
[src
].sel
;
458 elem
= alu
->src
[src
].chan
;
460 cycle
= cycle_for_bank_swizzle_vec
[bank_swizzle
][src
];
461 if (src
== 1 && sel
== alu
->src
[0].sel
&& elem
== alu
->src
[0].chan
)
462 /* Nothing to do; special-case optimization,
463 * second source uses first source’s reservation. */
466 r
= reserve_gpr(bs
, sel
, elem
, cycle
);
470 } else if (is_cfile(sel
)) {
471 r
= reserve_cfile(bc
, bs
, (alu
->src
[src
].kc_bank
<<16) + sel
, elem
);
475 /* No restrictions on PV, PS, literal or special constants. */
480 static int check_scalar(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
,
481 struct alu_bank_swizzle
*bs
, int bank_swizzle
)
483 int r
, src
, num_src
, const_count
, sel
, elem
, cycle
;
485 num_src
= r600_bytecode_get_num_operands(bc
, alu
);
486 for (const_count
= 0, src
= 0; src
< num_src
; ++src
) {
487 sel
= alu
->src
[src
].sel
;
488 elem
= alu
->src
[src
].chan
;
489 if (is_const(sel
)) { /* Any constant, including literal and inline constants. */
490 if (const_count
>= 2)
491 /* More than two references to a constant in
492 * transcendental operation. */
498 r
= reserve_cfile(bc
, bs
, (alu
->src
[src
].kc_bank
<<16) + sel
, elem
);
503 for (src
= 0; src
< num_src
; ++src
) {
504 sel
= alu
->src
[src
].sel
;
505 elem
= alu
->src
[src
].chan
;
507 cycle
= cycle_for_bank_swizzle_scl
[bank_swizzle
][src
];
508 if (cycle
< const_count
)
509 /* Cycle for GPR load conflicts with
510 * constant load in transcendental operation. */
512 r
= reserve_gpr(bs
, sel
, elem
, cycle
);
516 /* PV PS restrictions */
517 if (const_count
&& (sel
== 254 || sel
== 255)) {
518 cycle
= cycle_for_bank_swizzle_scl
[bank_swizzle
][src
];
519 if (cycle
< const_count
)
526 static int check_and_set_bank_swizzle(struct r600_bytecode
*bc
,
527 struct r600_bytecode_alu
*slots
[5])
529 struct alu_bank_swizzle bs
;
531 int i
, r
= 0, forced
= 1;
532 boolean scalar_only
= bc
->chip_class
== CAYMAN
? false : true;
533 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
535 for (i
= 0; i
< max_slots
; i
++) {
537 if (slots
[i
]->bank_swizzle_force
) {
538 slots
[i
]->bank_swizzle
= slots
[i
]->bank_swizzle_force
;
544 if (i
< 4 && slots
[i
])
550 /* Just check every possible combination of bank swizzle.
551 * Not very efficent, but works on the first try in most of the cases. */
552 for (i
= 0; i
< 4; i
++)
553 if (!slots
[i
] || !slots
[i
]->bank_swizzle_force
)
554 bank_swizzle
[i
] = SQ_ALU_VEC_012
;
556 bank_swizzle
[i
] = slots
[i
]->bank_swizzle
;
558 bank_swizzle
[4] = SQ_ALU_SCL_210
;
559 while(bank_swizzle
[4] <= SQ_ALU_SCL_221
) {
561 init_bank_swizzle(&bs
);
562 if (scalar_only
== false) {
563 for (i
= 0; i
< 4; i
++) {
565 r
= check_vector(bc
, slots
[i
], &bs
, bank_swizzle
[i
]);
573 if (!r
&& max_slots
== 5 && slots
[4]) {
574 r
= check_scalar(bc
, slots
[4], &bs
, bank_swizzle
[4]);
577 for (i
= 0; i
< max_slots
; i
++) {
579 slots
[i
]->bank_swizzle
= bank_swizzle
[i
];
587 for (i
= 0; i
< max_slots
; i
++) {
588 if (!slots
[i
] || !slots
[i
]->bank_swizzle_force
) {
590 if (bank_swizzle
[i
] <= SQ_ALU_VEC_210
)
592 else if (i
< max_slots
- 1)
593 bank_swizzle
[i
] = SQ_ALU_VEC_012
;
601 /* Couldn't find a working swizzle. */
605 static int replace_gpr_with_pv_ps(struct r600_bytecode
*bc
,
606 struct r600_bytecode_alu
*slots
[5], struct r600_bytecode_alu
*alu_prev
)
608 struct r600_bytecode_alu
*prev
[5];
610 int i
, j
, r
, src
, num_src
;
611 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
613 r
= assign_alu_units(bc
, alu_prev
, prev
);
617 for (i
= 0; i
< max_slots
; ++i
) {
618 if (prev
[i
] && alu_writes(prev
[i
]) && !prev
[i
]->dst
.rel
) {
620 if (is_alu_64bit_inst(bc
, prev
[i
])) {
625 gpr
[i
] = prev
[i
]->dst
.sel
;
626 /* cube writes more than PV.X */
627 if (is_alu_reduction_inst(bc
, prev
[i
]))
630 chan
[i
] = prev
[i
]->dst
.chan
;
635 for (i
= 0; i
< max_slots
; ++i
) {
636 struct r600_bytecode_alu
*alu
= slots
[i
];
640 if (is_alu_64bit_inst(bc
, alu
))
642 num_src
= r600_bytecode_get_num_operands(bc
, alu
);
643 for (src
= 0; src
< num_src
; ++src
) {
644 if (!is_gpr(alu
->src
[src
].sel
) || alu
->src
[src
].rel
)
647 if (bc
->chip_class
< CAYMAN
) {
648 if (alu
->src
[src
].sel
== gpr
[4] &&
649 alu
->src
[src
].chan
== chan
[4] &&
650 alu_prev
->pred_sel
== alu
->pred_sel
) {
651 alu
->src
[src
].sel
= V_SQ_ALU_SRC_PS
;
652 alu
->src
[src
].chan
= 0;
657 for (j
= 0; j
< 4; ++j
) {
658 if (alu
->src
[src
].sel
== gpr
[j
] &&
659 alu
->src
[src
].chan
== j
&&
660 alu_prev
->pred_sel
== alu
->pred_sel
) {
661 alu
->src
[src
].sel
= V_SQ_ALU_SRC_PV
;
662 alu
->src
[src
].chan
= chan
[j
];
672 void r600_bytecode_special_constants(uint32_t value
, unsigned *sel
, unsigned *neg
, unsigned abs
)
676 *sel
= V_SQ_ALU_SRC_0
;
679 *sel
= V_SQ_ALU_SRC_1_INT
;
682 *sel
= V_SQ_ALU_SRC_M_1_INT
;
684 case 0x3F800000: /* 1.0f */
685 *sel
= V_SQ_ALU_SRC_1
;
687 case 0x3F000000: /* 0.5f */
688 *sel
= V_SQ_ALU_SRC_0_5
;
690 case 0xBF800000: /* -1.0f */
691 *sel
= V_SQ_ALU_SRC_1
;
694 case 0xBF000000: /* -0.5f */
695 *sel
= V_SQ_ALU_SRC_0_5
;
699 *sel
= V_SQ_ALU_SRC_LITERAL
;
704 /* compute how many literal are needed */
705 static int r600_bytecode_alu_nliterals(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
,
706 uint32_t literal
[4], unsigned *nliteral
)
708 unsigned num_src
= r600_bytecode_get_num_operands(bc
, alu
);
711 for (i
= 0; i
< num_src
; ++i
) {
712 if (alu
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
713 uint32_t value
= alu
->src
[i
].value
;
715 for (j
= 0; j
< *nliteral
; ++j
) {
716 if (literal
[j
] == value
) {
724 literal
[(*nliteral
)++] = value
;
731 static void r600_bytecode_alu_adjust_literals(struct r600_bytecode
*bc
,
732 struct r600_bytecode_alu
*alu
,
733 uint32_t literal
[4], unsigned nliteral
)
735 unsigned num_src
= r600_bytecode_get_num_operands(bc
, alu
);
738 for (i
= 0; i
< num_src
; ++i
) {
739 if (alu
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
740 uint32_t value
= alu
->src
[i
].value
;
741 for (j
= 0; j
< nliteral
; ++j
) {
742 if (literal
[j
] == value
) {
743 alu
->src
[i
].chan
= j
;
751 static int merge_inst_groups(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*slots
[5],
752 struct r600_bytecode_alu
*alu_prev
)
754 struct r600_bytecode_alu
*prev
[5];
755 struct r600_bytecode_alu
*result
[5] = { NULL
};
757 uint32_t literal
[4], prev_literal
[4];
758 unsigned nliteral
= 0, prev_nliteral
= 0;
760 int i
, j
, r
, src
, num_src
;
761 int num_once_inst
= 0;
762 int have_mova
= 0, have_rel
= 0;
763 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
765 r
= assign_alu_units(bc
, alu_prev
, prev
);
769 for (i
= 0; i
< max_slots
; ++i
) {
771 if (prev
[i
]->pred_sel
)
773 if (is_alu_once_inst(bc
, prev
[i
]))
777 if (slots
[i
]->pred_sel
)
779 if (is_alu_once_inst(bc
, slots
[i
]))
784 for (i
= 0; i
< max_slots
; ++i
) {
785 struct r600_bytecode_alu
*alu
;
787 if (num_once_inst
> 0)
790 /* check number of literals */
792 if (r600_bytecode_alu_nliterals(bc
, prev
[i
], literal
, &nliteral
))
794 if (r600_bytecode_alu_nliterals(bc
, prev
[i
], prev_literal
, &prev_nliteral
))
796 if (is_alu_mova_inst(bc
, prev
[i
])) {
802 if (alu_uses_rel(bc
, prev
[i
])) {
808 if (alu_uses_lds(bc
, prev
[i
]))
811 num_once_inst
+= is_alu_once_inst(bc
, prev
[i
]);
813 if (slots
[i
] && r600_bytecode_alu_nliterals(bc
, slots
[i
], literal
, &nliteral
))
816 /* Let's check used slots. */
817 if (prev
[i
] && !slots
[i
]) {
820 } else if (prev
[i
] && slots
[i
]) {
821 if (max_slots
== 5 && result
[4] == NULL
&& prev
[4] == NULL
&& slots
[4] == NULL
) {
822 /* Trans unit is still free try to use it. */
823 if (is_alu_any_unit_inst(bc
, slots
[i
]) && !alu_uses_lds(bc
, slots
[i
])) {
825 result
[4] = slots
[i
];
826 } else if (is_alu_any_unit_inst(bc
, prev
[i
])) {
827 if (slots
[i
]->dst
.sel
== prev
[i
]->dst
.sel
&&
828 alu_writes(slots
[i
]) &&
832 result
[i
] = slots
[i
];
838 } else if(!slots
[i
]) {
841 if (max_slots
== 5 && slots
[i
] && prev
[4] &&
842 slots
[i
]->dst
.sel
== prev
[4]->dst
.sel
&&
843 slots
[i
]->dst
.chan
== prev
[4]->dst
.chan
&&
844 alu_writes(slots
[i
]) &&
848 result
[i
] = slots
[i
];
852 num_once_inst
+= is_alu_once_inst(bc
, alu
);
854 /* don't reschedule NOPs */
855 if (is_nop_inst(bc
, alu
))
858 if (is_alu_mova_inst(bc
, alu
)) {
865 if (alu_uses_rel(bc
, alu
)) {
872 if (alu
->op
== ALU_OP0_SET_CF_IDX0
||
873 alu
->op
== ALU_OP0_SET_CF_IDX1
)
874 return 0; /* data hazard with MOVA */
876 /* Let's check source gprs */
877 num_src
= r600_bytecode_get_num_operands(bc
, alu
);
878 for (src
= 0; src
< num_src
; ++src
) {
880 /* Constants don't matter. */
881 if (!is_gpr(alu
->src
[src
].sel
))
884 for (j
= 0; j
< max_slots
; ++j
) {
885 if (!prev
[j
] || !alu_writes(prev
[j
]))
888 /* If it's relative then we can't determin which gpr is really used. */
889 if (prev
[j
]->dst
.chan
== alu
->src
[src
].chan
&&
890 (prev
[j
]->dst
.sel
== alu
->src
[src
].sel
||
891 prev
[j
]->dst
.rel
|| alu
->src
[src
].rel
))
897 /* more than one PRED_ or KILL_ ? */
898 if (num_once_inst
> 1)
901 /* check if the result can still be swizzlet */
902 r
= check_and_set_bank_swizzle(bc
, result
);
906 /* looks like everything worked out right, apply the changes */
908 /* undo adding previus literals */
909 bc
->cf_last
->ndw
-= align(prev_nliteral
, 2);
911 /* sort instructions */
912 for (i
= 0; i
< max_slots
; ++i
) {
913 slots
[i
] = result
[i
];
915 LIST_DEL(&result
[i
]->list
);
917 LIST_ADDTAIL(&result
[i
]->list
, &bc
->cf_last
->alu
);
921 /* determine new last instruction */
922 LIST_ENTRY(struct r600_bytecode_alu
, bc
->cf_last
->alu
.prev
, list
)->last
= 1;
924 /* determine new first instruction */
925 for (i
= 0; i
< max_slots
; ++i
) {
927 bc
->cf_last
->curr_bs_head
= result
[i
];
932 bc
->cf_last
->prev_bs_head
= bc
->cf_last
->prev2_bs_head
;
933 bc
->cf_last
->prev2_bs_head
= NULL
;
938 /* we'll keep kcache sets sorted by bank & addr */
939 static int r600_bytecode_alloc_kcache_line(struct r600_bytecode
*bc
,
940 struct r600_bytecode_kcache
*kcache
,
941 unsigned bank
, unsigned line
, unsigned index_mode
)
943 int i
, kcache_banks
= bc
->chip_class
>= EVERGREEN
? 4 : 2;
945 for (i
= 0; i
< kcache_banks
; i
++) {
946 if (kcache
[i
].mode
) {
949 if (kcache
[i
].bank
< bank
)
952 if ((kcache
[i
].bank
== bank
&& kcache
[i
].addr
> line
+1) ||
953 kcache
[i
].bank
> bank
) {
954 /* try to insert new line */
955 if (kcache
[kcache_banks
-1].mode
) {
956 /* all sets are in use */
960 memmove(&kcache
[i
+1],&kcache
[i
], (kcache_banks
-i
-1)*sizeof(struct r600_bytecode_kcache
));
961 kcache
[i
].mode
= V_SQ_CF_KCACHE_LOCK_1
;
962 kcache
[i
].bank
= bank
;
963 kcache
[i
].addr
= line
;
964 kcache
[i
].index_mode
= index_mode
;
968 d
= line
- kcache
[i
].addr
;
972 if (kcache
[i
].mode
== V_SQ_CF_KCACHE_LOCK_2
) {
973 /* we are prepending the line to the current set,
974 * discarding the existing second line,
975 * so we'll have to insert line+2 after it */
978 } else if (kcache
[i
].mode
== V_SQ_CF_KCACHE_LOCK_1
) {
979 kcache
[i
].mode
= V_SQ_CF_KCACHE_LOCK_2
;
982 /* V_SQ_CF_KCACHE_LOCK_LOOP_INDEX is not supported */
986 kcache
[i
].mode
= V_SQ_CF_KCACHE_LOCK_2
;
990 } else { /* free kcache set - use it */
991 kcache
[i
].mode
= V_SQ_CF_KCACHE_LOCK_1
;
992 kcache
[i
].bank
= bank
;
993 kcache
[i
].addr
= line
;
994 kcache
[i
].index_mode
= index_mode
;
1001 static int r600_bytecode_alloc_inst_kcache_lines(struct r600_bytecode
*bc
,
1002 struct r600_bytecode_kcache
*kcache
,
1003 struct r600_bytecode_alu
*alu
)
1007 for (i
= 0; i
< 3; i
++) {
1008 unsigned bank
, line
, sel
= alu
->src
[i
].sel
, index_mode
;
1013 bank
= alu
->src
[i
].kc_bank
;
1014 line
= (sel
-512)>>4;
1015 index_mode
= alu
->src
[i
].kc_rel
? 1 : 0; // V_SQ_CF_INDEX_0 / V_SQ_CF_INDEX_NONE
1017 if ((r
= r600_bytecode_alloc_kcache_line(bc
, kcache
, bank
, line
, index_mode
)))
1023 static int r600_bytecode_assign_kcache_banks(struct r600_bytecode
*bc
,
1024 struct r600_bytecode_alu
*alu
,
1025 struct r600_bytecode_kcache
* kcache
)
1029 /* Alter the src operands to refer to the kcache. */
1030 for (i
= 0; i
< 3; ++i
) {
1031 static const unsigned int base
[] = {128, 160, 256, 288};
1032 unsigned int line
, sel
= alu
->src
[i
].sel
, found
= 0;
1040 for (j
= 0; j
< 4 && !found
; ++j
) {
1041 switch (kcache
[j
].mode
) {
1042 case V_SQ_CF_KCACHE_NOP
:
1043 case V_SQ_CF_KCACHE_LOCK_LOOP_INDEX
:
1044 R600_ERR("unexpected kcache line mode\n");
1047 if (kcache
[j
].bank
== alu
->src
[i
].kc_bank
&&
1048 kcache
[j
].addr
<= line
&&
1049 line
< kcache
[j
].addr
+ kcache
[j
].mode
) {
1050 alu
->src
[i
].sel
= sel
- (kcache
[j
].addr
<<4);
1051 alu
->src
[i
].sel
+= base
[j
];
1060 static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode
*bc
,
1061 struct r600_bytecode_alu
*alu
,
1064 struct r600_bytecode_kcache kcache_sets
[4];
1065 struct r600_bytecode_kcache
*kcache
= kcache_sets
;
1068 memcpy(kcache
, bc
->cf_last
->kcache
, 4 * sizeof(struct r600_bytecode_kcache
));
1070 if ((r
= r600_bytecode_alloc_inst_kcache_lines(bc
, kcache
, alu
))) {
1071 /* can't alloc, need to start new clause */
1072 if ((r
= r600_bytecode_add_cf(bc
))) {
1075 bc
->cf_last
->op
= type
;
1077 /* retry with the new clause */
1078 kcache
= bc
->cf_last
->kcache
;
1079 if ((r
= r600_bytecode_alloc_inst_kcache_lines(bc
, kcache
, alu
))) {
1080 /* can't alloc again- should never happen */
1084 /* update kcache sets */
1085 memcpy(bc
->cf_last
->kcache
, kcache
, 4 * sizeof(struct r600_bytecode_kcache
));
1088 /* if we actually used more than 2 kcache sets, or have relative indexing - use ALU_EXTENDED on eg+ */
1089 if (kcache
[2].mode
!= V_SQ_CF_KCACHE_NOP
||
1090 kcache
[0].index_mode
|| kcache
[1].index_mode
|| kcache
[2].index_mode
|| kcache
[3].index_mode
) {
1091 if (bc
->chip_class
< EVERGREEN
)
1093 bc
->cf_last
->eg_alu_extended
= 1;
1099 static int insert_nop_r6xx(struct r600_bytecode
*bc
)
1101 struct r600_bytecode_alu alu
;
1104 for (i
= 0; i
< 4; i
++) {
1105 memset(&alu
, 0, sizeof(alu
));
1106 alu
.op
= ALU_OP0_NOP
;
1107 alu
.src
[0].chan
= i
;
1109 alu
.last
= (i
== 3);
1110 r
= r600_bytecode_add_alu(bc
, &alu
);
1117 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1118 static int load_ar_r6xx(struct r600_bytecode
*bc
)
1120 struct r600_bytecode_alu alu
;
1126 /* hack to avoid making MOVA the last instruction in the clause */
1127 if ((bc
->cf_last
->ndw
>>1) >= 110)
1128 bc
->force_add_cf
= 1;
1130 memset(&alu
, 0, sizeof(alu
));
1131 alu
.op
= ALU_OP1_MOVA_GPR_INT
;
1132 alu
.src
[0].sel
= bc
->ar_reg
;
1133 alu
.src
[0].chan
= bc
->ar_chan
;
1135 alu
.index_mode
= INDEX_MODE_LOOP
;
1136 r
= r600_bytecode_add_alu(bc
, &alu
);
1140 /* no requirement to set uses waterfall on MOVA_GPR_INT */
1145 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1146 static int load_ar(struct r600_bytecode
*bc
)
1148 struct r600_bytecode_alu alu
;
1151 if (bc
->ar_handling
)
1152 return load_ar_r6xx(bc
);
1157 /* hack to avoid making MOVA the last instruction in the clause */
1158 if ((bc
->cf_last
->ndw
>>1) >= 110)
1159 bc
->force_add_cf
= 1;
1161 memset(&alu
, 0, sizeof(alu
));
1162 alu
.op
= ALU_OP1_MOVA_INT
;
1163 alu
.src
[0].sel
= bc
->ar_reg
;
1164 alu
.src
[0].chan
= bc
->ar_chan
;
1166 r
= r600_bytecode_add_alu(bc
, &alu
);
1170 bc
->cf_last
->r6xx_uses_waterfall
= 1;
1175 int r600_bytecode_add_alu_type(struct r600_bytecode
*bc
,
1176 const struct r600_bytecode_alu
*alu
, unsigned type
)
1178 struct r600_bytecode_alu
*nalu
= r600_bytecode_alu();
1179 struct r600_bytecode_alu
*lalu
;
1184 memcpy(nalu
, alu
, sizeof(struct r600_bytecode_alu
));
1187 /* will fail later since alu does not support it. */
1188 assert(!alu
->src
[0].abs
&& !alu
->src
[1].abs
&& !alu
->src
[2].abs
);
1191 if (bc
->cf_last
!= NULL
&& bc
->cf_last
->op
!= type
) {
1192 /* check if we could add it anyway */
1193 if (bc
->cf_last
->op
== CF_OP_ALU
&&
1194 type
== CF_OP_ALU_PUSH_BEFORE
) {
1195 LIST_FOR_EACH_ENTRY(lalu
, &bc
->cf_last
->alu
, list
) {
1196 if (lalu
->execute_mask
) {
1197 bc
->force_add_cf
= 1;
1202 bc
->force_add_cf
= 1;
1205 /* cf can contains only alu or only vtx or only tex */
1206 if (bc
->cf_last
== NULL
|| bc
->force_add_cf
) {
1207 r
= r600_bytecode_add_cf(bc
);
1213 bc
->cf_last
->op
= type
;
1215 /* Load index register if required */
1216 if (bc
->chip_class
>= EVERGREEN
) {
1217 for (i
= 0; i
< 3; i
++)
1218 if (nalu
->src
[i
].kc_bank
&& nalu
->src
[i
].kc_rel
)
1219 egcm_load_index_reg(bc
, 0, true);
1222 /* Check AR usage and load it if required */
1223 for (i
= 0; i
< 3; i
++)
1224 if (nalu
->src
[i
].rel
&& !bc
->ar_loaded
)
1227 if (nalu
->dst
.rel
&& !bc
->ar_loaded
)
1230 /* Setup the kcache for this ALU instruction. This will start a new
1231 * ALU clause if needed. */
1232 if ((r
= r600_bytecode_alloc_kcache_lines(bc
, nalu
, type
))) {
1237 if (!bc
->cf_last
->curr_bs_head
) {
1238 bc
->cf_last
->curr_bs_head
= nalu
;
1240 /* number of gpr == the last gpr used in any alu */
1241 for (i
= 0; i
< 3; i
++) {
1242 if (nalu
->src
[i
].sel
>= bc
->ngpr
&& nalu
->src
[i
].sel
< 128) {
1243 bc
->ngpr
= nalu
->src
[i
].sel
+ 1;
1245 if (nalu
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
)
1246 r600_bytecode_special_constants(nalu
->src
[i
].value
,
1247 &nalu
->src
[i
].sel
, &nalu
->src
[i
].neg
, nalu
->src
[i
].abs
);
1249 if (nalu
->dst
.sel
>= bc
->ngpr
) {
1250 bc
->ngpr
= nalu
->dst
.sel
+ 1;
1252 LIST_ADDTAIL(&nalu
->list
, &bc
->cf_last
->alu
);
1253 /* each alu use 2 dwords */
1254 bc
->cf_last
->ndw
+= 2;
1257 /* process cur ALU instructions for bank swizzle */
1259 uint32_t literal
[4];
1261 struct r600_bytecode_alu
*slots
[5];
1262 int max_slots
= bc
->chip_class
== CAYMAN
? 4 : 5;
1263 r
= assign_alu_units(bc
, bc
->cf_last
->curr_bs_head
, slots
);
1267 if (bc
->cf_last
->prev_bs_head
) {
1268 r
= merge_inst_groups(bc
, slots
, bc
->cf_last
->prev_bs_head
);
1273 if (bc
->cf_last
->prev_bs_head
) {
1274 r
= replace_gpr_with_pv_ps(bc
, slots
, bc
->cf_last
->prev_bs_head
);
1279 r
= check_and_set_bank_swizzle(bc
, slots
);
1283 for (i
= 0, nliteral
= 0; i
< max_slots
; i
++) {
1285 r
= r600_bytecode_alu_nliterals(bc
, slots
[i
], literal
, &nliteral
);
1290 bc
->cf_last
->ndw
+= align(nliteral
, 2);
1292 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1294 if ((bc
->cf_last
->ndw
>> 1) >= 120) {
1295 bc
->force_add_cf
= 1;
1298 bc
->cf_last
->prev2_bs_head
= bc
->cf_last
->prev_bs_head
;
1299 bc
->cf_last
->prev_bs_head
= bc
->cf_last
->curr_bs_head
;
1300 bc
->cf_last
->curr_bs_head
= NULL
;
1303 if (nalu
->dst
.rel
&& bc
->r6xx_nop_after_rel_dst
)
1304 insert_nop_r6xx(bc
);
1309 int r600_bytecode_add_alu(struct r600_bytecode
*bc
, const struct r600_bytecode_alu
*alu
)
1311 return r600_bytecode_add_alu_type(bc
, alu
, CF_OP_ALU
);
1314 static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode
*bc
)
1316 switch (bc
->chip_class
) {
1326 R600_ERR("Unknown chip class %d.\n", bc
->chip_class
);
1331 static inline boolean
last_inst_was_not_vtx_fetch(struct r600_bytecode
*bc
)
1333 return !((r600_isa_cf(bc
->cf_last
->op
)->flags
& CF_FETCH
) &&
1334 (bc
->chip_class
== CAYMAN
||
1335 bc
->cf_last
->op
!= CF_OP_TEX
));
1338 int r600_bytecode_add_vtx(struct r600_bytecode
*bc
, const struct r600_bytecode_vtx
*vtx
)
1340 struct r600_bytecode_vtx
*nvtx
= r600_bytecode_vtx();
1345 memcpy(nvtx
, vtx
, sizeof(struct r600_bytecode_vtx
));
1347 /* Load index register if required */
1348 if (bc
->chip_class
>= EVERGREEN
) {
1349 if (vtx
->buffer_index_mode
)
1350 egcm_load_index_reg(bc
, 0, false);
1353 /* cf can contains only alu or only vtx or only tex */
1354 if (bc
->cf_last
== NULL
||
1355 last_inst_was_not_vtx_fetch(bc
) ||
1357 r
= r600_bytecode_add_cf(bc
);
1362 switch (bc
->chip_class
) {
1366 bc
->cf_last
->op
= CF_OP_VTX
;
1369 bc
->cf_last
->op
= CF_OP_TEX
;
1372 R600_ERR("Unknown chip class %d.\n", bc
->chip_class
);
1377 LIST_ADDTAIL(&nvtx
->list
, &bc
->cf_last
->vtx
);
1378 /* each fetch use 4 dwords */
1379 bc
->cf_last
->ndw
+= 4;
1381 if ((bc
->cf_last
->ndw
/ 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc
))
1382 bc
->force_add_cf
= 1;
1384 bc
->ngpr
= MAX2(bc
->ngpr
, vtx
->src_gpr
+ 1);
1385 bc
->ngpr
= MAX2(bc
->ngpr
, vtx
->dst_gpr
+ 1);
1390 int r600_bytecode_add_tex(struct r600_bytecode
*bc
, const struct r600_bytecode_tex
*tex
)
1392 struct r600_bytecode_tex
*ntex
= r600_bytecode_tex();
1397 memcpy(ntex
, tex
, sizeof(struct r600_bytecode_tex
));
1399 /* Load index register if required */
1400 if (bc
->chip_class
>= EVERGREEN
) {
1401 if (tex
->sampler_index_mode
|| tex
->resource_index_mode
)
1402 egcm_load_index_reg(bc
, 1, false);
1405 /* we can't fetch data und use it as texture lookup address in the same TEX clause */
1406 if (bc
->cf_last
!= NULL
&&
1407 bc
->cf_last
->op
== CF_OP_TEX
) {
1408 struct r600_bytecode_tex
*ttex
;
1409 LIST_FOR_EACH_ENTRY(ttex
, &bc
->cf_last
->tex
, list
) {
1410 if (ttex
->dst_gpr
== ntex
->src_gpr
) {
1411 bc
->force_add_cf
= 1;
1415 /* slight hack to make gradients always go into same cf */
1416 if (ntex
->op
== FETCH_OP_SET_GRADIENTS_H
)
1417 bc
->force_add_cf
= 1;
1420 /* cf can contains only alu or only vtx or only tex */
1421 if (bc
->cf_last
== NULL
||
1422 bc
->cf_last
->op
!= CF_OP_TEX
||
1424 r
= r600_bytecode_add_cf(bc
);
1429 bc
->cf_last
->op
= CF_OP_TEX
;
1431 if (ntex
->src_gpr
>= bc
->ngpr
) {
1432 bc
->ngpr
= ntex
->src_gpr
+ 1;
1434 if (ntex
->dst_gpr
>= bc
->ngpr
) {
1435 bc
->ngpr
= ntex
->dst_gpr
+ 1;
1437 LIST_ADDTAIL(&ntex
->list
, &bc
->cf_last
->tex
);
1438 /* each texture fetch use 4 dwords */
1439 bc
->cf_last
->ndw
+= 4;
1441 if ((bc
->cf_last
->ndw
/ 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc
))
1442 bc
->force_add_cf
= 1;
1446 int r600_bytecode_add_gds(struct r600_bytecode
*bc
, const struct r600_bytecode_gds
*gds
)
1448 struct r600_bytecode_gds
*ngds
= r600_bytecode_gds();
1453 memcpy(ngds
, gds
, sizeof(struct r600_bytecode_gds
));
1455 if (bc
->cf_last
== NULL
||
1456 bc
->cf_last
->op
!= CF_OP_GDS
||
1458 r
= r600_bytecode_add_cf(bc
);
1463 bc
->cf_last
->op
= CF_OP_GDS
;
1466 LIST_ADDTAIL(&ngds
->list
, &bc
->cf_last
->gds
);
1467 bc
->cf_last
->ndw
+= 4; /* each GDS uses 4 dwords */
1468 if ((bc
->cf_last
->ndw
/ 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc
))
1469 bc
->force_add_cf
= 1;
1473 int r600_bytecode_add_cfinst(struct r600_bytecode
*bc
, unsigned op
)
1476 r
= r600_bytecode_add_cf(bc
);
1480 bc
->cf_last
->cond
= V_SQ_CF_COND_ACTIVE
;
1481 bc
->cf_last
->op
= op
;
1485 int cm_bytecode_add_cf_end(struct r600_bytecode
*bc
)
1487 return r600_bytecode_add_cfinst(bc
, CF_OP_CF_END
);
1490 /* common to all 3 families */
1491 static int r600_bytecode_vtx_build(struct r600_bytecode
*bc
, struct r600_bytecode_vtx
*vtx
, unsigned id
)
1493 bc
->bytecode
[id
] = S_SQ_VTX_WORD0_BUFFER_ID(vtx
->buffer_id
) |
1494 S_SQ_VTX_WORD0_FETCH_TYPE(vtx
->fetch_type
) |
1495 S_SQ_VTX_WORD0_SRC_GPR(vtx
->src_gpr
) |
1496 S_SQ_VTX_WORD0_SRC_SEL_X(vtx
->src_sel_x
);
1497 if (bc
->chip_class
< CAYMAN
)
1498 bc
->bytecode
[id
] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx
->mega_fetch_count
);
1500 bc
->bytecode
[id
++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx
->dst_sel_x
) |
1501 S_SQ_VTX_WORD1_DST_SEL_Y(vtx
->dst_sel_y
) |
1502 S_SQ_VTX_WORD1_DST_SEL_Z(vtx
->dst_sel_z
) |
1503 S_SQ_VTX_WORD1_DST_SEL_W(vtx
->dst_sel_w
) |
1504 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx
->use_const_fields
) |
1505 S_SQ_VTX_WORD1_DATA_FORMAT(vtx
->data_format
) |
1506 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx
->num_format_all
) |
1507 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx
->format_comp_all
) |
1508 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx
->srf_mode_all
) |
1509 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx
->dst_gpr
);
1510 bc
->bytecode
[id
] = S_SQ_VTX_WORD2_OFFSET(vtx
->offset
)|
1511 S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx
->endian
);
1512 if (bc
->chip_class
>= EVERGREEN
)
1513 bc
->bytecode
[id
] |= ((vtx
->buffer_index_mode
& 0x3) << 21); // S_SQ_VTX_WORD2_BIM(vtx->buffer_index_mode);
1514 if (bc
->chip_class
< CAYMAN
)
1515 bc
->bytecode
[id
] |= S_SQ_VTX_WORD2_MEGA_FETCH(1);
1517 bc
->bytecode
[id
++] = 0;
1521 /* common to all 3 families */
1522 static int r600_bytecode_tex_build(struct r600_bytecode
*bc
, struct r600_bytecode_tex
*tex
, unsigned id
)
1524 bc
->bytecode
[id
] = S_SQ_TEX_WORD0_TEX_INST(
1525 r600_isa_fetch_opcode(bc
->isa
->hw_class
, tex
->op
)) |
1526 EG_S_SQ_TEX_WORD0_INST_MOD(tex
->inst_mod
) |
1527 S_SQ_TEX_WORD0_RESOURCE_ID(tex
->resource_id
) |
1528 S_SQ_TEX_WORD0_SRC_GPR(tex
->src_gpr
) |
1529 S_SQ_TEX_WORD0_SRC_REL(tex
->src_rel
);
1530 if (bc
->chip_class
>= EVERGREEN
)
1531 bc
->bytecode
[id
] |= ((tex
->sampler_index_mode
& 0x3) << 27) | // S_SQ_TEX_WORD0_SIM(tex->sampler_index_mode);
1532 ((tex
->resource_index_mode
& 0x3) << 25); // S_SQ_TEX_WORD0_RIM(tex->resource_index_mode)
1534 bc
->bytecode
[id
++] = S_SQ_TEX_WORD1_DST_GPR(tex
->dst_gpr
) |
1535 S_SQ_TEX_WORD1_DST_REL(tex
->dst_rel
) |
1536 S_SQ_TEX_WORD1_DST_SEL_X(tex
->dst_sel_x
) |
1537 S_SQ_TEX_WORD1_DST_SEL_Y(tex
->dst_sel_y
) |
1538 S_SQ_TEX_WORD1_DST_SEL_Z(tex
->dst_sel_z
) |
1539 S_SQ_TEX_WORD1_DST_SEL_W(tex
->dst_sel_w
) |
1540 S_SQ_TEX_WORD1_LOD_BIAS(tex
->lod_bias
) |
1541 S_SQ_TEX_WORD1_COORD_TYPE_X(tex
->coord_type_x
) |
1542 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex
->coord_type_y
) |
1543 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex
->coord_type_z
) |
1544 S_SQ_TEX_WORD1_COORD_TYPE_W(tex
->coord_type_w
);
1545 bc
->bytecode
[id
++] = S_SQ_TEX_WORD2_OFFSET_X(tex
->offset_x
) |
1546 S_SQ_TEX_WORD2_OFFSET_Y(tex
->offset_y
) |
1547 S_SQ_TEX_WORD2_OFFSET_Z(tex
->offset_z
) |
1548 S_SQ_TEX_WORD2_SAMPLER_ID(tex
->sampler_id
) |
1549 S_SQ_TEX_WORD2_SRC_SEL_X(tex
->src_sel_x
) |
1550 S_SQ_TEX_WORD2_SRC_SEL_Y(tex
->src_sel_y
) |
1551 S_SQ_TEX_WORD2_SRC_SEL_Z(tex
->src_sel_z
) |
1552 S_SQ_TEX_WORD2_SRC_SEL_W(tex
->src_sel_w
);
1553 bc
->bytecode
[id
++] = 0;
1557 /* r600 only, r700/eg bits in r700_asm.c */
1558 static int r600_bytecode_alu_build(struct r600_bytecode
*bc
, struct r600_bytecode_alu
*alu
, unsigned id
)
1560 unsigned opcode
= r600_isa_alu_opcode(bc
->isa
->hw_class
, alu
->op
);
1562 /* don't replace gpr by pv or ps for destination register */
1563 bc
->bytecode
[id
++] = S_SQ_ALU_WORD0_SRC0_SEL(alu
->src
[0].sel
) |
1564 S_SQ_ALU_WORD0_SRC0_REL(alu
->src
[0].rel
) |
1565 S_SQ_ALU_WORD0_SRC0_CHAN(alu
->src
[0].chan
) |
1566 S_SQ_ALU_WORD0_SRC0_NEG(alu
->src
[0].neg
) |
1567 S_SQ_ALU_WORD0_SRC1_SEL(alu
->src
[1].sel
) |
1568 S_SQ_ALU_WORD0_SRC1_REL(alu
->src
[1].rel
) |
1569 S_SQ_ALU_WORD0_SRC1_CHAN(alu
->src
[1].chan
) |
1570 S_SQ_ALU_WORD0_SRC1_NEG(alu
->src
[1].neg
) |
1571 S_SQ_ALU_WORD0_INDEX_MODE(alu
->index_mode
) |
1572 S_SQ_ALU_WORD0_PRED_SEL(alu
->pred_sel
) |
1573 S_SQ_ALU_WORD0_LAST(alu
->last
);
1576 assert(!alu
->src
[0].abs
&& !alu
->src
[1].abs
&& !alu
->src
[2].abs
);
1577 bc
->bytecode
[id
++] = S_SQ_ALU_WORD1_DST_GPR(alu
->dst
.sel
) |
1578 S_SQ_ALU_WORD1_DST_CHAN(alu
->dst
.chan
) |
1579 S_SQ_ALU_WORD1_DST_REL(alu
->dst
.rel
) |
1580 S_SQ_ALU_WORD1_CLAMP(alu
->dst
.clamp
) |
1581 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu
->src
[2].sel
) |
1582 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu
->src
[2].rel
) |
1583 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu
->src
[2].chan
) |
1584 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu
->src
[2].neg
) |
1585 S_SQ_ALU_WORD1_OP3_ALU_INST(opcode
) |
1586 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu
->bank_swizzle
);
1588 bc
->bytecode
[id
++] = S_SQ_ALU_WORD1_DST_GPR(alu
->dst
.sel
) |
1589 S_SQ_ALU_WORD1_DST_CHAN(alu
->dst
.chan
) |
1590 S_SQ_ALU_WORD1_DST_REL(alu
->dst
.rel
) |
1591 S_SQ_ALU_WORD1_CLAMP(alu
->dst
.clamp
) |
1592 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu
->src
[0].abs
) |
1593 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu
->src
[1].abs
) |
1594 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu
->dst
.write
) |
1595 S_SQ_ALU_WORD1_OP2_OMOD(alu
->omod
) |
1596 S_SQ_ALU_WORD1_OP2_ALU_INST(opcode
) |
1597 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu
->bank_swizzle
) |
1598 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu
->execute_mask
) |
1599 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu
->update_pred
);
1604 static void r600_bytecode_cf_vtx_build(uint32_t *bytecode
, const struct r600_bytecode_cf
*cf
)
1606 *bytecode
++ = S_SQ_CF_WORD0_ADDR(cf
->addr
>> 1);
1607 *bytecode
++ = S_SQ_CF_WORD1_CF_INST(r600_isa_cf_opcode(ISA_CC_R600
, cf
->op
)) |
1608 S_SQ_CF_WORD1_BARRIER(1) |
1609 S_SQ_CF_WORD1_COUNT((cf
->ndw
/ 4) - 1);
1612 /* common for r600/r700 - eg in eg_asm.c */
1613 static int r600_bytecode_cf_build(struct r600_bytecode
*bc
, struct r600_bytecode_cf
*cf
)
1615 unsigned id
= cf
->id
;
1616 const struct cf_op_info
*cfop
= r600_isa_cf(cf
->op
);
1617 unsigned opcode
= r600_isa_cf_opcode(bc
->isa
->hw_class
, cf
->op
);
1620 if (cf
->op
== CF_NATIVE
) {
1621 bc
->bytecode
[id
++] = cf
->isa
[0];
1622 bc
->bytecode
[id
++] = cf
->isa
[1];
1623 } else if (cfop
->flags
& CF_ALU
) {
1624 bc
->bytecode
[id
++] = S_SQ_CF_ALU_WORD0_ADDR(cf
->addr
>> 1) |
1625 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf
->kcache
[0].mode
) |
1626 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf
->kcache
[0].bank
) |
1627 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf
->kcache
[1].bank
);
1629 bc
->bytecode
[id
++] = S_SQ_CF_ALU_WORD1_CF_INST(opcode
) |
1630 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf
->kcache
[1].mode
) |
1631 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf
->kcache
[0].addr
) |
1632 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf
->kcache
[1].addr
) |
1633 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1634 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc
->chip_class
== R600
? cf
->r6xx_uses_waterfall
: 0) |
1635 S_SQ_CF_ALU_WORD1_COUNT((cf
->ndw
/ 2) - 1);
1636 } else if (cfop
->flags
& CF_FETCH
) {
1637 if (bc
->chip_class
== R700
)
1638 r700_bytecode_cf_vtx_build(&bc
->bytecode
[id
], cf
);
1640 r600_bytecode_cf_vtx_build(&bc
->bytecode
[id
], cf
);
1641 } else if (cfop
->flags
& CF_EXP
) {
1642 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf
->output
.gpr
) |
1643 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf
->output
.elem_size
) |
1644 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf
->output
.array_base
) |
1645 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf
->output
.type
) |
1646 S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(cf
->output
.index_gpr
);
1647 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf
->output
.burst_count
- 1) |
1648 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf
->output
.swizzle_x
) |
1649 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf
->output
.swizzle_y
) |
1650 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf
->output
.swizzle_z
) |
1651 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf
->output
.swizzle_w
) |
1652 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf
->barrier
) |
1653 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode
) |
1654 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf
->end_of_program
);
1655 } else if (cfop
->flags
& CF_MEM
) {
1656 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf
->output
.gpr
) |
1657 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf
->output
.elem_size
) |
1658 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf
->output
.array_base
) |
1659 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf
->output
.type
) |
1660 S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(cf
->output
.index_gpr
);
1661 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf
->output
.burst_count
- 1) |
1662 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf
->barrier
) |
1663 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode
) |
1664 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf
->end_of_program
) |
1665 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf
->output
.array_size
) |
1666 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf
->output
.comp_mask
);
1668 bc
->bytecode
[id
++] = S_SQ_CF_WORD0_ADDR(cf
->cf_addr
>> 1);
1669 bc
->bytecode
[id
++] = S_SQ_CF_WORD1_CF_INST(opcode
) |
1670 S_SQ_CF_WORD1_BARRIER(1) |
1671 S_SQ_CF_WORD1_COND(cf
->cond
) |
1672 S_SQ_CF_WORD1_POP_COUNT(cf
->pop_count
) |
1673 S_SQ_CF_WORD1_END_OF_PROGRAM(cf
->end_of_program
);
1678 int r600_bytecode_build(struct r600_bytecode
*bc
)
1680 struct r600_bytecode_cf
*cf
;
1681 struct r600_bytecode_alu
*alu
;
1682 struct r600_bytecode_vtx
*vtx
;
1683 struct r600_bytecode_tex
*tex
;
1684 struct r600_bytecode_gds
*gds
;
1685 uint32_t literal
[4];
1690 if (!bc
->nstack
) // If not 0, Stack_size already provided by llvm
1691 bc
->nstack
= bc
->stack
.max_entries
;
1693 if (bc
->type
== TGSI_PROCESSOR_VERTEX
&& !bc
->nstack
) {
1697 /* first path compute addr of each CF block */
1698 /* addr start after all the CF instructions */
1699 addr
= bc
->cf_last
->id
+ 2;
1700 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
1701 if (r600_isa_cf(cf
->op
)->flags
& CF_FETCH
) {
1703 addr
&= 0xFFFFFFFCUL
;
1707 bc
->ndw
= cf
->addr
+ cf
->ndw
;
1710 bc
->bytecode
= calloc(4, bc
->ndw
);
1711 if (bc
->bytecode
== NULL
)
1713 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
1714 const struct cf_op_info
*cfop
= r600_isa_cf(cf
->op
);
1716 if (bc
->chip_class
>= EVERGREEN
)
1717 r
= eg_bytecode_cf_build(bc
, cf
);
1719 r
= r600_bytecode_cf_build(bc
, cf
);
1722 if (cfop
->flags
& CF_ALU
) {
1724 memset(literal
, 0, sizeof(literal
));
1725 LIST_FOR_EACH_ENTRY(alu
, &cf
->alu
, list
) {
1726 r
= r600_bytecode_alu_nliterals(bc
, alu
, literal
, &nliteral
);
1729 r600_bytecode_alu_adjust_literals(bc
, alu
, literal
, nliteral
);
1730 r600_bytecode_assign_kcache_banks(bc
, alu
, cf
->kcache
);
1732 switch(bc
->chip_class
) {
1734 r
= r600_bytecode_alu_build(bc
, alu
, addr
);
1737 r
= r700_bytecode_alu_build(bc
, alu
, addr
);
1741 r
= eg_bytecode_alu_build(bc
, alu
, addr
);
1744 R600_ERR("unknown chip class %d.\n", bc
->chip_class
);
1751 for (i
= 0; i
< align(nliteral
, 2); ++i
) {
1752 bc
->bytecode
[addr
++] = literal
[i
];
1755 memset(literal
, 0, sizeof(literal
));
1758 } else if (cf
->op
== CF_OP_VTX
) {
1759 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
1760 r
= r600_bytecode_vtx_build(bc
, vtx
, addr
);
1765 } else if (cf
->op
== CF_OP_GDS
) {
1766 assert(bc
->chip_class
>= EVERGREEN
);
1767 LIST_FOR_EACH_ENTRY(gds
, &cf
->gds
, list
) {
1768 r
= eg_bytecode_gds_build(bc
, gds
, addr
);
1773 } else if (cf
->op
== CF_OP_TEX
) {
1774 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
1775 assert(bc
->chip_class
>= EVERGREEN
);
1776 r
= r600_bytecode_vtx_build(bc
, vtx
, addr
);
1781 LIST_FOR_EACH_ENTRY(tex
, &cf
->tex
, list
) {
1782 r
= r600_bytecode_tex_build(bc
, tex
, addr
);
1792 void r600_bytecode_clear(struct r600_bytecode
*bc
)
1794 struct r600_bytecode_cf
*cf
= NULL
, *next_cf
;
1797 bc
->bytecode
= NULL
;
1799 LIST_FOR_EACH_ENTRY_SAFE(cf
, next_cf
, &bc
->cf
, list
) {
1800 struct r600_bytecode_alu
*alu
= NULL
, *next_alu
;
1801 struct r600_bytecode_tex
*tex
= NULL
, *next_tex
;
1802 struct r600_bytecode_tex
*vtx
= NULL
, *next_vtx
;
1803 struct r600_bytecode_gds
*gds
= NULL
, *next_gds
;
1805 LIST_FOR_EACH_ENTRY_SAFE(alu
, next_alu
, &cf
->alu
, list
) {
1809 LIST_INITHEAD(&cf
->alu
);
1811 LIST_FOR_EACH_ENTRY_SAFE(tex
, next_tex
, &cf
->tex
, list
) {
1815 LIST_INITHEAD(&cf
->tex
);
1817 LIST_FOR_EACH_ENTRY_SAFE(vtx
, next_vtx
, &cf
->vtx
, list
) {
1821 LIST_INITHEAD(&cf
->vtx
);
1823 LIST_FOR_EACH_ENTRY_SAFE(gds
, next_gds
, &cf
->gds
, list
) {
1827 LIST_INITHEAD(&cf
->gds
);
1832 LIST_INITHEAD(&cf
->list
);
1835 static int print_swizzle(unsigned swz
)
1837 const char * swzchars
= "xyzw01?_";
1838 assert(swz
<8 && swz
!= 6);
1839 return fprintf(stderr
, "%c", swzchars
[swz
]);
1842 static int print_sel(unsigned sel
, unsigned rel
, unsigned index_mode
,
1843 unsigned need_brackets
)
1846 if (rel
&& index_mode
>= 5 && sel
< 128)
1847 o
+= fprintf(stderr
, "G");
1848 if (rel
|| need_brackets
) {
1849 o
+= fprintf(stderr
, "[");
1851 o
+= fprintf(stderr
, "%d", sel
);
1853 if (index_mode
== 0 || index_mode
== 6)
1854 o
+= fprintf(stderr
, "+AR");
1855 else if (index_mode
== 4)
1856 o
+= fprintf(stderr
, "+AL");
1858 if (rel
|| need_brackets
) {
1859 o
+= fprintf(stderr
, "]");
1864 static int print_dst(struct r600_bytecode_alu
*alu
)
1867 unsigned sel
= alu
->dst
.sel
;
1868 char reg_char
= 'R';
1869 if (sel
> 128 - 4) { /* clause temporary gpr */
1874 if (alu_writes(alu
)) {
1875 o
+= fprintf(stderr
, "%c", reg_char
);
1876 o
+= print_sel(alu
->dst
.sel
, alu
->dst
.rel
, alu
->index_mode
, 0);
1878 o
+= fprintf(stderr
, "__");
1880 o
+= fprintf(stderr
, ".");
1881 o
+= print_swizzle(alu
->dst
.chan
);
1885 static int print_src(struct r600_bytecode_alu
*alu
, unsigned idx
)
1888 struct r600_bytecode_alu_src
*src
= &alu
->src
[idx
];
1889 unsigned sel
= src
->sel
, need_sel
= 1, need_chan
= 1, need_brackets
= 0;
1892 o
+= fprintf(stderr
,"-");
1894 o
+= fprintf(stderr
,"|");
1896 if (sel
< 128 - 4) {
1897 o
+= fprintf(stderr
, "R");
1898 } else if (sel
< 128) {
1899 o
+= fprintf(stderr
, "T");
1901 } else if (sel
< 160) {
1902 o
+= fprintf(stderr
, "KC0");
1905 } else if (sel
< 192) {
1906 o
+= fprintf(stderr
, "KC1");
1909 } else if (sel
>= 512) {
1910 o
+= fprintf(stderr
, "C%d", src
->kc_bank
);
1913 } else if (sel
>= 448) {
1914 o
+= fprintf(stderr
, "Param");
1917 } else if (sel
>= 288) {
1918 o
+= fprintf(stderr
, "KC3");
1921 } else if (sel
>= 256) {
1922 o
+= fprintf(stderr
, "KC2");
1929 case EG_V_SQ_ALU_SRC_LDS_DIRECT_A
:
1930 o
+= fprintf(stderr
, "LDS_A[0x%08X]", src
->value
);
1932 case EG_V_SQ_ALU_SRC_LDS_DIRECT_B
:
1933 o
+= fprintf(stderr
, "LDS_B[0x%08X]", src
->value
);
1935 case EG_V_SQ_ALU_SRC_LDS_OQ_A
:
1936 o
+= fprintf(stderr
, "LDS_OQ_A");
1939 case EG_V_SQ_ALU_SRC_LDS_OQ_B
:
1940 o
+= fprintf(stderr
, "LDS_OQ_B");
1943 case EG_V_SQ_ALU_SRC_LDS_OQ_A_POP
:
1944 o
+= fprintf(stderr
, "LDS_OQ_A_POP");
1947 case EG_V_SQ_ALU_SRC_LDS_OQ_B_POP
:
1948 o
+= fprintf(stderr
, "LDS_OQ_B_POP");
1951 case V_SQ_ALU_SRC_PS
:
1952 o
+= fprintf(stderr
, "PS");
1954 case V_SQ_ALU_SRC_PV
:
1955 o
+= fprintf(stderr
, "PV");
1958 case V_SQ_ALU_SRC_LITERAL
:
1959 o
+= fprintf(stderr
, "[0x%08X %f]", src
->value
, *(float*)&src
->value
);
1961 case V_SQ_ALU_SRC_0_5
:
1962 o
+= fprintf(stderr
, "0.5");
1964 case V_SQ_ALU_SRC_M_1_INT
:
1965 o
+= fprintf(stderr
, "-1");
1967 case V_SQ_ALU_SRC_1_INT
:
1968 o
+= fprintf(stderr
, "1");
1970 case V_SQ_ALU_SRC_1
:
1971 o
+= fprintf(stderr
, "1.0");
1973 case V_SQ_ALU_SRC_0
:
1974 o
+= fprintf(stderr
, "0");
1977 o
+= fprintf(stderr
, "??IMM_%d", sel
);
1983 o
+= print_sel(sel
, src
->rel
, alu
->index_mode
, need_brackets
);
1986 o
+= fprintf(stderr
, ".");
1987 o
+= print_swizzle(src
->chan
);
1991 o
+= fprintf(stderr
,"|");
1996 static int print_indent(int p
, int c
)
2000 o
+= fprintf(stderr
, " ");
2004 void r600_bytecode_disasm(struct r600_bytecode
*bc
)
2006 const char *index_mode
[] = {"CF_INDEX_NONE", "CF_INDEX_0", "CF_INDEX_1"};
2007 static int index
= 0;
2008 struct r600_bytecode_cf
*cf
= NULL
;
2009 struct r600_bytecode_alu
*alu
= NULL
;
2010 struct r600_bytecode_vtx
*vtx
= NULL
;
2011 struct r600_bytecode_tex
*tex
= NULL
;
2012 struct r600_bytecode_gds
*gds
= NULL
;
2014 unsigned i
, id
, ngr
= 0, last
;
2015 uint32_t literal
[4];
2019 switch (bc
->chip_class
) {
2034 fprintf(stderr
, "bytecode %d dw -- %d gprs -- %d nstack -------------\n",
2035 bc
->ndw
, bc
->ngpr
, bc
->nstack
);
2036 fprintf(stderr
, "shader %d -- %c\n", index
++, chip
);
2038 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
2040 if (cf
->op
== CF_NATIVE
) {
2041 fprintf(stderr
, "%04d %08X %08X CF_NATIVE\n", id
, bc
->bytecode
[id
],
2042 bc
->bytecode
[id
+ 1]);
2044 const struct cf_op_info
*cfop
= r600_isa_cf(cf
->op
);
2045 if (cfop
->flags
& CF_ALU
) {
2046 if (cf
->eg_alu_extended
) {
2047 fprintf(stderr
, "%04d %08X %08X %s\n", id
, bc
->bytecode
[id
],
2048 bc
->bytecode
[id
+ 1], "ALU_EXT");
2051 fprintf(stderr
, "%04d %08X %08X %s ", id
, bc
->bytecode
[id
],
2052 bc
->bytecode
[id
+ 1], cfop
->name
);
2053 fprintf(stderr
, "%d @%d ", cf
->ndw
/ 2, cf
->addr
);
2054 for (i
= 0; i
< 4; ++i
) {
2055 if (cf
->kcache
[i
].mode
) {
2056 int c_start
= (cf
->kcache
[i
].addr
<< 4);
2057 int c_end
= c_start
+ (cf
->kcache
[i
].mode
<< 4);
2058 fprintf(stderr
, "KC%d[CB%d:%d-%d%s%s] ",
2059 i
, cf
->kcache
[i
].bank
, c_start
, c_end
,
2060 cf
->kcache
[i
].index_mode
? " " : "",
2061 cf
->kcache
[i
].index_mode
? index_mode
[cf
->kcache
[i
].index_mode
] : "");
2064 fprintf(stderr
, "\n");
2065 } else if (cfop
->flags
& CF_FETCH
) {
2066 fprintf(stderr
, "%04d %08X %08X %s ", id
, bc
->bytecode
[id
],
2067 bc
->bytecode
[id
+ 1], cfop
->name
);
2068 fprintf(stderr
, "%d @%d ", cf
->ndw
/ 4, cf
->addr
);
2069 fprintf(stderr
, "\n");
2070 } else if (cfop
->flags
& CF_EXP
) {
2072 const char *exp_type
[] = {"PIXEL", "POS ", "PARAM"};
2073 o
+= fprintf(stderr
, "%04d %08X %08X %s ", id
, bc
->bytecode
[id
],
2074 bc
->bytecode
[id
+ 1], cfop
->name
);
2075 o
+= print_indent(o
, 43);
2076 o
+= fprintf(stderr
, "%s ", exp_type
[cf
->output
.type
]);
2077 if (cf
->output
.burst_count
> 1) {
2078 o
+= fprintf(stderr
, "%d-%d ", cf
->output
.array_base
,
2079 cf
->output
.array_base
+ cf
->output
.burst_count
- 1);
2081 o
+= print_indent(o
, 55);
2082 o
+= fprintf(stderr
, "R%d-%d.", cf
->output
.gpr
,
2083 cf
->output
.gpr
+ cf
->output
.burst_count
- 1);
2085 o
+= fprintf(stderr
, "%d ", cf
->output
.array_base
);
2086 o
+= print_indent(o
, 55);
2087 o
+= fprintf(stderr
, "R%d.", cf
->output
.gpr
);
2090 o
+= print_swizzle(cf
->output
.swizzle_x
);
2091 o
+= print_swizzle(cf
->output
.swizzle_y
);
2092 o
+= print_swizzle(cf
->output
.swizzle_z
);
2093 o
+= print_swizzle(cf
->output
.swizzle_w
);
2095 print_indent(o
, 67);
2097 fprintf(stderr
, " ES:%X ", cf
->output
.elem_size
);
2099 fprintf(stderr
, "NO_BARRIER ");
2100 if (cf
->end_of_program
)
2101 fprintf(stderr
, "EOP ");
2102 fprintf(stderr
, "\n");
2103 } else if (r600_isa_cf(cf
->op
)->flags
& CF_MEM
) {
2105 const char *exp_type
[] = {"WRITE", "WRITE_IND", "WRITE_ACK",
2107 o
+= fprintf(stderr
, "%04d %08X %08X %s ", id
,
2108 bc
->bytecode
[id
], bc
->bytecode
[id
+ 1], cfop
->name
);
2109 o
+= print_indent(o
, 43);
2110 o
+= fprintf(stderr
, "%s ", exp_type
[cf
->output
.type
]);
2111 if (cf
->output
.burst_count
> 1) {
2112 o
+= fprintf(stderr
, "%d-%d ", cf
->output
.array_base
,
2113 cf
->output
.array_base
+ cf
->output
.burst_count
- 1);
2114 o
+= print_indent(o
, 55);
2115 o
+= fprintf(stderr
, "R%d-%d.", cf
->output
.gpr
,
2116 cf
->output
.gpr
+ cf
->output
.burst_count
- 1);
2118 o
+= fprintf(stderr
, "%d ", cf
->output
.array_base
);
2119 o
+= print_indent(o
, 55);
2120 o
+= fprintf(stderr
, "R%d.", cf
->output
.gpr
);
2122 for (i
= 0; i
< 4; ++i
) {
2123 if (cf
->output
.comp_mask
& (1 << i
))
2124 o
+= print_swizzle(i
);
2126 o
+= print_swizzle(7);
2129 if (cf
->output
.type
== V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND
)
2130 o
+= fprintf(stderr
, " R%d", cf
->output
.index_gpr
);
2132 o
+= print_indent(o
, 67);
2134 fprintf(stderr
, " ES:%i ", cf
->output
.elem_size
);
2135 if (cf
->output
.array_size
!= 0xFFF)
2136 fprintf(stderr
, "AS:%i ", cf
->output
.array_size
);
2138 fprintf(stderr
, "NO_BARRIER ");
2139 if (cf
->end_of_program
)
2140 fprintf(stderr
, "EOP ");
2141 fprintf(stderr
, "\n");
2143 fprintf(stderr
, "%04d %08X %08X %s ", id
, bc
->bytecode
[id
],
2144 bc
->bytecode
[id
+ 1], cfop
->name
);
2145 fprintf(stderr
, "@%d ", cf
->cf_addr
);
2147 fprintf(stderr
, "CND:%X ", cf
->cond
);
2149 fprintf(stderr
, "POP:%X ", cf
->pop_count
);
2150 if (cf
->count
&& (cfop
->flags
& CF_EMIT
))
2151 fprintf(stderr
, "STREAM%d ", cf
->count
);
2152 if (cf
->end_of_program
)
2153 fprintf(stderr
, "EOP ");
2154 fprintf(stderr
, "\n");
2161 LIST_FOR_EACH_ENTRY(alu
, &cf
->alu
, list
) {
2162 const char *omod_str
[] = {"","*2","*4","/2"};
2163 const struct alu_op_info
*aop
= r600_isa_alu(alu
->op
);
2166 r600_bytecode_alu_nliterals(bc
, alu
, literal
, &nliteral
);
2167 o
+= fprintf(stderr
, " %04d %08X %08X ", id
, bc
->bytecode
[id
], bc
->bytecode
[id
+1]);
2169 o
+= fprintf(stderr
, "%4d ", ++ngr
);
2171 o
+= fprintf(stderr
, " ");
2172 o
+= fprintf(stderr
, "%c%c %c ", alu
->execute_mask
? 'M':' ',
2173 alu
->update_pred
? 'P':' ',
2174 alu
->pred_sel
? alu
->pred_sel
==2 ? '0':'1':' ');
2176 o
+= fprintf(stderr
, "%s%s%s ", aop
->name
,
2177 omod_str
[alu
->omod
], alu
->dst
.clamp
? "_sat":"");
2179 o
+= print_indent(o
,60);
2180 o
+= print_dst(alu
);
2181 for (i
= 0; i
< aop
->src_count
; ++i
) {
2182 o
+= fprintf(stderr
, i
== 0 ? ", ": ", ");
2183 o
+= print_src(alu
, i
);
2186 if (alu
->bank_swizzle
) {
2187 o
+= print_indent(o
,75);
2188 o
+= fprintf(stderr
, " BS:%d", alu
->bank_swizzle
);
2191 fprintf(stderr
, "\n");
2195 for (i
= 0; i
< nliteral
; i
++, id
++) {
2196 float *f
= (float*)(bc
->bytecode
+ id
);
2197 o
= fprintf(stderr
, " %04d %08X", id
, bc
->bytecode
[id
]);
2198 print_indent(o
, 60);
2199 fprintf(stderr
, " %f (%d)\n", *f
, *(bc
->bytecode
+ id
));
2207 LIST_FOR_EACH_ENTRY(tex
, &cf
->tex
, list
) {
2209 o
+= fprintf(stderr
, " %04d %08X %08X %08X ", id
, bc
->bytecode
[id
],
2210 bc
->bytecode
[id
+ 1], bc
->bytecode
[id
+ 2]);
2212 o
+= fprintf(stderr
, "%s ", r600_isa_fetch(tex
->op
)->name
);
2214 o
+= print_indent(o
, 50);
2216 o
+= fprintf(stderr
, "R%d.", tex
->dst_gpr
);
2217 o
+= print_swizzle(tex
->dst_sel_x
);
2218 o
+= print_swizzle(tex
->dst_sel_y
);
2219 o
+= print_swizzle(tex
->dst_sel_z
);
2220 o
+= print_swizzle(tex
->dst_sel_w
);
2222 o
+= fprintf(stderr
, ", R%d.", tex
->src_gpr
);
2223 o
+= print_swizzle(tex
->src_sel_x
);
2224 o
+= print_swizzle(tex
->src_sel_y
);
2225 o
+= print_swizzle(tex
->src_sel_z
);
2226 o
+= print_swizzle(tex
->src_sel_w
);
2228 o
+= fprintf(stderr
, ", RID:%d", tex
->resource_id
);
2229 o
+= fprintf(stderr
, ", SID:%d ", tex
->sampler_id
);
2231 if (tex
->sampler_index_mode
)
2232 fprintf(stderr
, "SQ_%s ", index_mode
[tex
->sampler_index_mode
]);
2235 fprintf(stderr
, "LB:%d ", tex
->lod_bias
);
2237 fprintf(stderr
, "CT:%c%c%c%c ",
2238 tex
->coord_type_x
? 'N' : 'U',
2239 tex
->coord_type_y
? 'N' : 'U',
2240 tex
->coord_type_z
? 'N' : 'U',
2241 tex
->coord_type_w
? 'N' : 'U');
2244 fprintf(stderr
, "OX:%d ", tex
->offset_x
);
2246 fprintf(stderr
, "OY:%d ", tex
->offset_y
);
2248 fprintf(stderr
, "OZ:%d ", tex
->offset_z
);
2251 fprintf(stderr
, "\n");
2254 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
2256 const char * fetch_type
[] = {"VERTEX", "INSTANCE", ""};
2257 o
+= fprintf(stderr
, " %04d %08X %08X %08X ", id
, bc
->bytecode
[id
],
2258 bc
->bytecode
[id
+ 1], bc
->bytecode
[id
+ 2]);
2260 o
+= fprintf(stderr
, "%s ", r600_isa_fetch(vtx
->op
)->name
);
2262 o
+= print_indent(o
, 50);
2264 o
+= fprintf(stderr
, "R%d.", vtx
->dst_gpr
);
2265 o
+= print_swizzle(vtx
->dst_sel_x
);
2266 o
+= print_swizzle(vtx
->dst_sel_y
);
2267 o
+= print_swizzle(vtx
->dst_sel_z
);
2268 o
+= print_swizzle(vtx
->dst_sel_w
);
2270 o
+= fprintf(stderr
, ", R%d.", vtx
->src_gpr
);
2271 o
+= print_swizzle(vtx
->src_sel_x
);
2274 fprintf(stderr
, " +%db", vtx
->offset
);
2276 o
+= print_indent(o
, 55);
2278 fprintf(stderr
, ", RID:%d ", vtx
->buffer_id
);
2280 fprintf(stderr
, "%s ", fetch_type
[vtx
->fetch_type
]);
2282 if (bc
->chip_class
< CAYMAN
&& vtx
->mega_fetch_count
)
2283 fprintf(stderr
, "MFC:%d ", vtx
->mega_fetch_count
);
2285 if (bc
->chip_class
>= EVERGREEN
&& vtx
->buffer_index_mode
)
2286 fprintf(stderr
, "SQ_%s ", index_mode
[vtx
->buffer_index_mode
]);
2288 fprintf(stderr
, "UCF:%d ", vtx
->use_const_fields
);
2289 fprintf(stderr
, "FMT(DTA:%d ", vtx
->data_format
);
2290 fprintf(stderr
, "NUM:%d ", vtx
->num_format_all
);
2291 fprintf(stderr
, "COMP:%d ", vtx
->format_comp_all
);
2292 fprintf(stderr
, "MODE:%d)\n", vtx
->srf_mode_all
);
2297 LIST_FOR_EACH_ENTRY(gds
, &cf
->gds
, list
) {
2299 o
+= fprintf(stderr
, " %04d %08X %08X %08X ", id
, bc
->bytecode
[id
],
2300 bc
->bytecode
[id
+ 1], bc
->bytecode
[id
+ 2]);
2302 o
+= fprintf(stderr
, "%s ", r600_isa_fetch(gds
->op
)->name
);
2304 if (gds
->op
!= FETCH_OP_TF_WRITE
) {
2305 o
+= fprintf(stderr
, "R%d.", gds
->dst_gpr
);
2306 o
+= print_swizzle(gds
->dst_sel_x
);
2307 o
+= print_swizzle(gds
->dst_sel_y
);
2308 o
+= print_swizzle(gds
->dst_sel_z
);
2309 o
+= print_swizzle(gds
->dst_sel_w
);
2312 o
+= fprintf(stderr
, ", R%d.", gds
->src_gpr
);
2313 o
+= print_swizzle(gds
->src_sel_x
);
2314 o
+= print_swizzle(gds
->src_sel_y
);
2315 o
+= print_swizzle(gds
->src_sel_z
);
2317 if (gds
->op
!= FETCH_OP_TF_WRITE
) {
2318 o
+= fprintf(stderr
, ", R%d.", gds
->src_gpr2
);
2320 fprintf(stderr
, "\n");
2325 fprintf(stderr
, "--------------------------------------\n");
2328 void r600_vertex_data_type(enum pipe_format pformat
,
2330 unsigned *num_format
, unsigned *format_comp
, unsigned *endian
)
2332 const struct util_format_description
*desc
;
2338 *endian
= ENDIAN_NONE
;
2340 if (pformat
== PIPE_FORMAT_R11G11B10_FLOAT
) {
2341 *format
= FMT_10_11_11_FLOAT
;
2342 *endian
= r600_endian_swap(32);
2346 desc
= util_format_description(pformat
);
2347 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
) {
2351 /* Find the first non-VOID channel. */
2352 for (i
= 0; i
< 4; i
++) {
2353 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2358 *endian
= r600_endian_swap(desc
->channel
[i
].size
);
2360 switch (desc
->channel
[i
].type
) {
2361 /* Half-floats, floats, ints */
2362 case UTIL_FORMAT_TYPE_FLOAT
:
2363 switch (desc
->channel
[i
].size
) {
2365 switch (desc
->nr_channels
) {
2367 *format
= FMT_16_FLOAT
;
2370 *format
= FMT_16_16_FLOAT
;
2374 *format
= FMT_16_16_16_16_FLOAT
;
2379 switch (desc
->nr_channels
) {
2381 *format
= FMT_32_FLOAT
;
2384 *format
= FMT_32_32_FLOAT
;
2387 *format
= FMT_32_32_32_FLOAT
;
2390 *format
= FMT_32_32_32_32_FLOAT
;
2399 case UTIL_FORMAT_TYPE_UNSIGNED
:
2401 case UTIL_FORMAT_TYPE_SIGNED
:
2402 switch (desc
->channel
[i
].size
) {
2404 switch (desc
->nr_channels
) {
2413 *format
= FMT_8_8_8_8
;
2418 if (desc
->nr_channels
!= 4)
2421 *format
= FMT_2_10_10_10
;
2424 switch (desc
->nr_channels
) {
2429 *format
= FMT_16_16
;
2433 *format
= FMT_16_16_16_16
;
2438 switch (desc
->nr_channels
) {
2443 *format
= FMT_32_32
;
2446 *format
= FMT_32_32_32
;
2449 *format
= FMT_32_32_32_32
;
2461 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2466 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
||
2467 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2468 if (!desc
->channel
[i
].normalized
) {
2469 if (desc
->channel
[i
].pure_integer
)
2477 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat
));
2480 void *r600_create_vertex_fetch_shader(struct pipe_context
*ctx
,
2482 const struct pipe_vertex_element
*elements
)
2484 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2485 struct r600_bytecode bc
;
2486 struct r600_bytecode_vtx vtx
;
2487 const struct util_format_description
*desc
;
2488 unsigned fetch_resource_start
= rctx
->b
.chip_class
>= EVERGREEN
? 0 : 160;
2489 unsigned format
, num_format
, format_comp
, endian
;
2491 int i
, j
, r
, fs_size
;
2492 struct r600_fetch_shader
*shader
;
2493 unsigned no_sb
= rctx
->screen
->b
.debug_flags
& DBG_NO_SB
;
2494 unsigned sb_disasm
= !no_sb
|| (rctx
->screen
->b
.debug_flags
& DBG_SB_DISASM
);
2498 memset(&bc
, 0, sizeof(bc
));
2499 r600_bytecode_init(&bc
, rctx
->b
.chip_class
, rctx
->b
.family
,
2500 rctx
->screen
->has_compressed_msaa_texturing
);
2504 for (i
= 0; i
< count
; i
++) {
2505 if (elements
[i
].instance_divisor
> 1) {
2506 if (rctx
->b
.chip_class
== CAYMAN
) {
2507 for (j
= 0; j
< 4; j
++) {
2508 struct r600_bytecode_alu alu
;
2509 memset(&alu
, 0, sizeof(alu
));
2510 alu
.op
= ALU_OP2_MULHI_UINT
;
2512 alu
.src
[0].chan
= 3;
2513 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2514 alu
.src
[1].value
= (1ll << 32) / elements
[i
].instance_divisor
+ 1;
2515 alu
.dst
.sel
= i
+ 1;
2517 alu
.dst
.write
= j
== 3;
2519 if ((r
= r600_bytecode_add_alu(&bc
, &alu
))) {
2520 r600_bytecode_clear(&bc
);
2525 struct r600_bytecode_alu alu
;
2526 memset(&alu
, 0, sizeof(alu
));
2527 alu
.op
= ALU_OP2_MULHI_UINT
;
2529 alu
.src
[0].chan
= 3;
2530 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2531 alu
.src
[1].value
= (1ll << 32) / elements
[i
].instance_divisor
+ 1;
2532 alu
.dst
.sel
= i
+ 1;
2536 if ((r
= r600_bytecode_add_alu(&bc
, &alu
))) {
2537 r600_bytecode_clear(&bc
);
2544 for (i
= 0; i
< count
; i
++) {
2545 r600_vertex_data_type(elements
[i
].src_format
,
2546 &format
, &num_format
, &format_comp
, &endian
);
2548 desc
= util_format_description(elements
[i
].src_format
);
2550 r600_bytecode_clear(&bc
);
2551 R600_ERR("unknown format %d\n", elements
[i
].src_format
);
2555 if (elements
[i
].src_offset
> 65535) {
2556 r600_bytecode_clear(&bc
);
2557 R600_ERR("too big src_offset: %u\n", elements
[i
].src_offset
);
2561 memset(&vtx
, 0, sizeof(vtx
));
2562 vtx
.buffer_id
= elements
[i
].vertex_buffer_index
+ fetch_resource_start
;
2563 vtx
.fetch_type
= elements
[i
].instance_divisor
? SQ_VTX_FETCH_INSTANCE_DATA
: SQ_VTX_FETCH_VERTEX_DATA
;
2564 vtx
.src_gpr
= elements
[i
].instance_divisor
> 1 ? i
+ 1 : 0;
2565 vtx
.src_sel_x
= elements
[i
].instance_divisor
? 3 : 0;
2566 vtx
.mega_fetch_count
= 0x1F;
2567 vtx
.dst_gpr
= i
+ 1;
2568 vtx
.dst_sel_x
= desc
->swizzle
[0];
2569 vtx
.dst_sel_y
= desc
->swizzle
[1];
2570 vtx
.dst_sel_z
= desc
->swizzle
[2];
2571 vtx
.dst_sel_w
= desc
->swizzle
[3];
2572 vtx
.data_format
= format
;
2573 vtx
.num_format_all
= num_format
;
2574 vtx
.format_comp_all
= format_comp
;
2575 vtx
.offset
= elements
[i
].src_offset
;
2576 vtx
.endian
= endian
;
2578 if ((r
= r600_bytecode_add_vtx(&bc
, &vtx
))) {
2579 r600_bytecode_clear(&bc
);
2584 r600_bytecode_add_cfinst(&bc
, CF_OP_RET
);
2586 if ((r
= r600_bytecode_build(&bc
))) {
2587 r600_bytecode_clear(&bc
);
2591 if (rctx
->screen
->b
.debug_flags
& DBG_FS
) {
2592 fprintf(stderr
, "--------------------------------------------------------------\n");
2593 fprintf(stderr
, "Vertex elements state:\n");
2594 for (i
= 0; i
< count
; i
++) {
2595 fprintf(stderr
, " ");
2596 util_dump_vertex_element(stderr
, elements
+i
);
2597 fprintf(stderr
, "\n");
2601 r600_bytecode_disasm(&bc
);
2603 fprintf(stderr
, "______________________________________________________________\n");
2605 r600_sb_bytecode_process(rctx
, &bc
, NULL
, 1 /*dump*/, 0 /*optimize*/);
2611 /* Allocate the CSO. */
2612 shader
= CALLOC_STRUCT(r600_fetch_shader
);
2614 r600_bytecode_clear(&bc
);
2618 u_suballocator_alloc(rctx
->allocator_fetch_shader
, fs_size
, &shader
->offset
,
2619 (struct pipe_resource
**)&shader
->buffer
);
2620 if (!shader
->buffer
) {
2621 r600_bytecode_clear(&bc
);
2626 bytecode
= r600_buffer_map_sync_with_rings(&rctx
->b
, shader
->buffer
, PIPE_TRANSFER_WRITE
| PIPE_TRANSFER_UNSYNCHRONIZED
);
2627 bytecode
+= shader
->offset
/ 4;
2629 if (R600_BIG_ENDIAN
) {
2630 for (i
= 0; i
< fs_size
/ 4; ++i
) {
2631 bytecode
[i
] = util_cpu_to_le32(bc
.bytecode
[i
]);
2634 memcpy(bytecode
, bc
.bytecode
, fs_size
);
2636 rctx
->b
.ws
->buffer_unmap(shader
->buffer
->cs_buf
);
2638 r600_bytecode_clear(&bc
);
2642 void r600_bytecode_alu_read(struct r600_bytecode
*bc
,
2643 struct r600_bytecode_alu
*alu
, uint32_t word0
, uint32_t word1
)
2646 alu
->src
[0].sel
= G_SQ_ALU_WORD0_SRC0_SEL(word0
);
2647 alu
->src
[0].rel
= G_SQ_ALU_WORD0_SRC0_REL(word0
);
2648 alu
->src
[0].chan
= G_SQ_ALU_WORD0_SRC0_CHAN(word0
);
2649 alu
->src
[0].neg
= G_SQ_ALU_WORD0_SRC0_NEG(word0
);
2650 alu
->src
[1].sel
= G_SQ_ALU_WORD0_SRC1_SEL(word0
);
2651 alu
->src
[1].rel
= G_SQ_ALU_WORD0_SRC1_REL(word0
);
2652 alu
->src
[1].chan
= G_SQ_ALU_WORD0_SRC1_CHAN(word0
);
2653 alu
->src
[1].neg
= G_SQ_ALU_WORD0_SRC1_NEG(word0
);
2654 alu
->index_mode
= G_SQ_ALU_WORD0_INDEX_MODE(word0
);
2655 alu
->pred_sel
= G_SQ_ALU_WORD0_PRED_SEL(word0
);
2656 alu
->last
= G_SQ_ALU_WORD0_LAST(word0
);
2659 alu
->bank_swizzle
= G_SQ_ALU_WORD1_BANK_SWIZZLE(word1
);
2660 if (alu
->bank_swizzle
)
2661 alu
->bank_swizzle_force
= alu
->bank_swizzle
;
2662 alu
->dst
.sel
= G_SQ_ALU_WORD1_DST_GPR(word1
);
2663 alu
->dst
.rel
= G_SQ_ALU_WORD1_DST_REL(word1
);
2664 alu
->dst
.chan
= G_SQ_ALU_WORD1_DST_CHAN(word1
);
2665 alu
->dst
.clamp
= G_SQ_ALU_WORD1_CLAMP(word1
);
2666 if (G_SQ_ALU_WORD1_ENCODING(word1
)) /*ALU_DWORD1_OP3*/
2669 alu
->src
[2].sel
= G_SQ_ALU_WORD1_OP3_SRC2_SEL(word1
);
2670 alu
->src
[2].rel
= G_SQ_ALU_WORD1_OP3_SRC2_REL(word1
);
2671 alu
->src
[2].chan
= G_SQ_ALU_WORD1_OP3_SRC2_CHAN(word1
);
2672 alu
->src
[2].neg
= G_SQ_ALU_WORD1_OP3_SRC2_NEG(word1
);
2673 alu
->op
= r600_isa_alu_by_opcode(bc
->isa
,
2674 G_SQ_ALU_WORD1_OP3_ALU_INST(word1
), /* is_op3 = */ 1);
2677 else /*ALU_DWORD1_OP2*/
2679 alu
->src
[0].abs
= G_SQ_ALU_WORD1_OP2_SRC0_ABS(word1
);
2680 alu
->src
[1].abs
= G_SQ_ALU_WORD1_OP2_SRC1_ABS(word1
);
2681 alu
->op
= r600_isa_alu_by_opcode(bc
->isa
,
2682 G_SQ_ALU_WORD1_OP2_ALU_INST(word1
), /* is_op3 = */ 0);
2683 alu
->omod
= G_SQ_ALU_WORD1_OP2_OMOD(word1
);
2684 alu
->dst
.write
= G_SQ_ALU_WORD1_OP2_WRITE_MASK(word1
);
2685 alu
->update_pred
= G_SQ_ALU_WORD1_OP2_UPDATE_PRED(word1
);
2687 G_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(word1
);
2692 void r600_bytecode_export_read(struct r600_bytecode
*bc
,
2693 struct r600_bytecode_output
*output
, uint32_t word0
, uint32_t word1
)
2695 output
->array_base
= G_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(word0
);
2696 output
->type
= G_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(word0
);
2697 output
->gpr
= G_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(word0
);
2698 output
->elem_size
= G_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(word0
);
2700 output
->swizzle_x
= G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(word1
);
2701 output
->swizzle_y
= G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(word1
);
2702 output
->swizzle_z
= G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(word1
);
2703 output
->swizzle_w
= G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(word1
);
2704 output
->burst_count
= G_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(word1
);
2705 output
->end_of_program
= G_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(word1
);
2706 output
->op
= r600_isa_cf_by_opcode(bc
->isa
,
2707 G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(word1
), 0);
2708 output
->barrier
= G_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(word1
);
2709 output
->array_size
= G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(word1
);
2710 output
->comp_mask
= G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(word1
);