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r600g: texture buffer object + glsl 1.40 enable support (v2)
[mesa.git] / src / gallium / drivers / r600 / r600_asm.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_opcodes.h"
25 #include "r600_formats.h"
26 #include "r600_shader.h"
27 #include "r600d.h"
28
29 #include <errno.h>
30 #include <byteswap.h>
31 #include "util/u_memory.h"
32 #include "pipe/p_shader_tokens.h"
33
34 #define NUM_OF_CYCLES 3
35 #define NUM_OF_COMPONENTS 4
36
37 static inline unsigned int r600_bytecode_get_num_operands(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
38 {
39 if(alu->is_op3)
40 return 3;
41
42 switch (bc->chip_class) {
43 default:
44 case R600:
45 case R700:
46 switch (alu->inst) {
47 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
48 return 0;
49 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
50 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT:
51 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT:
52 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT:
53 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT:
54 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
55 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
56 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
57 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
58 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
59 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE:
60 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT:
61 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT:
62 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT:
63 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT:
64 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
65 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
66 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT:
67 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT:
68 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT:
69 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT:
70 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
71 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT:
72 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
73 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT:
74 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
75 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT:
76 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT:
77 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
78 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT:
79 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT:
80 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
81 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
82 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
83 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
84 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT:
85 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT:
86 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
87 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
88 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
89 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT:
90 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT:
91 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT:
92 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT:
93 return 2;
94
95 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
96 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA:
97 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR:
98 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT:
99 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
100 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
101 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL:
102 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
103 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
104 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
105 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
106 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
107 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
108 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
109 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT:
110 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT:
111 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
112 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
113 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
114 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT:
115 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT:
116 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT:
117 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
118 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
119 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE:
120 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT:
121 return 1;
122 default: R600_ERR(
123 "Need instruction operand number for 0x%x.\n", alu->inst);
124 }
125 break;
126 case EVERGREEN:
127 case CAYMAN:
128 switch (alu->inst) {
129 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
130 return 0;
131 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
132 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT:
133 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT:
134 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT:
135 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT:
136 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
137 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
138 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
139 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
140 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
141 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE:
142 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT:
143 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT:
144 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT:
145 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT:
146 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
147 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
148 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT:
149 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT:
150 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT:
151 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT:
152 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
153 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT:
154 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
155 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT:
156 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
157 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT:
158 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT:
159 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
160 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT:
161 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT:
162 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
163 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT:
164 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
165 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
166 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
167 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT:
168 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
169 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
170 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
171 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_XY:
172 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_ZW:
173 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT:
174 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT:
175 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT:
176 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT:
177 return 2;
178
179 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
180 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
181 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
182 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL:
183 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
184 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
185 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
186 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
187 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
188 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
189 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
190 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
191 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
192 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
193 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR:
194 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT:
195 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT:
196 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT:
197 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
198 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
199 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE:
200 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT:
201 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_LOAD_P0:
202 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT:
203 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT:
204 return 1;
205 default:
206 R600_ERR("Need instruction operand number for 0x%x.\n", alu->inst);
207 }
208 break;
209 }
210
211 return 3;
212 }
213
214 int r700_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id);
215
216 static struct r600_bytecode_cf *r600_bytecode_cf(void)
217 {
218 struct r600_bytecode_cf *cf = CALLOC_STRUCT(r600_bytecode_cf);
219
220 if (cf == NULL)
221 return NULL;
222 LIST_INITHEAD(&cf->list);
223 LIST_INITHEAD(&cf->alu);
224 LIST_INITHEAD(&cf->vtx);
225 LIST_INITHEAD(&cf->tex);
226 return cf;
227 }
228
229 static struct r600_bytecode_alu *r600_bytecode_alu(void)
230 {
231 struct r600_bytecode_alu *alu = CALLOC_STRUCT(r600_bytecode_alu);
232
233 if (alu == NULL)
234 return NULL;
235 LIST_INITHEAD(&alu->list);
236 return alu;
237 }
238
239 static struct r600_bytecode_vtx *r600_bytecode_vtx(void)
240 {
241 struct r600_bytecode_vtx *vtx = CALLOC_STRUCT(r600_bytecode_vtx);
242
243 if (vtx == NULL)
244 return NULL;
245 LIST_INITHEAD(&vtx->list);
246 return vtx;
247 }
248
249 static struct r600_bytecode_tex *r600_bytecode_tex(void)
250 {
251 struct r600_bytecode_tex *tex = CALLOC_STRUCT(r600_bytecode_tex);
252
253 if (tex == NULL)
254 return NULL;
255 LIST_INITHEAD(&tex->list);
256 return tex;
257 }
258
259 void r600_bytecode_init(struct r600_bytecode *bc,
260 enum chip_class chip_class,
261 enum radeon_family family,
262 enum r600_msaa_texture_mode msaa_texture_mode)
263 {
264 if ((chip_class == R600) &&
265 (family != CHIP_RV670 && family != CHIP_RS780 && family != CHIP_RS880)) {
266 bc->ar_handling = AR_HANDLE_RV6XX;
267 bc->r6xx_nop_after_rel_dst = 1;
268 } else {
269 bc->ar_handling = AR_HANDLE_NORMAL;
270 bc->r6xx_nop_after_rel_dst = 0;
271 }
272
273 LIST_INITHEAD(&bc->cf);
274 bc->chip_class = chip_class;
275 bc->msaa_texture_mode = msaa_texture_mode;
276 }
277
278 static int r600_bytecode_add_cf(struct r600_bytecode *bc)
279 {
280 struct r600_bytecode_cf *cf = r600_bytecode_cf();
281
282 if (cf == NULL)
283 return -ENOMEM;
284 LIST_ADDTAIL(&cf->list, &bc->cf);
285 if (bc->cf_last) {
286 cf->id = bc->cf_last->id + 2;
287 if (bc->cf_last->eg_alu_extended) {
288 /* take into account extended alu size */
289 cf->id += 2;
290 bc->ndw += 2;
291 }
292 }
293 bc->cf_last = cf;
294 bc->ncf++;
295 bc->ndw += 2;
296 bc->force_add_cf = 0;
297 bc->ar_loaded = 0;
298 return 0;
299 }
300
301 int r600_bytecode_add_output(struct r600_bytecode *bc, const struct r600_bytecode_output *output)
302 {
303 int r;
304
305 if (output->gpr >= bc->ngpr)
306 bc->ngpr = output->gpr + 1;
307
308 if (bc->cf_last && (bc->cf_last->inst == output->inst ||
309 (bc->cf_last->inst == BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT) &&
310 output->inst == BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE))) &&
311 output->type == bc->cf_last->output.type &&
312 output->elem_size == bc->cf_last->output.elem_size &&
313 output->swizzle_x == bc->cf_last->output.swizzle_x &&
314 output->swizzle_y == bc->cf_last->output.swizzle_y &&
315 output->swizzle_z == bc->cf_last->output.swizzle_z &&
316 output->swizzle_w == bc->cf_last->output.swizzle_w &&
317 (output->burst_count + bc->cf_last->output.burst_count) <= 16) {
318
319 if ((output->gpr + output->burst_count) == bc->cf_last->output.gpr &&
320 (output->array_base + output->burst_count) == bc->cf_last->output.array_base) {
321
322 bc->cf_last->output.end_of_program |= output->end_of_program;
323 bc->cf_last->output.inst = output->inst;
324 bc->cf_last->output.gpr = output->gpr;
325 bc->cf_last->output.array_base = output->array_base;
326 bc->cf_last->output.burst_count += output->burst_count;
327 return 0;
328
329 } else if (output->gpr == (bc->cf_last->output.gpr + bc->cf_last->output.burst_count) &&
330 output->array_base == (bc->cf_last->output.array_base + bc->cf_last->output.burst_count)) {
331
332 bc->cf_last->output.end_of_program |= output->end_of_program;
333 bc->cf_last->output.inst = output->inst;
334 bc->cf_last->output.burst_count += output->burst_count;
335 return 0;
336 }
337 }
338
339 r = r600_bytecode_add_cf(bc);
340 if (r)
341 return r;
342 bc->cf_last->inst = output->inst;
343 memcpy(&bc->cf_last->output, output, sizeof(struct r600_bytecode_output));
344 return 0;
345 }
346
347 /* alu instructions that can ony exits once per group */
348 static int is_alu_once_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
349 {
350 switch (bc->chip_class) {
351 case R600:
352 case R700:
353 return !alu->is_op3 && (
354 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
355 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
356 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
357 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
358 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
359 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
360 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
361 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
362 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
363 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
364 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
365 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
366 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
367 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
368 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
369 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
370 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
371 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
372 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
373 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
374 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
375 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
376 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
377 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
378 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
379 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
380 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
381 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
382 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
383 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
384 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
385 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
386 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
387 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
388 case EVERGREEN:
389 case CAYMAN:
390 default:
391 return !alu->is_op3 && (
392 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
393 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
394 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
395 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
396 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
397 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
398 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
399 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
400 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
401 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
402 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
403 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
404 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
405 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
406 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
407 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
408 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
409 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
410 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
411 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
412 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
413 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
414 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
415 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
416 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
417 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
418 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
419 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
420 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
421 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
422 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
423 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
424 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
425 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
426 }
427 }
428
429 static int is_alu_reduction_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
430 {
431 switch (bc->chip_class) {
432 case R600:
433 case R700:
434 return !alu->is_op3 && (
435 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
436 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
437 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
438 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
439 case EVERGREEN:
440 case CAYMAN:
441 default:
442 return !alu->is_op3 && (
443 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
444 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
445 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
446 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
447 }
448 }
449
450 static int is_alu_cube_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
451 {
452 switch (bc->chip_class) {
453 case R600:
454 case R700:
455 return !alu->is_op3 &&
456 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
457 case EVERGREEN:
458 case CAYMAN:
459 default:
460 return !alu->is_op3 &&
461 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
462 }
463 }
464
465 static int is_alu_mova_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
466 {
467 switch (bc->chip_class) {
468 case R600:
469 case R700:
470 return !alu->is_op3 && (
471 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA ||
472 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR ||
473 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT ||
474 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT);
475 case EVERGREEN:
476 case CAYMAN:
477 default:
478 return !alu->is_op3 && (
479 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
480 }
481 }
482
483 static int is_opcode_in_range(unsigned opcode, unsigned min, unsigned max)
484 {
485 return min <= opcode && opcode <= max;
486 }
487
488 /* ALU instructions that can only execute on the vector unit:
489 *
490 * opcode ranges:
491 * R6xx/R7xx:
492 * op3 : [0x08 - 0x0B]
493 * op2 : 0x07, [0x15 - 0x18], [0x1B - 0x1D], [0x50 - 0x53], [0x7A - 0x7E]
494 *
495 * EVERGREEN:
496 * op3: [0x04 - 0x11]
497 * op2: [0xA0 - 0xE2]
498 */
499 static int is_alu_vec_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
500 {
501 switch (bc->chip_class) {
502 case R600:
503 case R700:
504 if (alu->is_op3)
505 return is_opcode_in_range(alu->inst,
506 V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_64,
507 V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_64_D2);
508 else
509 return (alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FREXP_64) ||
510 is_opcode_in_range(alu->inst,
511 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA,
512 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT) ||
513 is_opcode_in_range(alu->inst,
514 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_64,
515 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT32_TO_FLT64) ||
516 is_opcode_in_range(alu->inst,
517 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4,
518 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4) ||
519 is_opcode_in_range(alu->inst,
520 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LDEXP_64,
521 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_64);
522
523 case EVERGREEN:
524 if (alu->is_op3)
525 return is_opcode_in_range(alu->inst,
526 EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_BFE_UINT,
527 EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_LDS_IDX_OP);
528 else
529 return is_opcode_in_range(alu->inst,
530 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_BFM_INT,
531 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_LOAD_P20);
532 case CAYMAN:
533 default:
534 assert(0);
535 return 0;
536 }
537 }
538
539 /* ALU instructions that can only execute on the trans unit:
540 *
541 * opcode ranges:
542 * R600:
543 * op3: 0x0C
544 * op2: [0x60 - 0x79]
545 *
546 * R700:
547 * op3: 0x0C
548 * op2: [0x60 - 0x6F], [0x73 - 0x79]
549 *
550 * EVERGREEN:
551 * op3: 0x1F
552 * op2: [0x81 - 0x9C]
553 */
554 static int is_alu_trans_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
555 {
556
557 switch (bc->chip_class) {
558 case R600:
559 if (alu->is_op3)
560 return alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
561 else
562 return is_opcode_in_range(alu->inst,
563 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT,
564 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT);
565 case R700:
566 if (alu->is_op3)
567 return alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
568 else
569 return is_opcode_in_range(alu->inst,
570 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT,
571 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS) ||
572 is_opcode_in_range(alu->inst,
573 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT,
574 V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT);
575 case EVERGREEN:
576 if (alu->is_op3)
577 return alu->inst == EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
578 else
579 return is_opcode_in_range(alu->inst,
580 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE,
581 EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT);
582 case CAYMAN:
583 default:
584 assert(0);
585 return 0;
586 }
587 }
588
589 /* alu instructions that can execute on any unit */
590 static int is_alu_any_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
591 {
592 return !is_alu_vec_unit_inst(bc, alu) &&
593 !is_alu_trans_unit_inst(bc, alu);
594 }
595
596 static int is_nop_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
597 {
598 switch (bc->chip_class) {
599 case R600:
600 case R700:
601 return (!alu->is_op3 && alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
602 case EVERGREEN:
603 case CAYMAN:
604 default:
605 return (!alu->is_op3 && alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
606 }
607 }
608
609 static int assign_alu_units(struct r600_bytecode *bc, struct r600_bytecode_alu *alu_first,
610 struct r600_bytecode_alu *assignment[5])
611 {
612 struct r600_bytecode_alu *alu;
613 unsigned i, chan, trans;
614 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
615
616 for (i = 0; i < max_slots; i++)
617 assignment[i] = NULL;
618
619 for (alu = alu_first; alu; alu = LIST_ENTRY(struct r600_bytecode_alu, alu->list.next, list)) {
620 chan = alu->dst.chan;
621 if (max_slots == 4)
622 trans = 0;
623 else if (is_alu_trans_unit_inst(bc, alu))
624 trans = 1;
625 else if (is_alu_vec_unit_inst(bc, alu))
626 trans = 0;
627 else if (assignment[chan])
628 trans = 1; /* Assume ALU_INST_PREFER_VECTOR. */
629 else
630 trans = 0;
631
632 if (trans) {
633 if (assignment[4]) {
634 assert(0); /* ALU.Trans has already been allocated. */
635 return -1;
636 }
637 assignment[4] = alu;
638 } else {
639 if (assignment[chan]) {
640 assert(0); /* ALU.chan has already been allocated. */
641 return -1;
642 }
643 assignment[chan] = alu;
644 }
645
646 if (alu->last)
647 break;
648 }
649 return 0;
650 }
651
652 struct alu_bank_swizzle {
653 int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
654 int hw_cfile_addr[4];
655 int hw_cfile_elem[4];
656 };
657
658 static const unsigned cycle_for_bank_swizzle_vec[][3] = {
659 [SQ_ALU_VEC_012] = { 0, 1, 2 },
660 [SQ_ALU_VEC_021] = { 0, 2, 1 },
661 [SQ_ALU_VEC_120] = { 1, 2, 0 },
662 [SQ_ALU_VEC_102] = { 1, 0, 2 },
663 [SQ_ALU_VEC_201] = { 2, 0, 1 },
664 [SQ_ALU_VEC_210] = { 2, 1, 0 }
665 };
666
667 static const unsigned cycle_for_bank_swizzle_scl[][3] = {
668 [SQ_ALU_SCL_210] = { 2, 1, 0 },
669 [SQ_ALU_SCL_122] = { 1, 2, 2 },
670 [SQ_ALU_SCL_212] = { 2, 1, 2 },
671 [SQ_ALU_SCL_221] = { 2, 2, 1 }
672 };
673
674 static void init_bank_swizzle(struct alu_bank_swizzle *bs)
675 {
676 int i, cycle, component;
677 /* set up gpr use */
678 for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
679 for (component = 0; component < NUM_OF_COMPONENTS; component++)
680 bs->hw_gpr[cycle][component] = -1;
681 for (i = 0; i < 4; i++)
682 bs->hw_cfile_addr[i] = -1;
683 for (i = 0; i < 4; i++)
684 bs->hw_cfile_elem[i] = -1;
685 }
686
687 static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan, unsigned cycle)
688 {
689 if (bs->hw_gpr[cycle][chan] == -1)
690 bs->hw_gpr[cycle][chan] = sel;
691 else if (bs->hw_gpr[cycle][chan] != (int)sel) {
692 /* Another scalar operation has already used the GPR read port for the channel. */
693 return -1;
694 }
695 return 0;
696 }
697
698 static int reserve_cfile(struct r600_bytecode *bc, struct alu_bank_swizzle *bs, unsigned sel, unsigned chan)
699 {
700 int res, num_res = 4;
701 if (bc->chip_class >= R700) {
702 num_res = 2;
703 chan /= 2;
704 }
705 for (res = 0; res < num_res; ++res) {
706 if (bs->hw_cfile_addr[res] == -1) {
707 bs->hw_cfile_addr[res] = sel;
708 bs->hw_cfile_elem[res] = chan;
709 return 0;
710 } else if (bs->hw_cfile_addr[res] == sel &&
711 bs->hw_cfile_elem[res] == chan)
712 return 0; /* Read for this scalar element already reserved, nothing to do here. */
713 }
714 /* All cfile read ports are used, cannot reference vector element. */
715 return -1;
716 }
717
718 static int is_gpr(unsigned sel)
719 {
720 return (sel >= 0 && sel <= 127);
721 }
722
723 /* CB constants start at 512, and get translated to a kcache index when ALU
724 * clauses are constructed. Note that we handle kcache constants the same way
725 * as (the now gone) cfile constants, is that really required? */
726 static int is_cfile(unsigned sel)
727 {
728 return (sel > 255 && sel < 512) ||
729 (sel > 511 && sel < 4607) || /* Kcache before translation. */
730 (sel > 127 && sel < 192); /* Kcache after translation. */
731 }
732
733 static int is_const(int sel)
734 {
735 return is_cfile(sel) ||
736 (sel >= V_SQ_ALU_SRC_0 &&
737 sel <= V_SQ_ALU_SRC_LITERAL);
738 }
739
740 static int check_vector(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
741 struct alu_bank_swizzle *bs, int bank_swizzle)
742 {
743 int r, src, num_src, sel, elem, cycle;
744
745 num_src = r600_bytecode_get_num_operands(bc, alu);
746 for (src = 0; src < num_src; src++) {
747 sel = alu->src[src].sel;
748 elem = alu->src[src].chan;
749 if (is_gpr(sel)) {
750 cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src];
751 if (src == 1 && sel == alu->src[0].sel && elem == alu->src[0].chan)
752 /* Nothing to do; special-case optimization,
753 * second source uses first source’s reservation. */
754 continue;
755 else {
756 r = reserve_gpr(bs, sel, elem, cycle);
757 if (r)
758 return r;
759 }
760 } else if (is_cfile(sel)) {
761 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
762 if (r)
763 return r;
764 }
765 /* No restrictions on PV, PS, literal or special constants. */
766 }
767 return 0;
768 }
769
770 static int check_scalar(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
771 struct alu_bank_swizzle *bs, int bank_swizzle)
772 {
773 int r, src, num_src, const_count, sel, elem, cycle;
774
775 num_src = r600_bytecode_get_num_operands(bc, alu);
776 for (const_count = 0, src = 0; src < num_src; ++src) {
777 sel = alu->src[src].sel;
778 elem = alu->src[src].chan;
779 if (is_const(sel)) { /* Any constant, including literal and inline constants. */
780 if (const_count >= 2)
781 /* More than two references to a constant in
782 * transcendental operation. */
783 return -1;
784 else
785 const_count++;
786 }
787 if (is_cfile(sel)) {
788 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
789 if (r)
790 return r;
791 }
792 }
793 for (src = 0; src < num_src; ++src) {
794 sel = alu->src[src].sel;
795 elem = alu->src[src].chan;
796 if (is_gpr(sel)) {
797 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
798 if (cycle < const_count)
799 /* Cycle for GPR load conflicts with
800 * constant load in transcendental operation. */
801 return -1;
802 r = reserve_gpr(bs, sel, elem, cycle);
803 if (r)
804 return r;
805 }
806 /* PV PS restrictions */
807 if (const_count && (sel == 254 || sel == 255)) {
808 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
809 if (cycle < const_count)
810 return -1;
811 }
812 }
813 return 0;
814 }
815
816 static int check_and_set_bank_swizzle(struct r600_bytecode *bc,
817 struct r600_bytecode_alu *slots[5])
818 {
819 struct alu_bank_swizzle bs;
820 int bank_swizzle[5];
821 int i, r = 0, forced = 1;
822 boolean scalar_only = bc->chip_class == CAYMAN ? false : true;
823 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
824
825 for (i = 0; i < max_slots; i++) {
826 if (slots[i]) {
827 if (slots[i]->bank_swizzle_force) {
828 slots[i]->bank_swizzle = slots[i]->bank_swizzle_force;
829 } else {
830 forced = 0;
831 }
832 }
833
834 if (i < 4 && slots[i])
835 scalar_only = false;
836 }
837 if (forced)
838 return 0;
839
840 /* Just check every possible combination of bank swizzle.
841 * Not very efficent, but works on the first try in most of the cases. */
842 for (i = 0; i < 4; i++)
843 if (!slots[i] || !slots[i]->bank_swizzle_force)
844 bank_swizzle[i] = SQ_ALU_VEC_012;
845 else
846 bank_swizzle[i] = slots[i]->bank_swizzle;
847
848 bank_swizzle[4] = SQ_ALU_SCL_210;
849 while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
850
851 if (max_slots == 4) {
852 for (i = 0; i < max_slots; i++) {
853 if (bank_swizzle[i] == SQ_ALU_VEC_210)
854 return -1;
855 }
856 }
857 init_bank_swizzle(&bs);
858 if (scalar_only == false) {
859 for (i = 0; i < 4; i++) {
860 if (slots[i]) {
861 r = check_vector(bc, slots[i], &bs, bank_swizzle[i]);
862 if (r)
863 break;
864 }
865 }
866 } else
867 r = 0;
868
869 if (!r && slots[4] && max_slots == 5) {
870 r = check_scalar(bc, slots[4], &bs, bank_swizzle[4]);
871 }
872 if (!r) {
873 for (i = 0; i < max_slots; i++) {
874 if (slots[i])
875 slots[i]->bank_swizzle = bank_swizzle[i];
876 }
877 return 0;
878 }
879
880 if (scalar_only) {
881 bank_swizzle[4]++;
882 } else {
883 for (i = 0; i < max_slots; i++) {
884 if (!slots[i] || !slots[i]->bank_swizzle_force) {
885 bank_swizzle[i]++;
886 if (bank_swizzle[i] <= SQ_ALU_VEC_210)
887 break;
888 else
889 bank_swizzle[i] = SQ_ALU_VEC_012;
890 }
891 }
892 }
893 }
894
895 /* Couldn't find a working swizzle. */
896 return -1;
897 }
898
899 static int replace_gpr_with_pv_ps(struct r600_bytecode *bc,
900 struct r600_bytecode_alu *slots[5], struct r600_bytecode_alu *alu_prev)
901 {
902 struct r600_bytecode_alu *prev[5];
903 int gpr[5], chan[5];
904 int i, j, r, src, num_src;
905 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
906
907 r = assign_alu_units(bc, alu_prev, prev);
908 if (r)
909 return r;
910
911 for (i = 0; i < max_slots; ++i) {
912 if (prev[i] && (prev[i]->dst.write || prev[i]->is_op3) && !prev[i]->dst.rel) {
913 gpr[i] = prev[i]->dst.sel;
914 /* cube writes more than PV.X */
915 if (!is_alu_cube_inst(bc, prev[i]) && is_alu_reduction_inst(bc, prev[i]))
916 chan[i] = 0;
917 else
918 chan[i] = prev[i]->dst.chan;
919 } else
920 gpr[i] = -1;
921 }
922
923 for (i = 0; i < max_slots; ++i) {
924 struct r600_bytecode_alu *alu = slots[i];
925 if(!alu)
926 continue;
927
928 num_src = r600_bytecode_get_num_operands(bc, alu);
929 for (src = 0; src < num_src; ++src) {
930 if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
931 continue;
932
933 if (bc->chip_class < CAYMAN) {
934 if (alu->src[src].sel == gpr[4] &&
935 alu->src[src].chan == chan[4] &&
936 alu_prev->pred_sel == alu->pred_sel) {
937 alu->src[src].sel = V_SQ_ALU_SRC_PS;
938 alu->src[src].chan = 0;
939 continue;
940 }
941 }
942
943 for (j = 0; j < 4; ++j) {
944 if (alu->src[src].sel == gpr[j] &&
945 alu->src[src].chan == j &&
946 alu_prev->pred_sel == alu->pred_sel) {
947 alu->src[src].sel = V_SQ_ALU_SRC_PV;
948 alu->src[src].chan = chan[j];
949 break;
950 }
951 }
952 }
953 }
954
955 return 0;
956 }
957
958 void r600_bytecode_special_constants(uint32_t value, unsigned *sel, unsigned *neg)
959 {
960 switch(value) {
961 case 0:
962 *sel = V_SQ_ALU_SRC_0;
963 break;
964 case 1:
965 *sel = V_SQ_ALU_SRC_1_INT;
966 break;
967 case -1:
968 *sel = V_SQ_ALU_SRC_M_1_INT;
969 break;
970 case 0x3F800000: /* 1.0f */
971 *sel = V_SQ_ALU_SRC_1;
972 break;
973 case 0x3F000000: /* 0.5f */
974 *sel = V_SQ_ALU_SRC_0_5;
975 break;
976 case 0xBF800000: /* -1.0f */
977 *sel = V_SQ_ALU_SRC_1;
978 *neg ^= 1;
979 break;
980 case 0xBF000000: /* -0.5f */
981 *sel = V_SQ_ALU_SRC_0_5;
982 *neg ^= 1;
983 break;
984 default:
985 *sel = V_SQ_ALU_SRC_LITERAL;
986 break;
987 }
988 }
989
990 /* compute how many literal are needed */
991 static int r600_bytecode_alu_nliterals(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
992 uint32_t literal[4], unsigned *nliteral)
993 {
994 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
995 unsigned i, j;
996
997 for (i = 0; i < num_src; ++i) {
998 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
999 uint32_t value = alu->src[i].value;
1000 unsigned found = 0;
1001 for (j = 0; j < *nliteral; ++j) {
1002 if (literal[j] == value) {
1003 found = 1;
1004 break;
1005 }
1006 }
1007 if (!found) {
1008 if (*nliteral >= 4)
1009 return -EINVAL;
1010 literal[(*nliteral)++] = value;
1011 }
1012 }
1013 }
1014 return 0;
1015 }
1016
1017 static void r600_bytecode_alu_adjust_literals(struct r600_bytecode *bc,
1018 struct r600_bytecode_alu *alu,
1019 uint32_t literal[4], unsigned nliteral)
1020 {
1021 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
1022 unsigned i, j;
1023
1024 for (i = 0; i < num_src; ++i) {
1025 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1026 uint32_t value = alu->src[i].value;
1027 for (j = 0; j < nliteral; ++j) {
1028 if (literal[j] == value) {
1029 alu->src[i].chan = j;
1030 break;
1031 }
1032 }
1033 }
1034 }
1035 }
1036
1037 static int merge_inst_groups(struct r600_bytecode *bc, struct r600_bytecode_alu *slots[5],
1038 struct r600_bytecode_alu *alu_prev)
1039 {
1040 struct r600_bytecode_alu *prev[5];
1041 struct r600_bytecode_alu *result[5] = { NULL };
1042
1043 uint32_t literal[4], prev_literal[4];
1044 unsigned nliteral = 0, prev_nliteral = 0;
1045
1046 int i, j, r, src, num_src;
1047 int num_once_inst = 0;
1048 int have_mova = 0, have_rel = 0;
1049 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
1050
1051 r = assign_alu_units(bc, alu_prev, prev);
1052 if (r)
1053 return r;
1054
1055 for (i = 0; i < max_slots; ++i) {
1056 if (prev[i]) {
1057 if (prev[i]->pred_sel)
1058 return 0;
1059 if (is_alu_once_inst(bc, prev[i]))
1060 return 0;
1061 }
1062 if (slots[i]) {
1063 if (slots[i]->pred_sel)
1064 return 0;
1065 if (is_alu_once_inst(bc, slots[i]))
1066 return 0;
1067 }
1068 }
1069
1070 for (i = 0; i < max_slots; ++i) {
1071 struct r600_bytecode_alu *alu;
1072
1073 if (num_once_inst > 0)
1074 return 0;
1075
1076 /* check number of literals */
1077 if (prev[i]) {
1078 if (r600_bytecode_alu_nliterals(bc, prev[i], literal, &nliteral))
1079 return 0;
1080 if (r600_bytecode_alu_nliterals(bc, prev[i], prev_literal, &prev_nliteral))
1081 return 0;
1082 if (is_alu_mova_inst(bc, prev[i])) {
1083 if (have_rel)
1084 return 0;
1085 have_mova = 1;
1086 }
1087 num_once_inst += is_alu_once_inst(bc, prev[i]);
1088 }
1089 if (slots[i] && r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral))
1090 return 0;
1091
1092 /* Let's check used slots. */
1093 if (prev[i] && !slots[i]) {
1094 result[i] = prev[i];
1095 continue;
1096 } else if (prev[i] && slots[i]) {
1097 if (max_slots == 5 && result[4] == NULL && prev[4] == NULL && slots[4] == NULL) {
1098 /* Trans unit is still free try to use it. */
1099 if (is_alu_any_unit_inst(bc, slots[i])) {
1100 result[i] = prev[i];
1101 result[4] = slots[i];
1102 } else if (is_alu_any_unit_inst(bc, prev[i])) {
1103 if (slots[i]->dst.sel == prev[i]->dst.sel &&
1104 (slots[i]->dst.write == 1 || slots[i]->is_op3) &&
1105 (prev[i]->dst.write == 1 || prev[i]->is_op3))
1106 return 0;
1107
1108 result[i] = slots[i];
1109 result[4] = prev[i];
1110 } else
1111 return 0;
1112 } else
1113 return 0;
1114 } else if(!slots[i]) {
1115 continue;
1116 } else {
1117 if (max_slots == 5 && slots[i] && prev[4] &&
1118 slots[i]->dst.sel == prev[4]->dst.sel &&
1119 slots[i]->dst.chan == prev[4]->dst.chan &&
1120 (slots[i]->dst.write == 1 || slots[i]->is_op3) &&
1121 (prev[4]->dst.write == 1 || prev[4]->is_op3))
1122 return 0;
1123
1124 result[i] = slots[i];
1125 }
1126
1127 alu = slots[i];
1128 num_once_inst += is_alu_once_inst(bc, alu);
1129
1130 /* don't reschedule NOPs */
1131 if (is_nop_inst(bc, alu))
1132 return 0;
1133
1134 /* Let's check dst gpr. */
1135 if (alu->dst.rel) {
1136 if (have_mova)
1137 return 0;
1138 have_rel = 1;
1139 }
1140
1141 /* Let's check source gprs */
1142 num_src = r600_bytecode_get_num_operands(bc, alu);
1143 for (src = 0; src < num_src; ++src) {
1144 if (alu->src[src].rel) {
1145 if (have_mova)
1146 return 0;
1147 have_rel = 1;
1148 }
1149
1150 /* Constants don't matter. */
1151 if (!is_gpr(alu->src[src].sel))
1152 continue;
1153
1154 for (j = 0; j < max_slots; ++j) {
1155 if (!prev[j] || !(prev[j]->dst.write || prev[j]->is_op3))
1156 continue;
1157
1158 /* If it's relative then we can't determin which gpr is really used. */
1159 if (prev[j]->dst.chan == alu->src[src].chan &&
1160 (prev[j]->dst.sel == alu->src[src].sel ||
1161 prev[j]->dst.rel || alu->src[src].rel))
1162 return 0;
1163 }
1164 }
1165 }
1166
1167 /* more than one PRED_ or KILL_ ? */
1168 if (num_once_inst > 1)
1169 return 0;
1170
1171 /* check if the result can still be swizzlet */
1172 r = check_and_set_bank_swizzle(bc, result);
1173 if (r)
1174 return 0;
1175
1176 /* looks like everything worked out right, apply the changes */
1177
1178 /* undo adding previus literals */
1179 bc->cf_last->ndw -= align(prev_nliteral, 2);
1180
1181 /* sort instructions */
1182 for (i = 0; i < max_slots; ++i) {
1183 slots[i] = result[i];
1184 if (result[i]) {
1185 LIST_DEL(&result[i]->list);
1186 result[i]->last = 0;
1187 LIST_ADDTAIL(&result[i]->list, &bc->cf_last->alu);
1188 }
1189 }
1190
1191 /* determine new last instruction */
1192 LIST_ENTRY(struct r600_bytecode_alu, bc->cf_last->alu.prev, list)->last = 1;
1193
1194 /* determine new first instruction */
1195 for (i = 0; i < max_slots; ++i) {
1196 if (result[i]) {
1197 bc->cf_last->curr_bs_head = result[i];
1198 break;
1199 }
1200 }
1201
1202 bc->cf_last->prev_bs_head = bc->cf_last->prev2_bs_head;
1203 bc->cf_last->prev2_bs_head = NULL;
1204
1205 return 0;
1206 }
1207
1208 /* we'll keep kcache sets sorted by bank & addr */
1209 static int r600_bytecode_alloc_kcache_line(struct r600_bytecode *bc,
1210 struct r600_bytecode_kcache *kcache,
1211 unsigned bank, unsigned line)
1212 {
1213 int i, kcache_banks = bc->chip_class >= EVERGREEN ? 4 : 2;
1214
1215 for (i = 0; i < kcache_banks; i++) {
1216 if (kcache[i].mode) {
1217 int d;
1218
1219 if (kcache[i].bank < bank)
1220 continue;
1221
1222 if ((kcache[i].bank == bank && kcache[i].addr > line+1) ||
1223 kcache[i].bank > bank) {
1224 /* try to insert new line */
1225 if (kcache[kcache_banks-1].mode) {
1226 /* all sets are in use */
1227 return -ENOMEM;
1228 }
1229
1230 memmove(&kcache[i+1],&kcache[i], (kcache_banks-i-1)*sizeof(struct r600_bytecode_kcache));
1231 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
1232 kcache[i].bank = bank;
1233 kcache[i].addr = line;
1234 return 0;
1235 }
1236
1237 d = line - kcache[i].addr;
1238
1239 if (d == -1) {
1240 kcache[i].addr--;
1241 if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_2) {
1242 /* we are prepending the line to the current set,
1243 * discarding the existing second line,
1244 * so we'll have to insert line+2 after it */
1245 line += 2;
1246 continue;
1247 } else if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_1) {
1248 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
1249 return 0;
1250 } else {
1251 /* V_SQ_CF_KCACHE_LOCK_LOOP_INDEX is not supported */
1252 return -ENOMEM;
1253 }
1254 } else if (d == 1) {
1255 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
1256 return 0;
1257 } else if (d == 0)
1258 return 0;
1259 } else { /* free kcache set - use it */
1260 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
1261 kcache[i].bank = bank;
1262 kcache[i].addr = line;
1263 return 0;
1264 }
1265 }
1266 return -ENOMEM;
1267 }
1268
1269 static int r600_bytecode_alloc_inst_kcache_lines(struct r600_bytecode *bc,
1270 struct r600_bytecode_kcache *kcache,
1271 struct r600_bytecode_alu *alu)
1272 {
1273 int i, r;
1274
1275 for (i = 0; i < 3; i++) {
1276 unsigned bank, line, sel = alu->src[i].sel;
1277
1278 if (sel < 512)
1279 continue;
1280
1281 bank = alu->src[i].kc_bank;
1282 line = (sel-512)>>4;
1283
1284 if ((r = r600_bytecode_alloc_kcache_line(bc, kcache, bank, line)))
1285 return r;
1286 }
1287 return 0;
1288 }
1289
1290 static int r600_bytecode_assign_kcache_banks(struct r600_bytecode *bc,
1291 struct r600_bytecode_alu *alu,
1292 struct r600_bytecode_kcache * kcache)
1293 {
1294 int i, j;
1295
1296 /* Alter the src operands to refer to the kcache. */
1297 for (i = 0; i < 3; ++i) {
1298 static const unsigned int base[] = {128, 160, 256, 288};
1299 unsigned int line, sel = alu->src[i].sel, found = 0;
1300
1301 if (sel < 512)
1302 continue;
1303
1304 sel -= 512;
1305 line = sel>>4;
1306
1307 for (j = 0; j < 4 && !found; ++j) {
1308 switch (kcache[j].mode) {
1309 case V_SQ_CF_KCACHE_NOP:
1310 case V_SQ_CF_KCACHE_LOCK_LOOP_INDEX:
1311 R600_ERR("unexpected kcache line mode\n");
1312 return -ENOMEM;
1313 default:
1314 if (kcache[j].bank == alu->src[i].kc_bank &&
1315 kcache[j].addr <= line &&
1316 line < kcache[j].addr + kcache[j].mode) {
1317 alu->src[i].sel = sel - (kcache[j].addr<<4);
1318 alu->src[i].sel += base[j];
1319 found=1;
1320 }
1321 }
1322 }
1323 }
1324 return 0;
1325 }
1326
1327 static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, int type)
1328 {
1329 struct r600_bytecode_kcache kcache_sets[4];
1330 struct r600_bytecode_kcache *kcache = kcache_sets;
1331 int r;
1332
1333 memcpy(kcache, bc->cf_last->kcache, 4 * sizeof(struct r600_bytecode_kcache));
1334
1335 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1336 /* can't alloc, need to start new clause */
1337 if ((r = r600_bytecode_add_cf(bc))) {
1338 return r;
1339 }
1340 bc->cf_last->inst = type;
1341
1342 /* retry with the new clause */
1343 kcache = bc->cf_last->kcache;
1344 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1345 /* can't alloc again- should never happen */
1346 return r;
1347 }
1348 } else {
1349 /* update kcache sets */
1350 memcpy(bc->cf_last->kcache, kcache, 4 * sizeof(struct r600_bytecode_kcache));
1351 }
1352
1353 /* if we actually used more than 2 kcache sets - use ALU_EXTENDED on eg+ */
1354 if (kcache[2].mode != V_SQ_CF_KCACHE_NOP) {
1355 if (bc->chip_class < EVERGREEN)
1356 return -ENOMEM;
1357 bc->cf_last->eg_alu_extended = 1;
1358 }
1359
1360 return 0;
1361 }
1362
1363 static int insert_nop_r6xx(struct r600_bytecode *bc)
1364 {
1365 struct r600_bytecode_alu alu;
1366 int r, i;
1367
1368 for (i = 0; i < 4; i++) {
1369 memset(&alu, 0, sizeof(alu));
1370 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP;
1371 alu.src[0].chan = i;
1372 alu.dst.chan = i;
1373 alu.last = (i == 3);
1374 r = r600_bytecode_add_alu(bc, &alu);
1375 if (r)
1376 return r;
1377 }
1378 return 0;
1379 }
1380
1381 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1382 static int load_ar_r6xx(struct r600_bytecode *bc)
1383 {
1384 struct r600_bytecode_alu alu;
1385 int r;
1386
1387 if (bc->ar_loaded)
1388 return 0;
1389
1390 /* hack to avoid making MOVA the last instruction in the clause */
1391 if ((bc->cf_last->ndw>>1) >= 110)
1392 bc->force_add_cf = 1;
1393
1394 memset(&alu, 0, sizeof(alu));
1395 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT;
1396 alu.src[0].sel = bc->ar_reg;
1397 alu.last = 1;
1398 alu.index_mode = INDEX_MODE_LOOP;
1399 r = r600_bytecode_add_alu(bc, &alu);
1400 if (r)
1401 return r;
1402
1403 /* no requirement to set uses waterfall on MOVA_GPR_INT */
1404 bc->ar_loaded = 1;
1405 return 0;
1406 }
1407
1408 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1409 static int load_ar(struct r600_bytecode *bc)
1410 {
1411 struct r600_bytecode_alu alu;
1412 int r;
1413
1414 if (bc->ar_handling)
1415 return load_ar_r6xx(bc);
1416
1417 if (bc->ar_loaded)
1418 return 0;
1419
1420 /* hack to avoid making MOVA the last instruction in the clause */
1421 if ((bc->cf_last->ndw>>1) >= 110)
1422 bc->force_add_cf = 1;
1423
1424 memset(&alu, 0, sizeof(alu));
1425 alu.inst = BC_INST(bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
1426 alu.src[0].sel = bc->ar_reg;
1427 alu.last = 1;
1428 r = r600_bytecode_add_alu(bc, &alu);
1429 if (r)
1430 return r;
1431
1432 bc->cf_last->r6xx_uses_waterfall = 1;
1433 bc->ar_loaded = 1;
1434 return 0;
1435 }
1436
1437 int r600_bytecode_add_alu_type(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu, int type)
1438 {
1439 struct r600_bytecode_alu *nalu = r600_bytecode_alu();
1440 struct r600_bytecode_alu *lalu;
1441 int i, r;
1442
1443 if (nalu == NULL)
1444 return -ENOMEM;
1445 memcpy(nalu, alu, sizeof(struct r600_bytecode_alu));
1446
1447 if (bc->cf_last != NULL && bc->cf_last->inst != type) {
1448 /* check if we could add it anyway */
1449 if (bc->cf_last->inst == BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU) &&
1450 type == BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE)) {
1451 LIST_FOR_EACH_ENTRY(lalu, &bc->cf_last->alu, list) {
1452 if (lalu->execute_mask) {
1453 bc->force_add_cf = 1;
1454 break;
1455 }
1456 }
1457 } else
1458 bc->force_add_cf = 1;
1459 }
1460
1461 /* cf can contains only alu or only vtx or only tex */
1462 if (bc->cf_last == NULL || bc->force_add_cf) {
1463 r = r600_bytecode_add_cf(bc);
1464 if (r) {
1465 free(nalu);
1466 return r;
1467 }
1468 }
1469 bc->cf_last->inst = type;
1470
1471 /* Check AR usage and load it if required */
1472 for (i = 0; i < 3; i++)
1473 if (nalu->src[i].rel && !bc->ar_loaded)
1474 load_ar(bc);
1475
1476 if (nalu->dst.rel && !bc->ar_loaded)
1477 load_ar(bc);
1478
1479 /* Setup the kcache for this ALU instruction. This will start a new
1480 * ALU clause if needed. */
1481 if ((r = r600_bytecode_alloc_kcache_lines(bc, nalu, type))) {
1482 free(nalu);
1483 return r;
1484 }
1485
1486 if (!bc->cf_last->curr_bs_head) {
1487 bc->cf_last->curr_bs_head = nalu;
1488 }
1489 /* number of gpr == the last gpr used in any alu */
1490 for (i = 0; i < 3; i++) {
1491 if (nalu->src[i].sel >= bc->ngpr && nalu->src[i].sel < 128) {
1492 bc->ngpr = nalu->src[i].sel + 1;
1493 }
1494 if (nalu->src[i].sel == V_SQ_ALU_SRC_LITERAL)
1495 r600_bytecode_special_constants(nalu->src[i].value,
1496 &nalu->src[i].sel, &nalu->src[i].neg);
1497 }
1498 if (nalu->dst.sel >= bc->ngpr) {
1499 bc->ngpr = nalu->dst.sel + 1;
1500 }
1501 LIST_ADDTAIL(&nalu->list, &bc->cf_last->alu);
1502 /* each alu use 2 dwords */
1503 bc->cf_last->ndw += 2;
1504 bc->ndw += 2;
1505
1506 /* process cur ALU instructions for bank swizzle */
1507 if (nalu->last) {
1508 uint32_t literal[4];
1509 unsigned nliteral;
1510 struct r600_bytecode_alu *slots[5];
1511 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
1512 r = assign_alu_units(bc, bc->cf_last->curr_bs_head, slots);
1513 if (r)
1514 return r;
1515
1516 if (bc->cf_last->prev_bs_head) {
1517 r = merge_inst_groups(bc, slots, bc->cf_last->prev_bs_head);
1518 if (r)
1519 return r;
1520 }
1521
1522 if (bc->cf_last->prev_bs_head) {
1523 r = replace_gpr_with_pv_ps(bc, slots, bc->cf_last->prev_bs_head);
1524 if (r)
1525 return r;
1526 }
1527
1528 r = check_and_set_bank_swizzle(bc, slots);
1529 if (r)
1530 return r;
1531
1532 for (i = 0, nliteral = 0; i < max_slots; i++) {
1533 if (slots[i]) {
1534 r = r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral);
1535 if (r)
1536 return r;
1537 }
1538 }
1539 bc->cf_last->ndw += align(nliteral, 2);
1540
1541 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1542 * worst case */
1543 if ((bc->cf_last->ndw >> 1) >= 120) {
1544 bc->force_add_cf = 1;
1545 }
1546
1547 bc->cf_last->prev2_bs_head = bc->cf_last->prev_bs_head;
1548 bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head;
1549 bc->cf_last->curr_bs_head = NULL;
1550 }
1551
1552 if (nalu->dst.rel && bc->r6xx_nop_after_rel_dst)
1553 insert_nop_r6xx(bc);
1554
1555 return 0;
1556 }
1557
1558 int r600_bytecode_add_alu(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu)
1559 {
1560 return r600_bytecode_add_alu_type(bc, alu, BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
1561 }
1562
1563 static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode *bc)
1564 {
1565 switch (bc->chip_class) {
1566 case R600:
1567 return 8;
1568
1569 case R700:
1570 case EVERGREEN:
1571 case CAYMAN:
1572 return 16;
1573
1574 default:
1575 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1576 return 8;
1577 }
1578 }
1579
1580 static inline boolean last_inst_was_not_vtx_fetch(struct r600_bytecode *bc)
1581 {
1582 switch (bc->chip_class) {
1583 case R700:
1584 case R600:
1585 return bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX &&
1586 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC;
1587 case EVERGREEN:
1588 return bc->cf_last->inst != EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1589 case CAYMAN:
1590 return bc->cf_last->inst != CM_V_SQ_CF_WORD1_SQ_CF_INST_TC;
1591 default:
1592 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1593 return FALSE;
1594 }
1595 }
1596
1597 int r600_bytecode_add_vtx(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx)
1598 {
1599 struct r600_bytecode_vtx *nvtx = r600_bytecode_vtx();
1600 int r;
1601
1602 if (nvtx == NULL)
1603 return -ENOMEM;
1604 memcpy(nvtx, vtx, sizeof(struct r600_bytecode_vtx));
1605
1606 /* cf can contains only alu or only vtx or only tex */
1607 if (bc->cf_last == NULL ||
1608 last_inst_was_not_vtx_fetch(bc) ||
1609 bc->force_add_cf) {
1610 r = r600_bytecode_add_cf(bc);
1611 if (r) {
1612 free(nvtx);
1613 return r;
1614 }
1615 switch (bc->chip_class) {
1616 case R600:
1617 case R700:
1618 bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1619 break;
1620 case EVERGREEN:
1621 bc->cf_last->inst = EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1622 break;
1623 case CAYMAN:
1624 bc->cf_last->inst = CM_V_SQ_CF_WORD1_SQ_CF_INST_TC;
1625 break;
1626 default:
1627 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1628 free(nvtx);
1629 return -EINVAL;
1630 }
1631 }
1632 LIST_ADDTAIL(&nvtx->list, &bc->cf_last->vtx);
1633 /* each fetch use 4 dwords */
1634 bc->cf_last->ndw += 4;
1635 bc->ndw += 4;
1636 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1637 bc->force_add_cf = 1;
1638
1639 bc->ngpr = MAX2(bc->ngpr, vtx->src_gpr + 1);
1640 bc->ngpr = MAX2(bc->ngpr, vtx->dst_gpr + 1);
1641
1642 return 0;
1643 }
1644
1645 int r600_bytecode_add_tex(struct r600_bytecode *bc, const struct r600_bytecode_tex *tex)
1646 {
1647 struct r600_bytecode_tex *ntex = r600_bytecode_tex();
1648 int r;
1649
1650 if (ntex == NULL)
1651 return -ENOMEM;
1652 memcpy(ntex, tex, sizeof(struct r600_bytecode_tex));
1653
1654 /* we can't fetch data und use it as texture lookup address in the same TEX clause */
1655 if (bc->cf_last != NULL &&
1656 bc->cf_last->inst == BC_INST(bc, V_SQ_CF_WORD1_SQ_CF_INST_TEX)) {
1657 struct r600_bytecode_tex *ttex;
1658 LIST_FOR_EACH_ENTRY(ttex, &bc->cf_last->tex, list) {
1659 if (ttex->dst_gpr == ntex->src_gpr) {
1660 bc->force_add_cf = 1;
1661 break;
1662 }
1663 }
1664 /* slight hack to make gradients always go into same cf */
1665 if (ntex->inst == SQ_TEX_INST_SET_GRADIENTS_H)
1666 bc->force_add_cf = 1;
1667 }
1668
1669 /* cf can contains only alu or only vtx or only tex */
1670 if (bc->cf_last == NULL ||
1671 bc->cf_last->inst != BC_INST(bc, V_SQ_CF_WORD1_SQ_CF_INST_TEX) ||
1672 bc->force_add_cf) {
1673 r = r600_bytecode_add_cf(bc);
1674 if (r) {
1675 free(ntex);
1676 return r;
1677 }
1678 bc->cf_last->inst = BC_INST(bc, V_SQ_CF_WORD1_SQ_CF_INST_TEX);
1679 }
1680 if (ntex->src_gpr >= bc->ngpr) {
1681 bc->ngpr = ntex->src_gpr + 1;
1682 }
1683 if (ntex->dst_gpr >= bc->ngpr) {
1684 bc->ngpr = ntex->dst_gpr + 1;
1685 }
1686 LIST_ADDTAIL(&ntex->list, &bc->cf_last->tex);
1687 /* each texture fetch use 4 dwords */
1688 bc->cf_last->ndw += 4;
1689 bc->ndw += 4;
1690 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1691 bc->force_add_cf = 1;
1692 return 0;
1693 }
1694
1695 int r600_bytecode_add_cfinst(struct r600_bytecode *bc, int inst)
1696 {
1697 int r;
1698 r = r600_bytecode_add_cf(bc);
1699 if (r)
1700 return r;
1701
1702 bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
1703 bc->cf_last->inst = inst;
1704 return 0;
1705 }
1706
1707 int cm_bytecode_add_cf_end(struct r600_bytecode *bc)
1708 {
1709 return r600_bytecode_add_cfinst(bc, CM_V_SQ_CF_WORD1_SQ_CF_INST_END);
1710 }
1711
1712 /* common to all 3 families */
1713 static int r600_bytecode_vtx_build(struct r600_bytecode *bc, struct r600_bytecode_vtx *vtx, unsigned id)
1714 {
1715 bc->bytecode[id] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) |
1716 S_SQ_VTX_WORD0_FETCH_TYPE(vtx->fetch_type) |
1717 S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
1718 S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x);
1719 if (bc->chip_class < CAYMAN)
1720 bc->bytecode[id] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
1721 id++;
1722 bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
1723 S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
1724 S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
1725 S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
1726 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) |
1727 S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) |
1728 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) |
1729 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) |
1730 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
1731 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
1732 bc->bytecode[id] = S_SQ_VTX_WORD2_OFFSET(vtx->offset)|
1733 S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx->endian);
1734 if (bc->chip_class < CAYMAN)
1735 bc->bytecode[id] |= S_SQ_VTX_WORD2_MEGA_FETCH(1);
1736 id++;
1737 bc->bytecode[id++] = 0;
1738 return 0;
1739 }
1740
1741 /* common to all 3 families */
1742 static int r600_bytecode_tex_build(struct r600_bytecode *bc, struct r600_bytecode_tex *tex, unsigned id)
1743 {
1744 bc->bytecode[id++] = S_SQ_TEX_WORD0_TEX_INST(tex->inst) |
1745 EG_S_SQ_TEX_WORD0_INST_MOD(tex->inst_mod) |
1746 S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
1747 S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
1748 S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
1749 bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
1750 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
1751 S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
1752 S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
1753 S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
1754 S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
1755 S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
1756 S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
1757 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
1758 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
1759 S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
1760 bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
1761 S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
1762 S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
1763 S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
1764 S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
1765 S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
1766 S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
1767 S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
1768 bc->bytecode[id++] = 0;
1769 return 0;
1770 }
1771
1772 /* r600 only, r700/eg bits in r700_asm.c */
1773 static int r600_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id)
1774 {
1775 /* don't replace gpr by pv or ps for destination register */
1776 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
1777 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
1778 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
1779 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
1780 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
1781 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
1782 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
1783 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
1784 S_SQ_ALU_WORD0_INDEX_MODE(alu->index_mode) |
1785 S_SQ_ALU_WORD0_PRED_SEL(alu->pred_sel) |
1786 S_SQ_ALU_WORD0_LAST(alu->last);
1787
1788 if (alu->is_op3) {
1789 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1790 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1791 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1792 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1793 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
1794 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
1795 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
1796 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
1797 S_SQ_ALU_WORD1_OP3_ALU_INST(alu->inst) |
1798 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
1799 } else {
1800 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1801 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1802 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1803 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1804 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
1805 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
1806 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
1807 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
1808 S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
1809 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
1810 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->execute_mask) |
1811 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->update_pred);
1812 }
1813 return 0;
1814 }
1815
1816 static void r600_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_cf *cf)
1817 {
1818 *bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
1819 *bytecode++ = cf->inst |
1820 S_SQ_CF_WORD1_BARRIER(1) |
1821 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
1822 }
1823
1824 /* common for r600/r700 - eg in eg_asm.c */
1825 static int r600_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf)
1826 {
1827 unsigned id = cf->id;
1828
1829 switch (cf->inst) {
1830 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
1831 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
1832 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
1833 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
1834 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
1835 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
1836 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
1837 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank);
1838
1839 bc->bytecode[id++] = cf->inst |
1840 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) |
1841 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
1842 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
1843 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1844 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chip_class == R600 ? cf->r6xx_uses_waterfall : 0) |
1845 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
1846 break;
1847 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1848 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1849 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1850 if (bc->chip_class == R700)
1851 r700_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1852 else
1853 r600_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1854 break;
1855 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1856 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1857 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1858 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1859 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1860 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
1861 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1862 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
1863 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
1864 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
1865 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
1866 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
1867 cf->output.inst |
1868 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program);
1869 break;
1870 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
1871 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
1872 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
1873 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
1874 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1875 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1876 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1877 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
1878 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1879 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
1880 cf->output.inst |
1881 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program) |
1882 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf->output.array_size) |
1883 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf->output.comp_mask);
1884 break;
1885 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1886 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1887 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1888 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1889 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10:
1890 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1891 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1892 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1893 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1894 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1895 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
1896 bc->bytecode[id++] = cf->inst |
1897 S_SQ_CF_WORD1_BARRIER(1) |
1898 S_SQ_CF_WORD1_COND(cf->cond) |
1899 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count);
1900
1901 break;
1902 default:
1903 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1904 return -EINVAL;
1905 }
1906 return 0;
1907 }
1908
1909 int r600_bytecode_build(struct r600_bytecode *bc)
1910 {
1911 struct r600_bytecode_cf *cf;
1912 struct r600_bytecode_alu *alu;
1913 struct r600_bytecode_vtx *vtx;
1914 struct r600_bytecode_tex *tex;
1915 uint32_t literal[4];
1916 unsigned nliteral;
1917 unsigned addr;
1918 int i, r;
1919
1920 if (bc->callstack[0].max > 0)
1921 bc->nstack = ((bc->callstack[0].max + 3) >> 2) + 2;
1922 if (bc->type == TGSI_PROCESSOR_VERTEX && !bc->nstack) {
1923 bc->nstack = 1;
1924 }
1925
1926 /* first path compute addr of each CF block */
1927 /* addr start after all the CF instructions */
1928 addr = bc->cf_last->id + 2;
1929 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1930 if (bc->chip_class >= EVERGREEN) {
1931 switch (cf->inst) {
1932 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1933 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1934 /* fetch node need to be 16 bytes aligned*/
1935 addr += 3;
1936 addr &= 0xFFFFFFFCUL;
1937 break;
1938 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
1939 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
1940 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
1941 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
1942 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1943 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1944 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0:
1945 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1:
1946 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2:
1947 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3:
1948 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0:
1949 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1:
1950 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2:
1951 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3:
1952 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0:
1953 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1:
1954 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2:
1955 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3:
1956 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0:
1957 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1:
1958 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2:
1959 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3:
1960 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1961 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1962 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
1963 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1964 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10:
1965 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1966 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1967 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1968 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1969 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1970 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
1971 case CF_NATIVE:
1972 break;
1973 default:
1974 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1975 return -EINVAL;
1976 }
1977 } else {
1978 switch (cf->inst) {
1979 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1980 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1981 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1982 /* fetch node need to be 16 bytes aligned*/
1983 addr += 3;
1984 addr &= 0xFFFFFFFCUL;
1985 break;
1986 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
1987 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
1988 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
1989 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
1990 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1991 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1992 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
1993 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
1994 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
1995 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
1996 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1997 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1998 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1999 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10:
2000 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2001 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2002 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2003 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2004 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2005 break;
2006 default:
2007 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
2008 return -EINVAL;
2009 }
2010 }
2011 cf->addr = addr;
2012 addr += cf->ndw;
2013 bc->ndw = cf->addr + cf->ndw;
2014 }
2015 free(bc->bytecode);
2016 bc->bytecode = calloc(1, bc->ndw * 4);
2017 if (bc->bytecode == NULL)
2018 return -ENOMEM;
2019 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
2020 addr = cf->addr;
2021 if (bc->chip_class >= EVERGREEN) {
2022 r = eg_bytecode_cf_build(bc, cf);
2023 if (r)
2024 return r;
2025
2026 switch (cf->inst) {
2027 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
2028 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
2029 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
2030 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
2031 nliteral = 0;
2032 memset(literal, 0, sizeof(literal));
2033 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
2034 r = r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
2035 if (r)
2036 return r;
2037 r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral);
2038 r600_bytecode_assign_kcache_banks(bc, alu, cf->kcache);
2039
2040 switch(bc->chip_class) {
2041 case EVERGREEN: /* eg alu is same encoding as r700 */
2042 case CAYMAN:
2043 r = r700_bytecode_alu_build(bc, alu, addr);
2044 break;
2045 default:
2046 R600_ERR("unknown chip class %d.\n", bc->chip_class);
2047 return -EINVAL;
2048 }
2049 if (r)
2050 return r;
2051 addr += 2;
2052 if (alu->last) {
2053 for (i = 0; i < align(nliteral, 2); ++i) {
2054 bc->bytecode[addr++] = literal[i];
2055 }
2056 nliteral = 0;
2057 memset(literal, 0, sizeof(literal));
2058 }
2059 }
2060 break;
2061 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2062 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2063 r = r600_bytecode_vtx_build(bc, vtx, addr);
2064 if (r)
2065 return r;
2066 addr += 4;
2067 }
2068 break;
2069 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2070 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2071 assert(bc->chip_class >= EVERGREEN);
2072 r = r600_bytecode_vtx_build(bc, vtx, addr);
2073 if (r)
2074 return r;
2075 addr += 4;
2076 }
2077 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2078 r = r600_bytecode_tex_build(bc, tex, addr);
2079 if (r)
2080 return r;
2081 addr += 4;
2082 }
2083 break;
2084 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2085 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2086 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0:
2087 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1:
2088 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2:
2089 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3:
2090 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0:
2091 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1:
2092 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2:
2093 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3:
2094 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0:
2095 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1:
2096 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2:
2097 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3:
2098 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0:
2099 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1:
2100 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2:
2101 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3:
2102 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10:
2103 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
2104 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2105 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2106 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2107 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2108 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2109 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
2110 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2111 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2112 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
2113 break;
2114 case CF_NATIVE:
2115 break;
2116 default:
2117 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
2118 return -EINVAL;
2119 }
2120 } else {
2121 r = r600_bytecode_cf_build(bc, cf);
2122 if (r)
2123 return r;
2124
2125 switch (cf->inst) {
2126 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
2127 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
2128 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
2129 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
2130 nliteral = 0;
2131 memset(literal, 0, sizeof(literal));
2132 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
2133 r = r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
2134 if (r)
2135 return r;
2136 r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral);
2137 r600_bytecode_assign_kcache_banks(bc, alu, cf->kcache);
2138
2139 switch(bc->chip_class) {
2140 case R600:
2141 r = r600_bytecode_alu_build(bc, alu, addr);
2142 break;
2143 case R700:
2144 r = r700_bytecode_alu_build(bc, alu, addr);
2145 break;
2146 default:
2147 R600_ERR("unknown chip class %d.\n", bc->chip_class);
2148 return -EINVAL;
2149 }
2150 if (r)
2151 return r;
2152 addr += 2;
2153 if (alu->last) {
2154 for (i = 0; i < align(nliteral, 2); ++i) {
2155 bc->bytecode[addr++] = literal[i];
2156 }
2157 nliteral = 0;
2158 memset(literal, 0, sizeof(literal));
2159 }
2160 }
2161 break;
2162 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2163 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
2164 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2165 r = r600_bytecode_vtx_build(bc, vtx, addr);
2166 if (r)
2167 return r;
2168 addr += 4;
2169 }
2170 break;
2171 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2172 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2173 r = r600_bytecode_tex_build(bc, tex, addr);
2174 if (r)
2175 return r;
2176 addr += 4;
2177 }
2178 break;
2179 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2180 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2181 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
2182 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
2183 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
2184 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
2185 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
2186 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10:
2187 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2188 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2189 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2190 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2191 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2192 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
2193 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2194 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2195 break;
2196 default:
2197 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
2198 return -EINVAL;
2199 }
2200 }
2201 }
2202 return 0;
2203 }
2204
2205 void r600_bytecode_clear(struct r600_bytecode *bc)
2206 {
2207 struct r600_bytecode_cf *cf = NULL, *next_cf;
2208
2209 free(bc->bytecode);
2210 bc->bytecode = NULL;
2211
2212 LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
2213 struct r600_bytecode_alu *alu = NULL, *next_alu;
2214 struct r600_bytecode_tex *tex = NULL, *next_tex;
2215 struct r600_bytecode_tex *vtx = NULL, *next_vtx;
2216
2217 LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
2218 free(alu);
2219 }
2220
2221 LIST_INITHEAD(&cf->alu);
2222
2223 LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) {
2224 free(tex);
2225 }
2226
2227 LIST_INITHEAD(&cf->tex);
2228
2229 LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) {
2230 free(vtx);
2231 }
2232
2233 LIST_INITHEAD(&cf->vtx);
2234
2235 free(cf);
2236 }
2237
2238 LIST_INITHEAD(&cf->list);
2239 }
2240
2241 void r600_bytecode_dump(struct r600_bytecode *bc)
2242 {
2243 struct r600_bytecode_cf *cf = NULL;
2244 struct r600_bytecode_alu *alu = NULL;
2245 struct r600_bytecode_vtx *vtx = NULL;
2246 struct r600_bytecode_tex *tex = NULL;
2247
2248 unsigned i, id;
2249 uint32_t literal[4];
2250 unsigned nliteral;
2251 char chip = '6';
2252
2253 switch (bc->chip_class) {
2254 case R700:
2255 chip = '7';
2256 break;
2257 case EVERGREEN:
2258 chip = 'E';
2259 break;
2260 case CAYMAN:
2261 chip = 'C';
2262 break;
2263 case R600:
2264 default:
2265 chip = '6';
2266 break;
2267 }
2268 fprintf(stderr, "bytecode %d dw -- %d gprs ---------------------\n", bc->ndw, bc->ngpr);
2269 fprintf(stderr, " %c\n", chip);
2270
2271 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
2272 id = cf->id;
2273
2274 if (bc->chip_class >= EVERGREEN) {
2275 switch (cf->inst) {
2276 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
2277 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
2278 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
2279 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
2280 if (cf->eg_alu_extended) {
2281 fprintf(stderr, "%04d %08X ALU_EXT0 ", id, bc->bytecode[id]);
2282 fprintf(stderr, "KCACHE_BANK2:%X ", cf->kcache[2].bank);
2283 fprintf(stderr, "KCACHE_BANK3:%X ", cf->kcache[3].bank);
2284 fprintf(stderr, "KCACHE_MODE2:%X\n", cf->kcache[2].mode);
2285 id++;
2286 fprintf(stderr, "%04d %08X ALU_EXT1 ", id, bc->bytecode[id]);
2287 fprintf(stderr, "KCACHE_MODE3:%X ", cf->kcache[3].mode);
2288 fprintf(stderr, "KCACHE_ADDR2:%X ", cf->kcache[2].addr);
2289 fprintf(stderr, "KCACHE_ADDR3:%X\n", cf->kcache[3].addr);
2290 id++;
2291 }
2292
2293 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2294 fprintf(stderr, "ADDR:%d ", cf->addr);
2295 fprintf(stderr, "KCACHE_MODE0:%X ", cf->kcache[0].mode);
2296 fprintf(stderr, "KCACHE_BANK0:%X ", cf->kcache[0].bank);
2297 fprintf(stderr, "KCACHE_BANK1:%X\n", cf->kcache[1].bank);
2298 id++;
2299 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2300 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_ALU_WORD1_CF_INST(cf->inst));
2301 fprintf(stderr, "KCACHE_MODE1:%X ", cf->kcache[1].mode);
2302 fprintf(stderr, "KCACHE_ADDR0:%X ", cf->kcache[0].addr);
2303 fprintf(stderr, "KCACHE_ADDR1:%X ", cf->kcache[1].addr);
2304 fprintf(stderr, "COUNT:%d\n", cf->ndw / 2);
2305 break;
2306 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2307 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2308 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2309 fprintf(stderr, "ADDR:%d\n", cf->addr);
2310 id++;
2311 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2312 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_WORD1_CF_INST(cf->inst));
2313 fprintf(stderr, "COUNT:%d\n", cf->ndw / 4);
2314 break;
2315 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2316 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2317 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2318 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2319 fprintf(stderr, "ELEM_SIZE:%X ", cf->output.elem_size);
2320 fprintf(stderr, "ARRAY_BASE:%X ", cf->output.array_base);
2321 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2322 id++;
2323 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2324 fprintf(stderr, "SWIZ_X:%X ", cf->output.swizzle_x);
2325 fprintf(stderr, "SWIZ_Y:%X ", cf->output.swizzle_y);
2326 fprintf(stderr, "SWIZ_Z:%X ", cf->output.swizzle_z);
2327 fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
2328 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2329 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst));
2330 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2331 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2332 break;
2333 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0:
2334 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1:
2335 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2:
2336 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3:
2337 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0:
2338 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1:
2339 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2:
2340 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3:
2341 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0:
2342 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1:
2343 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2:
2344 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3:
2345 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0:
2346 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1:
2347 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2:
2348 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3:
2349 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i_BUF%i ", id, bc->bytecode[id],
2350 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2351 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) / 4,
2352 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2353 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) % 4);
2354 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2355 fprintf(stderr, "ELEM_SIZE:%i ", cf->output.elem_size);
2356 fprintf(stderr, "ARRAY_BASE:%i ", cf->output.array_base);
2357 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2358 id++;
2359 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i_BUF%i ", id, bc->bytecode[id],
2360 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2361 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) / 4,
2362 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2363 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) % 4);
2364 fprintf(stderr, "ARRAY_SIZE:%i ", cf->output.array_size);
2365 fprintf(stderr, "COMP_MASK:%X ", cf->output.comp_mask);
2366 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2367 fprintf(stderr, "INST:%d ", cf->output.inst);
2368 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2369 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2370 break;
2371 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2372 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2373 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
2374 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
2375 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10:
2376 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2377 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2378 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2379 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2380 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2381 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
2382 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2383 fprintf(stderr, "ADDR:%d\n", cf->cf_addr);
2384 id++;
2385 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2386 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_WORD1_CF_INST(cf->inst));
2387 fprintf(stderr, "COND:%X ", cf->cond);
2388 fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
2389 break;
2390 case CF_NATIVE:
2391 fprintf(stderr, "%04d %08X CF NATIVE\n", id, bc->bytecode[id]);
2392 fprintf(stderr, "%04d %08X CF NATIVE\n", id + 1, bc->bytecode[id + 1]);
2393 break;
2394 default:
2395 R600_ERR("Unknown instruction %0x\n", cf->inst);
2396 }
2397 } else {
2398 switch (cf->inst) {
2399 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
2400 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
2401 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
2402 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
2403 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2404 fprintf(stderr, "ADDR:%d ", cf->addr);
2405 fprintf(stderr, "KCACHE_MODE0:%X ", cf->kcache[0].mode);
2406 fprintf(stderr, "KCACHE_BANK0:%X ", cf->kcache[0].bank);
2407 fprintf(stderr, "KCACHE_BANK1:%X\n", cf->kcache[1].bank);
2408 id++;
2409 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2410 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_ALU_WORD1_CF_INST(cf->inst));
2411 fprintf(stderr, "KCACHE_MODE1:%X ", cf->kcache[1].mode);
2412 fprintf(stderr, "KCACHE_ADDR0:%X ", cf->kcache[0].addr);
2413 fprintf(stderr, "KCACHE_ADDR1:%X ", cf->kcache[1].addr);
2414 fprintf(stderr, "COUNT:%d\n", cf->ndw / 2);
2415 break;
2416 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2417 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2418 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
2419 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2420 fprintf(stderr, "ADDR:%d\n", cf->addr);
2421 id++;
2422 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2423 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_WORD1_CF_INST(cf->inst));
2424 fprintf(stderr, "COUNT:%d\n", cf->ndw / 4);
2425 break;
2426 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2427 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2428 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2429 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2430 fprintf(stderr, "ELEM_SIZE:%X ", cf->output.elem_size);
2431 fprintf(stderr, "ARRAY_BASE:%X ", cf->output.array_base);
2432 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2433 id++;
2434 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2435 fprintf(stderr, "SWIZ_X:%X ", cf->output.swizzle_x);
2436 fprintf(stderr, "SWIZ_Y:%X ", cf->output.swizzle_y);
2437 fprintf(stderr, "SWIZ_Z:%X ", cf->output.swizzle_z);
2438 fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
2439 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2440 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst));
2441 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2442 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2443 break;
2444 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
2445 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
2446 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
2447 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
2448 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i ", id, bc->bytecode[id],
2449 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2450 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0));
2451 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2452 fprintf(stderr, "ELEM_SIZE:%i ", cf->output.elem_size);
2453 fprintf(stderr, "ARRAY_BASE:%i ", cf->output.array_base);
2454 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2455 id++;
2456 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i ", id, bc->bytecode[id],
2457 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2458 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0));
2459 fprintf(stderr, "ARRAY_SIZE:%i ", cf->output.array_size);
2460 fprintf(stderr, "COMP_MASK:%X ", cf->output.comp_mask);
2461 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2462 fprintf(stderr, "INST:%d ", cf->output.inst);
2463 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2464 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2465 break;
2466 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2467 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2468 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
2469 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
2470 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10:
2471 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2472 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2473 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2474 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2475 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2476 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2477 fprintf(stderr, "ADDR:%d\n", cf->cf_addr);
2478 id++;
2479 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2480 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_WORD1_CF_INST(cf->inst));
2481 fprintf(stderr, "COND:%X ", cf->cond);
2482 fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
2483 break;
2484 default:
2485 R600_ERR("Unknown instruction %0x\n", cf->inst);
2486 }
2487 }
2488
2489 id = cf->addr;
2490 nliteral = 0;
2491 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
2492 r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
2493
2494 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2495 fprintf(stderr, "SRC0(SEL:%d ", alu->src[0].sel);
2496 fprintf(stderr, "REL:%d ", alu->src[0].rel);
2497 fprintf(stderr, "CHAN:%d ", alu->src[0].chan);
2498 fprintf(stderr, "NEG:%d) ", alu->src[0].neg);
2499 fprintf(stderr, "SRC1(SEL:%d ", alu->src[1].sel);
2500 fprintf(stderr, "REL:%d ", alu->src[1].rel);
2501 fprintf(stderr, "CHAN:%d ", alu->src[1].chan);
2502 fprintf(stderr, "NEG:%d ", alu->src[1].neg);
2503 fprintf(stderr, "IM:%d) ", alu->index_mode);
2504 fprintf(stderr, "PRED_SEL:%d ", alu->pred_sel);
2505 fprintf(stderr, "LAST:%d)\n", alu->last);
2506 id++;
2507 fprintf(stderr, "%04d %08X %c ", id, bc->bytecode[id], alu->last ? '*' : ' ');
2508 fprintf(stderr, "INST:0x%x ", alu->inst);
2509 fprintf(stderr, "DST(SEL:%d ", alu->dst.sel);
2510 fprintf(stderr, "CHAN:%d ", alu->dst.chan);
2511 fprintf(stderr, "REL:%d ", alu->dst.rel);
2512 fprintf(stderr, "CLAMP:%d) ", alu->dst.clamp);
2513 fprintf(stderr, "BANK_SWIZZLE:%d ", alu->bank_swizzle);
2514 if (alu->is_op3) {
2515 fprintf(stderr, "SRC2(SEL:%d ", alu->src[2].sel);
2516 fprintf(stderr, "REL:%d ", alu->src[2].rel);
2517 fprintf(stderr, "CHAN:%d ", alu->src[2].chan);
2518 fprintf(stderr, "NEG:%d)\n", alu->src[2].neg);
2519 } else {
2520 fprintf(stderr, "SRC0_ABS:%d ", alu->src[0].abs);
2521 fprintf(stderr, "SRC1_ABS:%d ", alu->src[1].abs);
2522 fprintf(stderr, "WRITE_MASK:%d ", alu->dst.write);
2523 fprintf(stderr, "OMOD:%d ", alu->omod);
2524 fprintf(stderr, "EXECUTE_MASK:%d ", alu->execute_mask);
2525 fprintf(stderr, "UPDATE_PRED:%d\n", alu->update_pred);
2526 }
2527
2528 id++;
2529 if (alu->last) {
2530 for (i = 0; i < nliteral; i++, id++) {
2531 float *f = (float*)(bc->bytecode + id);
2532 fprintf(stderr, "%04d %08X\t%f (%d)\n", id, bc->bytecode[id], *f,
2533 *(bc->bytecode + id));
2534 }
2535 id += nliteral & 1;
2536 nliteral = 0;
2537 }
2538 }
2539
2540 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2541 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2542 fprintf(stderr, "INST:0x%x ", tex->inst);
2543 fprintf(stderr, "RESOURCE_ID:%d ", tex->resource_id);
2544 fprintf(stderr, "SRC(GPR:%d ", tex->src_gpr);
2545 fprintf(stderr, "REL:%d)\n", tex->src_rel);
2546 id++;
2547 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2548 fprintf(stderr, "DST(GPR:%d ", tex->dst_gpr);
2549 fprintf(stderr, "REL:%d ", tex->dst_rel);
2550 fprintf(stderr, "SEL_X:%d ", tex->dst_sel_x);
2551 fprintf(stderr, "SEL_Y:%d ", tex->dst_sel_y);
2552 fprintf(stderr, "SEL_Z:%d ", tex->dst_sel_z);
2553 fprintf(stderr, "SEL_W:%d) ", tex->dst_sel_w);
2554 fprintf(stderr, "LOD_BIAS:%d ", tex->lod_bias);
2555 fprintf(stderr, "COORD_TYPE_X:%d ", tex->coord_type_x);
2556 fprintf(stderr, "COORD_TYPE_Y:%d ", tex->coord_type_y);
2557 fprintf(stderr, "COORD_TYPE_Z:%d ", tex->coord_type_z);
2558 fprintf(stderr, "COORD_TYPE_W:%d\n", tex->coord_type_w);
2559 id++;
2560 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2561 fprintf(stderr, "OFFSET_X:%d ", tex->offset_x);
2562 fprintf(stderr, "OFFSET_Y:%d ", tex->offset_y);
2563 fprintf(stderr, "OFFSET_Z:%d ", tex->offset_z);
2564 fprintf(stderr, "SAMPLER_ID:%d ", tex->sampler_id);
2565 fprintf(stderr, "SRC(SEL_X:%d ", tex->src_sel_x);
2566 fprintf(stderr, "SEL_Y:%d ", tex->src_sel_y);
2567 fprintf(stderr, "SEL_Z:%d ", tex->src_sel_z);
2568 fprintf(stderr, "SEL_W:%d)\n", tex->src_sel_w);
2569 id++;
2570 fprintf(stderr, "%04d %08X \n", id, bc->bytecode[id]);
2571 id++;
2572 }
2573
2574 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2575 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2576 fprintf(stderr, "INST:%d ", vtx->inst);
2577 fprintf(stderr, "FETCH_TYPE:%d ", vtx->fetch_type);
2578 fprintf(stderr, "BUFFER_ID:%d\n", vtx->buffer_id);
2579 id++;
2580 /* This assumes that no semantic fetches exist */
2581 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2582 fprintf(stderr, "SRC(GPR:%d ", vtx->src_gpr);
2583 fprintf(stderr, "SEL_X:%d) ", vtx->src_sel_x);
2584 if (bc->chip_class < CAYMAN)
2585 fprintf(stderr, "MEGA_FETCH_COUNT:%d ", vtx->mega_fetch_count);
2586 else
2587 fprintf(stderr, "SEL_Y:%d) ", 0);
2588 fprintf(stderr, "DST(GPR:%d ", vtx->dst_gpr);
2589 fprintf(stderr, "SEL_X:%d ", vtx->dst_sel_x);
2590 fprintf(stderr, "SEL_Y:%d ", vtx->dst_sel_y);
2591 fprintf(stderr, "SEL_Z:%d ", vtx->dst_sel_z);
2592 fprintf(stderr, "SEL_W:%d) ", vtx->dst_sel_w);
2593 fprintf(stderr, "USE_CONST_FIELDS:%d ", vtx->use_const_fields);
2594 fprintf(stderr, "FORMAT(DATA:%d ", vtx->data_format);
2595 fprintf(stderr, "NUM:%d ", vtx->num_format_all);
2596 fprintf(stderr, "COMP:%d ", vtx->format_comp_all);
2597 fprintf(stderr, "MODE:%d)\n", vtx->srf_mode_all);
2598 id++;
2599 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2600 fprintf(stderr, "ENDIAN:%d ", vtx->endian);
2601 fprintf(stderr, "OFFSET:%d\n", vtx->offset);
2602 /* XXX */
2603 id++;
2604 fprintf(stderr, "%04d %08X \n", id, bc->bytecode[id]);
2605 id++;
2606 }
2607 }
2608
2609 fprintf(stderr, "--------------------------------------\n");
2610 }
2611
2612 void r600_vertex_data_type(enum pipe_format pformat,
2613 unsigned *format,
2614 unsigned *num_format, unsigned *format_comp, unsigned *endian)
2615 {
2616 const struct util_format_description *desc;
2617 unsigned i;
2618
2619 *format = 0;
2620 *num_format = 0;
2621 *format_comp = 0;
2622 *endian = ENDIAN_NONE;
2623
2624 desc = util_format_description(pformat);
2625 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
2626 goto out_unknown;
2627 }
2628
2629 /* Find the first non-VOID channel. */
2630 for (i = 0; i < 4; i++) {
2631 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2632 break;
2633 }
2634 }
2635
2636 *endian = r600_endian_swap(desc->channel[i].size);
2637
2638 switch (desc->channel[i].type) {
2639 /* Half-floats, floats, ints */
2640 case UTIL_FORMAT_TYPE_FLOAT:
2641 switch (desc->channel[i].size) {
2642 case 16:
2643 switch (desc->nr_channels) {
2644 case 1:
2645 *format = FMT_16_FLOAT;
2646 break;
2647 case 2:
2648 *format = FMT_16_16_FLOAT;
2649 break;
2650 case 3:
2651 case 4:
2652 *format = FMT_16_16_16_16_FLOAT;
2653 break;
2654 }
2655 break;
2656 case 32:
2657 switch (desc->nr_channels) {
2658 case 1:
2659 *format = FMT_32_FLOAT;
2660 break;
2661 case 2:
2662 *format = FMT_32_32_FLOAT;
2663 break;
2664 case 3:
2665 *format = FMT_32_32_32_FLOAT;
2666 break;
2667 case 4:
2668 *format = FMT_32_32_32_32_FLOAT;
2669 break;
2670 }
2671 break;
2672 default:
2673 goto out_unknown;
2674 }
2675 break;
2676 /* Unsigned ints */
2677 case UTIL_FORMAT_TYPE_UNSIGNED:
2678 /* Signed ints */
2679 case UTIL_FORMAT_TYPE_SIGNED:
2680 switch (desc->channel[i].size) {
2681 case 8:
2682 switch (desc->nr_channels) {
2683 case 1:
2684 *format = FMT_8;
2685 break;
2686 case 2:
2687 *format = FMT_8_8;
2688 break;
2689 case 3:
2690 case 4:
2691 *format = FMT_8_8_8_8;
2692 break;
2693 }
2694 break;
2695 case 10:
2696 if (desc->nr_channels != 4)
2697 goto out_unknown;
2698
2699 *format = FMT_2_10_10_10;
2700 break;
2701 case 16:
2702 switch (desc->nr_channels) {
2703 case 1:
2704 *format = FMT_16;
2705 break;
2706 case 2:
2707 *format = FMT_16_16;
2708 break;
2709 case 3:
2710 case 4:
2711 *format = FMT_16_16_16_16;
2712 break;
2713 }
2714 break;
2715 case 32:
2716 switch (desc->nr_channels) {
2717 case 1:
2718 *format = FMT_32;
2719 break;
2720 case 2:
2721 *format = FMT_32_32;
2722 break;
2723 case 3:
2724 *format = FMT_32_32_32;
2725 break;
2726 case 4:
2727 *format = FMT_32_32_32_32;
2728 break;
2729 }
2730 break;
2731 default:
2732 goto out_unknown;
2733 }
2734 break;
2735 default:
2736 goto out_unknown;
2737 }
2738
2739 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2740 *format_comp = 1;
2741 }
2742
2743 *num_format = 0;
2744 if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED ||
2745 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2746 if (!desc->channel[i].normalized) {
2747 if (desc->channel[i].pure_integer)
2748 *num_format = 1;
2749 else
2750 *num_format = 2;
2751 }
2752 }
2753 return;
2754 out_unknown:
2755 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
2756 }
2757
2758 void *r600_create_vertex_fetch_shader(struct pipe_context *ctx,
2759 unsigned count,
2760 const struct pipe_vertex_element *elements)
2761 {
2762 struct r600_context *rctx = (struct r600_context *)ctx;
2763 static int dump_shaders = -1;
2764 struct r600_bytecode bc;
2765 struct r600_bytecode_vtx vtx;
2766 const struct util_format_description *desc;
2767 unsigned fetch_resource_start = rctx->chip_class >= EVERGREEN ? 0 : 160;
2768 unsigned format, num_format, format_comp, endian;
2769 uint32_t *bytecode;
2770 int i, j, r, fs_size;
2771 struct r600_fetch_shader *shader;
2772
2773 assert(count < 32);
2774
2775 memset(&bc, 0, sizeof(bc));
2776 r600_bytecode_init(&bc, rctx->chip_class, rctx->family,
2777 rctx->screen->msaa_texture_support);
2778
2779 for (i = 0; i < count; i++) {
2780 if (elements[i].instance_divisor > 1) {
2781 if (rctx->chip_class == CAYMAN) {
2782 for (j = 0; j < 4; j++) {
2783 struct r600_bytecode_alu alu;
2784 memset(&alu, 0, sizeof(alu));
2785 alu.inst = BC_INST(&bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
2786 alu.src[0].sel = 0;
2787 alu.src[0].chan = 3;
2788 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2789 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2790 alu.dst.sel = i + 1;
2791 alu.dst.chan = j;
2792 alu.dst.write = j == 3;
2793 alu.last = j == 3;
2794 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2795 r600_bytecode_clear(&bc);
2796 return NULL;
2797 }
2798 }
2799 } else {
2800 struct r600_bytecode_alu alu;
2801 memset(&alu, 0, sizeof(alu));
2802 alu.inst = BC_INST(&bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
2803 alu.src[0].sel = 0;
2804 alu.src[0].chan = 3;
2805 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2806 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2807 alu.dst.sel = i + 1;
2808 alu.dst.chan = 3;
2809 alu.dst.write = 1;
2810 alu.last = 1;
2811 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2812 r600_bytecode_clear(&bc);
2813 return NULL;
2814 }
2815 }
2816 }
2817 }
2818
2819 for (i = 0; i < count; i++) {
2820 r600_vertex_data_type(elements[i].src_format,
2821 &format, &num_format, &format_comp, &endian);
2822
2823 desc = util_format_description(elements[i].src_format);
2824 if (desc == NULL) {
2825 r600_bytecode_clear(&bc);
2826 R600_ERR("unknown format %d\n", elements[i].src_format);
2827 return NULL;
2828 }
2829
2830 if (elements[i].src_offset > 65535) {
2831 r600_bytecode_clear(&bc);
2832 R600_ERR("too big src_offset: %u\n", elements[i].src_offset);
2833 return NULL;
2834 }
2835
2836 memset(&vtx, 0, sizeof(vtx));
2837 vtx.buffer_id = elements[i].vertex_buffer_index + fetch_resource_start;
2838 vtx.fetch_type = elements[i].instance_divisor ? 1 : 0;
2839 vtx.src_gpr = elements[i].instance_divisor > 1 ? i + 1 : 0;
2840 vtx.src_sel_x = elements[i].instance_divisor ? 3 : 0;
2841 vtx.mega_fetch_count = 0x1F;
2842 vtx.dst_gpr = i + 1;
2843 vtx.dst_sel_x = desc->swizzle[0];
2844 vtx.dst_sel_y = desc->swizzle[1];
2845 vtx.dst_sel_z = desc->swizzle[2];
2846 vtx.dst_sel_w = desc->swizzle[3];
2847 vtx.data_format = format;
2848 vtx.num_format_all = num_format;
2849 vtx.format_comp_all = format_comp;
2850 vtx.srf_mode_all = 1;
2851 vtx.offset = elements[i].src_offset;
2852 vtx.endian = endian;
2853
2854 if ((r = r600_bytecode_add_vtx(&bc, &vtx))) {
2855 r600_bytecode_clear(&bc);
2856 return NULL;
2857 }
2858 }
2859
2860 r600_bytecode_add_cfinst(&bc, BC_INST(&bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN));
2861
2862 if ((r = r600_bytecode_build(&bc))) {
2863 r600_bytecode_clear(&bc);
2864 return NULL;
2865 }
2866
2867 if (dump_shaders == -1)
2868 dump_shaders = debug_get_bool_option("R600_DUMP_SHADERS", FALSE);
2869
2870 if (dump_shaders) {
2871 fprintf(stderr, "--------------------------------------------------------------\n");
2872 r600_bytecode_dump(&bc);
2873 fprintf(stderr, "______________________________________________________________\n");
2874 }
2875
2876 fs_size = bc.ndw*4;
2877
2878 /* Allocate the CSO. */
2879 shader = CALLOC_STRUCT(r600_fetch_shader);
2880 if (!shader) {
2881 r600_bytecode_clear(&bc);
2882 return NULL;
2883 }
2884
2885 u_suballocator_alloc(rctx->allocator_fetch_shader, fs_size, &shader->offset,
2886 (struct pipe_resource**)&shader->buffer);
2887 if (!shader->buffer) {
2888 r600_bytecode_clear(&bc);
2889 FREE(shader);
2890 return NULL;
2891 }
2892
2893 bytecode = rctx->ws->buffer_map(shader->buffer->cs_buf, rctx->cs,
2894 PIPE_TRANSFER_WRITE | PIPE_TRANSFER_UNSYNCHRONIZED);
2895 bytecode += shader->offset / 4;
2896
2897 if (R600_BIG_ENDIAN) {
2898 for (i = 0; i < fs_size / 4; ++i) {
2899 bytecode[i] = bswap_32(bc.bytecode[i]);
2900 }
2901 } else {
2902 memcpy(bytecode, bc.bytecode, fs_size);
2903 }
2904 rctx->ws->buffer_unmap(shader->buffer->cs_buf);
2905
2906 r600_bytecode_clear(&bc);
2907 return shader;
2908 }
2909
2910 void r600_bytecode_alu_read(struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1)
2911 {
2912 /* WORD0 */
2913 alu->src[0].sel = G_SQ_ALU_WORD0_SRC0_SEL(word0);
2914 alu->src[0].rel = G_SQ_ALU_WORD0_SRC0_REL(word0);
2915 alu->src[0].chan = G_SQ_ALU_WORD0_SRC0_CHAN(word0);
2916 alu->src[0].neg = G_SQ_ALU_WORD0_SRC0_NEG(word0);
2917 alu->src[1].sel = G_SQ_ALU_WORD0_SRC1_SEL(word0);
2918 alu->src[1].rel = G_SQ_ALU_WORD0_SRC1_REL(word0);
2919 alu->src[1].chan = G_SQ_ALU_WORD0_SRC1_CHAN(word0);
2920 alu->src[1].neg = G_SQ_ALU_WORD0_SRC1_NEG(word0);
2921 alu->index_mode = G_SQ_ALU_WORD0_INDEX_MODE(word0);
2922 alu->pred_sel = G_SQ_ALU_WORD0_PRED_SEL(word0);
2923 alu->last = G_SQ_ALU_WORD0_LAST(word0);
2924
2925 /* WORD1 */
2926 alu->bank_swizzle = G_SQ_ALU_WORD1_BANK_SWIZZLE(word1);
2927 if (alu->bank_swizzle)
2928 alu->bank_swizzle_force = alu->bank_swizzle;
2929 alu->dst.sel = G_SQ_ALU_WORD1_DST_GPR(word1);
2930 alu->dst.rel = G_SQ_ALU_WORD1_DST_REL(word1);
2931 alu->dst.chan = G_SQ_ALU_WORD1_DST_CHAN(word1);
2932 alu->dst.clamp = G_SQ_ALU_WORD1_CLAMP(word1);
2933 if (G_SQ_ALU_WORD1_ENCODING(word1)) /*ALU_DWORD1_OP3*/
2934 {
2935 alu->is_op3 = 1;
2936 alu->src[2].sel = G_SQ_ALU_WORD1_OP3_SRC2_SEL(word1);
2937 alu->src[2].rel = G_SQ_ALU_WORD1_OP3_SRC2_REL(word1);
2938 alu->src[2].chan = G_SQ_ALU_WORD1_OP3_SRC2_CHAN(word1);
2939 alu->src[2].neg = G_SQ_ALU_WORD1_OP3_SRC2_NEG(word1);
2940 alu->inst = G_SQ_ALU_WORD1_OP3_ALU_INST(word1);
2941 }
2942 else /*ALU_DWORD1_OP2*/
2943 {
2944 alu->src[0].abs = G_SQ_ALU_WORD1_OP2_SRC0_ABS(word1);
2945 alu->src[1].abs = G_SQ_ALU_WORD1_OP2_SRC1_ABS(word1);
2946 alu->inst = G_SQ_ALU_WORD1_OP2_ALU_INST(word1);
2947 alu->omod = G_SQ_ALU_WORD1_OP2_OMOD(word1);
2948 alu->dst.write = G_SQ_ALU_WORD1_OP2_WRITE_MASK(word1);
2949 alu->update_pred = G_SQ_ALU_WORD1_OP2_UPDATE_PRED(word1);
2950 alu->execute_mask =
2951 G_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(word1);
2952 }
2953 }
2954
2955 void r600_bytecode_export_read(struct r600_bytecode_output *output, uint32_t word0, uint32_t word1)
2956 {
2957 output->array_base = G_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(word0);
2958 output->type = G_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(word0);
2959 output->gpr = G_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(word0);
2960 output->elem_size = G_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(word0);
2961
2962 output->swizzle_x = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(word1);
2963 output->swizzle_y = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(word1);
2964 output->swizzle_z = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(word1);
2965 output->swizzle_w = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(word1);
2966 output->burst_count = G_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(word1);
2967 output->end_of_program = G_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(word1);
2968 output->inst = R600_S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(word1));
2969 output->barrier = G_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(word1);
2970 }