2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 #include "r600_context.h"
25 #include "util/u_memory.h"
27 #include "r600_opcodes.h"
32 static inline unsigned int r600_bc_get_num_operands(struct r600_bc_alu
*alu
)
38 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
:
40 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
:
41 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE
:
42 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
:
43 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE
:
44 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE
:
45 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
:
46 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
:
47 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN
:
48 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE
:
49 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE
:
50 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
:
51 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
:
52 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE
:
53 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT
:
54 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE
:
55 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE
:
56 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
:
57 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE
:
58 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE
:
61 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
:
62 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR
:
63 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
:
64 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
:
65 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC
:
66 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
:
67 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED
:
68 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
:
69 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
:
70 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE
:
71 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT
:
72 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
:
73 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
:
76 "Need instruction operand number for 0x%x.\n", alu
->inst
);
82 int r700_bc_alu_build(struct r600_bc
*bc
, struct r600_bc_alu
*alu
, unsigned id
);
84 static struct r600_bc_cf
*r600_bc_cf(void)
86 struct r600_bc_cf
*cf
= CALLOC_STRUCT(r600_bc_cf
);
90 LIST_INITHEAD(&cf
->list
);
91 LIST_INITHEAD(&cf
->alu
);
92 LIST_INITHEAD(&cf
->vtx
);
93 LIST_INITHEAD(&cf
->tex
);
97 static struct r600_bc_alu
*r600_bc_alu(void)
99 struct r600_bc_alu
*alu
= CALLOC_STRUCT(r600_bc_alu
);
103 LIST_INITHEAD(&alu
->list
);
104 LIST_INITHEAD(&alu
->bs_list
);
108 static struct r600_bc_vtx
*r600_bc_vtx(void)
110 struct r600_bc_vtx
*vtx
= CALLOC_STRUCT(r600_bc_vtx
);
114 LIST_INITHEAD(&vtx
->list
);
118 static struct r600_bc_tex
*r600_bc_tex(void)
120 struct r600_bc_tex
*tex
= CALLOC_STRUCT(r600_bc_tex
);
124 LIST_INITHEAD(&tex
->list
);
128 int r600_bc_init(struct r600_bc
*bc
, enum radeon_family family
)
130 LIST_INITHEAD(&bc
->cf
);
132 switch (bc
->family
) {
157 R600_ERR("unknown family %d\n", bc
->family
);
163 static int r600_bc_add_cf(struct r600_bc
*bc
)
165 struct r600_bc_cf
*cf
= r600_bc_cf();
169 LIST_ADDTAIL(&cf
->list
, &bc
->cf
);
171 cf
->id
= bc
->cf_last
->id
+ 2;
175 bc
->force_add_cf
= 0;
179 int r600_bc_add_output(struct r600_bc
*bc
, const struct r600_bc_output
*output
)
183 r
= r600_bc_add_cf(bc
);
186 bc
->cf_last
->inst
= output
->inst
;
187 memcpy(&bc
->cf_last
->output
, output
, sizeof(struct r600_bc_output
));
191 const unsigned bank_swizzle_vec
[8] = {SQ_ALU_VEC_210
, //000
192 SQ_ALU_VEC_120
, //001
193 SQ_ALU_VEC_102
, //010
195 SQ_ALU_VEC_201
, //011
196 SQ_ALU_VEC_012
, //100
197 SQ_ALU_VEC_021
, //101
199 SQ_ALU_VEC_012
, //110
200 SQ_ALU_VEC_012
}; //111
202 const unsigned bank_swizzle_scl
[8] = {SQ_ALU_SCL_210
, //000
203 SQ_ALU_SCL_122
, //001
204 SQ_ALU_SCL_122
, //010
206 SQ_ALU_SCL_221
, //011
207 SQ_ALU_SCL_212
, //100
208 SQ_ALU_SCL_122
, //101
210 SQ_ALU_SCL_122
, //110
211 SQ_ALU_SCL_122
}; //111
213 static int init_gpr(struct r600_bc_alu
*alu
)
215 int cycle
, component
;
217 for (cycle
= 0; cycle
< NUM_OF_CYCLES
; cycle
++)
218 for (component
= 0; component
< NUM_OF_COMPONENTS
; component
++)
219 alu
->hw_gpr
[cycle
][component
] = -1;
224 static int reserve_gpr(struct r600_bc_alu
*alu
, unsigned sel
, unsigned chan
, unsigned cycle
)
226 if (alu
->hw_gpr
[cycle
][chan
] < 0)
227 alu
->hw_gpr
[cycle
][chan
] = sel
;
228 else if (alu
->hw_gpr
[cycle
][chan
] != (int)sel
) {
229 R600_ERR("Another scalar operation has already used GPR read port for channel\n");
235 static int cycle_for_scalar_bank_swizzle(const int swiz
, const int sel
, unsigned *p_cycle
)
241 table
[0] = 2; table
[1] = 1; table
[2] = 0;
242 *p_cycle
= table
[sel
];
245 table
[0] = 1; table
[1] = 2; table
[2] = 2;
246 *p_cycle
= table
[sel
];
249 table
[0] = 2; table
[1] = 1; table
[2] = 2;
250 *p_cycle
= table
[sel
];
253 table
[0] = 2; table
[1] = 2; table
[2] = 1;
254 *p_cycle
= table
[sel
];
258 R600_ERR("bad scalar bank swizzle value\n");
265 static int cycle_for_vector_bank_swizzle(const int swiz
, const int sel
, unsigned *p_cycle
)
272 table
[0] = 0; table
[1] = 1; table
[2] = 2;
273 *p_cycle
= table
[sel
];
276 table
[0] = 0; table
[1] = 2; table
[2] = 1;
277 *p_cycle
= table
[sel
];
280 table
[0] = 1; table
[1] = 2; table
[2] = 0;
281 *p_cycle
= table
[sel
];
284 table
[0] = 1; table
[1] = 0; table
[2] = 2;
285 *p_cycle
= table
[sel
];
288 table
[0] = 2; table
[1] = 0; table
[2] = 1;
289 *p_cycle
= table
[sel
];
292 table
[0] = 2; table
[1] = 1; table
[2] = 0;
293 *p_cycle
= table
[sel
];
296 R600_ERR("bad vector bank swizzle value\n");
305 static void update_chan_counter(struct r600_bc_alu
*alu
, int *chan_counter
)
311 num_src
= r600_bc_get_num_operands(alu
);
313 for (i
= 0; i
< num_src
; i
++) {
314 channel_swizzle
= alu
->src
[i
].chan
;
315 if ((alu
->src
[i
].sel
> 0 && alu
->src
[i
].sel
< 128) && channel_swizzle
<= 3)
316 chan_counter
[channel_swizzle
]++;
320 /* we need something like this I think - but this is bogus */
321 int check_read_slots(struct r600_bc
*bc
, struct r600_bc_alu
*alu_first
)
323 struct r600_bc_alu
*alu
;
324 int chan_counter
[4] = { 0 };
326 update_chan_counter(alu_first
, chan_counter
);
328 LIST_FOR_EACH_ENTRY(alu
, &alu_first
->bs_list
, bs_list
) {
329 update_chan_counter(alu
, chan_counter
);
332 if (chan_counter
[0] > 3 ||
333 chan_counter
[1] > 3 ||
334 chan_counter
[2] > 3 ||
335 chan_counter
[3] > 3) {
336 R600_ERR("needed to split instruction for input ran out of banks %x %d %d %d %d\n",
337 alu_first
->inst
, chan_counter
[0], chan_counter
[1], chan_counter
[2], chan_counter
[3]);
344 static int is_const(int sel
)
346 if (sel
> 255 && sel
< 512)
348 if (sel
>= V_SQ_ALU_SRC_0
&& sel
<= V_SQ_ALU_SRC_LITERAL
)
353 static int check_scalar(struct r600_bc
*bc
, struct r600_bc_alu
*alu
)
355 unsigned swizzle_key
;
357 if (alu
->bank_swizzle_force
) {
358 alu
->bank_swizzle
= alu
->bank_swizzle_force
;
361 swizzle_key
= (is_const(alu
->src
[0].sel
) ? 4 : 0 ) +
362 (is_const(alu
->src
[1].sel
) ? 2 : 0 ) +
363 (is_const(alu
->src
[2].sel
) ? 1 : 0 );
365 alu
->bank_swizzle
= bank_swizzle_scl
[swizzle_key
];
369 static int check_vector(struct r600_bc
*bc
, struct r600_bc_alu
*alu
)
371 unsigned swizzle_key
;
373 if (alu
->bank_swizzle_force
) {
374 alu
->bank_swizzle
= alu
->bank_swizzle_force
;
377 swizzle_key
= (is_const(alu
->src
[0].sel
) ? 4 : 0 ) +
378 (is_const(alu
->src
[1].sel
) ? 2 : 0 ) +
379 (is_const(alu
->src
[2].sel
) ? 1 : 0 );
381 alu
->bank_swizzle
= bank_swizzle_vec
[swizzle_key
];
385 static int check_and_set_bank_swizzle(struct r600_bc
*bc
, struct r600_bc_alu
*alu_first
)
387 struct r600_bc_alu
*alu
= NULL
;
392 LIST_FOR_EACH_ENTRY(alu
, &alu_first
->bs_list
, bs_list
) {
396 if (num_instr
== 1) {
397 check_scalar(bc
, alu_first
);
400 /* check_read_slots(bc, bc->cf_last->curr_bs_head);*/
401 check_vector(bc
, alu_first
);
402 LIST_FOR_EACH_ENTRY(alu
, &alu_first
->bs_list
, bs_list
) {
403 check_vector(bc
, alu
);
409 int r600_bc_add_alu_type(struct r600_bc
*bc
, const struct r600_bc_alu
*alu
, int type
)
411 struct r600_bc_alu
*nalu
= r600_bc_alu();
412 struct r600_bc_alu
*lalu
;
417 memcpy(nalu
, alu
, sizeof(struct r600_bc_alu
));
420 /* cf can contains only alu or only vtx or only tex */
421 if (bc
->cf_last
== NULL
|| bc
->cf_last
->inst
!= (type
<< 3) ||
423 /* at most 128 slots, one add alu can add 4 slots + 4 constant worst case */
424 r
= r600_bc_add_cf(bc
);
429 bc
->cf_last
->inst
= (type
<< 3);
431 if (!bc
->cf_last
->curr_bs_head
) {
432 bc
->cf_last
->curr_bs_head
= nalu
;
433 LIST_INITHEAD(&nalu
->bs_list
);
435 LIST_ADDTAIL(&nalu
->bs_list
, &bc
->cf_last
->curr_bs_head
->bs_list
);
437 if (alu
->last
&& (bc
->cf_last
->ndw
>> 1) >= 124) {
438 bc
->force_add_cf
= 1;
440 /* number of gpr == the last gpr used in any alu */
441 for (i
= 0; i
< 3; i
++) {
442 if (alu
->src
[i
].sel
>= bc
->ngpr
&& alu
->src
[i
].sel
< 128) {
443 bc
->ngpr
= alu
->src
[i
].sel
+ 1;
445 /* compute how many literal are needed
446 * either 2 or 4 literals
448 if (alu
->src
[i
].sel
== 253) {
449 if (((alu
->src
[i
].chan
+ 2) & 0x6) > nalu
->nliteral
) {
450 nalu
->nliteral
= (alu
->src
[i
].chan
+ 2) & 0x6;
454 if (!LIST_IS_EMPTY(&bc
->cf_last
->alu
)) {
455 lalu
= LIST_ENTRY(struct r600_bc_alu
, bc
->cf_last
->alu
.prev
, list
);
456 if (!lalu
->last
&& lalu
->nliteral
> nalu
->nliteral
) {
457 nalu
->nliteral
= lalu
->nliteral
;
460 if (alu
->dst
.sel
>= bc
->ngpr
) {
461 bc
->ngpr
= alu
->dst
.sel
+ 1;
463 LIST_ADDTAIL(&nalu
->list
, &bc
->cf_last
->alu
);
464 /* each alu use 2 dwords */
465 bc
->cf_last
->ndw
+= 2;
468 if (bc
->use_mem_constant
)
469 bc
->cf_last
->kcache0_mode
= 2;
471 /* process cur ALU instructions for bank swizzle */
473 check_and_set_bank_swizzle(bc
, bc
->cf_last
->curr_bs_head
);
474 bc
->cf_last
->curr_bs_head
= NULL
;
479 int r600_bc_add_alu(struct r600_bc
*bc
, const struct r600_bc_alu
*alu
)
481 return r600_bc_add_alu_type(bc
, alu
, BC_INST(bc
, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
));
484 int r600_bc_add_literal(struct r600_bc
*bc
, const u32
*value
)
486 struct r600_bc_alu
*alu
;
488 if (bc
->cf_last
== NULL
) {
491 if (bc
->cf_last
->inst
== V_SQ_CF_WORD1_SQ_CF_INST_TEX
) {
495 if (bc
->cf_last
->inst
== V_SQ_CF_WORD1_SQ_CF_INST_JUMP
||
496 bc
->cf_last
->inst
== V_SQ_CF_WORD1_SQ_CF_INST_ELSE
||
497 bc
->cf_last
->inst
== V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL
||
498 bc
->cf_last
->inst
== V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
||
499 bc
->cf_last
->inst
== V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
||
500 bc
->cf_last
->inst
== V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
||
501 bc
->cf_last
->inst
== V_SQ_CF_WORD1_SQ_CF_INST_POP
) {
505 if (((bc
->cf_last
->inst
!= (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
<< 3)) &&
506 (bc
->cf_last
->inst
!= (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
<< 3))) ||
507 LIST_IS_EMPTY(&bc
->cf_last
->alu
)) {
508 R600_ERR("last CF is not ALU (%p)\n", bc
->cf_last
);
511 alu
= LIST_ENTRY(struct r600_bc_alu
, bc
->cf_last
->alu
.prev
, list
);
512 if (!alu
->last
|| !alu
->nliteral
|| alu
->literal_added
) {
515 memcpy(alu
->value
, value
, 4 * 4);
516 bc
->cf_last
->ndw
+= alu
->nliteral
;
517 bc
->ndw
+= alu
->nliteral
;
518 alu
->literal_added
= 1;
522 int r600_bc_add_vtx(struct r600_bc
*bc
, const struct r600_bc_vtx
*vtx
)
524 struct r600_bc_vtx
*nvtx
= r600_bc_vtx();
529 memcpy(nvtx
, vtx
, sizeof(struct r600_bc_vtx
));
531 /* cf can contains only alu or only vtx or only tex */
532 if (bc
->cf_last
== NULL
||
533 (bc
->cf_last
->inst
!= V_SQ_CF_WORD1_SQ_CF_INST_VTX
&&
534 bc
->cf_last
->inst
!= V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC
) ||
536 r
= r600_bc_add_cf(bc
);
541 bc
->cf_last
->inst
= V_SQ_CF_WORD1_SQ_CF_INST_VTX
;
543 LIST_ADDTAIL(&nvtx
->list
, &bc
->cf_last
->vtx
);
544 /* each fetch use 4 dwords */
545 bc
->cf_last
->ndw
+= 4;
547 if ((bc
->ndw
/ 4) > 7)
548 bc
->force_add_cf
= 1;
552 int r600_bc_add_tex(struct r600_bc
*bc
, const struct r600_bc_tex
*tex
)
554 struct r600_bc_tex
*ntex
= r600_bc_tex();
559 memcpy(ntex
, tex
, sizeof(struct r600_bc_tex
));
561 /* cf can contains only alu or only vtx or only tex */
562 if (bc
->cf_last
== NULL
||
563 bc
->cf_last
->inst
!= V_SQ_CF_WORD1_SQ_CF_INST_TEX
||
565 r
= r600_bc_add_cf(bc
);
570 bc
->cf_last
->inst
= V_SQ_CF_WORD1_SQ_CF_INST_TEX
;
572 LIST_ADDTAIL(&ntex
->list
, &bc
->cf_last
->tex
);
573 /* each texture fetch use 4 dwords */
574 bc
->cf_last
->ndw
+= 4;
576 if ((bc
->ndw
/ 4) > 7)
577 bc
->force_add_cf
= 1;
581 int r600_bc_add_cfinst(struct r600_bc
*bc
, int inst
)
584 r
= r600_bc_add_cf(bc
);
588 bc
->cf_last
->cond
= V_SQ_CF_COND_ACTIVE
;
589 bc
->cf_last
->inst
= inst
;
593 /* common to all 3 families */
594 static int r600_bc_vtx_build(struct r600_bc
*bc
, struct r600_bc_vtx
*vtx
, unsigned id
)
596 bc
->bytecode
[id
++] = S_SQ_VTX_WORD0_BUFFER_ID(vtx
->buffer_id
) |
597 S_SQ_VTX_WORD0_SRC_GPR(vtx
->src_gpr
) |
598 S_SQ_VTX_WORD0_SRC_SEL_X(vtx
->src_sel_x
) |
599 S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx
->mega_fetch_count
);
600 bc
->bytecode
[id
++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx
->dst_sel_x
) |
601 S_SQ_VTX_WORD1_DST_SEL_Y(vtx
->dst_sel_y
) |
602 S_SQ_VTX_WORD1_DST_SEL_Z(vtx
->dst_sel_z
) |
603 S_SQ_VTX_WORD1_DST_SEL_W(vtx
->dst_sel_w
) |
604 S_SQ_VTX_WORD1_USE_CONST_FIELDS(1) |
605 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx
->dst_gpr
);
606 bc
->bytecode
[id
++] = S_SQ_VTX_WORD2_MEGA_FETCH(1);
607 bc
->bytecode
[id
++] = 0;
611 /* common to all 3 families */
612 static int r600_bc_tex_build(struct r600_bc
*bc
, struct r600_bc_tex
*tex
, unsigned id
)
614 bc
->bytecode
[id
++] = S_SQ_TEX_WORD0_TEX_INST(tex
->inst
) |
615 S_SQ_TEX_WORD0_RESOURCE_ID(tex
->resource_id
) |
616 S_SQ_TEX_WORD0_SRC_GPR(tex
->src_gpr
) |
617 S_SQ_TEX_WORD0_SRC_REL(tex
->src_rel
);
618 bc
->bytecode
[id
++] = S_SQ_TEX_WORD1_DST_GPR(tex
->dst_gpr
) |
619 S_SQ_TEX_WORD1_DST_REL(tex
->dst_rel
) |
620 S_SQ_TEX_WORD1_DST_SEL_X(tex
->dst_sel_x
) |
621 S_SQ_TEX_WORD1_DST_SEL_Y(tex
->dst_sel_y
) |
622 S_SQ_TEX_WORD1_DST_SEL_Z(tex
->dst_sel_z
) |
623 S_SQ_TEX_WORD1_DST_SEL_W(tex
->dst_sel_w
) |
624 S_SQ_TEX_WORD1_LOD_BIAS(tex
->lod_bias
) |
625 S_SQ_TEX_WORD1_COORD_TYPE_X(tex
->coord_type_x
) |
626 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex
->coord_type_y
) |
627 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex
->coord_type_z
) |
628 S_SQ_TEX_WORD1_COORD_TYPE_W(tex
->coord_type_w
);
629 bc
->bytecode
[id
++] = S_SQ_TEX_WORD2_OFFSET_X(tex
->offset_x
) |
630 S_SQ_TEX_WORD2_OFFSET_Y(tex
->offset_y
) |
631 S_SQ_TEX_WORD2_OFFSET_Z(tex
->offset_z
) |
632 S_SQ_TEX_WORD2_SAMPLER_ID(tex
->sampler_id
) |
633 S_SQ_TEX_WORD2_SRC_SEL_X(tex
->src_sel_x
) |
634 S_SQ_TEX_WORD2_SRC_SEL_Y(tex
->src_sel_y
) |
635 S_SQ_TEX_WORD2_SRC_SEL_Z(tex
->src_sel_z
) |
636 S_SQ_TEX_WORD2_SRC_SEL_W(tex
->src_sel_w
);
637 bc
->bytecode
[id
++] = 0;
641 /* r600 only, r700/eg bits in r700_asm.c */
642 static int r600_bc_alu_build(struct r600_bc
*bc
, struct r600_bc_alu
*alu
, unsigned id
)
646 /* don't replace gpr by pv or ps for destination register */
647 bc
->bytecode
[id
++] = S_SQ_ALU_WORD0_SRC0_SEL(alu
->src
[0].sel
) |
648 S_SQ_ALU_WORD0_SRC0_REL(alu
->src
[0].rel
) |
649 S_SQ_ALU_WORD0_SRC0_CHAN(alu
->src
[0].chan
) |
650 S_SQ_ALU_WORD0_SRC0_NEG(alu
->src
[0].neg
) |
651 S_SQ_ALU_WORD0_SRC1_SEL(alu
->src
[1].sel
) |
652 S_SQ_ALU_WORD0_SRC1_REL(alu
->src
[1].rel
) |
653 S_SQ_ALU_WORD0_SRC1_CHAN(alu
->src
[1].chan
) |
654 S_SQ_ALU_WORD0_SRC1_NEG(alu
->src
[1].neg
) |
655 S_SQ_ALU_WORD0_LAST(alu
->last
);
658 bc
->bytecode
[id
++] = S_SQ_ALU_WORD1_DST_GPR(alu
->dst
.sel
) |
659 S_SQ_ALU_WORD1_DST_CHAN(alu
->dst
.chan
) |
660 S_SQ_ALU_WORD1_DST_REL(alu
->dst
.rel
) |
661 S_SQ_ALU_WORD1_CLAMP(alu
->dst
.clamp
) |
662 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu
->src
[2].sel
) |
663 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu
->src
[2].rel
) |
664 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu
->src
[2].chan
) |
665 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu
->src
[2].neg
) |
666 S_SQ_ALU_WORD1_OP3_ALU_INST(alu
->inst
) |
667 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu
->bank_swizzle
);
669 bc
->bytecode
[id
++] = S_SQ_ALU_WORD1_DST_GPR(alu
->dst
.sel
) |
670 S_SQ_ALU_WORD1_DST_CHAN(alu
->dst
.chan
) |
671 S_SQ_ALU_WORD1_DST_REL(alu
->dst
.rel
) |
672 S_SQ_ALU_WORD1_CLAMP(alu
->dst
.clamp
) |
673 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu
->src
[0].abs
) |
674 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu
->src
[1].abs
) |
675 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu
->dst
.write
) |
676 S_SQ_ALU_WORD1_OP2_ALU_INST(alu
->inst
) |
677 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu
->bank_swizzle
) |
678 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu
->predicate
) |
679 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu
->predicate
);
682 if (alu
->nliteral
&& !alu
->literal_added
) {
683 R600_ERR("Bug in ALU processing for instruction 0x%08x, literal not added correctly\n", alu
->inst
);
685 for (i
= 0; i
< alu
->nliteral
; i
++) {
686 bc
->bytecode
[id
++] = alu
->value
[i
];
692 /* common for r600/r700 - eg in eg_asm.c */
693 static int r600_bc_cf_build(struct r600_bc
*bc
, struct r600_bc_cf
*cf
)
695 unsigned id
= cf
->id
;
698 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
<< 3):
699 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
<< 3):
700 bc
->bytecode
[id
++] = S_SQ_CF_ALU_WORD0_ADDR(cf
->addr
>> 1) |
701 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf
->kcache0_mode
);
703 bc
->bytecode
[id
++] = S_SQ_CF_ALU_WORD1_CF_INST(cf
->inst
>> 3) |
704 S_SQ_CF_ALU_WORD1_BARRIER(1) |
705 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc
->chiprev
== 0 ? cf
->r6xx_uses_waterfall
: 0) |
706 S_SQ_CF_ALU_WORD1_COUNT((cf
->ndw
/ 2) - 1);
708 case V_SQ_CF_WORD1_SQ_CF_INST_TEX
:
709 case V_SQ_CF_WORD1_SQ_CF_INST_VTX
:
710 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC
:
711 bc
->bytecode
[id
++] = S_SQ_CF_WORD0_ADDR(cf
->addr
>> 1);
712 bc
->bytecode
[id
++] = S_SQ_CF_WORD1_CF_INST(cf
->inst
) |
713 S_SQ_CF_WORD1_BARRIER(1) |
714 S_SQ_CF_WORD1_COUNT((cf
->ndw
/ 4) - 1);
716 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
:
717 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
:
718 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf
->output
.gpr
) |
719 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf
->output
.elem_size
) |
720 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf
->output
.array_base
) |
721 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf
->output
.type
);
722 bc
->bytecode
[id
++] = S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf
->output
.swizzle_x
) |
723 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf
->output
.swizzle_y
) |
724 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf
->output
.swizzle_z
) |
725 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf
->output
.swizzle_w
) |
726 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf
->output
.barrier
) |
727 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf
->output
.inst
) |
728 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf
->output
.end_of_program
);
730 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP
:
731 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE
:
732 case V_SQ_CF_WORD1_SQ_CF_INST_POP
:
733 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL
:
734 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
:
735 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
:
736 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
:
737 bc
->bytecode
[id
++] = S_SQ_CF_WORD0_ADDR(cf
->cf_addr
>> 1);
738 bc
->bytecode
[id
++] = S_SQ_CF_WORD1_CF_INST(cf
->inst
) |
739 S_SQ_CF_WORD1_BARRIER(1) |
740 S_SQ_CF_WORD1_COND(cf
->cond
) |
741 S_SQ_CF_WORD1_POP_COUNT(cf
->pop_count
);
745 R600_ERR("unsupported CF instruction (0x%X)\n", cf
->inst
);
751 int r600_bc_build(struct r600_bc
*bc
)
753 struct r600_bc_cf
*cf
;
754 struct r600_bc_alu
*alu
;
755 struct r600_bc_vtx
*vtx
;
756 struct r600_bc_tex
*tex
;
760 if (bc
->callstack
[0].max
> 0)
761 bc
->nstack
= ((bc
->callstack
[0].max
+ 3) >> 2) + 2;
763 /* first path compute addr of each CF block */
764 /* addr start after all the CF instructions */
765 addr
= bc
->cf_last
->id
+ 2;
766 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
768 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
<< 3):
769 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
<< 3):
771 case V_SQ_CF_WORD1_SQ_CF_INST_TEX
:
772 case V_SQ_CF_WORD1_SQ_CF_INST_VTX
:
773 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC
:
774 /* fetch node need to be 16 bytes aligned*/
776 addr
&= 0xFFFFFFFCUL
;
778 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
:
779 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
:
780 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
:
781 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
:
783 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP
:
784 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE
:
785 case V_SQ_CF_WORD1_SQ_CF_INST_POP
:
786 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL
:
787 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
:
788 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
:
789 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
:
792 R600_ERR("unsupported CF instruction (0x%X)\n", cf
->inst
);
797 bc
->ndw
= cf
->addr
+ cf
->ndw
;
800 bc
->bytecode
= calloc(1, bc
->ndw
* 4);
801 if (bc
->bytecode
== NULL
)
803 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
805 if (bc
->chiprev
== 2)
806 r
= eg_bc_cf_build(bc
, cf
);
808 r
= r600_bc_cf_build(bc
, cf
);
812 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
<< 3):
813 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
<< 3):
814 LIST_FOR_EACH_ENTRY(alu
, &cf
->alu
, list
) {
815 switch(bc
->chiprev
) {
817 r
= r600_bc_alu_build(bc
, alu
, addr
);
820 case 2: /* eg alu is same encoding as r700 */
821 r
= r700_bc_alu_build(bc
, alu
, addr
);
824 R600_ERR("unknown family %d\n", bc
->family
);
831 addr
+= alu
->nliteral
;
835 case V_SQ_CF_WORD1_SQ_CF_INST_VTX
:
836 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC
:
837 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
838 r
= r600_bc_vtx_build(bc
, vtx
, addr
);
844 case V_SQ_CF_WORD1_SQ_CF_INST_TEX
:
845 LIST_FOR_EACH_ENTRY(tex
, &cf
->tex
, list
) {
846 r
= r600_bc_tex_build(bc
, tex
, addr
);
852 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
:
853 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
:
854 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
:
855 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
:
856 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL
:
857 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
:
858 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
:
859 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
:
860 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP
:
861 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE
:
862 case V_SQ_CF_WORD1_SQ_CF_INST_POP
:
865 R600_ERR("unsupported CF instruction (0x%X)\n", cf
->inst
);