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r600g: improve kcache line sets handling v2
[mesa.git] / src / gallium / drivers / r600 / r600_asm.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include <stdio.h>
24 #include <errno.h>
25 #include <byteswap.h>
26 #include "util/u_format.h"
27 #include "util/u_memory.h"
28 #include "pipe/p_shader_tokens.h"
29 #include "r600_pipe.h"
30 #include "r600_sq.h"
31 #include "r600_opcodes.h"
32 #include "r600_asm.h"
33 #include "r600_formats.h"
34 #include "r600d.h"
35
36 #define NUM_OF_CYCLES 3
37 #define NUM_OF_COMPONENTS 4
38
39 static inline unsigned int r600_bytecode_get_num_operands(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
40 {
41 if(alu->is_op3)
42 return 3;
43
44 switch (bc->chip_class) {
45 case R600:
46 case R700:
47 switch (alu->inst) {
48 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
49 return 0;
50 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
51 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT:
52 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT:
53 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT:
54 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT:
55 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
56 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
57 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
58 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
59 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
60 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT:
61 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT:
62 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT:
63 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT:
64 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
65 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
66 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT:
67 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT:
68 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT:
69 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT:
70 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
71 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT:
72 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
73 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT:
74 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
75 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT:
76 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT:
77 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
78 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT:
79 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT:
80 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
81 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
82 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
83 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
84 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT:
85 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
86 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
87 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
88 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT:
89 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT:
90 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT:
91 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT:
92 return 2;
93
94 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
95 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA:
96 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR:
97 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT:
98 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
99 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
100 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
101 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
102 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
103 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
104 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
105 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
106 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
107 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT:
108 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
109 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
110 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
111 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT:
112 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT:
113 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT:
114 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
115 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
116 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE:
117 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT:
118 return 1;
119 default: R600_ERR(
120 "Need instruction operand number for 0x%x.\n", alu->inst);
121 }
122 break;
123 case EVERGREEN:
124 case CAYMAN:
125 switch (alu->inst) {
126 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
127 return 0;
128 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
129 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT:
130 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT:
131 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT:
132 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT:
133 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
134 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
135 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
136 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
137 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
138 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT:
139 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT:
140 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT:
141 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT:
142 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
143 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
144 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT:
145 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT:
146 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT:
147 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT:
148 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
149 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT:
150 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
151 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT:
152 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
153 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT:
154 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT:
155 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
156 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT:
157 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT:
158 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
159 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
160 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
161 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
162 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT:
163 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
164 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
165 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
166 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY:
167 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW:
168 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT:
169 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT:
170 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT:
171 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT:
172 return 2;
173
174 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
175 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
176 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
177 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
178 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
179 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
180 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
181 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
182 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
183 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
184 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
185 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
186 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
187 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR:
188 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT:
189 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT:
190 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT:
191 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
192 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
193 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE:
194 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT:
195 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_LOAD_P0:
196 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT:
197 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT:
198 return 1;
199 default: R600_ERR(
200 "Need instruction operand number for 0x%x.\n", alu->inst);
201 }
202 break;
203 }
204
205 return 3;
206 }
207
208 int r700_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id);
209
210 static struct r600_bytecode_cf *r600_bytecode_cf(void)
211 {
212 struct r600_bytecode_cf *cf = CALLOC_STRUCT(r600_bytecode_cf);
213
214 if (cf == NULL)
215 return NULL;
216 LIST_INITHEAD(&cf->list);
217 LIST_INITHEAD(&cf->alu);
218 LIST_INITHEAD(&cf->vtx);
219 LIST_INITHEAD(&cf->tex);
220 return cf;
221 }
222
223 static struct r600_bytecode_alu *r600_bytecode_alu(void)
224 {
225 struct r600_bytecode_alu *alu = CALLOC_STRUCT(r600_bytecode_alu);
226
227 if (alu == NULL)
228 return NULL;
229 LIST_INITHEAD(&alu->list);
230 return alu;
231 }
232
233 static struct r600_bytecode_vtx *r600_bytecode_vtx(void)
234 {
235 struct r600_bytecode_vtx *vtx = CALLOC_STRUCT(r600_bytecode_vtx);
236
237 if (vtx == NULL)
238 return NULL;
239 LIST_INITHEAD(&vtx->list);
240 return vtx;
241 }
242
243 static struct r600_bytecode_tex *r600_bytecode_tex(void)
244 {
245 struct r600_bytecode_tex *tex = CALLOC_STRUCT(r600_bytecode_tex);
246
247 if (tex == NULL)
248 return NULL;
249 LIST_INITHEAD(&tex->list);
250 return tex;
251 }
252
253 void r600_bytecode_init(struct r600_bytecode *bc, enum chip_class chip_class, enum radeon_family family)
254 {
255 if ((chip_class == R600) && (family != CHIP_RV670))
256 bc->ar_handling = AR_HANDLE_RV6XX;
257 else
258 bc->ar_handling = AR_HANDLE_NORMAL;
259
260 if ((chip_class == R600) && (family != CHIP_RV670 && family != CHIP_RS780 &&
261 family != CHIP_RS880))
262 bc->r6xx_nop_after_rel_dst = 1;
263 else
264 bc->r6xx_nop_after_rel_dst = 0;
265 LIST_INITHEAD(&bc->cf);
266 bc->chip_class = chip_class;
267 }
268
269 static int r600_bytecode_add_cf(struct r600_bytecode *bc)
270 {
271 struct r600_bytecode_cf *cf = r600_bytecode_cf();
272
273 if (cf == NULL)
274 return -ENOMEM;
275 LIST_ADDTAIL(&cf->list, &bc->cf);
276 if (bc->cf_last) {
277 cf->id = bc->cf_last->id + 2;
278 if (bc->cf_last->eg_alu_extended) {
279 /* take into account extended alu size */
280 cf->id += 2;
281 bc->ndw += 2;
282 }
283 }
284 bc->cf_last = cf;
285 bc->ncf++;
286 bc->ndw += 2;
287 bc->force_add_cf = 0;
288 bc->ar_loaded = 0;
289 return 0;
290 }
291
292 int r600_bytecode_add_output(struct r600_bytecode *bc, const struct r600_bytecode_output *output)
293 {
294 int r;
295
296 if (bc->cf_last && (bc->cf_last->inst == output->inst ||
297 (bc->cf_last->inst == BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT) &&
298 output->inst == BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE))) &&
299 output->type == bc->cf_last->output.type &&
300 output->elem_size == bc->cf_last->output.elem_size &&
301 output->swizzle_x == bc->cf_last->output.swizzle_x &&
302 output->swizzle_y == bc->cf_last->output.swizzle_y &&
303 output->swizzle_z == bc->cf_last->output.swizzle_z &&
304 output->swizzle_w == bc->cf_last->output.swizzle_w &&
305 (output->burst_count + bc->cf_last->output.burst_count) <= 16) {
306
307 if ((output->gpr + output->burst_count) == bc->cf_last->output.gpr &&
308 (output->array_base + output->burst_count) == bc->cf_last->output.array_base) {
309
310 bc->cf_last->output.end_of_program |= output->end_of_program;
311 bc->cf_last->output.inst = output->inst;
312 bc->cf_last->output.gpr = output->gpr;
313 bc->cf_last->output.array_base = output->array_base;
314 bc->cf_last->output.burst_count += output->burst_count;
315 return 0;
316
317 } else if (output->gpr == (bc->cf_last->output.gpr + bc->cf_last->output.burst_count) &&
318 output->array_base == (bc->cf_last->output.array_base + bc->cf_last->output.burst_count)) {
319
320 bc->cf_last->output.end_of_program |= output->end_of_program;
321 bc->cf_last->output.inst = output->inst;
322 bc->cf_last->output.burst_count += output->burst_count;
323 return 0;
324 }
325 }
326
327 r = r600_bytecode_add_cf(bc);
328 if (r)
329 return r;
330 bc->cf_last->inst = output->inst;
331 memcpy(&bc->cf_last->output, output, sizeof(struct r600_bytecode_output));
332 return 0;
333 }
334
335 /* alu instructions that can ony exits once per group */
336 static int is_alu_once_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
337 {
338 switch (bc->chip_class) {
339 case R600:
340 case R700:
341 return !alu->is_op3 && (
342 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
343 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
344 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
345 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
346 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
347 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
348 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
349 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
350 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
351 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
352 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
353 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
354 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
355 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
356 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
357 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
358 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
359 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
360 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
361 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
362 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
363 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
364 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
365 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
366 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
367 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
368 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
369 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
370 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
371 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
372 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
373 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
374 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
375 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
376 case EVERGREEN:
377 case CAYMAN:
378 default:
379 return !alu->is_op3 && (
380 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
381 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
382 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
383 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
384 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
385 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
386 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
387 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
388 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
389 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
390 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
391 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
392 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
393 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
394 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
395 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
396 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
397 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
398 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
399 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
400 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
401 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
402 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
403 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
404 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
405 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
406 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
407 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
408 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
409 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
410 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
411 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
412 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
413 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
414 }
415 }
416
417 static int is_alu_reduction_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
418 {
419 switch (bc->chip_class) {
420 case R600:
421 case R700:
422 return !alu->is_op3 && (
423 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
424 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
425 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
426 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
427 case EVERGREEN:
428 case CAYMAN:
429 default:
430 return !alu->is_op3 && (
431 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
432 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
433 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
434 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
435 }
436 }
437
438 static int is_alu_cube_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
439 {
440 switch (bc->chip_class) {
441 case R600:
442 case R700:
443 return !alu->is_op3 &&
444 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
445 case EVERGREEN:
446 case CAYMAN:
447 default:
448 return !alu->is_op3 &&
449 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
450 }
451 }
452
453 static int is_alu_mova_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
454 {
455 switch (bc->chip_class) {
456 case R600:
457 case R700:
458 return !alu->is_op3 && (
459 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA ||
460 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR ||
461 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT ||
462 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT);
463 case EVERGREEN:
464 case CAYMAN:
465 default:
466 return !alu->is_op3 && (
467 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
468 }
469 }
470
471 /* alu instructions that can only execute on the vector unit */
472 static int is_alu_vec_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
473 {
474 switch (bc->chip_class) {
475 case R600:
476 case R700:
477 return is_alu_reduction_inst(bc, alu) ||
478 (is_alu_mova_inst(bc, alu) &&
479 (alu->inst != V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT));
480 case EVERGREEN:
481 case CAYMAN:
482 default:
483 return is_alu_reduction_inst(bc, alu) ||
484 is_alu_mova_inst(bc, alu) ||
485 (alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT ||
486 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR ||
487 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_LOAD_P0 ||
488 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY ||
489 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW);
490 }
491 }
492
493 /* alu instructions that can only execute on the trans unit */
494 static int is_alu_trans_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
495 {
496 switch (bc->chip_class) {
497 case R600:
498 case R700:
499 if (!alu->is_op3)
500 return alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT ||
501 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT ||
502 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT ||
503 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT ||
504 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT ||
505 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT ||
506 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT ||
507 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT ||
508 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT ||
509 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT ||
510 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT ||
511 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT ||
512 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT ||
513 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT ||
514 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS ||
515 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE ||
516 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED ||
517 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE ||
518 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED ||
519 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_FF ||
520 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE ||
521 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED ||
522 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF ||
523 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE ||
524 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN ||
525 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_IEEE;
526 else
527 return alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT ||
528 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_D2 ||
529 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M2 ||
530 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M4;
531 case EVERGREEN:
532 case CAYMAN:
533 default:
534 if (!alu->is_op3)
535 /* Note that FLT_TO_INT_* instructions are vector-only instructions
536 * on Evergreen, despite what the documentation says. FLT_TO_INT
537 * can do both vector and scalar. */
538 return alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT ||
539 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT ||
540 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT ||
541 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT ||
542 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT ||
543 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT ||
544 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT ||
545 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT ||
546 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT ||
547 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS ||
548 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE ||
549 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED ||
550 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE ||
551 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED ||
552 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_FF ||
553 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE ||
554 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED ||
555 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF ||
556 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE ||
557 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN ||
558 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_IEEE;
559 else
560 return alu->inst == EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
561 }
562 }
563
564 /* alu instructions that can execute on any unit */
565 static int is_alu_any_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
566 {
567 return !is_alu_vec_unit_inst(bc, alu) &&
568 !is_alu_trans_unit_inst(bc, alu);
569 }
570
571 static int is_nop_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
572 {
573 switch (bc->chip_class) {
574 case R600:
575 case R700:
576 return (!alu->is_op3 && alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
577 case EVERGREEN:
578 case CAYMAN:
579 default:
580 return (!alu->is_op3 && alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
581 }
582 }
583
584 static int assign_alu_units(struct r600_bytecode *bc, struct r600_bytecode_alu *alu_first,
585 struct r600_bytecode_alu *assignment[5])
586 {
587 struct r600_bytecode_alu *alu;
588 unsigned i, chan, trans;
589 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
590
591 for (i = 0; i < max_slots; i++)
592 assignment[i] = NULL;
593
594 for (alu = alu_first; alu; alu = LIST_ENTRY(struct r600_bytecode_alu, alu->list.next, list)) {
595 chan = alu->dst.chan;
596 if (max_slots == 4)
597 trans = 0;
598 else if (is_alu_trans_unit_inst(bc, alu))
599 trans = 1;
600 else if (is_alu_vec_unit_inst(bc, alu))
601 trans = 0;
602 else if (assignment[chan])
603 trans = 1; /* Assume ALU_INST_PREFER_VECTOR. */
604 else
605 trans = 0;
606
607 if (trans) {
608 if (assignment[4]) {
609 assert(0); /* ALU.Trans has already been allocated. */
610 return -1;
611 }
612 assignment[4] = alu;
613 } else {
614 if (assignment[chan]) {
615 assert(0); /* ALU.chan has already been allocated. */
616 return -1;
617 }
618 assignment[chan] = alu;
619 }
620
621 if (alu->last)
622 break;
623 }
624 return 0;
625 }
626
627 struct alu_bank_swizzle {
628 int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
629 int hw_cfile_addr[4];
630 int hw_cfile_elem[4];
631 };
632
633 static const unsigned cycle_for_bank_swizzle_vec[][3] = {
634 [SQ_ALU_VEC_012] = { 0, 1, 2 },
635 [SQ_ALU_VEC_021] = { 0, 2, 1 },
636 [SQ_ALU_VEC_120] = { 1, 2, 0 },
637 [SQ_ALU_VEC_102] = { 1, 0, 2 },
638 [SQ_ALU_VEC_201] = { 2, 0, 1 },
639 [SQ_ALU_VEC_210] = { 2, 1, 0 }
640 };
641
642 static const unsigned cycle_for_bank_swizzle_scl[][3] = {
643 [SQ_ALU_SCL_210] = { 2, 1, 0 },
644 [SQ_ALU_SCL_122] = { 1, 2, 2 },
645 [SQ_ALU_SCL_212] = { 2, 1, 2 },
646 [SQ_ALU_SCL_221] = { 2, 2, 1 }
647 };
648
649 static void init_bank_swizzle(struct alu_bank_swizzle *bs)
650 {
651 int i, cycle, component;
652 /* set up gpr use */
653 for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
654 for (component = 0; component < NUM_OF_COMPONENTS; component++)
655 bs->hw_gpr[cycle][component] = -1;
656 for (i = 0; i < 4; i++)
657 bs->hw_cfile_addr[i] = -1;
658 for (i = 0; i < 4; i++)
659 bs->hw_cfile_elem[i] = -1;
660 }
661
662 static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan, unsigned cycle)
663 {
664 if (bs->hw_gpr[cycle][chan] == -1)
665 bs->hw_gpr[cycle][chan] = sel;
666 else if (bs->hw_gpr[cycle][chan] != (int)sel) {
667 /* Another scalar operation has already used the GPR read port for the channel. */
668 return -1;
669 }
670 return 0;
671 }
672
673 static int reserve_cfile(struct r600_bytecode *bc, struct alu_bank_swizzle *bs, unsigned sel, unsigned chan)
674 {
675 int res, num_res = 4;
676 if (bc->chip_class >= R700) {
677 num_res = 2;
678 chan /= 2;
679 }
680 for (res = 0; res < num_res; ++res) {
681 if (bs->hw_cfile_addr[res] == -1) {
682 bs->hw_cfile_addr[res] = sel;
683 bs->hw_cfile_elem[res] = chan;
684 return 0;
685 } else if (bs->hw_cfile_addr[res] == sel &&
686 bs->hw_cfile_elem[res] == chan)
687 return 0; /* Read for this scalar element already reserved, nothing to do here. */
688 }
689 /* All cfile read ports are used, cannot reference vector element. */
690 return -1;
691 }
692
693 static int is_gpr(unsigned sel)
694 {
695 return (sel >= 0 && sel <= 127);
696 }
697
698 /* CB constants start at 512, and get translated to a kcache index when ALU
699 * clauses are constructed. Note that we handle kcache constants the same way
700 * as (the now gone) cfile constants, is that really required? */
701 static int is_cfile(unsigned sel)
702 {
703 return (sel > 255 && sel < 512) ||
704 (sel > 511 && sel < 4607) || /* Kcache before translation. */
705 (sel > 127 && sel < 192); /* Kcache after translation. */
706 }
707
708 static int is_const(int sel)
709 {
710 return is_cfile(sel) ||
711 (sel >= V_SQ_ALU_SRC_0 &&
712 sel <= V_SQ_ALU_SRC_LITERAL);
713 }
714
715 static int check_vector(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
716 struct alu_bank_swizzle *bs, int bank_swizzle)
717 {
718 int r, src, num_src, sel, elem, cycle;
719
720 num_src = r600_bytecode_get_num_operands(bc, alu);
721 for (src = 0; src < num_src; src++) {
722 sel = alu->src[src].sel;
723 elem = alu->src[src].chan;
724 if (is_gpr(sel)) {
725 cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src];
726 if (src == 1 && sel == alu->src[0].sel && elem == alu->src[0].chan)
727 /* Nothing to do; special-case optimization,
728 * second source uses first source’s reservation. */
729 continue;
730 else {
731 r = reserve_gpr(bs, sel, elem, cycle);
732 if (r)
733 return r;
734 }
735 } else if (is_cfile(sel)) {
736 r = reserve_cfile(bc, bs, sel, elem);
737 if (r)
738 return r;
739 }
740 /* No restrictions on PV, PS, literal or special constants. */
741 }
742 return 0;
743 }
744
745 static int check_scalar(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
746 struct alu_bank_swizzle *bs, int bank_swizzle)
747 {
748 int r, src, num_src, const_count, sel, elem, cycle;
749
750 num_src = r600_bytecode_get_num_operands(bc, alu);
751 for (const_count = 0, src = 0; src < num_src; ++src) {
752 sel = alu->src[src].sel;
753 elem = alu->src[src].chan;
754 if (is_const(sel)) { /* Any constant, including literal and inline constants. */
755 if (const_count >= 2)
756 /* More than two references to a constant in
757 * transcendental operation. */
758 return -1;
759 else
760 const_count++;
761 }
762 if (is_cfile(sel)) {
763 r = reserve_cfile(bc, bs, sel, elem);
764 if (r)
765 return r;
766 }
767 }
768 for (src = 0; src < num_src; ++src) {
769 sel = alu->src[src].sel;
770 elem = alu->src[src].chan;
771 if (is_gpr(sel)) {
772 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
773 if (cycle < const_count)
774 /* Cycle for GPR load conflicts with
775 * constant load in transcendental operation. */
776 return -1;
777 r = reserve_gpr(bs, sel, elem, cycle);
778 if (r)
779 return r;
780 }
781 /* PV PS restrictions */
782 if (const_count && (sel == 254 || sel == 255)) {
783 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
784 if (cycle < const_count)
785 return -1;
786 }
787 }
788 return 0;
789 }
790
791 static int check_and_set_bank_swizzle(struct r600_bytecode *bc,
792 struct r600_bytecode_alu *slots[5])
793 {
794 struct alu_bank_swizzle bs;
795 int bank_swizzle[5];
796 int i, r = 0, forced = 1;
797 boolean scalar_only = bc->chip_class == CAYMAN ? false : true;
798 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
799
800 for (i = 0; i < max_slots; i++) {
801 if (slots[i]) {
802 if (slots[i]->bank_swizzle_force) {
803 slots[i]->bank_swizzle = slots[i]->bank_swizzle_force;
804 } else {
805 forced = 0;
806 }
807 }
808
809 if (i < 4 && slots[i])
810 scalar_only = false;
811 }
812 if (forced)
813 return 0;
814
815 /* Just check every possible combination of bank swizzle.
816 * Not very efficent, but works on the first try in most of the cases. */
817 for (i = 0; i < 4; i++)
818 if (!slots[i] || !slots[i]->bank_swizzle_force)
819 bank_swizzle[i] = SQ_ALU_VEC_012;
820 else
821 bank_swizzle[i] = slots[i]->bank_swizzle;
822
823 bank_swizzle[4] = SQ_ALU_SCL_210;
824 while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
825
826 if (max_slots == 4) {
827 for (i = 0; i < max_slots; i++) {
828 if (bank_swizzle[i] == SQ_ALU_VEC_210)
829 return -1;
830 }
831 }
832 init_bank_swizzle(&bs);
833 if (scalar_only == false) {
834 for (i = 0; i < 4; i++) {
835 if (slots[i]) {
836 r = check_vector(bc, slots[i], &bs, bank_swizzle[i]);
837 if (r)
838 break;
839 }
840 }
841 } else
842 r = 0;
843
844 if (!r && slots[4] && max_slots == 5) {
845 r = check_scalar(bc, slots[4], &bs, bank_swizzle[4]);
846 }
847 if (!r) {
848 for (i = 0; i < max_slots; i++) {
849 if (slots[i])
850 slots[i]->bank_swizzle = bank_swizzle[i];
851 }
852 return 0;
853 }
854
855 if (scalar_only) {
856 bank_swizzle[4]++;
857 } else {
858 for (i = 0; i < max_slots; i++) {
859 if (!slots[i] || !slots[i]->bank_swizzle_force) {
860 bank_swizzle[i]++;
861 if (bank_swizzle[i] <= SQ_ALU_VEC_210)
862 break;
863 else
864 bank_swizzle[i] = SQ_ALU_VEC_012;
865 }
866 }
867 }
868 }
869
870 /* Couldn't find a working swizzle. */
871 return -1;
872 }
873
874 static int replace_gpr_with_pv_ps(struct r600_bytecode *bc,
875 struct r600_bytecode_alu *slots[5], struct r600_bytecode_alu *alu_prev)
876 {
877 struct r600_bytecode_alu *prev[5];
878 int gpr[5], chan[5];
879 int i, j, r, src, num_src;
880 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
881
882 r = assign_alu_units(bc, alu_prev, prev);
883 if (r)
884 return r;
885
886 for (i = 0; i < max_slots; ++i) {
887 if (prev[i] && (prev[i]->dst.write || prev[i]->is_op3) && !prev[i]->dst.rel) {
888 gpr[i] = prev[i]->dst.sel;
889 /* cube writes more than PV.X */
890 if (!is_alu_cube_inst(bc, prev[i]) && is_alu_reduction_inst(bc, prev[i]))
891 chan[i] = 0;
892 else
893 chan[i] = prev[i]->dst.chan;
894 } else
895 gpr[i] = -1;
896 }
897
898 for (i = 0; i < max_slots; ++i) {
899 struct r600_bytecode_alu *alu = slots[i];
900 if(!alu)
901 continue;
902
903 num_src = r600_bytecode_get_num_operands(bc, alu);
904 for (src = 0; src < num_src; ++src) {
905 if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
906 continue;
907
908 if (bc->chip_class < CAYMAN) {
909 if (alu->src[src].sel == gpr[4] &&
910 alu->src[src].chan == chan[4]) {
911 alu->src[src].sel = V_SQ_ALU_SRC_PS;
912 alu->src[src].chan = 0;
913 continue;
914 }
915 }
916
917 for (j = 0; j < 4; ++j) {
918 if (alu->src[src].sel == gpr[j] &&
919 alu->src[src].chan == j) {
920 alu->src[src].sel = V_SQ_ALU_SRC_PV;
921 alu->src[src].chan = chan[j];
922 break;
923 }
924 }
925 }
926 }
927
928 return 0;
929 }
930
931 void r600_bytecode_special_constants(u32 value, unsigned *sel, unsigned *neg)
932 {
933 switch(value) {
934 case 0:
935 *sel = V_SQ_ALU_SRC_0;
936 break;
937 case 1:
938 *sel = V_SQ_ALU_SRC_1_INT;
939 break;
940 case -1:
941 *sel = V_SQ_ALU_SRC_M_1_INT;
942 break;
943 case 0x3F800000: /* 1.0f */
944 *sel = V_SQ_ALU_SRC_1;
945 break;
946 case 0x3F000000: /* 0.5f */
947 *sel = V_SQ_ALU_SRC_0_5;
948 break;
949 case 0xBF800000: /* -1.0f */
950 *sel = V_SQ_ALU_SRC_1;
951 *neg ^= 1;
952 break;
953 case 0xBF000000: /* -0.5f */
954 *sel = V_SQ_ALU_SRC_0_5;
955 *neg ^= 1;
956 break;
957 default:
958 *sel = V_SQ_ALU_SRC_LITERAL;
959 break;
960 }
961 }
962
963 /* compute how many literal are needed */
964 static int r600_bytecode_alu_nliterals(struct r600_bytecode *bc, struct r600_bytecode_alu *alu,
965 uint32_t literal[4], unsigned *nliteral)
966 {
967 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
968 unsigned i, j;
969
970 for (i = 0; i < num_src; ++i) {
971 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
972 uint32_t value = alu->src[i].value;
973 unsigned found = 0;
974 for (j = 0; j < *nliteral; ++j) {
975 if (literal[j] == value) {
976 found = 1;
977 break;
978 }
979 }
980 if (!found) {
981 if (*nliteral >= 4)
982 return -EINVAL;
983 literal[(*nliteral)++] = value;
984 }
985 }
986 }
987 return 0;
988 }
989
990 static void r600_bytecode_alu_adjust_literals(struct r600_bytecode *bc,
991 struct r600_bytecode_alu *alu,
992 uint32_t literal[4], unsigned nliteral)
993 {
994 unsigned num_src = r600_bytecode_get_num_operands(bc, alu);
995 unsigned i, j;
996
997 for (i = 0; i < num_src; ++i) {
998 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
999 uint32_t value = alu->src[i].value;
1000 for (j = 0; j < nliteral; ++j) {
1001 if (literal[j] == value) {
1002 alu->src[i].chan = j;
1003 break;
1004 }
1005 }
1006 }
1007 }
1008 }
1009
1010 static int merge_inst_groups(struct r600_bytecode *bc, struct r600_bytecode_alu *slots[5],
1011 struct r600_bytecode_alu *alu_prev)
1012 {
1013 struct r600_bytecode_alu *prev[5];
1014 struct r600_bytecode_alu *result[5] = { NULL };
1015
1016 uint32_t literal[4], prev_literal[4];
1017 unsigned nliteral = 0, prev_nliteral = 0;
1018
1019 int i, j, r, src, num_src;
1020 int num_once_inst = 0;
1021 int have_mova = 0, have_rel = 0;
1022 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
1023
1024 r = assign_alu_units(bc, alu_prev, prev);
1025 if (r)
1026 return r;
1027
1028 for (i = 0; i < max_slots; ++i) {
1029 struct r600_bytecode_alu *alu;
1030
1031 /* check number of literals */
1032 if (prev[i]) {
1033 if (r600_bytecode_alu_nliterals(bc, prev[i], literal, &nliteral))
1034 return 0;
1035 if (r600_bytecode_alu_nliterals(bc, prev[i], prev_literal, &prev_nliteral))
1036 return 0;
1037 if (is_alu_mova_inst(bc, prev[i])) {
1038 if (have_rel)
1039 return 0;
1040 have_mova = 1;
1041 }
1042 num_once_inst += is_alu_once_inst(bc, prev[i]);
1043 }
1044 if (slots[i] && r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral))
1045 return 0;
1046
1047 /* Let's check used slots. */
1048 if (prev[i] && !slots[i]) {
1049 result[i] = prev[i];
1050 continue;
1051 } else if (prev[i] && slots[i]) {
1052 if (max_slots == 5 && result[4] == NULL && prev[4] == NULL && slots[4] == NULL) {
1053 /* Trans unit is still free try to use it. */
1054 if (is_alu_any_unit_inst(bc, slots[i])) {
1055 result[i] = prev[i];
1056 result[4] = slots[i];
1057 } else if (is_alu_any_unit_inst(bc, prev[i])) {
1058 if (slots[i]->dst.sel == prev[i]->dst.sel &&
1059 (slots[i]->dst.write == 1 || slots[i]->is_op3) &&
1060 (prev[i]->dst.write == 1 || prev[i]->is_op3))
1061 return 0;
1062
1063 result[i] = slots[i];
1064 result[4] = prev[i];
1065 } else
1066 return 0;
1067 } else
1068 return 0;
1069 } else if(!slots[i]) {
1070 continue;
1071 } else {
1072 if (max_slots == 5 && slots[i] && prev[4] &&
1073 slots[i]->dst.sel == prev[4]->dst.sel &&
1074 slots[i]->dst.chan == prev[4]->dst.chan &&
1075 (slots[i]->dst.write == 1 || slots[i]->is_op3) &&
1076 (prev[4]->dst.write == 1 || prev[4]->is_op3))
1077 return 0;
1078
1079 result[i] = slots[i];
1080 }
1081
1082 alu = slots[i];
1083 num_once_inst += is_alu_once_inst(bc, alu);
1084
1085 /* don't reschedule NOPs */
1086 if (is_nop_inst(bc, alu))
1087 return 0;
1088
1089 /* Let's check dst gpr. */
1090 if (alu->dst.rel) {
1091 if (have_mova)
1092 return 0;
1093 have_rel = 1;
1094 }
1095
1096 /* Let's check source gprs */
1097 num_src = r600_bytecode_get_num_operands(bc, alu);
1098 for (src = 0; src < num_src; ++src) {
1099 if (alu->src[src].rel) {
1100 if (have_mova)
1101 return 0;
1102 have_rel = 1;
1103 }
1104
1105 /* Constants don't matter. */
1106 if (!is_gpr(alu->src[src].sel))
1107 continue;
1108
1109 for (j = 0; j < max_slots; ++j) {
1110 if (!prev[j] || !(prev[j]->dst.write || prev[j]->is_op3))
1111 continue;
1112
1113 /* If it's relative then we can't determin which gpr is really used. */
1114 if (prev[j]->dst.chan == alu->src[src].chan &&
1115 (prev[j]->dst.sel == alu->src[src].sel ||
1116 prev[j]->dst.rel || alu->src[src].rel))
1117 return 0;
1118 }
1119 }
1120 }
1121
1122 /* more than one PRED_ or KILL_ ? */
1123 if (num_once_inst > 1)
1124 return 0;
1125
1126 /* check if the result can still be swizzlet */
1127 r = check_and_set_bank_swizzle(bc, result);
1128 if (r)
1129 return 0;
1130
1131 /* looks like everything worked out right, apply the changes */
1132
1133 /* undo adding previus literals */
1134 bc->cf_last->ndw -= align(prev_nliteral, 2);
1135
1136 /* sort instructions */
1137 for (i = 0; i < max_slots; ++i) {
1138 slots[i] = result[i];
1139 if (result[i]) {
1140 LIST_DEL(&result[i]->list);
1141 result[i]->last = 0;
1142 LIST_ADDTAIL(&result[i]->list, &bc->cf_last->alu);
1143 }
1144 }
1145
1146 /* determine new last instruction */
1147 LIST_ENTRY(struct r600_bytecode_alu, bc->cf_last->alu.prev, list)->last = 1;
1148
1149 /* determine new first instruction */
1150 for (i = 0; i < max_slots; ++i) {
1151 if (result[i]) {
1152 bc->cf_last->curr_bs_head = result[i];
1153 break;
1154 }
1155 }
1156
1157 bc->cf_last->prev_bs_head = bc->cf_last->prev2_bs_head;
1158 bc->cf_last->prev2_bs_head = NULL;
1159
1160 return 0;
1161 }
1162
1163 /* we'll keep kcache sets sorted by bank & addr */
1164 static int r600_bytecode_alloc_kcache_line(struct r600_bytecode *bc,
1165 struct r600_bytecode_kcache *kcache,
1166 unsigned bank, unsigned line)
1167 {
1168 int i, kcache_banks = bc->chip_class >= EVERGREEN ? 4 : 2;
1169
1170 for (i = 0; i < kcache_banks; i++) {
1171 if (kcache[i].mode) {
1172 int d;
1173
1174 if (kcache[i].bank < bank)
1175 continue;
1176
1177 if ((kcache[i].bank == bank && kcache[i].addr > line+1) ||
1178 kcache[i].bank > bank) {
1179 /* try to insert new line */
1180 if (kcache[kcache_banks-1].mode) {
1181 /* all sets are in use */
1182 return -ENOMEM;
1183 }
1184
1185 memmove(&kcache[i+1],&kcache[i], (kcache_banks-i-1)*sizeof(struct r600_bytecode_kcache));
1186 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
1187 kcache[i].bank = bank;
1188 kcache[i].addr = line;
1189 return 0;
1190 }
1191
1192 d = line - kcache[i].addr;
1193
1194 if (d == -1) {
1195 kcache[i].addr--;
1196 if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_2) {
1197 /* we are prepending the line to the current set,
1198 * discarding the existing second line,
1199 * so we'll have to insert line+2 after it */
1200 line += 2;
1201 continue;
1202 } else if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_1) {
1203 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
1204 return 0;
1205 } else {
1206 /* V_SQ_CF_KCACHE_LOCK_LOOP_INDEX is not supported */
1207 return -ENOMEM;
1208 }
1209 } else if (d == 1) {
1210 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
1211 return 0;
1212 } else if (d == 0)
1213 return 0;
1214 } else { /* free kcache set - use it */
1215 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
1216 kcache[i].bank = bank;
1217 kcache[i].addr = line;
1218 return 0;
1219 }
1220 }
1221 return -ENOMEM;
1222 }
1223
1224 static int r600_bytecode_alloc_inst_kcache_lines(struct r600_bytecode *bc,
1225 struct r600_bytecode_kcache *kcache,
1226 struct r600_bytecode_alu *alu)
1227 {
1228 int i, r;
1229
1230 for (i = 0; i < 3; i++) {
1231 unsigned bank, line, sel = alu->src[i].sel;
1232
1233 if (sel < 512)
1234 continue;
1235
1236 bank = alu->src[i].kc_bank;
1237 line = (sel-512)>>4;
1238
1239 if ((r = r600_bytecode_alloc_kcache_line(bc, kcache, bank, line)))
1240 return r;
1241 }
1242 return 0;
1243 }
1244
1245 static int r600_bytecode_assign_kcache_banks(struct r600_bytecode *bc,
1246 struct r600_bytecode_alu *alu,
1247 struct r600_bytecode_kcache * kcache)
1248 {
1249 int i, j;
1250
1251 /* Alter the src operands to refer to the kcache. */
1252 for (i = 0; i < 3; ++i) {
1253 static const unsigned int base[] = {128, 160, 256, 288};
1254 unsigned int line, sel = alu->src[i].sel, found = 0;
1255
1256 if (sel < 512)
1257 continue;
1258
1259 sel -= 512;
1260 line = sel>>4;
1261
1262 for (j = 0; j < 4 && !found; ++j) {
1263 switch (kcache[j].mode) {
1264 case V_SQ_CF_KCACHE_NOP:
1265 case V_SQ_CF_KCACHE_LOCK_LOOP_INDEX:
1266 R600_ERR("unexpected kcache line mode\n");
1267 return -ENOMEM;
1268 default:
1269 if (kcache[j].bank == alu->src[i].kc_bank &&
1270 kcache[j].addr <= line &&
1271 line < kcache[j].addr + kcache[j].mode) {
1272 alu->src[i].sel = sel - (kcache[j].addr<<4);
1273 alu->src[i].sel += base[j];
1274 found=1;
1275 }
1276 }
1277 }
1278 }
1279 return 0;
1280 }
1281
1282 static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, int type)
1283 {
1284 struct r600_bytecode_kcache kcache_sets[4];
1285 struct r600_bytecode_kcache *kcache = kcache_sets;
1286 int r;
1287
1288 memcpy(kcache, bc->cf_last->kcache, 4 * sizeof(struct r600_bytecode_kcache));
1289
1290 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1291 /* can't alloc, need to start new clause */
1292 if ((r = r600_bytecode_add_cf(bc))) {
1293 return r;
1294 }
1295 bc->cf_last->inst = type;
1296
1297 /* retry with the new clause */
1298 kcache = bc->cf_last->kcache;
1299 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1300 /* can't alloc again- should never happen */
1301 return r;
1302 }
1303 } else {
1304 /* update kcache sets */
1305 memcpy(bc->cf_last->kcache, kcache, 4 * sizeof(struct r600_bytecode_kcache));
1306 }
1307
1308 /* if we actually used more than 2 kcache sets - use ALU_EXTENDED on eg+ */
1309 if (kcache[2].mode != V_SQ_CF_KCACHE_NOP) {
1310 if (bc->chip_class < EVERGREEN)
1311 return -ENOMEM;
1312 bc->cf_last->eg_alu_extended = 1;
1313 }
1314
1315 return 0;
1316 }
1317
1318 static int insert_nop_r6xx(struct r600_bytecode *bc)
1319 {
1320 struct r600_bytecode_alu alu;
1321 int r, i;
1322
1323 for (i = 0; i < 4; i++) {
1324 memset(&alu, 0, sizeof(alu));
1325 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP;
1326 alu.src[0].chan = i;
1327 alu.dst.chan = i;
1328 alu.last = (i == 3);
1329 r = r600_bytecode_add_alu(bc, &alu);
1330 if (r)
1331 return r;
1332 }
1333 return 0;
1334 }
1335
1336 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1337 static int load_ar_r6xx(struct r600_bytecode *bc)
1338 {
1339 struct r600_bytecode_alu alu;
1340 int r;
1341
1342 if (bc->ar_loaded)
1343 return 0;
1344
1345 /* hack to avoid making MOVA the last instruction in the clause */
1346 if ((bc->cf_last->ndw>>1) >= 110)
1347 bc->force_add_cf = 1;
1348
1349 memset(&alu, 0, sizeof(alu));
1350 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT;
1351 alu.src[0].sel = bc->ar_reg;
1352 alu.last = 1;
1353 alu.index_mode = INDEX_MODE_LOOP;
1354 r = r600_bytecode_add_alu(bc, &alu);
1355 if (r)
1356 return r;
1357
1358 /* no requirement to set uses waterfall on MOVA_GPR_INT */
1359 bc->ar_loaded = 1;
1360 return 0;
1361 }
1362
1363 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1364 static int load_ar(struct r600_bytecode *bc)
1365 {
1366 struct r600_bytecode_alu alu;
1367 int r;
1368
1369 if (bc->ar_handling)
1370 return load_ar_r6xx(bc);
1371
1372 if (bc->ar_loaded)
1373 return 0;
1374
1375 /* hack to avoid making MOVA the last instruction in the clause */
1376 if ((bc->cf_last->ndw>>1) >= 110)
1377 bc->force_add_cf = 1;
1378
1379 memset(&alu, 0, sizeof(alu));
1380 alu.inst = BC_INST(bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
1381 alu.src[0].sel = bc->ar_reg;
1382 alu.last = 1;
1383 r = r600_bytecode_add_alu(bc, &alu);
1384 if (r)
1385 return r;
1386
1387 bc->cf_last->r6xx_uses_waterfall = 1;
1388 bc->ar_loaded = 1;
1389 return 0;
1390 }
1391
1392 int r600_bytecode_add_alu_type(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu, int type)
1393 {
1394 struct r600_bytecode_alu *nalu = r600_bytecode_alu();
1395 struct r600_bytecode_alu *lalu;
1396 int i, r;
1397
1398 if (nalu == NULL)
1399 return -ENOMEM;
1400 memcpy(nalu, alu, sizeof(struct r600_bytecode_alu));
1401
1402 if (bc->cf_last != NULL && bc->cf_last->inst != type) {
1403 /* check if we could add it anyway */
1404 if (bc->cf_last->inst == BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU) &&
1405 type == BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE)) {
1406 LIST_FOR_EACH_ENTRY(lalu, &bc->cf_last->alu, list) {
1407 if (lalu->predicate) {
1408 bc->force_add_cf = 1;
1409 break;
1410 }
1411 }
1412 } else
1413 bc->force_add_cf = 1;
1414 }
1415
1416 /* cf can contains only alu or only vtx or only tex */
1417 if (bc->cf_last == NULL || bc->force_add_cf) {
1418 r = r600_bytecode_add_cf(bc);
1419 if (r) {
1420 free(nalu);
1421 return r;
1422 }
1423 }
1424 bc->cf_last->inst = type;
1425
1426 /* Check AR usage and load it if required */
1427 for (i = 0; i < 3; i++)
1428 if (nalu->src[i].rel && !bc->ar_loaded)
1429 load_ar(bc);
1430
1431 if (nalu->dst.rel && !bc->ar_loaded)
1432 load_ar(bc);
1433
1434 /* Setup the kcache for this ALU instruction. This will start a new
1435 * ALU clause if needed. */
1436 if ((r = r600_bytecode_alloc_kcache_lines(bc, nalu, type))) {
1437 free(nalu);
1438 return r;
1439 }
1440
1441 if (!bc->cf_last->curr_bs_head) {
1442 bc->cf_last->curr_bs_head = nalu;
1443 }
1444 /* number of gpr == the last gpr used in any alu */
1445 for (i = 0; i < 3; i++) {
1446 if (nalu->src[i].sel >= bc->ngpr && nalu->src[i].sel < 128) {
1447 bc->ngpr = nalu->src[i].sel + 1;
1448 }
1449 if (nalu->src[i].sel == V_SQ_ALU_SRC_LITERAL)
1450 r600_bytecode_special_constants(nalu->src[i].value,
1451 &nalu->src[i].sel, &nalu->src[i].neg);
1452 }
1453 if (nalu->dst.sel >= bc->ngpr) {
1454 bc->ngpr = nalu->dst.sel + 1;
1455 }
1456 LIST_ADDTAIL(&nalu->list, &bc->cf_last->alu);
1457 /* each alu use 2 dwords */
1458 bc->cf_last->ndw += 2;
1459 bc->ndw += 2;
1460
1461 /* process cur ALU instructions for bank swizzle */
1462 if (nalu->last) {
1463 uint32_t literal[4];
1464 unsigned nliteral;
1465 struct r600_bytecode_alu *slots[5];
1466 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
1467 r = assign_alu_units(bc, bc->cf_last->curr_bs_head, slots);
1468 if (r)
1469 return r;
1470
1471 if (bc->cf_last->prev_bs_head) {
1472 r = merge_inst_groups(bc, slots, bc->cf_last->prev_bs_head);
1473 if (r)
1474 return r;
1475 }
1476
1477 if (bc->cf_last->prev_bs_head) {
1478 r = replace_gpr_with_pv_ps(bc, slots, bc->cf_last->prev_bs_head);
1479 if (r)
1480 return r;
1481 }
1482
1483 r = check_and_set_bank_swizzle(bc, slots);
1484 if (r)
1485 return r;
1486
1487 for (i = 0, nliteral = 0; i < max_slots; i++) {
1488 if (slots[i]) {
1489 r = r600_bytecode_alu_nliterals(bc, slots[i], literal, &nliteral);
1490 if (r)
1491 return r;
1492 }
1493 }
1494 bc->cf_last->ndw += align(nliteral, 2);
1495
1496 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1497 * worst case */
1498 if ((bc->cf_last->ndw >> 1) >= 120) {
1499 bc->force_add_cf = 1;
1500 }
1501
1502 bc->cf_last->prev2_bs_head = bc->cf_last->prev_bs_head;
1503 bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head;
1504 bc->cf_last->curr_bs_head = NULL;
1505 }
1506
1507 if (nalu->dst.rel && bc->r6xx_nop_after_rel_dst)
1508 insert_nop_r6xx(bc);
1509
1510 return 0;
1511 }
1512
1513 int r600_bytecode_add_alu(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu)
1514 {
1515 return r600_bytecode_add_alu_type(bc, alu, BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
1516 }
1517
1518 static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode *bc)
1519 {
1520 switch (bc->chip_class) {
1521 case R600:
1522 return 8;
1523
1524 case R700:
1525 case EVERGREEN:
1526 case CAYMAN:
1527 return 16;
1528
1529 default:
1530 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1531 return 8;
1532 }
1533 }
1534
1535 static inline boolean last_inst_was_not_vtx_fetch(struct r600_bytecode *bc)
1536 {
1537 switch (bc->chip_class) {
1538 case R700:
1539 case R600:
1540 return bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX &&
1541 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC;
1542 case EVERGREEN:
1543 return bc->cf_last->inst != EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1544 case CAYMAN:
1545 return bc->cf_last->inst != CM_V_SQ_CF_WORD1_SQ_CF_INST_TC;
1546 default:
1547 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1548 return FALSE;
1549 }
1550 }
1551
1552 int r600_bytecode_add_vtx(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx)
1553 {
1554 struct r600_bytecode_vtx *nvtx = r600_bytecode_vtx();
1555 int r;
1556
1557 if (nvtx == NULL)
1558 return -ENOMEM;
1559 memcpy(nvtx, vtx, sizeof(struct r600_bytecode_vtx));
1560
1561 /* cf can contains only alu or only vtx or only tex */
1562 if (bc->cf_last == NULL ||
1563 last_inst_was_not_vtx_fetch(bc) ||
1564 bc->force_add_cf) {
1565 r = r600_bytecode_add_cf(bc);
1566 if (r) {
1567 free(nvtx);
1568 return r;
1569 }
1570 switch (bc->chip_class) {
1571 case R600:
1572 case R700:
1573 bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1574 break;
1575 case EVERGREEN:
1576 bc->cf_last->inst = EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1577 break;
1578 case CAYMAN:
1579 bc->cf_last->inst = CM_V_SQ_CF_WORD1_SQ_CF_INST_TC;
1580 break;
1581 default:
1582 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1583 return -EINVAL;
1584 }
1585 }
1586 LIST_ADDTAIL(&nvtx->list, &bc->cf_last->vtx);
1587 /* each fetch use 4 dwords */
1588 bc->cf_last->ndw += 4;
1589 bc->ndw += 4;
1590 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1591 bc->force_add_cf = 1;
1592 return 0;
1593 }
1594
1595 int r600_bytecode_add_tex(struct r600_bytecode *bc, const struct r600_bytecode_tex *tex)
1596 {
1597 struct r600_bytecode_tex *ntex = r600_bytecode_tex();
1598 int r;
1599
1600 if (ntex == NULL)
1601 return -ENOMEM;
1602 memcpy(ntex, tex, sizeof(struct r600_bytecode_tex));
1603
1604 /* we can't fetch data und use it as texture lookup address in the same TEX clause */
1605 if (bc->cf_last != NULL &&
1606 bc->cf_last->inst == BC_INST(bc, V_SQ_CF_WORD1_SQ_CF_INST_TEX)) {
1607 struct r600_bytecode_tex *ttex;
1608 LIST_FOR_EACH_ENTRY(ttex, &bc->cf_last->tex, list) {
1609 if (ttex->dst_gpr == ntex->src_gpr) {
1610 bc->force_add_cf = 1;
1611 break;
1612 }
1613 }
1614 /* slight hack to make gradients always go into same cf */
1615 if (ntex->inst == SQ_TEX_INST_SET_GRADIENTS_H)
1616 bc->force_add_cf = 1;
1617 }
1618
1619 /* cf can contains only alu or only vtx or only tex */
1620 if (bc->cf_last == NULL ||
1621 bc->cf_last->inst != BC_INST(bc, V_SQ_CF_WORD1_SQ_CF_INST_TEX) ||
1622 bc->force_add_cf) {
1623 r = r600_bytecode_add_cf(bc);
1624 if (r) {
1625 free(ntex);
1626 return r;
1627 }
1628 bc->cf_last->inst = BC_INST(bc, V_SQ_CF_WORD1_SQ_CF_INST_TEX);
1629 }
1630 if (ntex->src_gpr >= bc->ngpr) {
1631 bc->ngpr = ntex->src_gpr + 1;
1632 }
1633 if (ntex->dst_gpr >= bc->ngpr) {
1634 bc->ngpr = ntex->dst_gpr + 1;
1635 }
1636 LIST_ADDTAIL(&ntex->list, &bc->cf_last->tex);
1637 /* each texture fetch use 4 dwords */
1638 bc->cf_last->ndw += 4;
1639 bc->ndw += 4;
1640 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1641 bc->force_add_cf = 1;
1642 return 0;
1643 }
1644
1645 int r600_bytecode_add_cfinst(struct r600_bytecode *bc, int inst)
1646 {
1647 int r;
1648 r = r600_bytecode_add_cf(bc);
1649 if (r)
1650 return r;
1651
1652 bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
1653 bc->cf_last->inst = inst;
1654 return 0;
1655 }
1656
1657 int cm_bytecode_add_cf_end(struct r600_bytecode *bc)
1658 {
1659 return r600_bytecode_add_cfinst(bc, CM_V_SQ_CF_WORD1_SQ_CF_INST_END);
1660 }
1661
1662 /* common to all 3 families */
1663 static int r600_bytecode_vtx_build(struct r600_bytecode *bc, struct r600_bytecode_vtx *vtx, unsigned id)
1664 {
1665 bc->bytecode[id] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) |
1666 S_SQ_VTX_WORD0_FETCH_TYPE(vtx->fetch_type) |
1667 S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
1668 S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x);
1669 if (bc->chip_class < CAYMAN)
1670 bc->bytecode[id] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
1671 id++;
1672 bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
1673 S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
1674 S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
1675 S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
1676 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) |
1677 S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) |
1678 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) |
1679 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) |
1680 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
1681 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
1682 bc->bytecode[id] = S_SQ_VTX_WORD2_OFFSET(vtx->offset)|
1683 S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx->endian);
1684 if (bc->chip_class < CAYMAN)
1685 bc->bytecode[id] |= S_SQ_VTX_WORD2_MEGA_FETCH(1);
1686 id++;
1687 bc->bytecode[id++] = 0;
1688 return 0;
1689 }
1690
1691 /* common to all 3 families */
1692 static int r600_bytecode_tex_build(struct r600_bytecode *bc, struct r600_bytecode_tex *tex, unsigned id)
1693 {
1694 bc->bytecode[id++] = S_SQ_TEX_WORD0_TEX_INST(tex->inst) |
1695 S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
1696 S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
1697 S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
1698 bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
1699 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
1700 S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
1701 S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
1702 S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
1703 S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
1704 S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
1705 S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
1706 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
1707 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
1708 S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
1709 bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
1710 S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
1711 S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
1712 S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
1713 S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
1714 S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
1715 S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
1716 S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
1717 bc->bytecode[id++] = 0;
1718 return 0;
1719 }
1720
1721 /* r600 only, r700/eg bits in r700_asm.c */
1722 static int r600_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id)
1723 {
1724 /* don't replace gpr by pv or ps for destination register */
1725 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
1726 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
1727 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
1728 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
1729 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
1730 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
1731 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
1732 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
1733 S_SQ_ALU_WORD0_INDEX_MODE(alu->index_mode) |
1734 S_SQ_ALU_WORD0_LAST(alu->last);
1735
1736 if (alu->is_op3) {
1737 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1738 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1739 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1740 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1741 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
1742 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
1743 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
1744 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
1745 S_SQ_ALU_WORD1_OP3_ALU_INST(alu->inst) |
1746 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
1747 } else {
1748 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1749 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1750 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1751 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1752 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
1753 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
1754 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
1755 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
1756 S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
1757 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
1758 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->predicate) |
1759 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->predicate);
1760 }
1761 return 0;
1762 }
1763
1764 static void r600_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_cf *cf)
1765 {
1766 *bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
1767 *bytecode++ = cf->inst |
1768 S_SQ_CF_WORD1_BARRIER(1) |
1769 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
1770 }
1771
1772 /* common for r600/r700 - eg in eg_asm.c */
1773 static int r600_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf)
1774 {
1775 unsigned id = cf->id;
1776
1777 switch (cf->inst) {
1778 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
1779 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
1780 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
1781 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
1782 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
1783 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
1784 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
1785 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank);
1786
1787 bc->bytecode[id++] = cf->inst |
1788 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) |
1789 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
1790 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
1791 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1792 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chip_class == R600 ? cf->r6xx_uses_waterfall : 0) |
1793 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
1794 break;
1795 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1796 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1797 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1798 if (bc->chip_class == R700)
1799 r700_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1800 else
1801 r600_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1802 break;
1803 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1804 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1805 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1806 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1807 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1808 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
1809 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1810 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
1811 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
1812 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
1813 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
1814 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
1815 cf->output.inst |
1816 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program);
1817 break;
1818 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
1819 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
1820 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
1821 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
1822 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1823 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1824 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1825 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
1826 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1827 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
1828 cf->output.inst |
1829 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program) |
1830 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf->output.array_size) |
1831 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf->output.comp_mask);
1832 break;
1833 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1834 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1835 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1836 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1837 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1838 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1839 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1840 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1841 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1842 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
1843 bc->bytecode[id++] = cf->inst |
1844 S_SQ_CF_WORD1_BARRIER(1) |
1845 S_SQ_CF_WORD1_COND(cf->cond) |
1846 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count);
1847
1848 break;
1849 default:
1850 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1851 return -EINVAL;
1852 }
1853 return 0;
1854 }
1855
1856 int r600_bytecode_build(struct r600_bytecode *bc)
1857 {
1858 struct r600_bytecode_cf *cf;
1859 struct r600_bytecode_alu *alu;
1860 struct r600_bytecode_vtx *vtx;
1861 struct r600_bytecode_tex *tex;
1862 uint32_t literal[4];
1863 unsigned nliteral;
1864 unsigned addr;
1865 int i, r;
1866
1867 if (bc->callstack[0].max > 0)
1868 bc->nstack = ((bc->callstack[0].max + 3) >> 2) + 2;
1869 if (bc->type == TGSI_PROCESSOR_VERTEX && !bc->nstack) {
1870 bc->nstack = 1;
1871 }
1872
1873 /* first path compute addr of each CF block */
1874 /* addr start after all the CF instructions */
1875 addr = bc->cf_last->id + 2;
1876 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1877 if (bc->chip_class >= EVERGREEN) {
1878 switch (cf->inst) {
1879 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1880 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1881 /* fetch node need to be 16 bytes aligned*/
1882 addr += 3;
1883 addr &= 0xFFFFFFFCUL;
1884 break;
1885 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
1886 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
1887 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
1888 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
1889 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1890 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1891 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0:
1892 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1:
1893 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2:
1894 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3:
1895 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0:
1896 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1:
1897 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2:
1898 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3:
1899 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0:
1900 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1:
1901 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2:
1902 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3:
1903 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0:
1904 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1:
1905 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2:
1906 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3:
1907 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1908 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1909 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
1910 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1911 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1912 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1913 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1914 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1915 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1916 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
1917 break;
1918 default:
1919 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1920 return -EINVAL;
1921 }
1922 } else {
1923 switch (cf->inst) {
1924 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1925 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1926 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1927 /* fetch node need to be 16 bytes aligned*/
1928 addr += 3;
1929 addr &= 0xFFFFFFFCUL;
1930 break;
1931 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
1932 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
1933 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
1934 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
1935 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1936 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1937 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
1938 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
1939 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
1940 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
1941 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1942 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1943 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1944 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1945 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1946 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1947 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1948 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1949 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1950 break;
1951 default:
1952 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1953 return -EINVAL;
1954 }
1955 }
1956 cf->addr = addr;
1957 addr += cf->ndw;
1958 bc->ndw = cf->addr + cf->ndw;
1959 }
1960 free(bc->bytecode);
1961 bc->bytecode = calloc(1, bc->ndw * 4);
1962 if (bc->bytecode == NULL)
1963 return -ENOMEM;
1964 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1965 addr = cf->addr;
1966 if (bc->chip_class >= EVERGREEN) {
1967 r = eg_bytecode_cf_build(bc, cf);
1968 if (r)
1969 return r;
1970
1971 switch (cf->inst) {
1972 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
1973 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
1974 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
1975 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
1976 nliteral = 0;
1977 memset(literal, 0, sizeof(literal));
1978 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1979 r = r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
1980 if (r)
1981 return r;
1982 r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral);
1983 r600_bytecode_assign_kcache_banks(bc, alu, cf->kcache);
1984
1985 switch(bc->chip_class) {
1986 case EVERGREEN: /* eg alu is same encoding as r700 */
1987 case CAYMAN:
1988 r = r700_bytecode_alu_build(bc, alu, addr);
1989 break;
1990 default:
1991 R600_ERR("unknown chip class %d.\n", bc->chip_class);
1992 return -EINVAL;
1993 }
1994 if (r)
1995 return r;
1996 addr += 2;
1997 if (alu->last) {
1998 for (i = 0; i < align(nliteral, 2); ++i) {
1999 bc->bytecode[addr++] = literal[i];
2000 }
2001 nliteral = 0;
2002 memset(literal, 0, sizeof(literal));
2003 }
2004 }
2005 break;
2006 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2007 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2008 r = r600_bytecode_vtx_build(bc, vtx, addr);
2009 if (r)
2010 return r;
2011 addr += 4;
2012 }
2013 break;
2014 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2015 if (bc->chip_class == CAYMAN) {
2016 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2017 r = r600_bytecode_vtx_build(bc, vtx, addr);
2018 if (r)
2019 return r;
2020 addr += 4;
2021 }
2022 }
2023 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2024 r = r600_bytecode_tex_build(bc, tex, addr);
2025 if (r)
2026 return r;
2027 addr += 4;
2028 }
2029 break;
2030 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2031 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2032 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0:
2033 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1:
2034 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2:
2035 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3:
2036 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0:
2037 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1:
2038 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2:
2039 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3:
2040 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0:
2041 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1:
2042 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2:
2043 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3:
2044 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0:
2045 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1:
2046 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2:
2047 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3:
2048 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
2049 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2050 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2051 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2052 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2053 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2054 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
2055 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2056 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2057 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
2058 break;
2059 default:
2060 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
2061 return -EINVAL;
2062 }
2063 } else {
2064 r = r600_bytecode_cf_build(bc, cf);
2065 if (r)
2066 return r;
2067
2068 switch (cf->inst) {
2069 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
2070 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
2071 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
2072 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
2073 nliteral = 0;
2074 memset(literal, 0, sizeof(literal));
2075 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
2076 r = r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
2077 if (r)
2078 return r;
2079 r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral);
2080 r600_bytecode_assign_kcache_banks(bc, alu, cf->kcache);
2081
2082 switch(bc->chip_class) {
2083 case R600:
2084 r = r600_bytecode_alu_build(bc, alu, addr);
2085 break;
2086 case R700:
2087 r = r700_bytecode_alu_build(bc, alu, addr);
2088 break;
2089 default:
2090 R600_ERR("unknown chip class %d.\n", bc->chip_class);
2091 return -EINVAL;
2092 }
2093 if (r)
2094 return r;
2095 addr += 2;
2096 if (alu->last) {
2097 for (i = 0; i < align(nliteral, 2); ++i) {
2098 bc->bytecode[addr++] = literal[i];
2099 }
2100 nliteral = 0;
2101 memset(literal, 0, sizeof(literal));
2102 }
2103 }
2104 break;
2105 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2106 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
2107 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2108 r = r600_bytecode_vtx_build(bc, vtx, addr);
2109 if (r)
2110 return r;
2111 addr += 4;
2112 }
2113 break;
2114 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2115 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2116 r = r600_bytecode_tex_build(bc, tex, addr);
2117 if (r)
2118 return r;
2119 addr += 4;
2120 }
2121 break;
2122 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2123 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2124 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
2125 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
2126 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
2127 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
2128 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
2129 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2130 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2131 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2132 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2133 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2134 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
2135 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2136 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2137 break;
2138 default:
2139 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
2140 return -EINVAL;
2141 }
2142 }
2143 }
2144 return 0;
2145 }
2146
2147 void r600_bytecode_clear(struct r600_bytecode *bc)
2148 {
2149 struct r600_bytecode_cf *cf = NULL, *next_cf;
2150
2151 free(bc->bytecode);
2152 bc->bytecode = NULL;
2153
2154 LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
2155 struct r600_bytecode_alu *alu = NULL, *next_alu;
2156 struct r600_bytecode_tex *tex = NULL, *next_tex;
2157 struct r600_bytecode_tex *vtx = NULL, *next_vtx;
2158
2159 LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
2160 free(alu);
2161 }
2162
2163 LIST_INITHEAD(&cf->alu);
2164
2165 LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) {
2166 free(tex);
2167 }
2168
2169 LIST_INITHEAD(&cf->tex);
2170
2171 LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) {
2172 free(vtx);
2173 }
2174
2175 LIST_INITHEAD(&cf->vtx);
2176
2177 free(cf);
2178 }
2179
2180 LIST_INITHEAD(&cf->list);
2181 }
2182
2183 void r600_bytecode_dump(struct r600_bytecode *bc)
2184 {
2185 struct r600_bytecode_cf *cf = NULL;
2186 struct r600_bytecode_alu *alu = NULL;
2187 struct r600_bytecode_vtx *vtx = NULL;
2188 struct r600_bytecode_tex *tex = NULL;
2189
2190 unsigned i, id;
2191 uint32_t literal[4];
2192 unsigned nliteral;
2193 char chip = '6';
2194
2195 switch (bc->chip_class) {
2196 case R700:
2197 chip = '7';
2198 break;
2199 case EVERGREEN:
2200 chip = 'E';
2201 break;
2202 case CAYMAN:
2203 chip = 'C';
2204 break;
2205 case R600:
2206 default:
2207 chip = '6';
2208 break;
2209 }
2210 fprintf(stderr, "bytecode %d dw -- %d gprs ---------------------\n", bc->ndw, bc->ngpr);
2211 fprintf(stderr, " %c\n", chip);
2212
2213 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
2214 id = cf->id;
2215
2216 if (bc->chip_class >= EVERGREEN) {
2217 switch (cf->inst) {
2218 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
2219 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
2220 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
2221 case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
2222 if (cf->eg_alu_extended) {
2223 fprintf(stderr, "%04d %08X ALU_EXT0 ", id, bc->bytecode[id]);
2224 fprintf(stderr, "KCACHE_BANK2:%X ", cf->kcache[2].bank);
2225 fprintf(stderr, "KCACHE_BANK3:%X ", cf->kcache[3].bank);
2226 fprintf(stderr, "KCACHE_MODE2:%X\n", cf->kcache[2].mode);
2227 id++;
2228 fprintf(stderr, "%04d %08X ALU_EXT1 ", id, bc->bytecode[id]);
2229 fprintf(stderr, "KCACHE_MODE3:%X ", cf->kcache[3].mode);
2230 fprintf(stderr, "KCACHE_ADDR2:%X ", cf->kcache[2].addr);
2231 fprintf(stderr, "KCACHE_ADDR3:%X\n", cf->kcache[3].addr);
2232 id++;
2233 }
2234
2235 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2236 fprintf(stderr, "ADDR:%d ", cf->addr);
2237 fprintf(stderr, "KCACHE_MODE0:%X ", cf->kcache[0].mode);
2238 fprintf(stderr, "KCACHE_BANK0:%X ", cf->kcache[0].bank);
2239 fprintf(stderr, "KCACHE_BANK1:%X\n", cf->kcache[1].bank);
2240 id++;
2241 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2242 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_ALU_WORD1_CF_INST(cf->inst));
2243 fprintf(stderr, "KCACHE_MODE1:%X ", cf->kcache[1].mode);
2244 fprintf(stderr, "KCACHE_ADDR0:%X ", cf->kcache[0].addr);
2245 fprintf(stderr, "KCACHE_ADDR1:%X ", cf->kcache[1].addr);
2246 fprintf(stderr, "COUNT:%d\n", cf->ndw / 2);
2247 break;
2248 case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2249 case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2250 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2251 fprintf(stderr, "ADDR:%d\n", cf->addr);
2252 id++;
2253 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2254 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_WORD1_CF_INST(cf->inst));
2255 fprintf(stderr, "COUNT:%d\n", cf->ndw / 4);
2256 break;
2257 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2258 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2259 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2260 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2261 fprintf(stderr, "ELEM_SIZE:%X ", cf->output.elem_size);
2262 fprintf(stderr, "ARRAY_BASE:%X ", cf->output.array_base);
2263 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2264 id++;
2265 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2266 fprintf(stderr, "SWIZ_X:%X ", cf->output.swizzle_x);
2267 fprintf(stderr, "SWIZ_Y:%X ", cf->output.swizzle_y);
2268 fprintf(stderr, "SWIZ_Z:%X ", cf->output.swizzle_z);
2269 fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
2270 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2271 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst));
2272 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2273 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2274 break;
2275 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0:
2276 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1:
2277 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2:
2278 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3:
2279 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0:
2280 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1:
2281 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2:
2282 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3:
2283 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0:
2284 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1:
2285 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2:
2286 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3:
2287 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0:
2288 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1:
2289 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2:
2290 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3:
2291 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i_BUF%i ", id, bc->bytecode[id],
2292 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2293 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) / 4,
2294 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2295 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) % 4);
2296 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2297 fprintf(stderr, "ELEM_SIZE:%i ", cf->output.elem_size);
2298 fprintf(stderr, "ARRAY_BASE:%i ", cf->output.array_base);
2299 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2300 id++;
2301 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i_BUF%i ", id, bc->bytecode[id],
2302 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2303 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) / 4,
2304 (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2305 EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) % 4);
2306 fprintf(stderr, "ARRAY_SIZE:%i ", cf->output.array_size);
2307 fprintf(stderr, "COMP_MASK:%X ", cf->output.comp_mask);
2308 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2309 fprintf(stderr, "INST:%d ", cf->output.inst);
2310 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2311 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2312 break;
2313 case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2314 case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2315 case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
2316 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
2317 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2318 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2319 case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2320 case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2321 case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2322 case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
2323 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2324 fprintf(stderr, "ADDR:%d\n", cf->cf_addr);
2325 id++;
2326 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2327 fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_WORD1_CF_INST(cf->inst));
2328 fprintf(stderr, "COND:%X ", cf->cond);
2329 fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
2330 break;
2331 default:
2332 R600_ERR("Unknown instruction %0x\n", cf->inst);
2333 }
2334 } else {
2335 switch (cf->inst) {
2336 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
2337 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
2338 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
2339 case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
2340 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2341 fprintf(stderr, "ADDR:%d ", cf->addr);
2342 fprintf(stderr, "KCACHE_MODE0:%X ", cf->kcache[0].mode);
2343 fprintf(stderr, "KCACHE_BANK0:%X ", cf->kcache[0].bank);
2344 fprintf(stderr, "KCACHE_BANK1:%X\n", cf->kcache[1].bank);
2345 id++;
2346 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
2347 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_ALU_WORD1_CF_INST(cf->inst));
2348 fprintf(stderr, "KCACHE_MODE1:%X ", cf->kcache[1].mode);
2349 fprintf(stderr, "KCACHE_ADDR0:%X ", cf->kcache[0].addr);
2350 fprintf(stderr, "KCACHE_ADDR1:%X ", cf->kcache[1].addr);
2351 fprintf(stderr, "COUNT:%d\n", cf->ndw / 2);
2352 break;
2353 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
2354 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
2355 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
2356 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2357 fprintf(stderr, "ADDR:%d\n", cf->addr);
2358 id++;
2359 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
2360 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_WORD1_CF_INST(cf->inst));
2361 fprintf(stderr, "COUNT:%d\n", cf->ndw / 4);
2362 break;
2363 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
2364 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
2365 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2366 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2367 fprintf(stderr, "ELEM_SIZE:%X ", cf->output.elem_size);
2368 fprintf(stderr, "ARRAY_BASE:%X ", cf->output.array_base);
2369 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2370 id++;
2371 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
2372 fprintf(stderr, "SWIZ_X:%X ", cf->output.swizzle_x);
2373 fprintf(stderr, "SWIZ_Y:%X ", cf->output.swizzle_y);
2374 fprintf(stderr, "SWIZ_Z:%X ", cf->output.swizzle_z);
2375 fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
2376 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2377 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst));
2378 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2379 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2380 break;
2381 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
2382 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
2383 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
2384 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
2385 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i ", id, bc->bytecode[id],
2386 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2387 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0));
2388 fprintf(stderr, "GPR:%X ", cf->output.gpr);
2389 fprintf(stderr, "ELEM_SIZE:%i ", cf->output.elem_size);
2390 fprintf(stderr, "ARRAY_BASE:%i ", cf->output.array_base);
2391 fprintf(stderr, "TYPE:%X\n", cf->output.type);
2392 id++;
2393 fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i ", id, bc->bytecode[id],
2394 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
2395 R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0));
2396 fprintf(stderr, "ARRAY_SIZE:%i ", cf->output.array_size);
2397 fprintf(stderr, "COMP_MASK:%X ", cf->output.comp_mask);
2398 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
2399 fprintf(stderr, "INST:%d ", cf->output.inst);
2400 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
2401 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
2402 break;
2403 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
2404 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
2405 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
2406 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
2407 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
2408 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
2409 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
2410 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
2411 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
2412 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2413 fprintf(stderr, "ADDR:%d\n", cf->cf_addr);
2414 id++;
2415 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
2416 fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_WORD1_CF_INST(cf->inst));
2417 fprintf(stderr, "COND:%X ", cf->cond);
2418 fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
2419 break;
2420 default:
2421 R600_ERR("Unknown instruction %0x\n", cf->inst);
2422 }
2423 }
2424
2425 id = cf->addr;
2426 nliteral = 0;
2427 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
2428 r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
2429
2430 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2431 fprintf(stderr, "SRC0(SEL:%d ", alu->src[0].sel);
2432 fprintf(stderr, "REL:%d ", alu->src[0].rel);
2433 fprintf(stderr, "CHAN:%d ", alu->src[0].chan);
2434 fprintf(stderr, "NEG:%d) ", alu->src[0].neg);
2435 fprintf(stderr, "SRC1(SEL:%d ", alu->src[1].sel);
2436 fprintf(stderr, "REL:%d ", alu->src[1].rel);
2437 fprintf(stderr, "CHAN:%d ", alu->src[1].chan);
2438 fprintf(stderr, "NEG:%d ", alu->src[1].neg);
2439 fprintf(stderr, "IM:%d) ", alu->index_mode);
2440 fprintf(stderr, "LAST:%d)\n", alu->last);
2441 id++;
2442 fprintf(stderr, "%04d %08X %c ", id, bc->bytecode[id], alu->last ? '*' : ' ');
2443 fprintf(stderr, "INST:0x%x ", alu->inst);
2444 fprintf(stderr, "DST(SEL:%d ", alu->dst.sel);
2445 fprintf(stderr, "CHAN:%d ", alu->dst.chan);
2446 fprintf(stderr, "REL:%d ", alu->dst.rel);
2447 fprintf(stderr, "CLAMP:%d) ", alu->dst.clamp);
2448 fprintf(stderr, "BANK_SWIZZLE:%d ", alu->bank_swizzle);
2449 if (alu->is_op3) {
2450 fprintf(stderr, "SRC2(SEL:%d ", alu->src[2].sel);
2451 fprintf(stderr, "REL:%d ", alu->src[2].rel);
2452 fprintf(stderr, "CHAN:%d ", alu->src[2].chan);
2453 fprintf(stderr, "NEG:%d)\n", alu->src[2].neg);
2454 } else {
2455 fprintf(stderr, "SRC0_ABS:%d ", alu->src[0].abs);
2456 fprintf(stderr, "SRC1_ABS:%d ", alu->src[1].abs);
2457 fprintf(stderr, "WRITE_MASK:%d ", alu->dst.write);
2458 fprintf(stderr, "OMOD:%d ", alu->omod);
2459 fprintf(stderr, "EXECUTE_MASK:%d ", alu->predicate);
2460 fprintf(stderr, "UPDATE_PRED:%d\n", alu->predicate);
2461 }
2462
2463 id++;
2464 if (alu->last) {
2465 for (i = 0; i < nliteral; i++, id++) {
2466 float *f = (float*)(bc->bytecode + id);
2467 fprintf(stderr, "%04d %08X\t%f\n", id, bc->bytecode[id], *f);
2468 }
2469 id += nliteral & 1;
2470 nliteral = 0;
2471 }
2472 }
2473
2474 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2475 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2476 fprintf(stderr, "INST:0x%x ", tex->inst);
2477 fprintf(stderr, "RESOURCE_ID:%d ", tex->resource_id);
2478 fprintf(stderr, "SRC(GPR:%d ", tex->src_gpr);
2479 fprintf(stderr, "REL:%d)\n", tex->src_rel);
2480 id++;
2481 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2482 fprintf(stderr, "DST(GPR:%d ", tex->dst_gpr);
2483 fprintf(stderr, "REL:%d ", tex->dst_rel);
2484 fprintf(stderr, "SEL_X:%d ", tex->dst_sel_x);
2485 fprintf(stderr, "SEL_Y:%d ", tex->dst_sel_y);
2486 fprintf(stderr, "SEL_Z:%d ", tex->dst_sel_z);
2487 fprintf(stderr, "SEL_W:%d) ", tex->dst_sel_w);
2488 fprintf(stderr, "LOD_BIAS:%d ", tex->lod_bias);
2489 fprintf(stderr, "COORD_TYPE_X:%d ", tex->coord_type_x);
2490 fprintf(stderr, "COORD_TYPE_Y:%d ", tex->coord_type_y);
2491 fprintf(stderr, "COORD_TYPE_Z:%d ", tex->coord_type_z);
2492 fprintf(stderr, "COORD_TYPE_W:%d\n", tex->coord_type_w);
2493 id++;
2494 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2495 fprintf(stderr, "OFFSET_X:%d ", tex->offset_x);
2496 fprintf(stderr, "OFFSET_Y:%d ", tex->offset_y);
2497 fprintf(stderr, "OFFSET_Z:%d ", tex->offset_z);
2498 fprintf(stderr, "SAMPLER_ID:%d ", tex->sampler_id);
2499 fprintf(stderr, "SRC(SEL_X:%d ", tex->src_sel_x);
2500 fprintf(stderr, "SEL_Y:%d ", tex->src_sel_y);
2501 fprintf(stderr, "SEL_Z:%d ", tex->src_sel_z);
2502 fprintf(stderr, "SEL_W:%d)\n", tex->src_sel_w);
2503 id++;
2504 fprintf(stderr, "%04d %08X \n", id, bc->bytecode[id]);
2505 id++;
2506 }
2507
2508 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2509 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2510 fprintf(stderr, "INST:%d ", vtx->inst);
2511 fprintf(stderr, "FETCH_TYPE:%d ", vtx->fetch_type);
2512 fprintf(stderr, "BUFFER_ID:%d\n", vtx->buffer_id);
2513 id++;
2514 /* This assumes that no semantic fetches exist */
2515 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2516 fprintf(stderr, "SRC(GPR:%d ", vtx->src_gpr);
2517 fprintf(stderr, "SEL_X:%d) ", vtx->src_sel_x);
2518 if (bc->chip_class < CAYMAN)
2519 fprintf(stderr, "MEGA_FETCH_COUNT:%d ", vtx->mega_fetch_count);
2520 else
2521 fprintf(stderr, "SEL_Y:%d) ", 0);
2522 fprintf(stderr, "DST(GPR:%d ", vtx->dst_gpr);
2523 fprintf(stderr, "SEL_X:%d ", vtx->dst_sel_x);
2524 fprintf(stderr, "SEL_Y:%d ", vtx->dst_sel_y);
2525 fprintf(stderr, "SEL_Z:%d ", vtx->dst_sel_z);
2526 fprintf(stderr, "SEL_W:%d) ", vtx->dst_sel_w);
2527 fprintf(stderr, "USE_CONST_FIELDS:%d ", vtx->use_const_fields);
2528 fprintf(stderr, "FORMAT(DATA:%d ", vtx->data_format);
2529 fprintf(stderr, "NUM:%d ", vtx->num_format_all);
2530 fprintf(stderr, "COMP:%d ", vtx->format_comp_all);
2531 fprintf(stderr, "MODE:%d)\n", vtx->srf_mode_all);
2532 id++;
2533 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
2534 fprintf(stderr, "ENDIAN:%d ", vtx->endian);
2535 fprintf(stderr, "OFFSET:%d\n", vtx->offset);
2536 /* TODO */
2537 id++;
2538 fprintf(stderr, "%04d %08X \n", id, bc->bytecode[id]);
2539 id++;
2540 }
2541 }
2542
2543 fprintf(stderr, "--------------------------------------\n");
2544 }
2545
2546 static void r600_vertex_data_type(enum pipe_format pformat,
2547 unsigned *format,
2548 unsigned *num_format, unsigned *format_comp, unsigned *endian)
2549 {
2550 const struct util_format_description *desc;
2551 unsigned i;
2552
2553 *format = 0;
2554 *num_format = 0;
2555 *format_comp = 0;
2556 *endian = ENDIAN_NONE;
2557
2558 desc = util_format_description(pformat);
2559 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
2560 goto out_unknown;
2561 }
2562
2563 /* Find the first non-VOID channel. */
2564 for (i = 0; i < 4; i++) {
2565 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2566 break;
2567 }
2568 }
2569
2570 *endian = r600_endian_swap(desc->channel[i].size);
2571
2572 switch (desc->channel[i].type) {
2573 /* Half-floats, floats, ints */
2574 case UTIL_FORMAT_TYPE_FLOAT:
2575 switch (desc->channel[i].size) {
2576 case 16:
2577 switch (desc->nr_channels) {
2578 case 1:
2579 *format = FMT_16_FLOAT;
2580 break;
2581 case 2:
2582 *format = FMT_16_16_FLOAT;
2583 break;
2584 case 3:
2585 case 4:
2586 *format = FMT_16_16_16_16_FLOAT;
2587 break;
2588 }
2589 break;
2590 case 32:
2591 switch (desc->nr_channels) {
2592 case 1:
2593 *format = FMT_32_FLOAT;
2594 break;
2595 case 2:
2596 *format = FMT_32_32_FLOAT;
2597 break;
2598 case 3:
2599 *format = FMT_32_32_32_FLOAT;
2600 break;
2601 case 4:
2602 *format = FMT_32_32_32_32_FLOAT;
2603 break;
2604 }
2605 break;
2606 default:
2607 goto out_unknown;
2608 }
2609 break;
2610 /* Unsigned ints */
2611 case UTIL_FORMAT_TYPE_UNSIGNED:
2612 /* Signed ints */
2613 case UTIL_FORMAT_TYPE_SIGNED:
2614 switch (desc->channel[i].size) {
2615 case 8:
2616 switch (desc->nr_channels) {
2617 case 1:
2618 *format = FMT_8;
2619 break;
2620 case 2:
2621 *format = FMT_8_8;
2622 break;
2623 case 3:
2624 case 4:
2625 *format = FMT_8_8_8_8;
2626 break;
2627 }
2628 break;
2629 case 10:
2630 if (desc->nr_channels != 4)
2631 goto out_unknown;
2632
2633 *format = FMT_2_10_10_10;
2634 break;
2635 case 16:
2636 switch (desc->nr_channels) {
2637 case 1:
2638 *format = FMT_16;
2639 break;
2640 case 2:
2641 *format = FMT_16_16;
2642 break;
2643 case 3:
2644 case 4:
2645 *format = FMT_16_16_16_16;
2646 break;
2647 }
2648 break;
2649 case 32:
2650 switch (desc->nr_channels) {
2651 case 1:
2652 *format = FMT_32;
2653 break;
2654 case 2:
2655 *format = FMT_32_32;
2656 break;
2657 case 3:
2658 *format = FMT_32_32_32;
2659 break;
2660 case 4:
2661 *format = FMT_32_32_32_32;
2662 break;
2663 }
2664 break;
2665 default:
2666 goto out_unknown;
2667 }
2668 break;
2669 default:
2670 goto out_unknown;
2671 }
2672
2673 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2674 *format_comp = 1;
2675 }
2676
2677 *num_format = 0;
2678 if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED ||
2679 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2680 if (!desc->channel[i].normalized) {
2681 if (desc->channel[i].pure_integer)
2682 *num_format = 1;
2683 else
2684 *num_format = 2;
2685 }
2686 }
2687 return;
2688 out_unknown:
2689 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
2690 }
2691
2692 int r600_vertex_elements_build_fetch_shader(struct r600_pipe_context *rctx, struct r600_vertex_element *ve)
2693 {
2694 static int dump_shaders = -1;
2695
2696 struct r600_bytecode bc;
2697 struct r600_bytecode_vtx vtx;
2698 struct pipe_vertex_element *elements = ve->elements;
2699 const struct util_format_description *desc;
2700 unsigned fetch_resource_start = rctx->chip_class >= EVERGREEN ? 0 : 160;
2701 unsigned format, num_format, format_comp, endian;
2702 u32 *bytecode;
2703 int i, r;
2704
2705 /* Vertex element offsets need special handling. If the offset is
2706 * bigger than what we can put in the fetch instruction we need to
2707 * alter the vertex resource offset. In order to simplify code we
2708 * will bind one resource per element in such cases. It's a worst
2709 * case scenario. */
2710 for (i = 0; i < ve->count; i++) {
2711 ve->vbuffer_offset[i] = C_SQ_VTX_WORD2_OFFSET & elements[i].src_offset;
2712 if (ve->vbuffer_offset[i]) {
2713 ve->vbuffer_need_offset = 1;
2714 }
2715 }
2716
2717 memset(&bc, 0, sizeof(bc));
2718 r600_bytecode_init(&bc, rctx->chip_class, rctx->family);
2719
2720 for (i = 0; i < ve->count; i++) {
2721 if (elements[i].instance_divisor > 1) {
2722 struct r600_bytecode_alu alu;
2723
2724 memset(&alu, 0, sizeof(alu));
2725 alu.inst = BC_INST(&bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
2726 alu.src[0].sel = 0;
2727 alu.src[0].chan = 3;
2728
2729 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2730 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2731
2732 alu.dst.sel = i + 1;
2733 alu.dst.chan = 3;
2734 alu.dst.write = 1;
2735 alu.last = 1;
2736
2737 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2738 r600_bytecode_clear(&bc);
2739 return r;
2740 }
2741 }
2742 }
2743
2744 for (i = 0; i < ve->count; i++) {
2745 unsigned vbuffer_index;
2746 r600_vertex_data_type(ve->elements[i].src_format,
2747 &format, &num_format, &format_comp, &endian);
2748 desc = util_format_description(ve->elements[i].src_format);
2749 if (desc == NULL) {
2750 r600_bytecode_clear(&bc);
2751 R600_ERR("unknown format %d\n", ve->elements[i].src_format);
2752 return -EINVAL;
2753 }
2754
2755 /* see above for vbuffer_need_offset explanation */
2756 vbuffer_index = elements[i].vertex_buffer_index;
2757 memset(&vtx, 0, sizeof(vtx));
2758 vtx.buffer_id = (ve->vbuffer_need_offset ? i : vbuffer_index) + fetch_resource_start;
2759 vtx.fetch_type = elements[i].instance_divisor ? 1 : 0;
2760 vtx.src_gpr = elements[i].instance_divisor > 1 ? i + 1 : 0;
2761 vtx.src_sel_x = elements[i].instance_divisor ? 3 : 0;
2762 vtx.mega_fetch_count = 0x1F;
2763 vtx.dst_gpr = i + 1;
2764 vtx.dst_sel_x = desc->swizzle[0];
2765 vtx.dst_sel_y = desc->swizzle[1];
2766 vtx.dst_sel_z = desc->swizzle[2];
2767 vtx.dst_sel_w = desc->swizzle[3];
2768 vtx.data_format = format;
2769 vtx.num_format_all = num_format;
2770 vtx.format_comp_all = format_comp;
2771 vtx.srf_mode_all = 1;
2772 vtx.offset = elements[i].src_offset;
2773 vtx.endian = endian;
2774
2775 if ((r = r600_bytecode_add_vtx(&bc, &vtx))) {
2776 r600_bytecode_clear(&bc);
2777 return r;
2778 }
2779 }
2780
2781 r600_bytecode_add_cfinst(&bc, BC_INST(&bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN));
2782
2783 if ((r = r600_bytecode_build(&bc))) {
2784 r600_bytecode_clear(&bc);
2785 return r;
2786 }
2787
2788 if (dump_shaders == -1)
2789 dump_shaders = debug_get_bool_option("R600_DUMP_SHADERS", FALSE);
2790
2791 if (dump_shaders) {
2792 fprintf(stderr, "--------------------------------------------------------------\n");
2793 r600_bytecode_dump(&bc);
2794 fprintf(stderr, "______________________________________________________________\n");
2795 }
2796
2797 ve->fs_size = bc.ndw*4;
2798
2799 ve->fetch_shader = (struct r600_resource*)
2800 pipe_buffer_create(rctx->context.screen,
2801 PIPE_BIND_CUSTOM,
2802 PIPE_USAGE_IMMUTABLE, ve->fs_size);
2803 if (ve->fetch_shader == NULL) {
2804 r600_bytecode_clear(&bc);
2805 return -ENOMEM;
2806 }
2807
2808 bytecode = rctx->ws->buffer_map(ve->fetch_shader->buf, rctx->ctx.cs, PIPE_TRANSFER_WRITE);
2809 if (bytecode == NULL) {
2810 r600_bytecode_clear(&bc);
2811 pipe_resource_reference((struct pipe_resource**)&ve->fetch_shader, NULL);
2812 return -ENOMEM;
2813 }
2814
2815 if (R600_BIG_ENDIAN) {
2816 for (i = 0; i < ve->fs_size / 4; ++i) {
2817 bytecode[i] = bswap_32(bc.bytecode[i]);
2818 }
2819 } else {
2820 memcpy(bytecode, bc.bytecode, ve->fs_size);
2821 }
2822
2823 rctx->ws->buffer_unmap(ve->fetch_shader->buf);
2824 r600_bytecode_clear(&bc);
2825
2826 if (rctx->chip_class >= EVERGREEN)
2827 evergreen_fetch_shader(&rctx->context, ve);
2828 else
2829 r600_fetch_shader(&rctx->context, ve);
2830
2831 return 0;
2832 }