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r600g: Cleanup the big endian support a bit.
[mesa.git] / src / gallium / drivers / r600 / r600_asm.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include <stdio.h>
24 #include <errno.h>
25 #include <byteswap.h>
26 #include "util/u_format.h"
27 #include "util/u_memory.h"
28 #include "pipe/p_shader_tokens.h"
29 #include "r600_pipe.h"
30 #include "r600_sq.h"
31 #include "r600_opcodes.h"
32 #include "r600_asm.h"
33 #include "r600_formats.h"
34 #include "r600d.h"
35
36 #define NUM_OF_CYCLES 3
37 #define NUM_OF_COMPONENTS 4
38
39 static inline unsigned int r600_bc_get_num_operands(struct r600_bc *bc, struct r600_bc_alu *alu)
40 {
41 if(alu->is_op3)
42 return 3;
43
44 switch (bc->chiprev) {
45 case CHIPREV_R600:
46 case CHIPREV_R700:
47 switch (alu->inst) {
48 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
49 return 0;
50 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
51 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT:
52 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
53 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
54 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
55 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
56 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
57 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT:
58 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
59 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
60 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
61 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
62 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
63 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
64 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
65 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
66 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
67 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
68 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
69 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
70 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
71 return 2;
72
73 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
74 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA:
75 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR:
76 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
77 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
78 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
79 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
80 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
81 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
82 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
83 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
84 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
85 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
86 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
87 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
88 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT:
89 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
90 case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
91 return 1;
92 default: R600_ERR(
93 "Need instruction operand number for 0x%x.\n", alu->inst);
94 }
95 break;
96 case CHIPREV_EVERGREEN:
97 switch (alu->inst) {
98 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
99 return 0;
100 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
101 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT:
102 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
103 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
104 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
105 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
106 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
107 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT:
108 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
109 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
110 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
111 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
112 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
113 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
114 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
115 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
116 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
117 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
118 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
119 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
120 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
121 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY:
122 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW:
123 return 2;
124
125 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
126 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
127 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
128 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
129 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
130 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
131 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED:
132 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
133 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
134 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
135 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
136 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
137 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
138 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR:
139 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT:
140 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
141 case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
142 return 1;
143 default: R600_ERR(
144 "Need instruction operand number for 0x%x.\n", alu->inst);
145 }
146 break;
147 }
148
149 return 3;
150 }
151
152 int r700_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id);
153
154 static struct r600_bc_cf *r600_bc_cf(void)
155 {
156 struct r600_bc_cf *cf = CALLOC_STRUCT(r600_bc_cf);
157
158 if (cf == NULL)
159 return NULL;
160 LIST_INITHEAD(&cf->list);
161 LIST_INITHEAD(&cf->alu);
162 LIST_INITHEAD(&cf->vtx);
163 LIST_INITHEAD(&cf->tex);
164 return cf;
165 }
166
167 static struct r600_bc_alu *r600_bc_alu(void)
168 {
169 struct r600_bc_alu *alu = CALLOC_STRUCT(r600_bc_alu);
170
171 if (alu == NULL)
172 return NULL;
173 LIST_INITHEAD(&alu->list);
174 return alu;
175 }
176
177 static struct r600_bc_vtx *r600_bc_vtx(void)
178 {
179 struct r600_bc_vtx *vtx = CALLOC_STRUCT(r600_bc_vtx);
180
181 if (vtx == NULL)
182 return NULL;
183 LIST_INITHEAD(&vtx->list);
184 return vtx;
185 }
186
187 static struct r600_bc_tex *r600_bc_tex(void)
188 {
189 struct r600_bc_tex *tex = CALLOC_STRUCT(r600_bc_tex);
190
191 if (tex == NULL)
192 return NULL;
193 LIST_INITHEAD(&tex->list);
194 return tex;
195 }
196
197 int r600_bc_init(struct r600_bc *bc, enum radeon_family family)
198 {
199 LIST_INITHEAD(&bc->cf);
200 bc->family = family;
201 switch (bc->family) {
202 case CHIP_R600:
203 case CHIP_RV610:
204 case CHIP_RV630:
205 case CHIP_RV670:
206 case CHIP_RV620:
207 case CHIP_RV635:
208 case CHIP_RS780:
209 case CHIP_RS880:
210 bc->chiprev = CHIPREV_R600;
211 break;
212 case CHIP_RV770:
213 case CHIP_RV730:
214 case CHIP_RV710:
215 case CHIP_RV740:
216 bc->chiprev = CHIPREV_R700;
217 break;
218 case CHIP_CEDAR:
219 case CHIP_REDWOOD:
220 case CHIP_JUNIPER:
221 case CHIP_CYPRESS:
222 case CHIP_HEMLOCK:
223 case CHIP_PALM:
224 case CHIP_BARTS:
225 case CHIP_TURKS:
226 case CHIP_CAICOS:
227 bc->chiprev = CHIPREV_EVERGREEN;
228 break;
229 default:
230 R600_ERR("unknown family %d\n", bc->family);
231 return -EINVAL;
232 }
233 return 0;
234 }
235
236 static int r600_bc_add_cf(struct r600_bc *bc)
237 {
238 struct r600_bc_cf *cf = r600_bc_cf();
239
240 if (cf == NULL)
241 return -ENOMEM;
242 LIST_ADDTAIL(&cf->list, &bc->cf);
243 if (bc->cf_last)
244 cf->id = bc->cf_last->id + 2;
245 bc->cf_last = cf;
246 bc->ncf++;
247 bc->ndw += 2;
248 bc->force_add_cf = 0;
249 return 0;
250 }
251
252 int r600_bc_add_output(struct r600_bc *bc, const struct r600_bc_output *output)
253 {
254 int r;
255
256 if (bc->cf_last && (bc->cf_last->inst == output->inst ||
257 (bc->cf_last->inst == BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT) &&
258 output->inst == BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE))) &&
259 output->type == bc->cf_last->output.type &&
260 output->elem_size == bc->cf_last->output.elem_size &&
261 output->swizzle_x == bc->cf_last->output.swizzle_x &&
262 output->swizzle_y == bc->cf_last->output.swizzle_y &&
263 output->swizzle_z == bc->cf_last->output.swizzle_z &&
264 output->swizzle_w == bc->cf_last->output.swizzle_w &&
265 (output->burst_count + bc->cf_last->output.burst_count) <= 16) {
266
267 if ((output->gpr + output->burst_count) == bc->cf_last->output.gpr &&
268 (output->array_base + output->burst_count) == bc->cf_last->output.array_base) {
269
270 bc->cf_last->output.end_of_program |= output->end_of_program;
271 bc->cf_last->output.inst = output->inst;
272 bc->cf_last->output.gpr = output->gpr;
273 bc->cf_last->output.array_base = output->array_base;
274 bc->cf_last->output.burst_count += output->burst_count;
275 return 0;
276
277 } else if (output->gpr == (bc->cf_last->output.gpr + bc->cf_last->output.burst_count) &&
278 output->array_base == (bc->cf_last->output.array_base + bc->cf_last->output.burst_count)) {
279
280 bc->cf_last->output.end_of_program |= output->end_of_program;
281 bc->cf_last->output.inst = output->inst;
282 bc->cf_last->output.burst_count += output->burst_count;
283 return 0;
284 }
285 }
286
287 r = r600_bc_add_cf(bc);
288 if (r)
289 return r;
290 bc->cf_last->inst = output->inst;
291 memcpy(&bc->cf_last->output, output, sizeof(struct r600_bc_output));
292 return 0;
293 }
294
295 /* alu instructions that can ony exits once per group */
296 static int is_alu_once_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
297 {
298 switch (bc->chiprev) {
299 case CHIPREV_R600:
300 case CHIPREV_R700:
301 return !alu->is_op3 && (
302 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
303 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
304 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
305 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
306 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
307 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
308 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
309 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
310 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
311 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
312 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
313 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
314 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
315 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
316 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
317 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
318 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
319 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
320 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
321 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
322 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
323 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
324 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
325 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
326 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
327 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
328 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
329 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
330 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
331 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
332 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
333 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
334 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
335 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
336 case CHIPREV_EVERGREEN:
337 default:
338 return !alu->is_op3 && (
339 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
340 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
341 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE ||
342 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE ||
343 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT ||
344 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT ||
345 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT ||
346 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT ||
347 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT ||
348 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT ||
349 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT ||
350 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT ||
351 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE ||
352 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT ||
353 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE ||
354 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE ||
355 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV ||
356 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP ||
357 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR ||
358 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE ||
359 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH ||
360 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH ||
361 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH ||
362 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH ||
363 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT ||
364 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT ||
365 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT ||
366 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT ||
367 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT ||
368 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT ||
369 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT ||
370 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
371 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
372 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
373 }
374 }
375
376 static int is_alu_reduction_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
377 {
378 switch (bc->chiprev) {
379 case CHIPREV_R600:
380 case CHIPREV_R700:
381 return !alu->is_op3 && (
382 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
383 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
384 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
385 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
386 case CHIPREV_EVERGREEN:
387 default:
388 return !alu->is_op3 && (
389 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
390 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
391 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
392 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
393 }
394 }
395
396 static int is_alu_cube_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
397 {
398 switch (bc->chiprev) {
399 case CHIPREV_R600:
400 case CHIPREV_R700:
401 return !alu->is_op3 &&
402 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
403 case CHIPREV_EVERGREEN:
404 default:
405 return !alu->is_op3 &&
406 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
407 }
408 }
409
410 static int is_alu_mova_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
411 {
412 switch (bc->chiprev) {
413 case CHIPREV_R600:
414 case CHIPREV_R700:
415 return !alu->is_op3 && (
416 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA ||
417 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR ||
418 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
419 case CHIPREV_EVERGREEN:
420 default:
421 return !alu->is_op3 && (
422 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
423 }
424 }
425
426 /* alu instructions that can only execute on the vector unit */
427 static int is_alu_vec_unit_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
428 {
429 return is_alu_reduction_inst(bc, alu) ||
430 is_alu_mova_inst(bc, alu) ||
431 (bc->chiprev == CHIPREV_EVERGREEN &&
432 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR);
433 }
434
435 /* alu instructions that can only execute on the trans unit */
436 static int is_alu_trans_unit_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
437 {
438 switch (bc->chiprev) {
439 case CHIPREV_R600:
440 case CHIPREV_R700:
441 if (!alu->is_op3)
442 return alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT ||
443 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT ||
444 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT ||
445 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT ||
446 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT ||
447 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT ||
448 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT ||
449 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT ||
450 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT ||
451 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT ||
452 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT ||
453 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT ||
454 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS ||
455 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE ||
456 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED ||
457 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE ||
458 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED ||
459 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_FF ||
460 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE ||
461 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED ||
462 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF ||
463 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE ||
464 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN ||
465 alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_IEEE;
466 else
467 return alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT ||
468 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_D2 ||
469 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M2 ||
470 alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M4;
471 case CHIPREV_EVERGREEN:
472 default:
473 if (!alu->is_op3)
474 /* Note that FLT_TO_INT_* instructions are vector-only instructions
475 * on Evergreen, despite what the documentation says. FLT_TO_INT
476 * can do both vector and scalar. */
477 return alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT ||
478 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT ||
479 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT ||
480 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT ||
481 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT ||
482 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT ||
483 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT ||
484 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT ||
485 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT ||
486 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT ||
487 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT ||
488 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS ||
489 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE ||
490 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED ||
491 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE ||
492 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED ||
493 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_FF ||
494 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE ||
495 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED ||
496 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF ||
497 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE ||
498 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN ||
499 alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_IEEE;
500 else
501 return alu->inst == EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
502 }
503 }
504
505 /* alu instructions that can execute on any unit */
506 static int is_alu_any_unit_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
507 {
508 return !is_alu_vec_unit_inst(bc, alu) &&
509 !is_alu_trans_unit_inst(bc, alu);
510 }
511
512 static int assign_alu_units(struct r600_bc *bc, struct r600_bc_alu *alu_first,
513 struct r600_bc_alu *assignment[5])
514 {
515 struct r600_bc_alu *alu;
516 unsigned i, chan, trans;
517
518 for (i = 0; i < 5; i++)
519 assignment[i] = NULL;
520
521 for (alu = alu_first; alu; alu = LIST_ENTRY(struct r600_bc_alu, alu->list.next, list)) {
522 chan = alu->dst.chan;
523 if (is_alu_trans_unit_inst(bc, alu))
524 trans = 1;
525 else if (is_alu_vec_unit_inst(bc, alu))
526 trans = 0;
527 else if (assignment[chan])
528 trans = 1; // assume ALU_INST_PREFER_VECTOR
529 else
530 trans = 0;
531
532 if (trans) {
533 if (assignment[4]) {
534 assert(0); //ALU.Trans has already been allocated
535 return -1;
536 }
537 assignment[4] = alu;
538 } else {
539 if (assignment[chan]) {
540 assert(0); //ALU.chan has already been allocated
541 return -1;
542 }
543 assignment[chan] = alu;
544 }
545
546 if (alu->last)
547 break;
548 }
549 return 0;
550 }
551
552 struct alu_bank_swizzle {
553 int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
554 int hw_cfile_addr[4];
555 int hw_cfile_elem[4];
556 };
557
558 static const unsigned cycle_for_bank_swizzle_vec[][3] = {
559 [SQ_ALU_VEC_012] = { 0, 1, 2 },
560 [SQ_ALU_VEC_021] = { 0, 2, 1 },
561 [SQ_ALU_VEC_120] = { 1, 2, 0 },
562 [SQ_ALU_VEC_102] = { 1, 0, 2 },
563 [SQ_ALU_VEC_201] = { 2, 0, 1 },
564 [SQ_ALU_VEC_210] = { 2, 1, 0 }
565 };
566
567 static const unsigned cycle_for_bank_swizzle_scl[][3] = {
568 [SQ_ALU_SCL_210] = { 2, 1, 0 },
569 [SQ_ALU_SCL_122] = { 1, 2, 2 },
570 [SQ_ALU_SCL_212] = { 2, 1, 2 },
571 [SQ_ALU_SCL_221] = { 2, 2, 1 }
572 };
573
574 static void init_bank_swizzle(struct alu_bank_swizzle *bs)
575 {
576 int i, cycle, component;
577 /* set up gpr use */
578 for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
579 for (component = 0; component < NUM_OF_COMPONENTS; component++)
580 bs->hw_gpr[cycle][component] = -1;
581 for (i = 0; i < 4; i++)
582 bs->hw_cfile_addr[i] = -1;
583 for (i = 0; i < 4; i++)
584 bs->hw_cfile_elem[i] = -1;
585 }
586
587 static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan, unsigned cycle)
588 {
589 if (bs->hw_gpr[cycle][chan] == -1)
590 bs->hw_gpr[cycle][chan] = sel;
591 else if (bs->hw_gpr[cycle][chan] != (int)sel) {
592 // Another scalar operation has already used GPR read port for channel
593 return -1;
594 }
595 return 0;
596 }
597
598 static int reserve_cfile(struct r600_bc *bc, struct alu_bank_swizzle *bs, unsigned sel, unsigned chan)
599 {
600 int res, num_res = 4;
601 if (bc->chiprev >= CHIPREV_R700) {
602 num_res = 2;
603 chan /= 2;
604 }
605 for (res = 0; res < num_res; ++res) {
606 if (bs->hw_cfile_addr[res] == -1) {
607 bs->hw_cfile_addr[res] = sel;
608 bs->hw_cfile_elem[res] = chan;
609 return 0;
610 } else if (bs->hw_cfile_addr[res] == sel &&
611 bs->hw_cfile_elem[res] == chan)
612 return 0; // Read for this scalar element already reserved, nothing to do here.
613 }
614 // All cfile read ports are used, cannot reference vector element
615 return -1;
616 }
617
618 static int is_gpr(unsigned sel)
619 {
620 return (sel >= 0 && sel <= 127);
621 }
622
623 /* CB constants start at 512, and get translated to a kcache index when ALU
624 * clauses are constructed. Note that we handle kcache constants the same way
625 * as (the now gone) cfile constants, is that really required? */
626 static int is_cfile(unsigned sel)
627 {
628 return (sel > 255 && sel < 512) ||
629 (sel > 511 && sel < 4607) || // Kcache before translate
630 (sel > 127 && sel < 192); // Kcache after translate
631 }
632
633 static int is_const(int sel)
634 {
635 return is_cfile(sel) ||
636 (sel >= V_SQ_ALU_SRC_0 &&
637 sel <= V_SQ_ALU_SRC_LITERAL);
638 }
639
640 static int check_vector(struct r600_bc *bc, struct r600_bc_alu *alu,
641 struct alu_bank_swizzle *bs, int bank_swizzle)
642 {
643 int r, src, num_src, sel, elem, cycle;
644
645 num_src = r600_bc_get_num_operands(bc, alu);
646 for (src = 0; src < num_src; src++) {
647 sel = alu->src[src].sel;
648 elem = alu->src[src].chan;
649 if (is_gpr(sel)) {
650 cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src];
651 if (src == 1 && sel == alu->src[0].sel && elem == alu->src[0].chan)
652 // Nothing to do; special-case optimization,
653 // second source uses first source’s reservation
654 continue;
655 else {
656 r = reserve_gpr(bs, sel, elem, cycle);
657 if (r)
658 return r;
659 }
660 } else if (is_cfile(sel)) {
661 r = reserve_cfile(bc, bs, sel, elem);
662 if (r)
663 return r;
664 }
665 // No restrictions on PV, PS, literal or special constants
666 }
667 return 0;
668 }
669
670 static int check_scalar(struct r600_bc *bc, struct r600_bc_alu *alu,
671 struct alu_bank_swizzle *bs, int bank_swizzle)
672 {
673 int r, src, num_src, const_count, sel, elem, cycle;
674
675 num_src = r600_bc_get_num_operands(bc, alu);
676 for (const_count = 0, src = 0; src < num_src; ++src) {
677 sel = alu->src[src].sel;
678 elem = alu->src[src].chan;
679 if (is_const(sel)) { // Any constant, including literal and inline constants
680 if (const_count >= 2)
681 // More than two references to a constant in
682 // transcendental operation.
683 return -1;
684 else
685 const_count++;
686 }
687 if (is_cfile(sel)) {
688 r = reserve_cfile(bc, bs, sel, elem);
689 if (r)
690 return r;
691 }
692 }
693 for (src = 0; src < num_src; ++src) {
694 sel = alu->src[src].sel;
695 elem = alu->src[src].chan;
696 if (is_gpr(sel)) {
697 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
698 if (cycle < const_count)
699 // Cycle for GPR load conflicts with
700 // constant load in transcendental operation.
701 return -1;
702 r = reserve_gpr(bs, sel, elem, cycle);
703 if (r)
704 return r;
705 }
706 // PV PS restrictions
707 if (const_count && (sel == 254 || sel == 255)) {
708 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
709 if (cycle < const_count)
710 return -1;
711 }
712 }
713 return 0;
714 }
715
716 static int check_and_set_bank_swizzle(struct r600_bc *bc,
717 struct r600_bc_alu *slots[5])
718 {
719 struct alu_bank_swizzle bs;
720 int bank_swizzle[5];
721 int i, r = 0, forced = 0;
722 boolean scalar_only = true;
723 for (i = 0; i < 5; i++) {
724 if (slots[i] && slots[i]->bank_swizzle_force) {
725 slots[i]->bank_swizzle = slots[i]->bank_swizzle_force;
726 forced = 1;
727 }
728 if (i < 4 && slots[i])
729 scalar_only = false;
730 }
731 if (forced)
732 return 0;
733
734 // just check every possible combination of bank swizzle
735 // not very efficent, but works on the first try in most of the cases
736 for (i = 0; i < 4; i++)
737 bank_swizzle[i] = SQ_ALU_VEC_012;
738 bank_swizzle[4] = SQ_ALU_SCL_210;
739 while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
740 init_bank_swizzle(&bs);
741 if (scalar_only == false) {
742 for (i = 0; i < 4; i++) {
743 if (slots[i]) {
744 r = check_vector(bc, slots[i], &bs, bank_swizzle[i]);
745 if (r)
746 break;
747 }
748 }
749 } else
750 r = 0;
751
752 if (!r && slots[4]) {
753 r = check_scalar(bc, slots[4], &bs, bank_swizzle[4]);
754 }
755 if (!r) {
756 for (i = 0; i < 5; i++) {
757 if (slots[i])
758 slots[i]->bank_swizzle = bank_swizzle[i];
759 }
760 return 0;
761 }
762
763 if (scalar_only) {
764 bank_swizzle[4]++;
765 } else {
766 for (i = 0; i < 5; i++) {
767 bank_swizzle[i]++;
768 if (bank_swizzle[i] <= SQ_ALU_VEC_210)
769 break;
770 else
771 bank_swizzle[i] = SQ_ALU_VEC_012;
772 }
773 }
774 }
775
776 // couldn't find a working swizzle
777 return -1;
778 }
779
780 static int replace_gpr_with_pv_ps(struct r600_bc *bc,
781 struct r600_bc_alu *slots[5], struct r600_bc_alu *alu_prev)
782 {
783 struct r600_bc_alu *prev[5];
784 int gpr[5], chan[5];
785 int i, j, r, src, num_src;
786
787 r = assign_alu_units(bc, alu_prev, prev);
788 if (r)
789 return r;
790
791 for (i = 0; i < 5; ++i) {
792 if(prev[i] && prev[i]->dst.write && !prev[i]->dst.rel) {
793 gpr[i] = prev[i]->dst.sel;
794 /* cube writes more than PV.X */
795 if (!is_alu_cube_inst(bc, prev[i]) && is_alu_reduction_inst(bc, prev[i]))
796 chan[i] = 0;
797 else
798 chan[i] = prev[i]->dst.chan;
799 } else
800 gpr[i] = -1;
801 }
802
803 for (i = 0; i < 5; ++i) {
804 struct r600_bc_alu *alu = slots[i];
805 if(!alu)
806 continue;
807
808 num_src = r600_bc_get_num_operands(bc, alu);
809 for (src = 0; src < num_src; ++src) {
810 if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
811 continue;
812
813 if (alu->src[src].sel == gpr[4] &&
814 alu->src[src].chan == chan[4]) {
815 alu->src[src].sel = V_SQ_ALU_SRC_PS;
816 alu->src[src].chan = 0;
817 continue;
818 }
819
820 for (j = 0; j < 4; ++j) {
821 if (alu->src[src].sel == gpr[j] &&
822 alu->src[src].chan == j) {
823 alu->src[src].sel = V_SQ_ALU_SRC_PV;
824 alu->src[src].chan = chan[j];
825 break;
826 }
827 }
828 }
829 }
830
831 return 0;
832 }
833
834 void r600_bc_special_constants(u32 value, unsigned *sel, unsigned *neg)
835 {
836 switch(value) {
837 case 0:
838 *sel = V_SQ_ALU_SRC_0;
839 break;
840 case 1:
841 *sel = V_SQ_ALU_SRC_1_INT;
842 break;
843 case -1:
844 *sel = V_SQ_ALU_SRC_M_1_INT;
845 break;
846 case 0x3F800000: // 1.0f
847 *sel = V_SQ_ALU_SRC_1;
848 break;
849 case 0x3F000000: // 0.5f
850 *sel = V_SQ_ALU_SRC_0_5;
851 break;
852 case 0xBF800000: // -1.0f
853 *sel = V_SQ_ALU_SRC_1;
854 *neg ^= 1;
855 break;
856 case 0xBF000000: // -0.5f
857 *sel = V_SQ_ALU_SRC_0_5;
858 *neg ^= 1;
859 break;
860 default:
861 *sel = V_SQ_ALU_SRC_LITERAL;
862 break;
863 }
864 }
865
866 /* compute how many literal are needed */
867 static int r600_bc_alu_nliterals(struct r600_bc *bc, struct r600_bc_alu *alu,
868 uint32_t literal[4], unsigned *nliteral)
869 {
870 unsigned num_src = r600_bc_get_num_operands(bc, alu);
871 unsigned i, j;
872
873 for (i = 0; i < num_src; ++i) {
874 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
875 uint32_t value = alu->src[i].value;
876 unsigned found = 0;
877 for (j = 0; j < *nliteral; ++j) {
878 if (literal[j] == value) {
879 found = 1;
880 break;
881 }
882 }
883 if (!found) {
884 if (*nliteral >= 4)
885 return -EINVAL;
886 literal[(*nliteral)++] = value;
887 }
888 }
889 }
890 return 0;
891 }
892
893 static void r600_bc_alu_adjust_literals(struct r600_bc *bc,
894 struct r600_bc_alu *alu,
895 uint32_t literal[4], unsigned nliteral)
896 {
897 unsigned num_src = r600_bc_get_num_operands(bc, alu);
898 unsigned i, j;
899
900 for (i = 0; i < num_src; ++i) {
901 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
902 uint32_t value = alu->src[i].value;
903 for (j = 0; j < nliteral; ++j) {
904 if (literal[j] == value) {
905 alu->src[i].chan = j;
906 break;
907 }
908 }
909 }
910 }
911 }
912
913 static int merge_inst_groups(struct r600_bc *bc, struct r600_bc_alu *slots[5],
914 struct r600_bc_alu *alu_prev)
915 {
916 struct r600_bc_alu *prev[5];
917 struct r600_bc_alu *result[5] = { NULL };
918
919 uint32_t literal[4], prev_literal[4];
920 unsigned nliteral = 0, prev_nliteral = 0;
921
922 int i, j, r, src, num_src;
923 int num_once_inst = 0;
924 int have_mova = 0, have_rel = 0;
925
926 r = assign_alu_units(bc, alu_prev, prev);
927 if (r)
928 return r;
929
930 for (i = 0; i < 5; ++i) {
931 struct r600_bc_alu *alu;
932
933 /* check number of literals */
934 if (prev[i]) {
935 if (r600_bc_alu_nliterals(bc, prev[i], literal, &nliteral))
936 return 0;
937 if (r600_bc_alu_nliterals(bc, prev[i], prev_literal, &prev_nliteral))
938 return 0;
939 if (is_alu_mova_inst(bc, prev[i])) {
940 if (have_rel)
941 return 0;
942 have_mova = 1;
943 }
944 num_once_inst += is_alu_once_inst(bc, prev[i]);
945 }
946 if (slots[i] && r600_bc_alu_nliterals(bc, slots[i], literal, &nliteral))
947 return 0;
948
949 // let's check used slots
950 if (prev[i] && !slots[i]) {
951 result[i] = prev[i];
952 continue;
953 } else if (prev[i] && slots[i]) {
954 if (result[4] == NULL && prev[4] == NULL && slots[4] == NULL) {
955 // trans unit is still free try to use it
956 if (is_alu_any_unit_inst(bc, slots[i])) {
957 result[i] = prev[i];
958 result[4] = slots[i];
959 } else if (is_alu_any_unit_inst(bc, prev[i])) {
960 result[i] = slots[i];
961 result[4] = prev[i];
962 } else
963 return 0;
964 } else
965 return 0;
966 } else if(!slots[i]) {
967 continue;
968 } else
969 result[i] = slots[i];
970
971 alu = slots[i];
972 num_once_inst += is_alu_once_inst(bc, alu);
973
974 // let's check dst gpr
975 if (alu->dst.rel) {
976 if (have_mova)
977 return 0;
978 have_rel = 1;
979 }
980
981 // let's check source gprs
982 num_src = r600_bc_get_num_operands(bc, alu);
983 for (src = 0; src < num_src; ++src) {
984 if (alu->src[src].rel) {
985 if (have_mova)
986 return 0;
987 have_rel = 1;
988 }
989
990 // constants doesn't matter
991 if (!is_gpr(alu->src[src].sel))
992 continue;
993
994 for (j = 0; j < 5; ++j) {
995 if (!prev[j] || !prev[j]->dst.write)
996 continue;
997
998 // if it's relative then we can't determin which gpr is really used
999 if (prev[j]->dst.chan == alu->src[src].chan &&
1000 (prev[j]->dst.sel == alu->src[src].sel ||
1001 prev[j]->dst.rel || alu->src[src].rel))
1002 return 0;
1003 }
1004 }
1005 }
1006
1007 /* more than one PRED_ or KILL_ ? */
1008 if (num_once_inst > 1)
1009 return 0;
1010
1011 /* check if the result can still be swizzlet */
1012 r = check_and_set_bank_swizzle(bc, result);
1013 if (r)
1014 return 0;
1015
1016 /* looks like everything worked out right, apply the changes */
1017
1018 /* undo adding previus literals */
1019 bc->cf_last->ndw -= align(prev_nliteral, 2);
1020
1021 /* sort instructions */
1022 for (i = 0; i < 5; ++i) {
1023 slots[i] = result[i];
1024 if (result[i]) {
1025 LIST_DEL(&result[i]->list);
1026 result[i]->last = 0;
1027 LIST_ADDTAIL(&result[i]->list, &bc->cf_last->alu);
1028 }
1029 }
1030
1031 /* determine new last instruction */
1032 LIST_ENTRY(struct r600_bc_alu, bc->cf_last->alu.prev, list)->last = 1;
1033
1034 /* determine new first instruction */
1035 for (i = 0; i < 5; ++i) {
1036 if (result[i]) {
1037 bc->cf_last->curr_bs_head = result[i];
1038 break;
1039 }
1040 }
1041
1042 bc->cf_last->prev_bs_head = bc->cf_last->prev2_bs_head;
1043 bc->cf_last->prev2_bs_head = NULL;
1044
1045 return 0;
1046 }
1047
1048 /* This code handles kcache lines as single blocks of 32 constants. We could
1049 * probably do slightly better by recognizing that we actually have two
1050 * consecutive lines of 16 constants, but the resulting code would also be
1051 * somewhat more complicated. */
1052 static int r600_bc_alloc_kcache_lines(struct r600_bc *bc, struct r600_bc_alu *alu, int type)
1053 {
1054 struct r600_bc_kcache *kcache = bc->cf_last->kcache;
1055 unsigned int required_lines;
1056 unsigned int free_lines = 0;
1057 unsigned int cache_line[3];
1058 unsigned int count = 0;
1059 unsigned int i, j;
1060 int r;
1061
1062 /* Collect required cache lines. */
1063 for (i = 0; i < 3; ++i) {
1064 bool found = false;
1065 unsigned int line;
1066
1067 if (alu->src[i].sel < 512)
1068 continue;
1069
1070 line = ((alu->src[i].sel - 512) / 32) * 2;
1071
1072 for (j = 0; j < count; ++j) {
1073 if (cache_line[j] == line) {
1074 found = true;
1075 break;
1076 }
1077 }
1078
1079 if (!found)
1080 cache_line[count++] = line;
1081 }
1082
1083 /* This should never actually happen. */
1084 if (count >= 3) return -ENOMEM;
1085
1086 for (i = 0; i < 2; ++i) {
1087 if (kcache[i].mode == V_SQ_CF_KCACHE_NOP) {
1088 ++free_lines;
1089 }
1090 }
1091
1092 /* Filter lines pulled in by previous intructions. Note that this is
1093 * only for the required_lines count, we can't remove these from the
1094 * cache_line array since we may have to start a new ALU clause. */
1095 for (i = 0, required_lines = count; i < count; ++i) {
1096 for (j = 0; j < 2; ++j) {
1097 if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
1098 kcache[j].addr == cache_line[i]) {
1099 --required_lines;
1100 break;
1101 }
1102 }
1103 }
1104
1105 /* Start a new ALU clause if needed. */
1106 if (required_lines > free_lines) {
1107 if ((r = r600_bc_add_cf(bc))) {
1108 return r;
1109 }
1110 bc->cf_last->inst = (type << 3);
1111 kcache = bc->cf_last->kcache;
1112 }
1113
1114 /* Setup the kcache lines. */
1115 for (i = 0; i < count; ++i) {
1116 bool found = false;
1117
1118 for (j = 0; j < 2; ++j) {
1119 if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
1120 kcache[j].addr == cache_line[i]) {
1121 found = true;
1122 break;
1123 }
1124 }
1125
1126 if (found) continue;
1127
1128 for (j = 0; j < 2; ++j) {
1129 if (kcache[j].mode == V_SQ_CF_KCACHE_NOP) {
1130 kcache[j].bank = 0;
1131 kcache[j].addr = cache_line[i];
1132 kcache[j].mode = V_SQ_CF_KCACHE_LOCK_2;
1133 break;
1134 }
1135 }
1136 }
1137
1138 /* Alter the src operands to refer to the kcache. */
1139 for (i = 0; i < 3; ++i) {
1140 static const unsigned int base[] = {128, 160, 256, 288};
1141 unsigned int line;
1142
1143 if (alu->src[i].sel < 512)
1144 continue;
1145
1146 alu->src[i].sel -= 512;
1147 line = (alu->src[i].sel / 32) * 2;
1148
1149 for (j = 0; j < 2; ++j) {
1150 if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
1151 kcache[j].addr == line) {
1152 alu->src[i].sel &= 0x1f;
1153 alu->src[i].sel += base[j];
1154 break;
1155 }
1156 }
1157 }
1158
1159 return 0;
1160 }
1161
1162 int r600_bc_add_alu_type(struct r600_bc *bc, const struct r600_bc_alu *alu, int type)
1163 {
1164 struct r600_bc_alu *nalu = r600_bc_alu();
1165 struct r600_bc_alu *lalu;
1166 int i, r;
1167
1168 if (nalu == NULL)
1169 return -ENOMEM;
1170 memcpy(nalu, alu, sizeof(struct r600_bc_alu));
1171
1172 if (bc->cf_last != NULL && bc->cf_last->inst != (type << 3)) {
1173 /* check if we could add it anyway */
1174 if (bc->cf_last->inst == (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3) &&
1175 type == V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE) {
1176 LIST_FOR_EACH_ENTRY(lalu, &bc->cf_last->alu, list) {
1177 if (lalu->predicate) {
1178 bc->force_add_cf = 1;
1179 break;
1180 }
1181 }
1182 } else
1183 bc->force_add_cf = 1;
1184 }
1185
1186 /* cf can contains only alu or only vtx or only tex */
1187 if (bc->cf_last == NULL || bc->force_add_cf) {
1188 r = r600_bc_add_cf(bc);
1189 if (r) {
1190 free(nalu);
1191 return r;
1192 }
1193 }
1194 bc->cf_last->inst = (type << 3);
1195
1196 /* Setup the kcache for this ALU instruction. This will start a new
1197 * ALU clause if needed. */
1198 if ((r = r600_bc_alloc_kcache_lines(bc, nalu, type))) {
1199 free(nalu);
1200 return r;
1201 }
1202
1203 if (!bc->cf_last->curr_bs_head) {
1204 bc->cf_last->curr_bs_head = nalu;
1205 }
1206 /* number of gpr == the last gpr used in any alu */
1207 for (i = 0; i < 3; i++) {
1208 if (nalu->src[i].sel >= bc->ngpr && nalu->src[i].sel < 128) {
1209 bc->ngpr = nalu->src[i].sel + 1;
1210 }
1211 if (nalu->src[i].sel == V_SQ_ALU_SRC_LITERAL)
1212 r600_bc_special_constants(nalu->src[i].value,
1213 &nalu->src[i].sel, &nalu->src[i].neg);
1214 }
1215 if (nalu->dst.sel >= bc->ngpr) {
1216 bc->ngpr = nalu->dst.sel + 1;
1217 }
1218 LIST_ADDTAIL(&nalu->list, &bc->cf_last->alu);
1219 /* each alu use 2 dwords */
1220 bc->cf_last->ndw += 2;
1221 bc->ndw += 2;
1222
1223 /* process cur ALU instructions for bank swizzle */
1224 if (nalu->last) {
1225 uint32_t literal[4];
1226 unsigned nliteral;
1227 struct r600_bc_alu *slots[5];
1228 r = assign_alu_units(bc, bc->cf_last->curr_bs_head, slots);
1229 if (r)
1230 return r;
1231
1232 if (bc->cf_last->prev_bs_head) {
1233 r = merge_inst_groups(bc, slots, bc->cf_last->prev_bs_head);
1234 if (r)
1235 return r;
1236 }
1237
1238 if (bc->cf_last->prev_bs_head) {
1239 r = replace_gpr_with_pv_ps(bc, slots, bc->cf_last->prev_bs_head);
1240 if (r)
1241 return r;
1242 }
1243
1244 r = check_and_set_bank_swizzle(bc, slots);
1245 if (r)
1246 return r;
1247
1248 for (i = 0, nliteral = 0; i < 5; i++) {
1249 if (slots[i]) {
1250 r = r600_bc_alu_nliterals(bc, slots[i], literal, &nliteral);
1251 if (r)
1252 return r;
1253 }
1254 }
1255 bc->cf_last->ndw += align(nliteral, 2);
1256
1257 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1258 * worst case */
1259 if ((bc->cf_last->ndw >> 1) >= 120) {
1260 bc->force_add_cf = 1;
1261 }
1262
1263 bc->cf_last->prev2_bs_head = bc->cf_last->prev_bs_head;
1264 bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head;
1265 bc->cf_last->curr_bs_head = NULL;
1266 }
1267 return 0;
1268 }
1269
1270 int r600_bc_add_alu(struct r600_bc *bc, const struct r600_bc_alu *alu)
1271 {
1272 return r600_bc_add_alu_type(bc, alu, BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
1273 }
1274
1275 static unsigned r600_bc_num_tex_and_vtx_instructions(const struct r600_bc *bc)
1276 {
1277 switch (bc->chiprev) {
1278 case CHIPREV_R600:
1279 return 8;
1280
1281 case CHIPREV_R700:
1282 return 16;
1283
1284 case CHIPREV_EVERGREEN:
1285 return 64;
1286
1287 default:
1288 R600_ERR("Unknown chiprev %d.\n", bc->chiprev);
1289 return 8;
1290 }
1291 }
1292
1293 int r600_bc_add_vtx(struct r600_bc *bc, const struct r600_bc_vtx *vtx)
1294 {
1295 struct r600_bc_vtx *nvtx = r600_bc_vtx();
1296 int r;
1297
1298 if (nvtx == NULL)
1299 return -ENOMEM;
1300 memcpy(nvtx, vtx, sizeof(struct r600_bc_vtx));
1301
1302 /* cf can contains only alu or only vtx or only tex */
1303 if (bc->cf_last == NULL ||
1304 (bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX &&
1305 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC) ||
1306 bc->force_add_cf) {
1307 r = r600_bc_add_cf(bc);
1308 if (r) {
1309 free(nvtx);
1310 return r;
1311 }
1312 bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_VTX;
1313 }
1314 LIST_ADDTAIL(&nvtx->list, &bc->cf_last->vtx);
1315 /* each fetch use 4 dwords */
1316 bc->cf_last->ndw += 4;
1317 bc->ndw += 4;
1318 if ((bc->cf_last->ndw / 4) >= r600_bc_num_tex_and_vtx_instructions(bc))
1319 bc->force_add_cf = 1;
1320 return 0;
1321 }
1322
1323 int r600_bc_add_tex(struct r600_bc *bc, const struct r600_bc_tex *tex)
1324 {
1325 struct r600_bc_tex *ntex = r600_bc_tex();
1326 int r;
1327
1328 if (ntex == NULL)
1329 return -ENOMEM;
1330 memcpy(ntex, tex, sizeof(struct r600_bc_tex));
1331
1332 /* we can't fetch data und use it as texture lookup address in the same TEX clause */
1333 if (bc->cf_last != NULL &&
1334 bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_TEX) {
1335 struct r600_bc_tex *ttex;
1336 LIST_FOR_EACH_ENTRY(ttex, &bc->cf_last->tex, list) {
1337 if (ttex->dst_gpr == ntex->src_gpr) {
1338 bc->force_add_cf = 1;
1339 break;
1340 }
1341 }
1342 }
1343
1344 /* cf can contains only alu or only vtx or only tex */
1345 if (bc->cf_last == NULL ||
1346 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_TEX ||
1347 bc->force_add_cf) {
1348 r = r600_bc_add_cf(bc);
1349 if (r) {
1350 free(ntex);
1351 return r;
1352 }
1353 bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_TEX;
1354 }
1355 if (ntex->src_gpr >= bc->ngpr) {
1356 bc->ngpr = ntex->src_gpr + 1;
1357 }
1358 if (ntex->dst_gpr >= bc->ngpr) {
1359 bc->ngpr = ntex->dst_gpr + 1;
1360 }
1361 LIST_ADDTAIL(&ntex->list, &bc->cf_last->tex);
1362 /* each texture fetch use 4 dwords */
1363 bc->cf_last->ndw += 4;
1364 bc->ndw += 4;
1365 if ((bc->cf_last->ndw / 4) >= r600_bc_num_tex_and_vtx_instructions(bc))
1366 bc->force_add_cf = 1;
1367 return 0;
1368 }
1369
1370 int r600_bc_add_cfinst(struct r600_bc *bc, int inst)
1371 {
1372 int r;
1373 r = r600_bc_add_cf(bc);
1374 if (r)
1375 return r;
1376
1377 bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
1378 bc->cf_last->inst = inst;
1379 return 0;
1380 }
1381
1382 /* common to all 3 families */
1383 static int r600_bc_vtx_build(struct r600_bc *bc, struct r600_bc_vtx *vtx, unsigned id)
1384 {
1385 bc->bytecode[id++] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) |
1386 S_SQ_VTX_WORD0_FETCH_TYPE(vtx->fetch_type) |
1387 S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
1388 S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x) |
1389 S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
1390 bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
1391 S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
1392 S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
1393 S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
1394 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) |
1395 S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) |
1396 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) |
1397 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) |
1398 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
1399 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
1400 bc->bytecode[id++] = S_SQ_VTX_WORD2_OFFSET(vtx->offset) |
1401 S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx->endian) |
1402 S_SQ_VTX_WORD2_MEGA_FETCH(1);
1403 bc->bytecode[id++] = 0;
1404 return 0;
1405 }
1406
1407 /* common to all 3 families */
1408 static int r600_bc_tex_build(struct r600_bc *bc, struct r600_bc_tex *tex, unsigned id)
1409 {
1410 bc->bytecode[id++] = S_SQ_TEX_WORD0_TEX_INST(tex->inst) |
1411 S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
1412 S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
1413 S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
1414 bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
1415 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
1416 S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
1417 S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
1418 S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
1419 S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
1420 S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
1421 S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
1422 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
1423 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
1424 S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
1425 bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
1426 S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
1427 S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
1428 S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
1429 S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
1430 S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
1431 S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
1432 S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
1433 bc->bytecode[id++] = 0;
1434 return 0;
1435 }
1436
1437 /* r600 only, r700/eg bits in r700_asm.c */
1438 static int r600_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id)
1439 {
1440 /* don't replace gpr by pv or ps for destination register */
1441 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
1442 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
1443 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
1444 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
1445 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
1446 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
1447 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
1448 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
1449 S_SQ_ALU_WORD0_LAST(alu->last);
1450
1451 if (alu->is_op3) {
1452 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1453 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1454 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1455 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1456 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
1457 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
1458 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
1459 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
1460 S_SQ_ALU_WORD1_OP3_ALU_INST(alu->inst) |
1461 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
1462 } else {
1463 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1464 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1465 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1466 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1467 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
1468 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
1469 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
1470 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
1471 S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
1472 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
1473 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->predicate) |
1474 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->predicate);
1475 }
1476 return 0;
1477 }
1478
1479 static void r600_bc_cf_vtx_build(uint32_t *bytecode, const struct r600_bc_cf *cf)
1480 {
1481 *bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
1482 *bytecode++ = S_SQ_CF_WORD1_CF_INST(cf->inst) |
1483 S_SQ_CF_WORD1_BARRIER(1) |
1484 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
1485 }
1486
1487 /* common for r600/r700 - eg in eg_asm.c */
1488 static int r600_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf)
1489 {
1490 unsigned id = cf->id;
1491
1492 switch (cf->inst) {
1493 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1494 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1495 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1496 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1497 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
1498 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
1499 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
1500 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank);
1501
1502 bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(cf->inst >> 3) |
1503 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) |
1504 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
1505 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
1506 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1507 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chiprev == CHIPREV_R600 ? cf->r6xx_uses_waterfall : 0) |
1508 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
1509 break;
1510 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1511 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1512 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1513 if (bc->chiprev == CHIPREV_R700)
1514 r700_bc_cf_vtx_build(&bc->bytecode[id], cf);
1515 else
1516 r600_bc_cf_vtx_build(&bc->bytecode[id], cf);
1517 break;
1518 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1519 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1520 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1521 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1522 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1523 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
1524 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1525 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
1526 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
1527 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
1528 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
1529 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
1530 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst) |
1531 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program);
1532 break;
1533 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1534 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1535 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1536 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1537 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1538 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1539 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1540 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1541 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1542 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
1543 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) |
1544 S_SQ_CF_WORD1_BARRIER(1) |
1545 S_SQ_CF_WORD1_COND(cf->cond) |
1546 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count);
1547
1548 break;
1549 default:
1550 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1551 return -EINVAL;
1552 }
1553 return 0;
1554 }
1555
1556 int r600_bc_build(struct r600_bc *bc)
1557 {
1558 struct r600_bc_cf *cf;
1559 struct r600_bc_alu *alu;
1560 struct r600_bc_vtx *vtx;
1561 struct r600_bc_tex *tex;
1562 uint32_t literal[4];
1563 unsigned nliteral;
1564 unsigned addr;
1565 int i, r;
1566
1567 if (bc->callstack[0].max > 0)
1568 bc->nstack = ((bc->callstack[0].max + 3) >> 2) + 2;
1569 if (bc->type == TGSI_PROCESSOR_VERTEX && !bc->nstack) {
1570 bc->nstack = 1;
1571 }
1572
1573 /* first path compute addr of each CF block */
1574 /* addr start after all the CF instructions */
1575 addr = bc->cf_last->id + 2;
1576 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1577 switch (cf->inst) {
1578 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1579 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1580 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1581 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1582 break;
1583 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1584 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1585 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1586 /* fetch node need to be 16 bytes aligned*/
1587 addr += 3;
1588 addr &= 0xFFFFFFFCUL;
1589 break;
1590 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1591 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1592 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1593 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1594 break;
1595 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1596 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1597 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1598 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1599 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1600 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1601 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1602 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1603 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1604 break;
1605 default:
1606 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1607 return -EINVAL;
1608 }
1609 cf->addr = addr;
1610 addr += cf->ndw;
1611 bc->ndw = cf->addr + cf->ndw;
1612 }
1613 free(bc->bytecode);
1614 bc->bytecode = calloc(1, bc->ndw * 4);
1615 if (bc->bytecode == NULL)
1616 return -ENOMEM;
1617 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1618 addr = cf->addr;
1619 if (bc->chiprev == CHIPREV_EVERGREEN)
1620 r = eg_bc_cf_build(bc, cf);
1621 else
1622 r = r600_bc_cf_build(bc, cf);
1623 if (r)
1624 return r;
1625 switch (cf->inst) {
1626 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1627 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1628 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1629 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1630 nliteral = 0;
1631 memset(literal, 0, sizeof(literal));
1632 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1633 r = r600_bc_alu_nliterals(bc, alu, literal, &nliteral);
1634 if (r)
1635 return r;
1636 r600_bc_alu_adjust_literals(bc, alu, literal, nliteral);
1637 switch(bc->chiprev) {
1638 case CHIPREV_R600:
1639 r = r600_bc_alu_build(bc, alu, addr);
1640 break;
1641 case CHIPREV_R700:
1642 case CHIPREV_EVERGREEN: /* eg alu is same encoding as r700 */
1643 r = r700_bc_alu_build(bc, alu, addr);
1644 break;
1645 default:
1646 R600_ERR("unknown family %d\n", bc->family);
1647 return -EINVAL;
1648 }
1649 if (r)
1650 return r;
1651 addr += 2;
1652 if (alu->last) {
1653 for (i = 0; i < align(nliteral, 2); ++i) {
1654 bc->bytecode[addr++] = literal[i];
1655 }
1656 nliteral = 0;
1657 memset(literal, 0, sizeof(literal));
1658 }
1659 }
1660 break;
1661 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1662 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1663 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1664 r = r600_bc_vtx_build(bc, vtx, addr);
1665 if (r)
1666 return r;
1667 addr += 4;
1668 }
1669 break;
1670 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1671 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
1672 r = r600_bc_tex_build(bc, tex, addr);
1673 if (r)
1674 return r;
1675 addr += 4;
1676 }
1677 break;
1678 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1679 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1680 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1681 case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1682 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1683 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1684 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1685 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1686 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1687 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1688 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1689 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1690 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1691 break;
1692 default:
1693 R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
1694 return -EINVAL;
1695 }
1696 }
1697 return 0;
1698 }
1699
1700 void r600_bc_clear(struct r600_bc *bc)
1701 {
1702 struct r600_bc_cf *cf = NULL, *next_cf;
1703
1704 free(bc->bytecode);
1705 bc->bytecode = NULL;
1706
1707 LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
1708 struct r600_bc_alu *alu = NULL, *next_alu;
1709 struct r600_bc_tex *tex = NULL, *next_tex;
1710 struct r600_bc_tex *vtx = NULL, *next_vtx;
1711
1712 LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
1713 free(alu);
1714 }
1715
1716 LIST_INITHEAD(&cf->alu);
1717
1718 LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) {
1719 free(tex);
1720 }
1721
1722 LIST_INITHEAD(&cf->tex);
1723
1724 LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) {
1725 free(vtx);
1726 }
1727
1728 LIST_INITHEAD(&cf->vtx);
1729
1730 free(cf);
1731 }
1732
1733 LIST_INITHEAD(&cf->list);
1734 }
1735
1736 void r600_bc_dump(struct r600_bc *bc)
1737 {
1738 struct r600_bc_cf *cf = NULL;
1739 struct r600_bc_alu *alu = NULL;
1740 struct r600_bc_vtx *vtx = NULL;
1741 struct r600_bc_tex *tex = NULL;
1742
1743 unsigned i, id;
1744 uint32_t literal[4];
1745 unsigned nliteral;
1746 char chip = '6';
1747
1748 switch (bc->chiprev) {
1749 case 1:
1750 chip = '7';
1751 break;
1752 case 2:
1753 chip = 'E';
1754 break;
1755 case 0:
1756 default:
1757 chip = '6';
1758 break;
1759 }
1760 fprintf(stderr, "bytecode %d dw -- %d gprs ---------------------\n", bc->ndw, bc->ngpr);
1761 fprintf(stderr, " %c\n", chip);
1762
1763 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1764 id = cf->id;
1765
1766 switch (cf->inst) {
1767 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
1768 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
1769 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
1770 case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
1771 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
1772 fprintf(stderr, "ADDR:%d ", cf->addr);
1773 fprintf(stderr, "KCACHE_MODE0:%X ", cf->kcache[0].mode);
1774 fprintf(stderr, "KCACHE_BANK0:%X ", cf->kcache[0].bank);
1775 fprintf(stderr, "KCACHE_BANK1:%X\n", cf->kcache[1].bank);
1776 id++;
1777 fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
1778 fprintf(stderr, "INST:%d ", cf->inst);
1779 fprintf(stderr, "KCACHE_MODE1:%X ", cf->kcache[1].mode);
1780 fprintf(stderr, "KCACHE_ADDR0:%X ", cf->kcache[0].addr);
1781 fprintf(stderr, "KCACHE_ADDR1:%X ", cf->kcache[1].addr);
1782 fprintf(stderr, "COUNT:%d\n", cf->ndw / 2);
1783 break;
1784 case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
1785 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
1786 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
1787 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
1788 fprintf(stderr, "ADDR:%d\n", cf->addr);
1789 id++;
1790 fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
1791 fprintf(stderr, "INST:%d ", cf->inst);
1792 fprintf(stderr, "COUNT:%d\n", cf->ndw / 4);
1793 break;
1794 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
1795 case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
1796 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
1797 fprintf(stderr, "GPR:%X ", cf->output.gpr);
1798 fprintf(stderr, "ELEM_SIZE:%X ", cf->output.elem_size);
1799 fprintf(stderr, "ARRAY_BASE:%X ", cf->output.array_base);
1800 fprintf(stderr, "TYPE:%X\n", cf->output.type);
1801 id++;
1802 fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
1803 fprintf(stderr, "SWIZ_X:%X ", cf->output.swizzle_x);
1804 fprintf(stderr, "SWIZ_Y:%X ", cf->output.swizzle_y);
1805 fprintf(stderr, "SWIZ_Z:%X ", cf->output.swizzle_z);
1806 fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
1807 fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
1808 fprintf(stderr, "INST:%d ", cf->output.inst);
1809 fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
1810 fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
1811 break;
1812 case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
1813 case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
1814 case V_SQ_CF_WORD1_SQ_CF_INST_POP:
1815 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
1816 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
1817 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
1818 case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
1819 case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
1820 case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
1821 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
1822 fprintf(stderr, "ADDR:%d\n", cf->cf_addr);
1823 id++;
1824 fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
1825 fprintf(stderr, "INST:%d ", cf->inst);
1826 fprintf(stderr, "COND:%X ", cf->cond);
1827 fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
1828 break;
1829 }
1830
1831 id = cf->addr;
1832 nliteral = 0;
1833 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1834 r600_bc_alu_nliterals(bc, alu, literal, &nliteral);
1835
1836 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
1837 fprintf(stderr, "SRC0(SEL:%d ", alu->src[0].sel);
1838 fprintf(stderr, "REL:%d ", alu->src[0].rel);
1839 fprintf(stderr, "CHAN:%d ", alu->src[0].chan);
1840 fprintf(stderr, "NEG:%d) ", alu->src[0].neg);
1841 fprintf(stderr, "SRC1(SEL:%d ", alu->src[1].sel);
1842 fprintf(stderr, "REL:%d ", alu->src[1].rel);
1843 fprintf(stderr, "CHAN:%d ", alu->src[1].chan);
1844 fprintf(stderr, "NEG:%d) ", alu->src[1].neg);
1845 fprintf(stderr, "LAST:%d)\n", alu->last);
1846 id++;
1847 fprintf(stderr, "%04d %08X %c ", id, bc->bytecode[id], alu->last ? '*' : ' ');
1848 fprintf(stderr, "INST:%d ", alu->inst);
1849 fprintf(stderr, "DST(SEL:%d ", alu->dst.sel);
1850 fprintf(stderr, "CHAN:%d ", alu->dst.chan);
1851 fprintf(stderr, "REL:%d ", alu->dst.rel);
1852 fprintf(stderr, "CLAMP:%d) ", alu->dst.clamp);
1853 fprintf(stderr, "BANK_SWIZZLE:%d ", alu->bank_swizzle);
1854 if (alu->is_op3) {
1855 fprintf(stderr, "SRC2(SEL:%d ", alu->src[2].sel);
1856 fprintf(stderr, "REL:%d ", alu->src[2].rel);
1857 fprintf(stderr, "CHAN:%d ", alu->src[2].chan);
1858 fprintf(stderr, "NEG:%d)\n", alu->src[2].neg);
1859 } else {
1860 fprintf(stderr, "SRC0_ABS:%d ", alu->src[0].abs);
1861 fprintf(stderr, "SRC1_ABS:%d ", alu->src[1].abs);
1862 fprintf(stderr, "WRITE_MASK:%d ", alu->dst.write);
1863 fprintf(stderr, "OMOD:%d ", alu->omod);
1864 fprintf(stderr, "EXECUTE_MASK:%d ", alu->predicate);
1865 fprintf(stderr, "UPDATE_PRED:%d\n", alu->predicate);
1866 }
1867
1868 id++;
1869 if (alu->last) {
1870 for (i = 0; i < nliteral; i++, id++) {
1871 float *f = (float*)(bc->bytecode + id);
1872 fprintf(stderr, "%04d %08X\t%f\n", id, bc->bytecode[id], *f);
1873 }
1874 id += nliteral & 1;
1875 nliteral = 0;
1876 }
1877 }
1878
1879 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
1880 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
1881 fprintf(stderr, "INST:%d ", tex->inst);
1882 fprintf(stderr, "RESOURCE_ID:%d ", tex->resource_id);
1883 fprintf(stderr, "SRC(GPR:%d ", tex->src_gpr);
1884 fprintf(stderr, "REL:%d)\n", tex->src_rel);
1885 id++;
1886 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
1887 fprintf(stderr, "DST(GPR:%d ", tex->dst_gpr);
1888 fprintf(stderr, "REL:%d ", tex->dst_rel);
1889 fprintf(stderr, "SEL_X:%d ", tex->dst_sel_x);
1890 fprintf(stderr, "SEL_Y:%d ", tex->dst_sel_y);
1891 fprintf(stderr, "SEL_Z:%d ", tex->dst_sel_z);
1892 fprintf(stderr, "SEL_W:%d) ", tex->dst_sel_w);
1893 fprintf(stderr, "LOD_BIAS:%d ", tex->lod_bias);
1894 fprintf(stderr, "COORD_TYPE_X:%d ", tex->coord_type_x);
1895 fprintf(stderr, "COORD_TYPE_Y:%d ", tex->coord_type_y);
1896 fprintf(stderr, "COORD_TYPE_Z:%d ", tex->coord_type_z);
1897 fprintf(stderr, "COORD_TYPE_W:%d\n", tex->coord_type_w);
1898 id++;
1899 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
1900 fprintf(stderr, "OFFSET_X:%d ", tex->offset_x);
1901 fprintf(stderr, "OFFSET_Y:%d ", tex->offset_y);
1902 fprintf(stderr, "OFFSET_Z:%d ", tex->offset_z);
1903 fprintf(stderr, "SAMPLER_ID:%d ", tex->sampler_id);
1904 fprintf(stderr, "SRC(SEL_X:%d ", tex->src_sel_x);
1905 fprintf(stderr, "SEL_Y:%d ", tex->src_sel_y);
1906 fprintf(stderr, "SEL_Z:%d ", tex->src_sel_z);
1907 fprintf(stderr, "SEL_W:%d)\n", tex->src_sel_w);
1908 id++;
1909 fprintf(stderr, "%04d %08X \n", id, bc->bytecode[id]);
1910 id++;
1911 }
1912
1913 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1914 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
1915 fprintf(stderr, "INST:%d ", vtx->inst);
1916 fprintf(stderr, "FETCH_TYPE:%d ", vtx->fetch_type);
1917 fprintf(stderr, "BUFFER_ID:%d\n", vtx->buffer_id);
1918 id++;
1919 /* This assumes that no semantic fetches exist */
1920 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
1921 fprintf(stderr, "SRC(GPR:%d ", vtx->src_gpr);
1922 fprintf(stderr, "SEL_X:%d) ", vtx->src_sel_x);
1923 fprintf(stderr, "MEGA_FETCH_COUNT:%d ", vtx->mega_fetch_count);
1924 fprintf(stderr, "DST(GPR:%d ", vtx->dst_gpr);
1925 fprintf(stderr, "SEL_X:%d ", vtx->dst_sel_x);
1926 fprintf(stderr, "SEL_Y:%d ", vtx->dst_sel_y);
1927 fprintf(stderr, "SEL_Z:%d ", vtx->dst_sel_z);
1928 fprintf(stderr, "SEL_W:%d) ", vtx->dst_sel_w);
1929 fprintf(stderr, "USE_CONST_FIELDS:%d ", vtx->use_const_fields);
1930 fprintf(stderr, "FORMAT(DATA:%d ", vtx->data_format);
1931 fprintf(stderr, "NUM:%d ", vtx->num_format_all);
1932 fprintf(stderr, "COMP:%d ", vtx->format_comp_all);
1933 fprintf(stderr, "MODE:%d)\n", vtx->srf_mode_all);
1934 id++;
1935 fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
1936 fprintf(stderr, "ENDIAN:%d ", vtx->endian);
1937 fprintf(stderr, "OFFSET:%d\n", vtx->offset);
1938 //TODO
1939 id++;
1940 fprintf(stderr, "%04d %08X \n", id, bc->bytecode[id]);
1941 id++;
1942 }
1943 }
1944
1945 fprintf(stderr, "--------------------------------------\n");
1946 }
1947
1948 static void r600_vertex_data_type(enum pipe_format pformat, unsigned *format,
1949 unsigned *num_format, unsigned *format_comp, unsigned *endian)
1950 {
1951 const struct util_format_description *desc;
1952 unsigned i;
1953
1954 *format = 0;
1955 *num_format = 0;
1956 *format_comp = 0;
1957 *endian = ENDIAN_NONE;
1958
1959 desc = util_format_description(pformat);
1960 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
1961 goto out_unknown;
1962 }
1963
1964 /* Find the first non-VOID channel. */
1965 for (i = 0; i < 4; i++) {
1966 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1967 break;
1968 }
1969 }
1970
1971 *endian = r600_endian_swap(desc->channel[i].size);
1972
1973 switch (desc->channel[i].type) {
1974 /* Half-floats, floats, ints */
1975 case UTIL_FORMAT_TYPE_FLOAT:
1976 switch (desc->channel[i].size) {
1977 case 16:
1978 switch (desc->nr_channels) {
1979 case 1:
1980 *format = FMT_16_FLOAT;
1981 break;
1982 case 2:
1983 *format = FMT_16_16_FLOAT;
1984 break;
1985 case 3:
1986 case 4:
1987 *format = FMT_16_16_16_16_FLOAT;
1988 break;
1989 }
1990 break;
1991 case 32:
1992 switch (desc->nr_channels) {
1993 case 1:
1994 *format = FMT_32_FLOAT;
1995 break;
1996 case 2:
1997 *format = FMT_32_32_FLOAT;
1998 break;
1999 case 3:
2000 *format = FMT_32_32_32_FLOAT;
2001 break;
2002 case 4:
2003 *format = FMT_32_32_32_32_FLOAT;
2004 break;
2005 }
2006 break;
2007 default:
2008 goto out_unknown;
2009 }
2010 break;
2011 /* Unsigned ints */
2012 case UTIL_FORMAT_TYPE_UNSIGNED:
2013 /* Signed ints */
2014 case UTIL_FORMAT_TYPE_SIGNED:
2015 switch (desc->channel[i].size) {
2016 case 8:
2017 switch (desc->nr_channels) {
2018 case 1:
2019 *format = FMT_8;
2020 break;
2021 case 2:
2022 *format = FMT_8_8;
2023 break;
2024 case 3:
2025 case 4:
2026 *format = FMT_8_8_8_8;
2027 break;
2028 }
2029 break;
2030 case 16:
2031 switch (desc->nr_channels) {
2032 case 1:
2033 *format = FMT_16;
2034 break;
2035 case 2:
2036 *format = FMT_16_16;
2037 break;
2038 case 3:
2039 case 4:
2040 *format = FMT_16_16_16_16;
2041 break;
2042 }
2043 break;
2044 case 32:
2045 switch (desc->nr_channels) {
2046 case 1:
2047 *format = FMT_32;
2048 break;
2049 case 2:
2050 *format = FMT_32_32;
2051 break;
2052 case 3:
2053 *format = FMT_32_32_32;
2054 break;
2055 case 4:
2056 *format = FMT_32_32_32_32;
2057 break;
2058 }
2059 break;
2060 default:
2061 goto out_unknown;
2062 }
2063 break;
2064 default:
2065 goto out_unknown;
2066 }
2067
2068 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2069 *format_comp = 1;
2070 }
2071 if (desc->channel[i].normalized) {
2072 *num_format = 0;
2073 } else {
2074 *num_format = 2;
2075 }
2076 return;
2077 out_unknown:
2078 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
2079 }
2080
2081 int r600_vertex_elements_build_fetch_shader(struct r600_pipe_context *rctx, struct r600_vertex_element *ve)
2082 {
2083 static int dump_shaders = -1;
2084
2085 struct r600_bc bc;
2086 struct r600_bc_vtx vtx;
2087 struct pipe_vertex_element *elements = ve->elements;
2088 const struct util_format_description *desc;
2089 unsigned fetch_resource_start = rctx->family >= CHIP_CEDAR ? 0 : 160;
2090 unsigned format, num_format, format_comp, endian;
2091 u32 *bytecode;
2092 int i, r;
2093
2094 /* vertex elements offset need special handling, if offset is bigger
2095 + * than what we can put in fetch instruction then we need to alterate
2096 * the vertex resource offset. In such case in order to simplify code
2097 * we will bound one resource per elements. It's a worst case scenario.
2098 */
2099 for (i = 0; i < ve->count; i++) {
2100 ve->vbuffer_offset[i] = C_SQ_VTX_WORD2_OFFSET & elements[i].src_offset;
2101 if (ve->vbuffer_offset[i]) {
2102 ve->vbuffer_need_offset = 1;
2103 }
2104 }
2105
2106 memset(&bc, 0, sizeof(bc));
2107 r = r600_bc_init(&bc, r600_get_family(rctx->radeon));
2108 if (r)
2109 return r;
2110
2111 for (i = 0; i < ve->count; i++) {
2112 if (elements[i].instance_divisor > 1) {
2113 struct r600_bc_alu alu;
2114
2115 memset(&alu, 0, sizeof(alu));
2116 alu.inst = BC_INST(&bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
2117 alu.src[0].sel = 0;
2118 alu.src[0].chan = 3;
2119
2120 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2121 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2122
2123 alu.dst.sel = i + 1;
2124 alu.dst.chan = 3;
2125 alu.dst.write = 1;
2126 alu.last = 1;
2127
2128 if ((r = r600_bc_add_alu(&bc, &alu))) {
2129 r600_bc_clear(&bc);
2130 return r;
2131 }
2132 }
2133 }
2134
2135 for (i = 0; i < ve->count; i++) {
2136 unsigned vbuffer_index;
2137 r600_vertex_data_type(ve->elements[i].src_format, &format, &num_format, &format_comp, &endian);
2138 desc = util_format_description(ve->elements[i].src_format);
2139 if (desc == NULL) {
2140 r600_bc_clear(&bc);
2141 R600_ERR("unknown format %d\n", ve->elements[i].src_format);
2142 return -EINVAL;
2143 }
2144
2145 /* see above for vbuffer_need_offset explanation */
2146 vbuffer_index = elements[i].vertex_buffer_index;
2147 memset(&vtx, 0, sizeof(vtx));
2148 vtx.buffer_id = (ve->vbuffer_need_offset ? i : vbuffer_index) + fetch_resource_start;
2149 vtx.fetch_type = elements[i].instance_divisor ? 1 : 0;
2150 vtx.src_gpr = elements[i].instance_divisor > 1 ? i + 1 : 0;
2151 vtx.src_sel_x = elements[i].instance_divisor ? 3 : 0;
2152 vtx.mega_fetch_count = 0x1F;
2153 vtx.dst_gpr = i + 1;
2154 vtx.dst_sel_x = desc->swizzle[0];
2155 vtx.dst_sel_y = desc->swizzle[1];
2156 vtx.dst_sel_z = desc->swizzle[2];
2157 vtx.dst_sel_w = desc->swizzle[3];
2158 vtx.data_format = format;
2159 vtx.num_format_all = num_format;
2160 vtx.format_comp_all = format_comp;
2161 vtx.srf_mode_all = 1;
2162 vtx.offset = elements[i].src_offset;
2163 vtx.endian = endian;
2164
2165 if ((r = r600_bc_add_vtx(&bc, &vtx))) {
2166 r600_bc_clear(&bc);
2167 return r;
2168 }
2169 }
2170
2171 r600_bc_add_cfinst(&bc, BC_INST(&bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN));
2172
2173 if ((r = r600_bc_build(&bc))) {
2174 r600_bc_clear(&bc);
2175 return r;
2176 }
2177
2178 if (dump_shaders == -1)
2179 dump_shaders = debug_get_bool_option("R600_DUMP_SHADERS", FALSE);
2180
2181 if (dump_shaders) {
2182 fprintf(stderr, "--------------------------------------------------------------\n");
2183 r600_bc_dump(&bc);
2184 fprintf(stderr, "______________________________________________________________\n");
2185 }
2186
2187 ve->fs_size = bc.ndw*4;
2188
2189 /* use PIPE_BIND_VERTEX_BUFFER so we use the cache buffer manager */
2190 ve->fetch_shader = r600_bo(rctx->radeon, ve->fs_size, 256, PIPE_BIND_VERTEX_BUFFER, 0);
2191 if (ve->fetch_shader == NULL) {
2192 r600_bc_clear(&bc);
2193 return -ENOMEM;
2194 }
2195
2196 bytecode = r600_bo_map(rctx->radeon, ve->fetch_shader, 0, NULL);
2197 if (bytecode == NULL) {
2198 r600_bc_clear(&bc);
2199 r600_bo_reference(rctx->radeon, &ve->fetch_shader, NULL);
2200 return -ENOMEM;
2201 }
2202
2203 if (R600_BIG_ENDIAN) {
2204 for (i = 0; i < ve->fs_size / 4; ++i) {
2205 bytecode[i] = bswap_32(bc.bytecode[i]);
2206 }
2207 } else {
2208 memcpy(bytecode, bc.bytecode, ve->fs_size);
2209 }
2210
2211 r600_bo_unmap(rctx->radeon, ve->fetch_shader);
2212 r600_bc_clear(&bc);
2213
2214 if (rctx->family >= CHIP_CEDAR)
2215 evergreen_fetch_shader(ve);
2216 else
2217 r600_fetch_shader(ve);
2218
2219 return 0;
2220 }