radeonsi: drop useless memcmp() check in si_set_blend_color()
[mesa.git] / src / gallium / drivers / r600 / r600_asm.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #ifndef R600_ASM_H
24 #define R600_ASM_H
25
26 #include "r600_pipe.h"
27 #include "r600_isa.h"
28 #include "tgsi/tgsi_exec.h"
29
30 struct r600_bytecode_alu_src {
31 unsigned sel;
32 unsigned chan;
33 unsigned neg;
34 unsigned abs;
35 unsigned rel;
36 unsigned kc_bank;
37 unsigned kc_rel;
38 uint32_t value;
39 };
40
41 struct r600_bytecode_alu_dst {
42 unsigned sel;
43 unsigned chan;
44 unsigned clamp;
45 unsigned write;
46 unsigned rel;
47 };
48
49 struct r600_bytecode_alu {
50 struct list_head list;
51 struct r600_bytecode_alu_src src[3];
52 struct r600_bytecode_alu_dst dst;
53 unsigned op;
54 unsigned last;
55 unsigned is_op3;
56 unsigned is_lds_idx_op;
57 unsigned execute_mask;
58 unsigned update_pred;
59 unsigned pred_sel;
60 unsigned bank_swizzle;
61 unsigned bank_swizzle_force;
62 unsigned omod;
63 unsigned index_mode;
64 unsigned lds_idx;
65 };
66
67 struct r600_bytecode_tex {
68 struct list_head list;
69 unsigned op;
70 unsigned inst_mod;
71 unsigned resource_id;
72 unsigned src_gpr;
73 unsigned src_rel;
74 unsigned dst_gpr;
75 unsigned dst_rel;
76 unsigned dst_sel_x;
77 unsigned dst_sel_y;
78 unsigned dst_sel_z;
79 unsigned dst_sel_w;
80 unsigned lod_bias;
81 unsigned coord_type_x;
82 unsigned coord_type_y;
83 unsigned coord_type_z;
84 unsigned coord_type_w;
85 int offset_x;
86 int offset_y;
87 int offset_z;
88 unsigned sampler_id;
89 unsigned src_sel_x;
90 unsigned src_sel_y;
91 unsigned src_sel_z;
92 unsigned src_sel_w;
93 /* indexed samplers/resources only on evergreen/cayman */
94 unsigned sampler_index_mode;
95 unsigned resource_index_mode;
96 };
97
98 struct r600_bytecode_vtx {
99 struct list_head list;
100 unsigned op;
101 unsigned fetch_type;
102 unsigned buffer_id;
103 unsigned src_gpr;
104 unsigned src_sel_x;
105 unsigned mega_fetch_count;
106 unsigned dst_gpr;
107 unsigned dst_sel_x;
108 unsigned dst_sel_y;
109 unsigned dst_sel_z;
110 unsigned dst_sel_w;
111 unsigned use_const_fields;
112 unsigned data_format;
113 unsigned num_format_all;
114 unsigned format_comp_all;
115 unsigned srf_mode_all;
116 unsigned offset;
117 unsigned endian;
118 unsigned buffer_index_mode;
119 };
120
121 struct r600_bytecode_gds {
122 struct list_head list;
123 unsigned op;
124 unsigned gds_op;
125 unsigned src_gpr;
126 unsigned src_rel;
127 unsigned src_sel_x;
128 unsigned src_sel_y;
129 unsigned src_sel_z;
130 unsigned src_gpr2;
131 unsigned dst_gpr;
132 unsigned dst_rel;
133 unsigned dst_sel_x;
134 unsigned dst_sel_y;
135 unsigned dst_sel_z;
136 unsigned dst_sel_w;
137 };
138
139 struct r600_bytecode_output {
140 unsigned array_base;
141 unsigned array_size;
142 unsigned comp_mask;
143 unsigned type;
144
145 unsigned op;
146
147 unsigned elem_size;
148 unsigned gpr;
149 unsigned swizzle_x;
150 unsigned swizzle_y;
151 unsigned swizzle_z;
152 unsigned swizzle_w;
153 unsigned burst_count;
154 unsigned index_gpr;
155 };
156
157 struct r600_bytecode_kcache {
158 unsigned bank;
159 unsigned mode;
160 unsigned addr;
161 unsigned index_mode;
162 };
163
164 struct r600_bytecode_cf {
165 struct list_head list;
166
167 unsigned op;
168 unsigned addr;
169 unsigned ndw;
170 unsigned id;
171 unsigned cond;
172 unsigned pop_count;
173 unsigned count;
174 unsigned cf_addr; /* control flow addr */
175 struct r600_bytecode_kcache kcache[4];
176 unsigned r6xx_uses_waterfall;
177 unsigned eg_alu_extended;
178 unsigned barrier;
179 unsigned end_of_program;
180 struct list_head alu;
181 struct list_head tex;
182 struct list_head vtx;
183 struct list_head gds;
184 struct r600_bytecode_output output;
185 struct r600_bytecode_alu *curr_bs_head;
186 struct r600_bytecode_alu *prev_bs_head;
187 struct r600_bytecode_alu *prev2_bs_head;
188 unsigned isa[2];
189 };
190
191 #define FC_NONE 0
192 #define FC_IF 1
193 #define FC_LOOP 2
194 #define FC_REP 3
195 #define FC_PUSH_VPM 4
196 #define FC_PUSH_WQM 5
197
198 struct r600_cf_stack_entry {
199 int type;
200 struct r600_bytecode_cf *start;
201 struct r600_bytecode_cf **mid; /* used to store the else point */
202 int num_mid;
203 };
204
205 #define SQ_MAX_CALL_DEPTH 0x00000020
206
207 #define AR_HANDLE_NORMAL 0
208 #define AR_HANDLE_RV6XX 1 /* except RV670 */
209
210 struct r600_stack_info {
211 /* current level of non-WQM PUSH operations
212 * (PUSH, PUSH_ELSE, ALU_PUSH_BEFORE) */
213 int push;
214 /* current level of WQM PUSH operations
215 * (PUSH, PUSH_ELSE, PUSH_WQM) */
216 int push_wqm;
217 /* current loop level */
218 int loop;
219
220 /* required depth */
221 int max_entries;
222 /* subentries per entry */
223 int entry_size;
224 };
225
226 struct r600_bytecode {
227 enum chip_class chip_class;
228 enum radeon_family family;
229 bool has_compressed_msaa_texturing;
230 int type;
231 struct list_head cf;
232 struct r600_bytecode_cf *cf_last;
233 unsigned ndw;
234 unsigned ncf;
235 unsigned ngpr;
236 unsigned nstack;
237 unsigned nlds_dw;
238 unsigned nresource;
239 unsigned force_add_cf;
240 uint32_t *bytecode;
241 uint32_t fc_sp;
242 struct r600_cf_stack_entry fc_stack[TGSI_EXEC_MAX_NESTING];
243 struct r600_stack_info stack;
244 unsigned ar_loaded;
245 unsigned ar_reg;
246 unsigned ar_chan;
247 unsigned ar_handling;
248 unsigned r6xx_nop_after_rel_dst;
249 bool index_loaded[2];
250 unsigned index_reg[2]; /* indexing register CF_INDEX_[01] */
251 unsigned debug_id;
252 struct r600_isa* isa;
253 };
254
255 /* eg_asm.c */
256 int eg_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf);
257 int egcm_load_index_reg(struct r600_bytecode *bc, unsigned id, bool inside_alu_clause);
258 int eg_bytecode_gds_build(struct r600_bytecode *bc, struct r600_bytecode_gds *gds, unsigned id);
259 int eg_bytecode_alu_build(struct r600_bytecode *bc,
260 struct r600_bytecode_alu *alu, unsigned id);
261 /* r600_asm.c */
262 void r600_bytecode_init(struct r600_bytecode *bc,
263 enum chip_class chip_class,
264 enum radeon_family family,
265 bool has_compressed_msaa_texturing);
266 void r600_bytecode_clear(struct r600_bytecode *bc);
267 int r600_bytecode_add_alu(struct r600_bytecode *bc,
268 const struct r600_bytecode_alu *alu);
269 int r600_bytecode_add_vtx(struct r600_bytecode *bc,
270 const struct r600_bytecode_vtx *vtx);
271 int r600_bytecode_add_tex(struct r600_bytecode *bc,
272 const struct r600_bytecode_tex *tex);
273 int r600_bytecode_add_gds(struct r600_bytecode *bc,
274 const struct r600_bytecode_gds *gds);
275 int r600_bytecode_add_output(struct r600_bytecode *bc,
276 const struct r600_bytecode_output *output);
277 int r600_bytecode_build(struct r600_bytecode *bc);
278 int r600_bytecode_add_cf(struct r600_bytecode *bc);
279 int r600_bytecode_add_cfinst(struct r600_bytecode *bc,
280 unsigned op);
281 int r600_bytecode_add_alu_type(struct r600_bytecode *bc,
282 const struct r600_bytecode_alu *alu, unsigned type);
283 void r600_bytecode_special_constants(uint32_t value,
284 unsigned *sel, unsigned *neg, unsigned abs);
285 void r600_bytecode_disasm(struct r600_bytecode *bc);
286 void r600_bytecode_alu_read(struct r600_bytecode *bc,
287 struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1);
288
289 int cm_bytecode_add_cf_end(struct r600_bytecode *bc);
290
291 void *r600_create_vertex_fetch_shader(struct pipe_context *ctx,
292 unsigned count,
293 const struct pipe_vertex_element *elements);
294
295 /* r700_asm.c */
296 void r700_bytecode_cf_vtx_build(uint32_t *bytecode,
297 const struct r600_bytecode_cf *cf);
298 int r700_bytecode_alu_build(struct r600_bytecode *bc,
299 struct r600_bytecode_alu *alu, unsigned id);
300 void r700_bytecode_alu_read(struct r600_bytecode *bc,
301 struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1);
302 void r600_bytecode_export_read(struct r600_bytecode *bc,
303 struct r600_bytecode_output *output, uint32_t word0, uint32_t word1);
304 void eg_bytecode_export_read(struct r600_bytecode *bc,
305 struct r600_bytecode_output *output, uint32_t word0, uint32_t word1);
306
307 void r600_vertex_data_type(enum pipe_format pformat, unsigned *format,
308 unsigned *num_format, unsigned *format_comp, unsigned *endian);
309
310 static inline int fp64_switch(int i)
311 {
312 switch (i) {
313 case 0:
314 return 1;
315 case 1:
316 return 0;
317 case 2:
318 return 3;
319 case 3:
320 return 2;
321 }
322 return 0;
323 }
324 #endif