0b22f037015f641ffa73c462bb7c5e885ca69c1a
[mesa.git] / src / gallium / drivers / r600 / r600_blit.c
1 /*
2 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Marek Olšák
26 */
27 #include <errno.h>
28 #include <pipe/p_screen.h>
29 #include <util/u_blitter.h>
30 #include <util/u_inlines.h>
31 #include <util/u_memory.h>
32 #include "util/u_surface.h"
33 #include "r600_screen.h"
34 #include "r600_context.h"
35 #include "r600d.h"
36
37 static void r600_blitter_save_states(struct pipe_context *ctx)
38 {
39 struct r600_context *rctx = r600_context(ctx);
40
41 util_blitter_save_blend(rctx->blitter, rctx->blend);
42 util_blitter_save_depth_stencil_alpha(rctx->blitter, rctx->dsa);
43 if (rctx->stencil_ref) {
44 util_blitter_save_stencil_ref(rctx->blitter,
45 &rctx->stencil_ref->state.stencil_ref);
46 }
47 util_blitter_save_rasterizer(rctx->blitter, rctx->rasterizer);
48 util_blitter_save_fragment_shader(rctx->blitter, rctx->ps_shader);
49 util_blitter_save_vertex_shader(rctx->blitter, rctx->vs_shader);
50 util_blitter_save_vertex_elements(rctx->blitter, rctx->vertex_elements);
51 if (rctx->viewport) {
52 util_blitter_save_viewport(rctx->blitter, &rctx->viewport->state.viewport);
53 }
54 if (rctx->clip) {
55 util_blitter_save_clip(rctx->blitter, &rctx->clip->state.clip);
56 }
57 util_blitter_save_vertex_buffers(rctx->blitter, rctx->nvertex_buffer,
58 rctx->vertex_buffer);
59
60 /* remove ptr so they don't get deleted */
61 rctx->blend = NULL;
62 rctx->clip = NULL;
63 rctx->vs_shader = NULL;
64 rctx->ps_shader = NULL;
65 rctx->rasterizer = NULL;
66 rctx->dsa = NULL;
67 rctx->vertex_elements = NULL;
68
69 /* suspend queries */
70 r600_queries_suspend(ctx);
71 }
72
73 static void r600_clear(struct pipe_context *ctx, unsigned buffers,
74 const float *rgba, double depth, unsigned stencil)
75 {
76 struct r600_context *rctx = r600_context(ctx);
77 struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
78
79 r600_blitter_save_states(ctx);
80 util_blitter_clear(rctx->blitter, fb->width, fb->height,
81 fb->nr_cbufs, buffers, rgba, depth,
82 stencil);
83 /* resume queries */
84 r600_queries_resume(ctx);
85 }
86
87 static void r600_clear_render_target(struct pipe_context *ctx,
88 struct pipe_surface *dst,
89 const float *rgba,
90 unsigned dstx, unsigned dsty,
91 unsigned width, unsigned height)
92 {
93 struct r600_context *rctx = r600_context(ctx);
94 struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
95
96 r600_blitter_save_states(ctx);
97 util_blitter_save_framebuffer(rctx->blitter, fb);
98
99 util_blitter_clear_render_target(rctx->blitter, dst, rgba,
100 dstx, dsty, width, height);
101 /* resume queries */
102 r600_queries_resume(ctx);
103 }
104
105 static void r600_clear_depth_stencil(struct pipe_context *ctx,
106 struct pipe_surface *dst,
107 unsigned clear_flags,
108 double depth,
109 unsigned stencil,
110 unsigned dstx, unsigned dsty,
111 unsigned width, unsigned height)
112 {
113 struct r600_context *rctx = r600_context(ctx);
114 struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
115
116 r600_blitter_save_states(ctx);
117 util_blitter_save_framebuffer(rctx->blitter, fb);
118
119 util_blitter_clear_depth_stencil(rctx->blitter, dst, clear_flags, depth, stencil,
120 dstx, dsty, width, height);
121 /* resume queries */
122 r600_queries_resume(ctx);
123 }
124
125
126 static void r600_resource_copy_region(struct pipe_context *ctx,
127 struct pipe_resource *dst,
128 struct pipe_subresource subdst,
129 unsigned dstx, unsigned dsty, unsigned dstz,
130 struct pipe_resource *src,
131 struct pipe_subresource subsrc,
132 unsigned srcx, unsigned srcy, unsigned srcz,
133 unsigned width, unsigned height)
134 {
135 util_resource_copy_region(ctx, dst, subdst, dstx, dsty, dstz,
136 src, subsrc, srcx, srcy, srcz, width, height);
137 }
138
139 static void *r600_create_db_flush_dsa(struct r600_context *rctx)
140 {
141 struct r600_screen *rscreen = rctx->screen;
142 struct pipe_depth_stencil_alpha_state dsa;
143 struct r600_context_state *state;
144 boolean quirk = false;
145 enum radeon_family family;
146
147 family = radeon_get_family(rscreen->rw);
148 if (family == CHIP_RV610 || family == CHIP_RV630 || family == CHIP_RV620 ||
149 family == CHIP_RV635)
150 quirk = true;
151
152 memset(&dsa, 0, sizeof(dsa));
153
154 if (quirk) {
155 dsa.depth.enabled = 1;
156 dsa.depth.func = PIPE_FUNC_LEQUAL;
157 dsa.stencil[0].enabled = 1;
158 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
159 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
160 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
161 dsa.stencil[0].writemask = 0xff;
162 }
163
164 state = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
165 state->flags |= R600_STATE_FLAG_DSA_FLUSH;
166 return state;
167
168 }
169
170 void r600_init_blit_functions(struct r600_context *rctx)
171 {
172 rctx->context.clear = r600_clear;
173 rctx->context.clear_render_target = r600_clear_render_target;
174 rctx->context.clear_depth_stencil = r600_clear_depth_stencil;
175 rctx->context.resource_copy_region = r600_resource_copy_region;
176
177 /* create a custom depth stencil for DB flush */
178 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
179 }
180
181 int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture)
182 {
183 struct r600_context *rctx = r600_context(ctx);
184 struct r600_screen *rscreen = rctx->screen;
185 struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
186 struct pipe_surface *zsurf, *cbsurf;
187 enum radeon_family family;
188 int level = 0;
189 float depth = 1.0f;
190
191 zsurf = ctx->screen->get_tex_surface(ctx->screen, &texture->resource.base.b, 0, level, 0,
192 PIPE_BIND_DEPTH_STENCIL);
193
194 cbsurf = ctx->screen->get_tex_surface(ctx->screen, texture->flushed_depth_texture, 0, level, 0,
195 PIPE_BIND_RENDER_TARGET);
196
197 r600_blitter_save_states(ctx);
198 util_blitter_save_framebuffer(rctx->blitter, fb);
199
200 family = radeon_get_family(rscreen->rw);
201 if (family == CHIP_RV610 || family == CHIP_RV630 || family == CHIP_RV620 ||
202 family == CHIP_RV635)
203 depth = 0.0f;
204
205 util_blitter_custom_depth_stencil(rctx->blitter, zsurf, cbsurf, rctx->custom_dsa_flush, depth);
206
207 /* resume queries */
208 r600_queries_resume(ctx);
209 return 0;
210 }