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[mesa.git] / src / gallium / drivers / r600 / r600_blit.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_pipe.h"
24 #include "compute_memory_pool.h"
25 #include "evergreen_compute.h"
26 #include "util/u_surface.h"
27 #include "util/u_format.h"
28 #include "evergreend.h"
29
30 enum r600_blitter_op /* bitmask */
31 {
32 R600_SAVE_FRAGMENT_STATE = 1,
33 R600_SAVE_TEXTURES = 2,
34 R600_SAVE_FRAMEBUFFER = 4,
35 R600_DISABLE_RENDER_COND = 8,
36
37 R600_CLEAR = R600_SAVE_FRAGMENT_STATE,
38
39 R600_CLEAR_SURFACE = R600_SAVE_FRAGMENT_STATE | R600_SAVE_FRAMEBUFFER,
40
41 R600_COPY_BUFFER = R600_DISABLE_RENDER_COND,
42
43 R600_COPY_TEXTURE = R600_SAVE_FRAGMENT_STATE | R600_SAVE_FRAMEBUFFER | R600_SAVE_TEXTURES |
44 R600_DISABLE_RENDER_COND,
45
46 R600_BLIT = R600_SAVE_FRAGMENT_STATE | R600_SAVE_FRAMEBUFFER | R600_SAVE_TEXTURES,
47
48 R600_DECOMPRESS = R600_SAVE_FRAGMENT_STATE | R600_SAVE_FRAMEBUFFER | R600_DISABLE_RENDER_COND,
49
50 R600_COLOR_RESOLVE = R600_SAVE_FRAGMENT_STATE | R600_SAVE_FRAMEBUFFER
51 };
52
53 static void r600_blitter_begin(struct pipe_context *ctx, enum r600_blitter_op op)
54 {
55 struct r600_context *rctx = (struct r600_context *)ctx;
56
57 r600_suspend_nontimer_queries(&rctx->b);
58
59 util_blitter_save_vertex_buffer_slot(rctx->blitter, rctx->vertex_buffer_state.vb);
60 util_blitter_save_vertex_elements(rctx->blitter, rctx->vertex_fetch_shader.cso);
61 util_blitter_save_vertex_shader(rctx->blitter, rctx->vs_shader);
62 util_blitter_save_geometry_shader(rctx->blitter, rctx->gs_shader);
63 util_blitter_save_so_targets(rctx->blitter, rctx->b.streamout.num_targets,
64 (struct pipe_stream_output_target**)rctx->b.streamout.targets);
65 util_blitter_save_rasterizer(rctx->blitter, rctx->rasterizer_state.cso);
66
67 if (op & R600_SAVE_FRAGMENT_STATE) {
68 util_blitter_save_viewport(rctx->blitter, &rctx->viewport.state[0]);
69 util_blitter_save_scissor(rctx->blitter, &rctx->scissor.scissor[0]);
70 util_blitter_save_fragment_shader(rctx->blitter, rctx->ps_shader);
71 util_blitter_save_blend(rctx->blitter, rctx->blend_state.cso);
72 util_blitter_save_depth_stencil_alpha(rctx->blitter, rctx->dsa_state.cso);
73 util_blitter_save_stencil_ref(rctx->blitter, &rctx->stencil_ref.pipe_state);
74 util_blitter_save_sample_mask(rctx->blitter, rctx->sample_mask.sample_mask);
75 }
76
77 if (op & R600_SAVE_FRAMEBUFFER)
78 util_blitter_save_framebuffer(rctx->blitter, &rctx->framebuffer.state);
79
80 if (op & R600_SAVE_TEXTURES) {
81 util_blitter_save_fragment_sampler_states(
82 rctx->blitter, util_last_bit(rctx->samplers[PIPE_SHADER_FRAGMENT].states.enabled_mask),
83 (void**)rctx->samplers[PIPE_SHADER_FRAGMENT].states.states);
84
85 util_blitter_save_fragment_sampler_views(
86 rctx->blitter, util_last_bit(rctx->samplers[PIPE_SHADER_FRAGMENT].views.enabled_mask),
87 (struct pipe_sampler_view**)rctx->samplers[PIPE_SHADER_FRAGMENT].views.views);
88 }
89
90 if (op & R600_DISABLE_RENDER_COND)
91 rctx->b.render_cond_force_off = true;
92 }
93
94 static void r600_blitter_end(struct pipe_context *ctx)
95 {
96 struct r600_context *rctx = (struct r600_context *)ctx;
97
98 rctx->b.render_cond_force_off = false;
99 r600_resume_nontimer_queries(&rctx->b);
100 }
101
102 static unsigned u_max_sample(struct pipe_resource *r)
103 {
104 return r->nr_samples ? r->nr_samples - 1 : 0;
105 }
106
107 static void r600_blit_decompress_depth(struct pipe_context *ctx,
108 struct r600_texture *texture,
109 struct r600_texture *staging,
110 unsigned first_level, unsigned last_level,
111 unsigned first_layer, unsigned last_layer,
112 unsigned first_sample, unsigned last_sample)
113 {
114 struct r600_context *rctx = (struct r600_context *)ctx;
115 unsigned layer, level, sample, checked_last_layer, max_layer, max_sample;
116 struct r600_texture *flushed_depth_texture = staging ?
117 staging : texture->flushed_depth_texture;
118 const struct util_format_description *desc =
119 util_format_description(texture->resource.b.b.format);
120 float depth;
121
122 if (!staging && !texture->dirty_level_mask)
123 return;
124
125 max_sample = u_max_sample(&texture->resource.b.b);
126
127 /* XXX Decompressing MSAA depth textures is broken on R6xx.
128 * There is also a hardlock if CMASK and FMASK are not present.
129 * Just skip this until we find out how to fix it. */
130 if (rctx->b.chip_class == R600 && max_sample > 0) {
131 texture->dirty_level_mask = 0;
132 return;
133 }
134
135 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
136 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
137 depth = 0.0f;
138 else
139 depth = 1.0f;
140
141 /* Enable decompression in DB_RENDER_CONTROL */
142 rctx->db_misc_state.flush_depthstencil_through_cb = true;
143 rctx->db_misc_state.copy_depth = util_format_has_depth(desc);
144 rctx->db_misc_state.copy_stencil = util_format_has_stencil(desc);
145 rctx->db_misc_state.copy_sample = first_sample;
146 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
147
148 for (level = first_level; level <= last_level; level++) {
149 if (!staging && !(texture->dirty_level_mask & (1 << level)))
150 continue;
151
152 /* The smaller the mipmap level, the less layers there are
153 * as far as 3D textures are concerned. */
154 max_layer = util_max_layer(&texture->resource.b.b, level);
155 checked_last_layer = last_layer < max_layer ? last_layer : max_layer;
156
157 for (layer = first_layer; layer <= checked_last_layer; layer++) {
158 for (sample = first_sample; sample <= last_sample; sample++) {
159 struct pipe_surface *zsurf, *cbsurf, surf_tmpl;
160
161 if (sample != rctx->db_misc_state.copy_sample) {
162 rctx->db_misc_state.copy_sample = sample;
163 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
164 }
165
166 surf_tmpl.format = texture->resource.b.b.format;
167 surf_tmpl.u.tex.level = level;
168 surf_tmpl.u.tex.first_layer = layer;
169 surf_tmpl.u.tex.last_layer = layer;
170
171 zsurf = ctx->create_surface(ctx, &texture->resource.b.b, &surf_tmpl);
172
173 surf_tmpl.format = flushed_depth_texture->resource.b.b.format;
174 cbsurf = ctx->create_surface(ctx,
175 &flushed_depth_texture->resource.b.b, &surf_tmpl);
176
177 r600_blitter_begin(ctx, R600_DECOMPRESS);
178 util_blitter_custom_depth_stencil(rctx->blitter, zsurf, cbsurf, 1 << sample,
179 rctx->custom_dsa_flush, depth);
180 r600_blitter_end(ctx);
181
182 pipe_surface_reference(&zsurf, NULL);
183 pipe_surface_reference(&cbsurf, NULL);
184 }
185 }
186
187 /* The texture will always be dirty if some layers or samples aren't flushed.
188 * I don't think this case occurs often though. */
189 if (!staging &&
190 first_layer == 0 && last_layer == max_layer &&
191 first_sample == 0 && last_sample == max_sample) {
192 texture->dirty_level_mask &= ~(1 << level);
193 }
194 }
195
196 /* reenable compression in DB_RENDER_CONTROL */
197 rctx->db_misc_state.flush_depthstencil_through_cb = false;
198 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
199 }
200
201 static void r600_blit_decompress_depth_in_place(struct r600_context *rctx,
202 struct r600_texture *texture,
203 bool is_stencil_sampler,
204 unsigned first_level, unsigned last_level,
205 unsigned first_layer, unsigned last_layer)
206 {
207 struct pipe_surface *zsurf, surf_tmpl = {{0}};
208 unsigned layer, max_layer, checked_last_layer, level;
209 unsigned *dirty_level_mask;
210
211 /* Enable decompression in DB_RENDER_CONTROL */
212 if (is_stencil_sampler) {
213 rctx->db_misc_state.flush_stencil_inplace = true;
214 dirty_level_mask = &texture->stencil_dirty_level_mask;
215 } else {
216 rctx->db_misc_state.flush_depth_inplace = true;
217 dirty_level_mask = &texture->dirty_level_mask;
218 }
219 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
220
221 surf_tmpl.format = texture->resource.b.b.format;
222
223 for (level = first_level; level <= last_level; level++) {
224 if (!(*dirty_level_mask & (1 << level)))
225 continue;
226
227 surf_tmpl.u.tex.level = level;
228
229 /* The smaller the mipmap level, the less layers there are
230 * as far as 3D textures are concerned. */
231 max_layer = util_max_layer(&texture->resource.b.b, level);
232 checked_last_layer = last_layer < max_layer ? last_layer : max_layer;
233
234 for (layer = first_layer; layer <= checked_last_layer; layer++) {
235 surf_tmpl.u.tex.first_layer = layer;
236 surf_tmpl.u.tex.last_layer = layer;
237
238 zsurf = rctx->b.b.create_surface(&rctx->b.b, &texture->resource.b.b, &surf_tmpl);
239
240 r600_blitter_begin(&rctx->b.b, R600_DECOMPRESS);
241 util_blitter_custom_depth_stencil(rctx->blitter, zsurf, NULL, ~0,
242 rctx->custom_dsa_flush, 1.0f);
243 r600_blitter_end(&rctx->b.b);
244
245 pipe_surface_reference(&zsurf, NULL);
246 }
247
248 /* The texture will always be dirty if some layers or samples aren't flushed.
249 * I don't think this case occurs often though. */
250 if (first_layer == 0 && last_layer == max_layer) {
251 *dirty_level_mask &= ~(1 << level);
252 }
253 }
254
255 /* Disable decompression in DB_RENDER_CONTROL */
256 rctx->db_misc_state.flush_depth_inplace = false;
257 rctx->db_misc_state.flush_stencil_inplace = false;
258 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
259 }
260
261 void r600_decompress_depth_textures(struct r600_context *rctx,
262 struct r600_samplerview_state *textures)
263 {
264 unsigned i;
265 unsigned depth_texture_mask = textures->compressed_depthtex_mask;
266
267 while (depth_texture_mask) {
268 struct pipe_sampler_view *view;
269 struct r600_pipe_sampler_view *rview;
270 struct r600_texture *tex;
271
272 i = u_bit_scan(&depth_texture_mask);
273
274 view = &textures->views[i]->base;
275 assert(view);
276 rview = (struct r600_pipe_sampler_view*)view;
277
278 tex = (struct r600_texture *)view->texture;
279 assert(tex->is_depth && !tex->is_flushing_texture);
280
281 if (rctx->b.chip_class >= EVERGREEN ||
282 r600_can_read_depth(tex)) {
283 r600_blit_decompress_depth_in_place(rctx, tex,
284 rview->is_stencil_sampler,
285 view->u.tex.first_level, view->u.tex.last_level,
286 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));
287 } else {
288 r600_blit_decompress_depth(&rctx->b.b, tex, NULL,
289 view->u.tex.first_level, view->u.tex.last_level,
290 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level),
291 0, u_max_sample(&tex->resource.b.b));
292 }
293 }
294 }
295
296 static void r600_blit_decompress_color(struct pipe_context *ctx,
297 struct r600_texture *rtex,
298 unsigned first_level, unsigned last_level,
299 unsigned first_layer, unsigned last_layer)
300 {
301 struct r600_context *rctx = (struct r600_context *)ctx;
302 unsigned layer, level, checked_last_layer, max_layer;
303
304 if (!rtex->dirty_level_mask)
305 return;
306
307 for (level = first_level; level <= last_level; level++) {
308 if (!(rtex->dirty_level_mask & (1 << level)))
309 continue;
310
311 /* The smaller the mipmap level, the less layers there are
312 * as far as 3D textures are concerned. */
313 max_layer = util_max_layer(&rtex->resource.b.b, level);
314 checked_last_layer = last_layer < max_layer ? last_layer : max_layer;
315
316 for (layer = first_layer; layer <= checked_last_layer; layer++) {
317 struct pipe_surface *cbsurf, surf_tmpl;
318
319 surf_tmpl.format = rtex->resource.b.b.format;
320 surf_tmpl.u.tex.level = level;
321 surf_tmpl.u.tex.first_layer = layer;
322 surf_tmpl.u.tex.last_layer = layer;
323 cbsurf = ctx->create_surface(ctx, &rtex->resource.b.b, &surf_tmpl);
324
325 r600_blitter_begin(ctx, R600_DECOMPRESS);
326 util_blitter_custom_color(rctx->blitter, cbsurf,
327 rtex->fmask.size ? rctx->custom_blend_decompress : rctx->custom_blend_fastclear);
328 r600_blitter_end(ctx);
329
330 pipe_surface_reference(&cbsurf, NULL);
331 }
332
333 /* The texture will always be dirty if some layers aren't flushed.
334 * I don't think this case occurs often though. */
335 if (first_layer == 0 && last_layer == max_layer) {
336 rtex->dirty_level_mask &= ~(1 << level);
337 }
338 }
339 }
340
341 void r600_decompress_color_textures(struct r600_context *rctx,
342 struct r600_samplerview_state *textures)
343 {
344 unsigned i;
345 unsigned mask = textures->compressed_colortex_mask;
346
347 while (mask) {
348 struct pipe_sampler_view *view;
349 struct r600_texture *tex;
350
351 i = u_bit_scan(&mask);
352
353 view = &textures->views[i]->base;
354 assert(view);
355
356 tex = (struct r600_texture *)view->texture;
357 assert(tex->cmask.size);
358
359 r600_blit_decompress_color(&rctx->b.b, tex,
360 view->u.tex.first_level, view->u.tex.last_level,
361 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));
362 }
363 }
364
365 /* Helper for decompressing a portion of a color or depth resource before
366 * blitting if any decompression is needed.
367 * The driver doesn't decompress resources automatically while u_blitter is
368 * rendering. */
369 static bool r600_decompress_subresource(struct pipe_context *ctx,
370 struct pipe_resource *tex,
371 unsigned level,
372 unsigned first_layer, unsigned last_layer)
373 {
374 struct r600_context *rctx = (struct r600_context *)ctx;
375 struct r600_texture *rtex = (struct r600_texture*)tex;
376
377 if (rtex->is_depth && !rtex->is_flushing_texture) {
378 if (rctx->b.chip_class >= EVERGREEN ||
379 r600_can_read_depth(rtex)) {
380 r600_blit_decompress_depth_in_place(rctx, rtex, false,
381 level, level,
382 first_layer, last_layer);
383 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
384 r600_blit_decompress_depth_in_place(rctx, rtex, true,
385 level, level,
386 first_layer, last_layer);
387 }
388 } else {
389 if (!r600_init_flushed_depth_texture(ctx, tex, NULL))
390 return false; /* error */
391
392 r600_blit_decompress_depth(ctx, rtex, NULL,
393 level, level,
394 first_layer, last_layer,
395 0, u_max_sample(tex));
396 }
397 } else if (rtex->cmask.size) {
398 r600_blit_decompress_color(ctx, rtex, level, level,
399 first_layer, last_layer);
400 }
401 return true;
402 }
403
404 static void r600_clear(struct pipe_context *ctx, unsigned buffers,
405 const union pipe_color_union *color,
406 double depth, unsigned stencil)
407 {
408 struct r600_context *rctx = (struct r600_context *)ctx;
409 struct pipe_framebuffer_state *fb = &rctx->framebuffer.state;
410
411 if (buffers & PIPE_CLEAR_COLOR && rctx->b.chip_class >= EVERGREEN) {
412 evergreen_do_fast_color_clear(&rctx->b, fb, &rctx->framebuffer.atom,
413 &buffers, NULL, color);
414 if (!buffers)
415 return; /* all buffers have been fast cleared */
416 }
417
418 if (buffers & PIPE_CLEAR_COLOR) {
419 int i;
420
421 /* These buffers cannot use fast clear, make sure to disable expansion. */
422 for (i = 0; i < fb->nr_cbufs; i++) {
423 struct r600_texture *tex;
424
425 /* If not clearing this buffer, skip. */
426 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
427 continue;
428
429 if (!fb->cbufs[i])
430 continue;
431
432 tex = (struct r600_texture *)fb->cbufs[i]->texture;
433 if (tex->fmask.size == 0)
434 tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
435 }
436 }
437
438 /* if hyperz enabled just clear hyperz */
439 if (fb->zsbuf && (buffers & PIPE_CLEAR_DEPTH)) {
440 struct r600_texture *rtex;
441 unsigned level = fb->zsbuf->u.tex.level;
442
443 rtex = (struct r600_texture*)fb->zsbuf->texture;
444
445 /* We can't use hyperz fast clear if each slice of a texture
446 * array are clear to different value. To simplify code just
447 * disable fast clear for texture array.
448 */
449 /* Only use htile for first level */
450 if (rtex->htile_buffer && !level &&
451 fb->zsbuf->u.tex.first_layer == 0 &&
452 fb->zsbuf->u.tex.last_layer == util_max_layer(&rtex->resource.b.b, level)) {
453 if (rtex->depth_clear_value != depth) {
454 rtex->depth_clear_value = depth;
455 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
456 }
457 rctx->db_misc_state.htile_clear = true;
458 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
459 }
460 }
461
462 r600_blitter_begin(ctx, R600_CLEAR);
463 util_blitter_clear(rctx->blitter, fb->width, fb->height,
464 util_framebuffer_get_num_layers(fb),
465 buffers, color, depth, stencil);
466 r600_blitter_end(ctx);
467
468 /* disable fast clear */
469 if (rctx->db_misc_state.htile_clear) {
470 rctx->db_misc_state.htile_clear = false;
471 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
472 }
473 }
474
475 static void r600_clear_render_target(struct pipe_context *ctx,
476 struct pipe_surface *dst,
477 const union pipe_color_union *color,
478 unsigned dstx, unsigned dsty,
479 unsigned width, unsigned height)
480 {
481 struct r600_context *rctx = (struct r600_context *)ctx;
482
483 r600_blitter_begin(ctx, R600_CLEAR_SURFACE);
484 util_blitter_clear_render_target(rctx->blitter, dst, color,
485 dstx, dsty, width, height);
486 r600_blitter_end(ctx);
487 }
488
489 static void r600_clear_depth_stencil(struct pipe_context *ctx,
490 struct pipe_surface *dst,
491 unsigned clear_flags,
492 double depth,
493 unsigned stencil,
494 unsigned dstx, unsigned dsty,
495 unsigned width, unsigned height)
496 {
497 struct r600_context *rctx = (struct r600_context *)ctx;
498
499 r600_blitter_begin(ctx, R600_CLEAR_SURFACE);
500 util_blitter_clear_depth_stencil(rctx->blitter, dst, clear_flags, depth, stencil,
501 dstx, dsty, width, height);
502 r600_blitter_end(ctx);
503 }
504
505 static void r600_copy_buffer(struct pipe_context *ctx, struct pipe_resource *dst, unsigned dstx,
506 struct pipe_resource *src, const struct pipe_box *src_box)
507 {
508 struct r600_context *rctx = (struct r600_context*)ctx;
509
510 if (rctx->screen->b.has_cp_dma) {
511 r600_cp_dma_copy_buffer(rctx, dst, dstx, src, src_box->x, src_box->width);
512 }
513 else if (rctx->screen->b.has_streamout &&
514 /* Require 4-byte alignment. */
515 dstx % 4 == 0 && src_box->x % 4 == 0 && src_box->width % 4 == 0) {
516
517 r600_blitter_begin(ctx, R600_COPY_BUFFER);
518 util_blitter_copy_buffer(rctx->blitter, dst, dstx, src, src_box->x, src_box->width);
519 r600_blitter_end(ctx);
520 } else {
521 util_resource_copy_region(ctx, dst, 0, dstx, 0, 0, src, 0, src_box);
522 }
523
524 /* The index buffer (VGT) doesn't seem to see the result of the copying.
525 * Can we somehow flush the index buffer cache? Starting a new IB seems
526 * to do the trick. */
527 if (rctx->b.chip_class <= R700)
528 rctx->b.gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
529 }
530
531 /**
532 * Global buffers are not really resources, they are are actually offsets
533 * into a single global resource (r600_screen::global_pool). The means
534 * they don't have their own cs_buf handle, so they cannot be passed
535 * to r600_copy_buffer() and must be handled separately.
536 */
537 static void r600_copy_global_buffer(struct pipe_context *ctx,
538 struct pipe_resource *dst, unsigned
539 dstx, struct pipe_resource *src,
540 const struct pipe_box *src_box)
541 {
542 struct r600_context *rctx = (struct r600_context*)ctx;
543 struct compute_memory_pool *pool = rctx->screen->global_pool;
544 struct pipe_box new_src_box = *src_box;
545
546 if (src->bind & PIPE_BIND_GLOBAL) {
547 struct r600_resource_global *rsrc =
548 (struct r600_resource_global *)src;
549 struct compute_memory_item *item = rsrc->chunk;
550
551 if (is_item_in_pool(item)) {
552 new_src_box.x += 4 * item->start_in_dw;
553 src = (struct pipe_resource *)pool->bo;
554 } else {
555 if (item->real_buffer == NULL) {
556 item->real_buffer =
557 r600_compute_buffer_alloc_vram(pool->screen,
558 item->size_in_dw * 4);
559 }
560 src = (struct pipe_resource*)item->real_buffer;
561 }
562 }
563 if (dst->bind & PIPE_BIND_GLOBAL) {
564 struct r600_resource_global *rdst =
565 (struct r600_resource_global *)dst;
566 struct compute_memory_item *item = rdst->chunk;
567
568 if (is_item_in_pool(item)) {
569 dstx += 4 * item->start_in_dw;
570 dst = (struct pipe_resource *)pool->bo;
571 } else {
572 if (item->real_buffer == NULL) {
573 item->real_buffer =
574 r600_compute_buffer_alloc_vram(pool->screen,
575 item->size_in_dw * 4);
576 }
577 dst = (struct pipe_resource*)item->real_buffer;
578 }
579 }
580
581 r600_copy_buffer(ctx, dst, dstx, src, &new_src_box);
582 }
583
584 static void r600_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst,
585 unsigned offset, unsigned size, unsigned value,
586 bool is_framebuffer)
587 {
588 struct r600_context *rctx = (struct r600_context*)ctx;
589
590 if (rctx->screen->b.has_cp_dma &&
591 rctx->b.chip_class >= EVERGREEN &&
592 offset % 4 == 0 && size % 4 == 0) {
593 evergreen_cp_dma_clear_buffer(rctx, dst, offset, size, value);
594 } else if (rctx->screen->b.has_streamout && offset % 4 == 0 && size % 4 == 0) {
595 union pipe_color_union clear_value;
596 clear_value.ui[0] = value;
597
598 r600_blitter_begin(ctx, R600_DISABLE_RENDER_COND);
599 util_blitter_clear_buffer(rctx->blitter, dst, offset, size,
600 1, &clear_value);
601 r600_blitter_end(ctx);
602 } else {
603 uint32_t *map = r600_buffer_map_sync_with_rings(&rctx->b, r600_resource(dst),
604 PIPE_TRANSFER_WRITE);
605 map += offset / 4;
606 size /= 4;
607 for (unsigned i = 0; i < size; i++)
608 *map++ = value;
609 }
610 }
611
612 void r600_resource_copy_region(struct pipe_context *ctx,
613 struct pipe_resource *dst,
614 unsigned dst_level,
615 unsigned dstx, unsigned dsty, unsigned dstz,
616 struct pipe_resource *src,
617 unsigned src_level,
618 const struct pipe_box *src_box)
619 {
620 struct r600_context *rctx = (struct r600_context *)ctx;
621 struct pipe_surface *dst_view, dst_templ;
622 struct pipe_sampler_view src_templ, *src_view;
623 unsigned dst_width, dst_height, src_width0, src_height0, src_widthFL, src_heightFL;
624 unsigned src_force_level = 0;
625 struct pipe_box sbox, dstbox;
626
627 /* Handle buffers first. */
628 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
629 if ((src->bind & PIPE_BIND_GLOBAL) ||
630 (dst->bind & PIPE_BIND_GLOBAL)) {
631 r600_copy_global_buffer(ctx, dst, dstx, src, src_box);
632 } else {
633 r600_copy_buffer(ctx, dst, dstx, src, src_box);
634 }
635 return;
636 }
637
638 assert(u_max_sample(dst) == u_max_sample(src));
639
640 /* The driver doesn't decompress resources automatically while
641 * u_blitter is rendering. */
642 if (!r600_decompress_subresource(ctx, src, src_level,
643 src_box->z, src_box->z + src_box->depth - 1)) {
644 return; /* error */
645 }
646
647 dst_width = u_minify(dst->width0, dst_level);
648 dst_height = u_minify(dst->height0, dst_level);
649 src_width0 = src->width0;
650 src_height0 = src->height0;
651 src_widthFL = u_minify(src->width0, src_level);
652 src_heightFL = u_minify(src->height0, src_level);
653
654 util_blitter_default_dst_texture(&dst_templ, dst, dst_level, dstz);
655 util_blitter_default_src_texture(&src_templ, src, src_level);
656
657 if (util_format_is_compressed(src->format)) {
658 unsigned blocksize = util_format_get_blocksize(src->format);
659
660 if (blocksize == 8)
661 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT; /* 64-bit block */
662 else
663 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT; /* 128-bit block */
664 dst_templ.format = src_templ.format;
665
666 dst_width = util_format_get_nblocksx(dst->format, dst_width);
667 dst_height = util_format_get_nblocksy(dst->format, dst_height);
668 src_width0 = util_format_get_nblocksx(src->format, src_width0);
669 src_height0 = util_format_get_nblocksy(src->format, src_height0);
670 src_widthFL = util_format_get_nblocksx(src->format, src_widthFL);
671 src_heightFL = util_format_get_nblocksy(src->format, src_heightFL);
672
673 dstx = util_format_get_nblocksx(dst->format, dstx);
674 dsty = util_format_get_nblocksy(dst->format, dsty);
675
676 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
677 sbox.y = util_format_get_nblocksy(src->format, src_box->y);
678 sbox.z = src_box->z;
679 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
680 sbox.height = util_format_get_nblocksy(src->format, src_box->height);
681 sbox.depth = src_box->depth;
682 src_box = &sbox;
683
684 src_force_level = src_level;
685 } else if (!util_blitter_is_copy_supported(rctx->blitter, dst, src)) {
686 if (util_format_is_subsampled_422(src->format)) {
687
688 src_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
689 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
690
691 dst_width = util_format_get_nblocksx(dst->format, dst_width);
692 src_width0 = util_format_get_nblocksx(src->format, src_width0);
693 src_widthFL = util_format_get_nblocksx(src->format, src_widthFL);
694
695 dstx = util_format_get_nblocksx(dst->format, dstx);
696
697 sbox = *src_box;
698 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
699 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
700 src_box = &sbox;
701 } else {
702 unsigned blocksize = util_format_get_blocksize(src->format);
703
704 switch (blocksize) {
705 case 1:
706 dst_templ.format = PIPE_FORMAT_R8_UNORM;
707 src_templ.format = PIPE_FORMAT_R8_UNORM;
708 break;
709 case 2:
710 dst_templ.format = PIPE_FORMAT_R8G8_UNORM;
711 src_templ.format = PIPE_FORMAT_R8G8_UNORM;
712 break;
713 case 4:
714 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
715 src_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
716 break;
717 case 8:
718 dst_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
719 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
720 break;
721 case 16:
722 dst_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
723 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
724 break;
725 default:
726 fprintf(stderr, "Unhandled format %s with blocksize %u\n",
727 util_format_short_name(src->format), blocksize);
728 assert(0);
729 }
730 }
731 }
732
733 dst_view = r600_create_surface_custom(ctx, dst, &dst_templ, dst_width, dst_height);
734
735 if (rctx->b.chip_class >= EVERGREEN) {
736 src_view = evergreen_create_sampler_view_custom(ctx, src, &src_templ,
737 src_width0, src_height0,
738 src_force_level);
739 } else {
740 src_view = r600_create_sampler_view_custom(ctx, src, &src_templ,
741 src_widthFL, src_heightFL);
742 }
743
744 u_box_3d(dstx, dsty, dstz, abs(src_box->width), abs(src_box->height),
745 abs(src_box->depth), &dstbox);
746
747 /* Copy. */
748 r600_blitter_begin(ctx, R600_COPY_TEXTURE);
749 util_blitter_blit_generic(rctx->blitter, dst_view, &dstbox,
750 src_view, src_box, src_width0, src_height0,
751 PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL,
752 FALSE);
753 r600_blitter_end(ctx);
754
755 pipe_surface_reference(&dst_view, NULL);
756 pipe_sampler_view_reference(&src_view, NULL);
757 }
758
759 /* For MSAA integer resolving to work, we change the format to NORM using this function. */
760 static enum pipe_format int_to_norm_format(enum pipe_format format)
761 {
762 switch (format) {
763 #define REPLACE_FORMAT_SIGN(format,sign) \
764 case PIPE_FORMAT_##format##_##sign##INT: \
765 return PIPE_FORMAT_##format##_##sign##NORM
766 #define REPLACE_FORMAT(format) \
767 REPLACE_FORMAT_SIGN(format, U); \
768 REPLACE_FORMAT_SIGN(format, S)
769
770 REPLACE_FORMAT_SIGN(B10G10R10A2, U);
771 REPLACE_FORMAT(R8);
772 REPLACE_FORMAT(R8G8);
773 REPLACE_FORMAT(R8G8B8X8);
774 REPLACE_FORMAT(R8G8B8A8);
775 REPLACE_FORMAT(A8);
776 REPLACE_FORMAT(I8);
777 REPLACE_FORMAT(L8);
778 REPLACE_FORMAT(L8A8);
779 REPLACE_FORMAT(R16);
780 REPLACE_FORMAT(R16G16);
781 REPLACE_FORMAT(R16G16B16X16);
782 REPLACE_FORMAT(R16G16B16A16);
783 REPLACE_FORMAT(A16);
784 REPLACE_FORMAT(I16);
785 REPLACE_FORMAT(L16);
786 REPLACE_FORMAT(L16A16);
787
788 #undef REPLACE_FORMAT
789 #undef REPLACE_FORMAT_SIGN
790 default:
791 return format;
792 }
793 }
794
795 static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
796 const struct pipe_blit_info *info)
797 {
798 struct r600_context *rctx = (struct r600_context*)ctx;
799 struct r600_texture *dst = (struct r600_texture*)info->dst.resource;
800 unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level);
801 unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level);
802 enum pipe_format format = int_to_norm_format(info->dst.format);
803 unsigned sample_mask =
804 rctx->b.chip_class == CAYMAN ? ~0 :
805 ((1ull << MAX2(1, info->src.resource->nr_samples)) - 1);
806
807 if (info->src.resource->nr_samples > 1 &&
808 info->dst.resource->nr_samples <= 1 &&
809 util_max_layer(info->src.resource, 0) == 0 &&
810 util_max_layer(info->dst.resource, info->dst.level) == 0 &&
811 info->dst.format == info->src.format &&
812 !util_format_is_pure_integer(format) &&
813 !util_format_is_depth_or_stencil(format) &&
814 !info->scissor_enable &&
815 (info->mask & PIPE_MASK_RGBA) == PIPE_MASK_RGBA &&
816 dst_width == info->src.resource->width0 &&
817 dst_height == info->src.resource->height0 &&
818 info->dst.box.x == 0 &&
819 info->dst.box.y == 0 &&
820 info->dst.box.width == dst_width &&
821 info->dst.box.height == dst_height &&
822 info->dst.box.depth == 1 &&
823 info->src.box.x == 0 &&
824 info->src.box.y == 0 &&
825 info->src.box.width == dst_width &&
826 info->src.box.height == dst_height &&
827 info->src.box.depth == 1 &&
828 dst->surface.level[info->dst.level].mode >= RADEON_SURF_MODE_1D &&
829 (!dst->cmask.size || !dst->dirty_level_mask) /* dst cannot be fast-cleared */) {
830 r600_blitter_begin(ctx, R600_COLOR_RESOLVE |
831 (info->render_condition_enable ? 0 : R600_DISABLE_RENDER_COND));
832 util_blitter_custom_resolve_color(rctx->blitter,
833 info->dst.resource, info->dst.level,
834 info->dst.box.z,
835 info->src.resource, info->src.box.z,
836 sample_mask, rctx->custom_blend_resolve,
837 format);
838 r600_blitter_end(ctx);
839 return true;
840 }
841 return false;
842 }
843
844 static void r600_blit(struct pipe_context *ctx,
845 const struct pipe_blit_info *info)
846 {
847 struct r600_context *rctx = (struct r600_context*)ctx;
848
849 if (do_hardware_msaa_resolve(ctx, info)) {
850 return;
851 }
852
853 assert(util_blitter_is_blit_supported(rctx->blitter, info));
854
855 /* The driver doesn't decompress resources automatically while
856 * u_blitter is rendering. */
857 if (!r600_decompress_subresource(ctx, info->src.resource, info->src.level,
858 info->src.box.z,
859 info->src.box.z + info->src.box.depth - 1)) {
860 return; /* error */
861 }
862
863 if (rctx->screen->b.debug_flags & DBG_FORCE_DMA &&
864 util_try_blit_via_copy_region(ctx, info))
865 return;
866
867 r600_blitter_begin(ctx, R600_BLIT |
868 (info->render_condition_enable ? 0 : R600_DISABLE_RENDER_COND));
869 util_blitter_blit(rctx->blitter, info);
870 r600_blitter_end(ctx);
871 }
872
873 static void r600_flush_resource(struct pipe_context *ctx,
874 struct pipe_resource *res)
875 {
876 struct r600_texture *rtex = (struct r600_texture*)res;
877
878 assert(res->target != PIPE_BUFFER);
879
880 if (!rtex->is_depth && rtex->cmask.size) {
881 r600_blit_decompress_color(ctx, rtex, 0, res->last_level,
882 0, util_max_layer(res, 0));
883 }
884 }
885
886 void r600_init_blit_functions(struct r600_context *rctx)
887 {
888 rctx->b.b.clear = r600_clear;
889 rctx->b.b.clear_render_target = r600_clear_render_target;
890 rctx->b.b.clear_depth_stencil = r600_clear_depth_stencil;
891 rctx->b.b.resource_copy_region = r600_resource_copy_region;
892 rctx->b.b.blit = r600_blit;
893 rctx->b.b.flush_resource = r600_flush_resource;
894 rctx->b.clear_buffer = r600_clear_buffer;
895 rctx->b.blit_decompress_depth = r600_blit_decompress_depth;
896 }