2 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include <pipe/p_screen.h>
29 #include <util/u_blitter.h>
30 #include <util/u_inlines.h>
31 #include <util/u_memory.h>
32 #include "util/u_surface.h"
33 #include "r600_screen.h"
34 #include "r600_context.h"
37 static void r600_blitter_save_states(struct pipe_context
*ctx
)
39 struct r600_context
*rctx
= r600_context(ctx
);
41 util_blitter_save_blend(rctx
->blitter
, rctx
->blend
);
42 util_blitter_save_depth_stencil_alpha(rctx
->blitter
, rctx
->dsa
);
43 if (rctx
->stencil_ref
) {
44 util_blitter_save_stencil_ref(rctx
->blitter
,
45 &rctx
->stencil_ref
->state
.stencil_ref
);
47 util_blitter_save_rasterizer(rctx
->blitter
, rctx
->rasterizer
);
48 util_blitter_save_fragment_shader(rctx
->blitter
, rctx
->ps_shader
);
49 util_blitter_save_vertex_shader(rctx
->blitter
, rctx
->vs_shader
);
50 util_blitter_save_vertex_elements(rctx
->blitter
, rctx
->vertex_elements
);
52 util_blitter_save_viewport(rctx
->blitter
, &rctx
->viewport
->state
.viewport
);
55 util_blitter_save_clip(rctx
->blitter
, &rctx
->clip
->state
.clip
);
57 util_blitter_save_vertex_buffers(rctx
->blitter
, rctx
->nvertex_buffer
,
60 /* remove ptr so they don't get deleted */
63 rctx
->vs_shader
= NULL
;
64 rctx
->ps_shader
= NULL
;
65 rctx
->rasterizer
= NULL
;
67 rctx
->vertex_elements
= NULL
;
70 r600_queries_suspend(ctx
);
73 static void r600_clear(struct pipe_context
*ctx
, unsigned buffers
,
74 const float *rgba
, double depth
, unsigned stencil
)
76 struct r600_context
*rctx
= r600_context(ctx
);
77 struct pipe_framebuffer_state
*fb
= &rctx
->framebuffer
->state
.framebuffer
;
79 r600_blitter_save_states(ctx
);
80 util_blitter_clear(rctx
->blitter
, fb
->width
, fb
->height
,
81 fb
->nr_cbufs
, buffers
, rgba
, depth
,
84 r600_queries_resume(ctx
);
87 static void r600_clear_render_target(struct pipe_context
*ctx
,
88 struct pipe_surface
*dst
,
90 unsigned dstx
, unsigned dsty
,
91 unsigned width
, unsigned height
)
93 struct r600_context
*rctx
= r600_context(ctx
);
94 struct pipe_framebuffer_state
*fb
= &rctx
->framebuffer
->state
.framebuffer
;
96 r600_blitter_save_states(ctx
);
97 util_blitter_save_framebuffer(rctx
->blitter
, fb
);
99 util_blitter_clear_render_target(rctx
->blitter
, dst
, rgba
,
100 dstx
, dsty
, width
, height
);
102 r600_queries_resume(ctx
);
105 static void r600_clear_depth_stencil(struct pipe_context
*ctx
,
106 struct pipe_surface
*dst
,
107 unsigned clear_flags
,
110 unsigned dstx
, unsigned dsty
,
111 unsigned width
, unsigned height
)
113 struct r600_context
*rctx
= r600_context(ctx
);
114 struct pipe_framebuffer_state
*fb
= &rctx
->framebuffer
->state
.framebuffer
;
116 r600_blitter_save_states(ctx
);
117 util_blitter_save_framebuffer(rctx
->blitter
, fb
);
119 util_blitter_clear_depth_stencil(rctx
->blitter
, dst
, clear_flags
, depth
, stencil
,
120 dstx
, dsty
, width
, height
);
122 r600_queries_resume(ctx
);
126 static void r600_resource_copy_region(struct pipe_context
*ctx
,
127 struct pipe_resource
*dst
,
128 struct pipe_subresource subdst
,
129 unsigned dstx
, unsigned dsty
, unsigned dstz
,
130 struct pipe_resource
*src
,
131 struct pipe_subresource subsrc
,
132 unsigned srcx
, unsigned srcy
, unsigned srcz
,
133 unsigned width
, unsigned height
)
135 util_resource_copy_region(ctx
, dst
, subdst
, dstx
, dsty
, dstz
,
136 src
, subsrc
, srcx
, srcy
, srcz
, width
, height
);
139 void r600_init_blit_functions(struct r600_context
*rctx
)
141 rctx
->context
.clear
= r600_clear
;
142 rctx
->context
.clear_render_target
= r600_clear_render_target
;
143 rctx
->context
.clear_depth_stencil
= r600_clear_depth_stencil
;
144 rctx
->context
.resource_copy_region
= r600_resource_copy_region
;
148 struct r600_blit_states
{
149 struct radeon_state rasterizer
;
150 struct radeon_state dsa
;
151 struct radeon_state blend
;
152 struct radeon_state cb_cntl
;
153 struct radeon_state vgt
;
154 struct radeon_state draw
;
155 struct radeon_state vs_constant0
;
156 struct radeon_state vs_constant1
;
157 struct radeon_state vs_constant2
;
158 struct radeon_state vs_constant3
;
159 struct radeon_state ps_shader
;
160 struct radeon_state vs_shader
;
161 struct radeon_state vs_resource0
;
162 struct radeon_state vs_resource1
;
165 static int r600_blit_state_vs_resources(struct r600_screen
*rscreen
, struct r600_blit_states
*bstates
)
167 struct radeon_state
*rstate
;
168 struct radeon_bo
*bo
;
170 0xBF800000, 0xBF800000, 0x3F800000, 0x3F800000,
171 0x3F000000, 0x3F000000, 0x3F000000, 0x00000000,
172 0x3F800000, 0xBF800000, 0x3F800000, 0x3F800000,
173 0x3F000000, 0x3F000000, 0x3F000000, 0x00000000,
174 0x3F800000, 0x3F800000, 0x3F800000, 0x3F800000,
175 0x3F000000, 0x3F000000, 0x3F000000, 0x00000000,
176 0xBF800000, 0x3F800000, 0x3F800000, 0x3F800000,
177 0x3F000000, 0x3F000000, 0x3F000000, 0x00000000
181 bo
= radeon_bo(rscreen
->rw
, 0, 128, 4096, NULL
);
185 if (radeon_bo_map(rscreen
->rw
, bo
)) {
186 radeon_bo_decref(rscreen
->rw
, bo
);
189 memcpy(bo
->data
, vbo
, 128);
190 radeon_bo_unmap(rscreen
->rw
, bo
);
192 rstate
= &bstates
->vs_resource0
;
193 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_RESOURCE
, 0, R600_SHADER_VS
);
195 /* set states (most default value are 0 and struct already
196 * initialized to 0, thus avoid resetting them)
198 rstate
->states
[R600_VS_RESOURCE__RESOURCE160_WORD0
] = 0x00000000;
199 rstate
->states
[R600_VS_RESOURCE__RESOURCE160_WORD1
] = 0x00000080;
200 rstate
->states
[R600_VS_RESOURCE__RESOURCE160_WORD2
] = 0x02302000;
201 rstate
->states
[R600_VS_RESOURCE__RESOURCE160_WORD3
] = 0x00000000;
202 rstate
->states
[R600_VS_RESOURCE__RESOURCE160_WORD4
] = 0x00000000;
203 rstate
->states
[R600_VS_RESOURCE__RESOURCE160_WORD5
] = 0x00000000;
204 rstate
->states
[R600_VS_RESOURCE__RESOURCE160_WORD6
] = 0xC0000000;
207 rstate
->placement
[0] = RADEON_GEM_DOMAIN_GTT
;
208 if (radeon_state_pm4(rstate
)) {
209 radeon_state_fini(rstate
);
213 rstate
= &bstates
->vs_resource1
;
214 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_RESOURCE
, 1, R600_SHADER_VS
);
215 rstate
->states
[R600_VS_RESOURCE__RESOURCE160_WORD0
] = 0x00000010;
216 rstate
->states
[R600_VS_RESOURCE__RESOURCE160_WORD1
] = 0x00000070;
217 rstate
->states
[R600_VS_RESOURCE__RESOURCE160_WORD2
] = 0x02302000;
218 rstate
->states
[R600_VS_RESOURCE__RESOURCE160_WORD3
] = 0x00000000;
219 rstate
->states
[R600_VS_RESOURCE__RESOURCE160_WORD4
] = 0x00000000;
220 rstate
->states
[R600_VS_RESOURCE__RESOURCE160_WORD5
] = 0x00000000;
221 rstate
->states
[R600_VS_RESOURCE__RESOURCE160_WORD6
] = 0xC0000000;
222 rstate
->bo
[0] = radeon_bo_incref(rscreen
->rw
, bo
);
224 rstate
->placement
[0] = RADEON_GEM_DOMAIN_GTT
;
225 if (radeon_state_pm4(rstate
)) {
226 radeon_state_fini(rstate
);
233 static void r600_blit_state_vs_shader(struct r600_screen
*rscreen
, struct radeon_state
*rstate
)
235 struct radeon_bo
*bo
;
236 u32 shader_bc_r600
[] = {
237 0x00000004, 0x81000400,
238 0x00000008, 0xA01C0000,
239 0xC001A03C, 0x94000688,
240 0xC0024000, 0x94200688,
241 0x7C000000, 0x002D1001,
242 0x00080000, 0x00000000,
243 0x7C000100, 0x002D1002,
244 0x00080000, 0x00000000,
245 0x00000001, 0x00601910,
246 0x00000401, 0x20601910,
247 0x00000801, 0x40601910,
248 0x80000C01, 0x60601910,
249 0x00000002, 0x00801910,
250 0x00000402, 0x20801910,
251 0x00000802, 0x40801910,
252 0x80000C02, 0x60801910
254 u32 shader_bc_r700
[] = {
255 0x00000004, 0x81000400,
256 0x00000008, 0xA01C0000,
257 0xC001A03C, 0x94000688,
258 0xC0024000, 0x94200688,
259 0x7C000000, 0x002D1001,
260 0x00080000, 0x00000000,
261 0x7C000100, 0x002D1002,
262 0x00080000, 0x00000000,
263 0x00000001, 0x00600C90,
264 0x00000401, 0x20600C90,
265 0x00000801, 0x40600C90,
266 0x80000C01, 0x60600C90,
267 0x00000002, 0x00800C90,
268 0x00000402, 0x20800C90,
269 0x00000802, 0x40800C90,
270 0x80000C02, 0x60800C90
274 bo
= radeon_bo(rscreen
->rw
, 0, 128, 4096, NULL
);
278 if (radeon_bo_map(rscreen
->rw
, bo
)) {
279 radeon_bo_decref(rscreen
->rw
, bo
);
282 switch (rscreen
->chip_class
) {
284 memcpy(bo
->data
, shader_bc_r600
, 128);
287 memcpy(bo
->data
, shader_bc_r700
, 128);
290 R600_ERR("unsupported chip family\n");
291 radeon_bo_unmap(rscreen
->rw
, bo
);
292 radeon_bo_decref(rscreen
->rw
, bo
);
295 radeon_bo_unmap(rscreen
->rw
, bo
);
297 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_SHADER
, 0, R600_SHADER_VS
);
299 /* set states (most default value are 0 and struct already
300 * initialized to 0, thus avoid resetting them)
302 rstate
->states
[R600_VS_SHADER__SPI_VS_OUT_ID_0
] = 0x03020100;
303 rstate
->states
[R600_VS_SHADER__SPI_VS_OUT_ID_1
] = 0x07060504;
304 rstate
->states
[R600_VS_SHADER__SQ_PGM_RESOURCES_VS
] = 0x00000005;
307 rstate
->bo
[1] = radeon_bo_incref(rscreen
->rw
, bo
);
309 rstate
->placement
[0] = RADEON_GEM_DOMAIN_GTT
;
310 rstate
->placement
[2] = RADEON_GEM_DOMAIN_GTT
;
312 radeon_state_pm4(rstate
);
315 static void r600_blit_state_ps_shader(struct r600_screen
*rscreen
, struct radeon_state
*rstate
)
317 struct radeon_bo
*bo
;
318 u32 shader_bc_r600
[] = {
319 0x00000002, 0xA00C0000,
320 0xC0008000, 0x94200688,
321 0x00000000, 0x00201910,
322 0x00000400, 0x20201910,
323 0x00000800, 0x40201910,
324 0x80000C00, 0x60201910
326 u32 shader_bc_r700
[] = {
327 0x00000002, 0xA00C0000,
328 0xC0008000, 0x94200688,
329 0x00000000, 0x00200C90,
330 0x00000400, 0x20200C90,
331 0x00000800, 0x40200C90,
332 0x80000C00, 0x60200C90
336 bo
= radeon_bo(rscreen
->rw
, 0, 128, 4096, NULL
);
338 radeon_bo_decref(rscreen
->rw
, bo
);
341 if (radeon_bo_map(rscreen
->rw
, bo
)) {
344 switch (rscreen
->chip_class
) {
346 memcpy(bo
->data
, shader_bc_r600
, 48);
349 memcpy(bo
->data
, shader_bc_r700
, 48);
352 R600_ERR("unsupported chip family\n");
353 radeon_bo_unmap(rscreen
->rw
, bo
);
354 radeon_bo_decref(rscreen
->rw
, bo
);
357 radeon_bo_unmap(rscreen
->rw
, bo
);
359 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_SHADER
, 0, R600_SHADER_PS
);
361 /* set states (most default value are 0 and struct already
362 * initialized to 0, thus avoid resetting them)
364 rstate
->states
[R600_PS_SHADER__SPI_PS_INPUT_CNTL_0
] = 0x00000C00;
365 rstate
->states
[R600_PS_SHADER__SPI_PS_IN_CONTROL_0
] = 0x10000001;
366 rstate
->states
[R600_PS_SHADER__SQ_PGM_EXPORTS_PS
] = 0x00000002;
367 rstate
->states
[R600_PS_SHADER__SQ_PGM_RESOURCES_PS
] = 0x00000002;
371 rstate
->placement
[0] = RADEON_GEM_DOMAIN_GTT
;
373 radeon_state_pm4(rstate
);
376 static void r600_blit_state_vgt(struct r600_screen
*rscreen
, struct radeon_state
*rstate
)
378 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_VGT
, 0, 0);
380 /* set states (most default value are 0 and struct already
381 * initialized to 0, thus avoid resetting them)
383 rstate
->states
[R600_VGT__VGT_DMA_NUM_INSTANCES
] = 0x00000001;
384 rstate
->states
[R600_VGT__VGT_MAX_VTX_INDX
] = 0x00FFFFFF;
385 rstate
->states
[R600_VGT__VGT_PRIMITIVE_TYPE
] = 0x00000005;
387 radeon_state_pm4(rstate
);
390 static void r600_blit_state_draw(struct r600_screen
*rscreen
, struct radeon_state
*rstate
)
392 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_DRAW
, 0, 0);
394 /* set states (most default value are 0 and struct already
395 * initialized to 0, thus avoid resetting them)
397 rstate
->states
[R600_DRAW__VGT_DRAW_INITIATOR
] = 0x00000002;
398 rstate
->states
[R600_DRAW__VGT_NUM_INDICES
] = 0x00000004;
400 radeon_state_pm4(rstate
);
403 static void r600_blit_state_vs_constant(struct r600_screen
*rscreen
, struct radeon_state
*rstate
,
404 unsigned id
, float c0
, float c1
, float c2
, float c3
)
406 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_CONSTANT
, id
, R600_SHADER_VS
);
408 /* set states (most default value are 0 and struct already
409 * initialized to 0, thus avoid resetting them)
411 rstate
->states
[R600_VS_CONSTANT__SQ_ALU_CONSTANT0_256
] = fui(c0
);
412 rstate
->states
[R600_VS_CONSTANT__SQ_ALU_CONSTANT1_256
] = fui(c1
);
413 rstate
->states
[R600_VS_CONSTANT__SQ_ALU_CONSTANT2_256
] = fui(c2
);
414 rstate
->states
[R600_VS_CONSTANT__SQ_ALU_CONSTANT3_256
] = fui(c3
);
416 radeon_state_pm4(rstate
);
419 static void r600_blit_state_rasterizer(struct r600_screen
*rscreen
, struct radeon_state
*rstate
)
421 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_RASTERIZER
, 0, 0);
423 /* set states (most default value are 0 and struct already
424 * initialized to 0, thus avoid resetting them)
426 rstate
->states
[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ
] = 0x3F800000;
427 rstate
->states
[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ
] = 0x3F800000;
428 rstate
->states
[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ
] = 0x3F800000;
429 rstate
->states
[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ
] = 0x3F800000;
430 rstate
->states
[R600_RASTERIZER__PA_SC_LINE_CNTL
] = 0x00000400;
431 rstate
->states
[R600_RASTERIZER__PA_SC_LINE_STIPPLE
] = 0x00000005;
432 rstate
->states
[R600_RASTERIZER__PA_SU_LINE_CNTL
] = 0x00000008;
433 rstate
->states
[R600_RASTERIZER__PA_SU_POINT_MINMAX
] = 0x80000000;
434 rstate
->states
[R600_RASTERIZER__PA_SU_SC_MODE_CNTL
] = 0x00080004;
435 rstate
->states
[R600_RASTERIZER__SPI_INTERP_CONTROL_0
] = 0x00000001;
437 radeon_state_pm4(rstate
);
440 static void r600_blit_state_dsa(struct r600_screen
*rscreen
, struct radeon_state
*rstate
)
442 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_DSA
, 0, 0);
444 /* set states (most default value are 0 and struct already
445 * initialized to 0, thus avoid resetting them)
447 rstate
->states
[R600_DSA__DB_ALPHA_TO_MASK
] = 0x0000AA00;
448 rstate
->states
[R600_DSA__DB_DEPTH_CLEAR
] = 0x3F800000;
449 rstate
->states
[R600_DSA__DB_RENDER_CONTROL
] = 0x00000060;
450 rstate
->states
[R600_DSA__DB_RENDER_OVERRIDE
] = 0x0000002A;
451 rstate
->states
[R600_DSA__DB_SHADER_CONTROL
] = 0x00000210;
453 radeon_state_pm4(rstate
);
456 static void r600_blit_state_blend(struct r600_screen
*rscreen
, struct radeon_state
*rstate
)
458 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_BLEND
, 0, 0);
459 radeon_state_pm4(rstate
);
462 static void r600_blit_state_cb_cntl(struct r600_screen
*rscreen
, struct radeon_state
*rstate
)
464 radeon_state_init(rstate
, rscreen
->rw
, R600_STATE_CB_CNTL
, 0, 0);
465 rstate
->states
[R600_CB_CNTL__CB_CLRCMP_CONTROL
] = 0x01000000;
466 rstate
->states
[R600_CB_CNTL__CB_CLRCMP_DST
] = 0x000000FF;
467 rstate
->states
[R600_CB_CNTL__CB_CLRCMP_MSK
] = 0xFFFFFFFF;
468 rstate
->states
[R600_CB_CNTL__CB_COLOR_CONTROL
] = 0x00CC0080;
469 rstate
->states
[R600_CB_CNTL__CB_SHADER_MASK
] = 0x0000000F;
470 rstate
->states
[R600_CB_CNTL__CB_TARGET_MASK
] = 0x0000000F;
471 rstate
->states
[R600_CB_CNTL__PA_SC_AA_MASK
] = 0xFFFFFFFF;
472 radeon_state_pm4(rstate
);
475 static int r600_blit_states_init(struct pipe_context
*ctx
, struct r600_blit_states
*bstates
)
477 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
479 r600_blit_state_ps_shader(rscreen
, &bstates
->ps_shader
);
480 r600_blit_state_vs_shader(rscreen
, &bstates
->vs_shader
);
481 r600_blit_state_vgt(rscreen
, &bstates
->vgt
);
482 r600_blit_state_draw(rscreen
, &bstates
->draw
);
483 r600_blit_state_vs_constant(rscreen
, &bstates
->vs_constant0
, 0, 1.0, 0.0, 0.0, 0.0);
484 r600_blit_state_vs_constant(rscreen
, &bstates
->vs_constant1
, 1, 0.0, 1.0, 0.0, 0.0);
485 r600_blit_state_vs_constant(rscreen
, &bstates
->vs_constant2
, 2, 0.0, 0.0, -0.00199900055, 0.0);
486 r600_blit_state_vs_constant(rscreen
, &bstates
->vs_constant3
, 3, 0.0, 0.0, -0.99900049, 1.0);
487 r600_blit_state_rasterizer(rscreen
, &bstates
->rasterizer
);
488 r600_blit_state_dsa(rscreen
, &bstates
->dsa
);
489 r600_blit_state_blend(rscreen
, &bstates
->blend
);
490 r600_blit_state_cb_cntl(rscreen
, &bstates
->cb_cntl
);
491 r600_blit_state_vs_resources(rscreen
, bstates
);
495 static void r600_blit_states_destroy(struct pipe_context
*ctx
, struct r600_blit_states
*bstates
)
497 radeon_state_fini(&bstates
->ps_shader
);
498 radeon_state_fini(&bstates
->vs_shader
);
499 radeon_state_fini(&bstates
->vs_resource0
);
500 radeon_state_fini(&bstates
->vs_resource1
);
503 int r600_blit_uncompress_depth(struct pipe_context
*ctx
, struct r600_resource_texture
*rtexture
, unsigned level
)
505 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
506 struct r600_context
*rctx
= r600_context(ctx
);
507 struct radeon_draw draw
;
508 struct r600_blit_states bstates
;
511 r
= r600_texture_scissor(ctx
, rtexture
, level
);
515 r
= r600_texture_cb(ctx
, rtexture
, 0, level
);
519 r
= r600_texture_db(ctx
, rtexture
, level
);
523 r
= r600_texture_viewport(ctx
, rtexture
, level
);
528 r
= r600_blit_states_init(ctx
, &bstates
);
532 bstates
.dsa
.states
[R600_DSA__DB_RENDER_CONTROL
] = 0x0000008C;
533 bstates
.cb_cntl
.states
[R600_CB_CNTL__CB_TARGET_MASK
] = 0x00000001;
535 bstates
.dsa
.cpm4
= bstates
.cb_cntl
.cpm4
= 0;
536 if (radeon_state_pm4(&bstates
.dsa
)) {
539 if (radeon_state_pm4(&bstates
.cb_cntl
)) {
543 r
= radeon_draw_init(&draw
, rscreen
->rw
);
545 R600_ERR("failed creating draw for uncompressing textures\n");
549 radeon_draw_bind(&draw
, &bstates
.vs_shader
);
550 radeon_draw_bind(&draw
, &bstates
.ps_shader
);
551 radeon_draw_bind(&draw
, &bstates
.rasterizer
);
552 radeon_draw_bind(&draw
, &bstates
.dsa
);
553 radeon_draw_bind(&draw
, &bstates
.blend
);
554 radeon_draw_bind(&draw
, &bstates
.cb_cntl
);
555 radeon_draw_bind(&draw
, &rctx
->config
);
556 radeon_draw_bind(&draw
, &bstates
.vgt
);
557 radeon_draw_bind(&draw
, &bstates
.draw
);
558 radeon_draw_bind(&draw
, &bstates
.vs_resource0
);
559 radeon_draw_bind(&draw
, &bstates
.vs_resource1
);
560 radeon_draw_bind(&draw
, &bstates
.vs_constant0
);
561 radeon_draw_bind(&draw
, &bstates
.vs_constant1
);
562 radeon_draw_bind(&draw
, &bstates
.vs_constant2
);
563 radeon_draw_bind(&draw
, &bstates
.vs_constant3
);
564 radeon_draw_bind(&draw
, &rtexture
->viewport
[level
]);
565 radeon_draw_bind(&draw
, &rtexture
->scissor
[level
]);
566 radeon_draw_bind(&draw
, &rtexture
->cb
[0][level
]);
567 radeon_draw_bind(&draw
, &rtexture
->db
[level
]);
569 /* suspend queries */
570 r600_queries_suspend(ctx
);
573 r
= radeon_ctx_set_draw(&rctx
->ctx
, &draw
);
575 r600_flush(ctx
, 0, NULL
);
576 r
= radeon_ctx_set_draw(&rctx
->ctx
, &draw
);
583 r600_queries_resume(ctx
);
586 r600_blit_states_destroy(ctx
, &bstates
);