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Merge ../mesa into vulkan
[mesa.git] / src / gallium / drivers / r600 / r600_blit.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_pipe.h"
24 #include "compute_memory_pool.h"
25 #include "evergreen_compute.h"
26 #include "util/u_surface.h"
27 #include "util/u_format.h"
28 #include "evergreend.h"
29
30 enum r600_blitter_op /* bitmask */
31 {
32 R600_SAVE_FRAGMENT_STATE = 1,
33 R600_SAVE_TEXTURES = 2,
34 R600_SAVE_FRAMEBUFFER = 4,
35 R600_DISABLE_RENDER_COND = 8,
36
37 R600_CLEAR = R600_SAVE_FRAGMENT_STATE,
38
39 R600_CLEAR_SURFACE = R600_SAVE_FRAGMENT_STATE | R600_SAVE_FRAMEBUFFER,
40
41 R600_COPY_BUFFER = R600_DISABLE_RENDER_COND,
42
43 R600_COPY_TEXTURE = R600_SAVE_FRAGMENT_STATE | R600_SAVE_FRAMEBUFFER | R600_SAVE_TEXTURES |
44 R600_DISABLE_RENDER_COND,
45
46 R600_BLIT = R600_SAVE_FRAGMENT_STATE | R600_SAVE_FRAMEBUFFER | R600_SAVE_TEXTURES,
47
48 R600_DECOMPRESS = R600_SAVE_FRAGMENT_STATE | R600_SAVE_FRAMEBUFFER | R600_DISABLE_RENDER_COND,
49
50 R600_COLOR_RESOLVE = R600_SAVE_FRAGMENT_STATE | R600_SAVE_FRAMEBUFFER
51 };
52
53 static void r600_blitter_begin(struct pipe_context *ctx, enum r600_blitter_op op)
54 {
55 struct r600_context *rctx = (struct r600_context *)ctx;
56
57 r600_suspend_nontimer_queries(&rctx->b);
58
59 util_blitter_save_vertex_buffer_slot(rctx->blitter, rctx->vertex_buffer_state.vb);
60 util_blitter_save_vertex_elements(rctx->blitter, rctx->vertex_fetch_shader.cso);
61 util_blitter_save_vertex_shader(rctx->blitter, rctx->vs_shader);
62 util_blitter_save_geometry_shader(rctx->blitter, rctx->gs_shader);
63 util_blitter_save_tessctrl_shader(rctx->blitter, rctx->tcs_shader);
64 util_blitter_save_tesseval_shader(rctx->blitter, rctx->tes_shader);
65 util_blitter_save_so_targets(rctx->blitter, rctx->b.streamout.num_targets,
66 (struct pipe_stream_output_target**)rctx->b.streamout.targets);
67 util_blitter_save_rasterizer(rctx->blitter, rctx->rasterizer_state.cso);
68
69 if (op & R600_SAVE_FRAGMENT_STATE) {
70 util_blitter_save_viewport(rctx->blitter, &rctx->viewport.state[0]);
71 util_blitter_save_scissor(rctx->blitter, &rctx->scissor.scissor[0]);
72 util_blitter_save_fragment_shader(rctx->blitter, rctx->ps_shader);
73 util_blitter_save_blend(rctx->blitter, rctx->blend_state.cso);
74 util_blitter_save_depth_stencil_alpha(rctx->blitter, rctx->dsa_state.cso);
75 util_blitter_save_stencil_ref(rctx->blitter, &rctx->stencil_ref.pipe_state);
76 util_blitter_save_sample_mask(rctx->blitter, rctx->sample_mask.sample_mask);
77 }
78
79 if (op & R600_SAVE_FRAMEBUFFER)
80 util_blitter_save_framebuffer(rctx->blitter, &rctx->framebuffer.state);
81
82 if (op & R600_SAVE_TEXTURES) {
83 util_blitter_save_fragment_sampler_states(
84 rctx->blitter, util_last_bit(rctx->samplers[PIPE_SHADER_FRAGMENT].states.enabled_mask),
85 (void**)rctx->samplers[PIPE_SHADER_FRAGMENT].states.states);
86
87 util_blitter_save_fragment_sampler_views(
88 rctx->blitter, util_last_bit(rctx->samplers[PIPE_SHADER_FRAGMENT].views.enabled_mask),
89 (struct pipe_sampler_view**)rctx->samplers[PIPE_SHADER_FRAGMENT].views.views);
90 }
91
92 if (op & R600_DISABLE_RENDER_COND)
93 rctx->b.render_cond_force_off = true;
94 }
95
96 static void r600_blitter_end(struct pipe_context *ctx)
97 {
98 struct r600_context *rctx = (struct r600_context *)ctx;
99
100 rctx->b.render_cond_force_off = false;
101 r600_resume_nontimer_queries(&rctx->b);
102 }
103
104 static unsigned u_max_sample(struct pipe_resource *r)
105 {
106 return r->nr_samples ? r->nr_samples - 1 : 0;
107 }
108
109 static void r600_blit_decompress_depth(struct pipe_context *ctx,
110 struct r600_texture *texture,
111 struct r600_texture *staging,
112 unsigned first_level, unsigned last_level,
113 unsigned first_layer, unsigned last_layer,
114 unsigned first_sample, unsigned last_sample)
115 {
116 struct r600_context *rctx = (struct r600_context *)ctx;
117 unsigned layer, level, sample, checked_last_layer, max_layer, max_sample;
118 struct r600_texture *flushed_depth_texture = staging ?
119 staging : texture->flushed_depth_texture;
120 const struct util_format_description *desc =
121 util_format_description(texture->resource.b.b.format);
122 float depth;
123
124 if (!staging && !texture->dirty_level_mask)
125 return;
126
127 max_sample = u_max_sample(&texture->resource.b.b);
128
129 /* XXX Decompressing MSAA depth textures is broken on R6xx.
130 * There is also a hardlock if CMASK and FMASK are not present.
131 * Just skip this until we find out how to fix it. */
132 if (rctx->b.chip_class == R600 && max_sample > 0) {
133 texture->dirty_level_mask = 0;
134 return;
135 }
136
137 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
138 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
139 depth = 0.0f;
140 else
141 depth = 1.0f;
142
143 /* Enable decompression in DB_RENDER_CONTROL */
144 rctx->db_misc_state.flush_depthstencil_through_cb = true;
145 rctx->db_misc_state.copy_depth = util_format_has_depth(desc);
146 rctx->db_misc_state.copy_stencil = util_format_has_stencil(desc);
147 rctx->db_misc_state.copy_sample = first_sample;
148 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
149
150 for (level = first_level; level <= last_level; level++) {
151 if (!staging && !(texture->dirty_level_mask & (1 << level)))
152 continue;
153
154 /* The smaller the mipmap level, the less layers there are
155 * as far as 3D textures are concerned. */
156 max_layer = util_max_layer(&texture->resource.b.b, level);
157 checked_last_layer = last_layer < max_layer ? last_layer : max_layer;
158
159 for (layer = first_layer; layer <= checked_last_layer; layer++) {
160 for (sample = first_sample; sample <= last_sample; sample++) {
161 struct pipe_surface *zsurf, *cbsurf, surf_tmpl;
162
163 if (sample != rctx->db_misc_state.copy_sample) {
164 rctx->db_misc_state.copy_sample = sample;
165 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
166 }
167
168 surf_tmpl.format = texture->resource.b.b.format;
169 surf_tmpl.u.tex.level = level;
170 surf_tmpl.u.tex.first_layer = layer;
171 surf_tmpl.u.tex.last_layer = layer;
172
173 zsurf = ctx->create_surface(ctx, &texture->resource.b.b, &surf_tmpl);
174
175 surf_tmpl.format = flushed_depth_texture->resource.b.b.format;
176 cbsurf = ctx->create_surface(ctx,
177 &flushed_depth_texture->resource.b.b, &surf_tmpl);
178
179 r600_blitter_begin(ctx, R600_DECOMPRESS);
180 util_blitter_custom_depth_stencil(rctx->blitter, zsurf, cbsurf, 1 << sample,
181 rctx->custom_dsa_flush, depth);
182 r600_blitter_end(ctx);
183
184 pipe_surface_reference(&zsurf, NULL);
185 pipe_surface_reference(&cbsurf, NULL);
186 }
187 }
188
189 /* The texture will always be dirty if some layers or samples aren't flushed.
190 * I don't think this case occurs often though. */
191 if (!staging &&
192 first_layer == 0 && last_layer == max_layer &&
193 first_sample == 0 && last_sample == max_sample) {
194 texture->dirty_level_mask &= ~(1 << level);
195 }
196 }
197
198 /* reenable compression in DB_RENDER_CONTROL */
199 rctx->db_misc_state.flush_depthstencil_through_cb = false;
200 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
201 }
202
203 static void r600_blit_decompress_depth_in_place(struct r600_context *rctx,
204 struct r600_texture *texture,
205 bool is_stencil_sampler,
206 unsigned first_level, unsigned last_level,
207 unsigned first_layer, unsigned last_layer)
208 {
209 struct pipe_surface *zsurf, surf_tmpl = {{0}};
210 unsigned layer, max_layer, checked_last_layer, level;
211 unsigned *dirty_level_mask;
212
213 /* Enable decompression in DB_RENDER_CONTROL */
214 if (is_stencil_sampler) {
215 rctx->db_misc_state.flush_stencil_inplace = true;
216 dirty_level_mask = &texture->stencil_dirty_level_mask;
217 } else {
218 rctx->db_misc_state.flush_depth_inplace = true;
219 dirty_level_mask = &texture->dirty_level_mask;
220 }
221 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
222
223 surf_tmpl.format = texture->resource.b.b.format;
224
225 for (level = first_level; level <= last_level; level++) {
226 if (!(*dirty_level_mask & (1 << level)))
227 continue;
228
229 surf_tmpl.u.tex.level = level;
230
231 /* The smaller the mipmap level, the less layers there are
232 * as far as 3D textures are concerned. */
233 max_layer = util_max_layer(&texture->resource.b.b, level);
234 checked_last_layer = last_layer < max_layer ? last_layer : max_layer;
235
236 for (layer = first_layer; layer <= checked_last_layer; layer++) {
237 surf_tmpl.u.tex.first_layer = layer;
238 surf_tmpl.u.tex.last_layer = layer;
239
240 zsurf = rctx->b.b.create_surface(&rctx->b.b, &texture->resource.b.b, &surf_tmpl);
241
242 r600_blitter_begin(&rctx->b.b, R600_DECOMPRESS);
243 util_blitter_custom_depth_stencil(rctx->blitter, zsurf, NULL, ~0,
244 rctx->custom_dsa_flush, 1.0f);
245 r600_blitter_end(&rctx->b.b);
246
247 pipe_surface_reference(&zsurf, NULL);
248 }
249
250 /* The texture will always be dirty if some layers or samples aren't flushed.
251 * I don't think this case occurs often though. */
252 if (first_layer == 0 && last_layer == max_layer) {
253 *dirty_level_mask &= ~(1 << level);
254 }
255 }
256
257 /* Disable decompression in DB_RENDER_CONTROL */
258 rctx->db_misc_state.flush_depth_inplace = false;
259 rctx->db_misc_state.flush_stencil_inplace = false;
260 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
261 }
262
263 void r600_decompress_depth_textures(struct r600_context *rctx,
264 struct r600_samplerview_state *textures)
265 {
266 unsigned i;
267 unsigned depth_texture_mask = textures->compressed_depthtex_mask;
268
269 while (depth_texture_mask) {
270 struct pipe_sampler_view *view;
271 struct r600_pipe_sampler_view *rview;
272 struct r600_texture *tex;
273
274 i = u_bit_scan(&depth_texture_mask);
275
276 view = &textures->views[i]->base;
277 assert(view);
278 rview = (struct r600_pipe_sampler_view*)view;
279
280 tex = (struct r600_texture *)view->texture;
281 assert(tex->is_depth && !tex->is_flushing_texture);
282
283 if (rctx->b.chip_class >= EVERGREEN ||
284 r600_can_read_depth(tex)) {
285 r600_blit_decompress_depth_in_place(rctx, tex,
286 rview->is_stencil_sampler,
287 view->u.tex.first_level, view->u.tex.last_level,
288 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));
289 } else {
290 r600_blit_decompress_depth(&rctx->b.b, tex, NULL,
291 view->u.tex.first_level, view->u.tex.last_level,
292 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level),
293 0, u_max_sample(&tex->resource.b.b));
294 }
295 }
296 }
297
298 static void r600_blit_decompress_color(struct pipe_context *ctx,
299 struct r600_texture *rtex,
300 unsigned first_level, unsigned last_level,
301 unsigned first_layer, unsigned last_layer)
302 {
303 struct r600_context *rctx = (struct r600_context *)ctx;
304 unsigned layer, level, checked_last_layer, max_layer;
305
306 if (!rtex->dirty_level_mask)
307 return;
308
309 for (level = first_level; level <= last_level; level++) {
310 if (!(rtex->dirty_level_mask & (1 << level)))
311 continue;
312
313 /* The smaller the mipmap level, the less layers there are
314 * as far as 3D textures are concerned. */
315 max_layer = util_max_layer(&rtex->resource.b.b, level);
316 checked_last_layer = last_layer < max_layer ? last_layer : max_layer;
317
318 for (layer = first_layer; layer <= checked_last_layer; layer++) {
319 struct pipe_surface *cbsurf, surf_tmpl;
320
321 surf_tmpl.format = rtex->resource.b.b.format;
322 surf_tmpl.u.tex.level = level;
323 surf_tmpl.u.tex.first_layer = layer;
324 surf_tmpl.u.tex.last_layer = layer;
325 cbsurf = ctx->create_surface(ctx, &rtex->resource.b.b, &surf_tmpl);
326
327 r600_blitter_begin(ctx, R600_DECOMPRESS);
328 util_blitter_custom_color(rctx->blitter, cbsurf,
329 rtex->fmask.size ? rctx->custom_blend_decompress : rctx->custom_blend_fastclear);
330 r600_blitter_end(ctx);
331
332 pipe_surface_reference(&cbsurf, NULL);
333 }
334
335 /* The texture will always be dirty if some layers aren't flushed.
336 * I don't think this case occurs often though. */
337 if (first_layer == 0 && last_layer == max_layer) {
338 rtex->dirty_level_mask &= ~(1 << level);
339 }
340 }
341 }
342
343 void r600_decompress_color_textures(struct r600_context *rctx,
344 struct r600_samplerview_state *textures)
345 {
346 unsigned i;
347 unsigned mask = textures->compressed_colortex_mask;
348
349 while (mask) {
350 struct pipe_sampler_view *view;
351 struct r600_texture *tex;
352
353 i = u_bit_scan(&mask);
354
355 view = &textures->views[i]->base;
356 assert(view);
357
358 tex = (struct r600_texture *)view->texture;
359 assert(tex->cmask.size);
360
361 r600_blit_decompress_color(&rctx->b.b, tex,
362 view->u.tex.first_level, view->u.tex.last_level,
363 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));
364 }
365 }
366
367 /* Helper for decompressing a portion of a color or depth resource before
368 * blitting if any decompression is needed.
369 * The driver doesn't decompress resources automatically while u_blitter is
370 * rendering. */
371 static bool r600_decompress_subresource(struct pipe_context *ctx,
372 struct pipe_resource *tex,
373 unsigned level,
374 unsigned first_layer, unsigned last_layer)
375 {
376 struct r600_context *rctx = (struct r600_context *)ctx;
377 struct r600_texture *rtex = (struct r600_texture*)tex;
378
379 if (rtex->is_depth && !rtex->is_flushing_texture) {
380 if (rctx->b.chip_class >= EVERGREEN ||
381 r600_can_read_depth(rtex)) {
382 r600_blit_decompress_depth_in_place(rctx, rtex, false,
383 level, level,
384 first_layer, last_layer);
385 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
386 r600_blit_decompress_depth_in_place(rctx, rtex, true,
387 level, level,
388 first_layer, last_layer);
389 }
390 } else {
391 if (!r600_init_flushed_depth_texture(ctx, tex, NULL))
392 return false; /* error */
393
394 r600_blit_decompress_depth(ctx, rtex, NULL,
395 level, level,
396 first_layer, last_layer,
397 0, u_max_sample(tex));
398 }
399 } else if (rtex->cmask.size) {
400 r600_blit_decompress_color(ctx, rtex, level, level,
401 first_layer, last_layer);
402 }
403 return true;
404 }
405
406 static void r600_clear(struct pipe_context *ctx, unsigned buffers,
407 const union pipe_color_union *color,
408 double depth, unsigned stencil)
409 {
410 struct r600_context *rctx = (struct r600_context *)ctx;
411 struct pipe_framebuffer_state *fb = &rctx->framebuffer.state;
412
413 if (buffers & PIPE_CLEAR_COLOR && rctx->b.chip_class >= EVERGREEN) {
414 evergreen_do_fast_color_clear(&rctx->b, fb, &rctx->framebuffer.atom,
415 &buffers, NULL, color);
416 if (!buffers)
417 return; /* all buffers have been fast cleared */
418 }
419
420 if (buffers & PIPE_CLEAR_COLOR) {
421 int i;
422
423 /* These buffers cannot use fast clear, make sure to disable expansion. */
424 for (i = 0; i < fb->nr_cbufs; i++) {
425 struct r600_texture *tex;
426
427 /* If not clearing this buffer, skip. */
428 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
429 continue;
430
431 if (!fb->cbufs[i])
432 continue;
433
434 tex = (struct r600_texture *)fb->cbufs[i]->texture;
435 if (tex->fmask.size == 0)
436 tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
437 }
438 }
439
440 /* if hyperz enabled just clear hyperz */
441 if (fb->zsbuf && (buffers & PIPE_CLEAR_DEPTH)) {
442 struct r600_texture *rtex;
443 unsigned level = fb->zsbuf->u.tex.level;
444
445 rtex = (struct r600_texture*)fb->zsbuf->texture;
446
447 /* We can't use hyperz fast clear if each slice of a texture
448 * array are clear to different value. To simplify code just
449 * disable fast clear for texture array.
450 */
451 /* Only use htile for first level */
452 if (rtex->htile_buffer && !level &&
453 fb->zsbuf->u.tex.first_layer == 0 &&
454 fb->zsbuf->u.tex.last_layer == util_max_layer(&rtex->resource.b.b, level)) {
455 if (rtex->depth_clear_value != depth) {
456 rtex->depth_clear_value = depth;
457 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
458 }
459 rctx->db_misc_state.htile_clear = true;
460 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
461 }
462 }
463
464 r600_blitter_begin(ctx, R600_CLEAR);
465 util_blitter_clear(rctx->blitter, fb->width, fb->height,
466 util_framebuffer_get_num_layers(fb),
467 buffers, color, depth, stencil);
468 r600_blitter_end(ctx);
469
470 /* disable fast clear */
471 if (rctx->db_misc_state.htile_clear) {
472 rctx->db_misc_state.htile_clear = false;
473 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
474 }
475 }
476
477 static void r600_clear_render_target(struct pipe_context *ctx,
478 struct pipe_surface *dst,
479 const union pipe_color_union *color,
480 unsigned dstx, unsigned dsty,
481 unsigned width, unsigned height)
482 {
483 struct r600_context *rctx = (struct r600_context *)ctx;
484
485 r600_blitter_begin(ctx, R600_CLEAR_SURFACE);
486 util_blitter_clear_render_target(rctx->blitter, dst, color,
487 dstx, dsty, width, height);
488 r600_blitter_end(ctx);
489 }
490
491 static void r600_clear_depth_stencil(struct pipe_context *ctx,
492 struct pipe_surface *dst,
493 unsigned clear_flags,
494 double depth,
495 unsigned stencil,
496 unsigned dstx, unsigned dsty,
497 unsigned width, unsigned height)
498 {
499 struct r600_context *rctx = (struct r600_context *)ctx;
500
501 r600_blitter_begin(ctx, R600_CLEAR_SURFACE);
502 util_blitter_clear_depth_stencil(rctx->blitter, dst, clear_flags, depth, stencil,
503 dstx, dsty, width, height);
504 r600_blitter_end(ctx);
505 }
506
507 static void r600_copy_buffer(struct pipe_context *ctx, struct pipe_resource *dst, unsigned dstx,
508 struct pipe_resource *src, const struct pipe_box *src_box)
509 {
510 struct r600_context *rctx = (struct r600_context*)ctx;
511
512 if (rctx->screen->b.has_cp_dma) {
513 r600_cp_dma_copy_buffer(rctx, dst, dstx, src, src_box->x, src_box->width);
514 }
515 else if (rctx->screen->b.has_streamout &&
516 /* Require 4-byte alignment. */
517 dstx % 4 == 0 && src_box->x % 4 == 0 && src_box->width % 4 == 0) {
518
519 r600_blitter_begin(ctx, R600_COPY_BUFFER);
520 util_blitter_copy_buffer(rctx->blitter, dst, dstx, src, src_box->x, src_box->width);
521 r600_blitter_end(ctx);
522 } else {
523 util_resource_copy_region(ctx, dst, 0, dstx, 0, 0, src, 0, src_box);
524 }
525
526 /* The index buffer (VGT) doesn't seem to see the result of the copying.
527 * Can we somehow flush the index buffer cache? Starting a new IB seems
528 * to do the trick. */
529 if (rctx->b.chip_class <= R700)
530 rctx->b.gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
531 }
532
533 /**
534 * Global buffers are not really resources, they are are actually offsets
535 * into a single global resource (r600_screen::global_pool). The means
536 * they don't have their own buf handle, so they cannot be passed
537 * to r600_copy_buffer() and must be handled separately.
538 */
539 static void r600_copy_global_buffer(struct pipe_context *ctx,
540 struct pipe_resource *dst, unsigned
541 dstx, struct pipe_resource *src,
542 const struct pipe_box *src_box)
543 {
544 struct r600_context *rctx = (struct r600_context*)ctx;
545 struct compute_memory_pool *pool = rctx->screen->global_pool;
546 struct pipe_box new_src_box = *src_box;
547
548 if (src->bind & PIPE_BIND_GLOBAL) {
549 struct r600_resource_global *rsrc =
550 (struct r600_resource_global *)src;
551 struct compute_memory_item *item = rsrc->chunk;
552
553 if (is_item_in_pool(item)) {
554 new_src_box.x += 4 * item->start_in_dw;
555 src = (struct pipe_resource *)pool->bo;
556 } else {
557 if (item->real_buffer == NULL) {
558 item->real_buffer =
559 r600_compute_buffer_alloc_vram(pool->screen,
560 item->size_in_dw * 4);
561 }
562 src = (struct pipe_resource*)item->real_buffer;
563 }
564 }
565 if (dst->bind & PIPE_BIND_GLOBAL) {
566 struct r600_resource_global *rdst =
567 (struct r600_resource_global *)dst;
568 struct compute_memory_item *item = rdst->chunk;
569
570 if (is_item_in_pool(item)) {
571 dstx += 4 * item->start_in_dw;
572 dst = (struct pipe_resource *)pool->bo;
573 } else {
574 if (item->real_buffer == NULL) {
575 item->real_buffer =
576 r600_compute_buffer_alloc_vram(pool->screen,
577 item->size_in_dw * 4);
578 }
579 dst = (struct pipe_resource*)item->real_buffer;
580 }
581 }
582
583 r600_copy_buffer(ctx, dst, dstx, src, &new_src_box);
584 }
585
586 static void r600_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst,
587 unsigned offset, unsigned size, unsigned value,
588 bool is_framebuffer)
589 {
590 struct r600_context *rctx = (struct r600_context*)ctx;
591
592 if (rctx->screen->b.has_cp_dma &&
593 rctx->b.chip_class >= EVERGREEN &&
594 offset % 4 == 0 && size % 4 == 0) {
595 evergreen_cp_dma_clear_buffer(rctx, dst, offset, size, value);
596 } else if (rctx->screen->b.has_streamout && offset % 4 == 0 && size % 4 == 0) {
597 union pipe_color_union clear_value;
598 clear_value.ui[0] = value;
599
600 r600_blitter_begin(ctx, R600_DISABLE_RENDER_COND);
601 util_blitter_clear_buffer(rctx->blitter, dst, offset, size,
602 1, &clear_value);
603 r600_blitter_end(ctx);
604 } else {
605 uint32_t *map = r600_buffer_map_sync_with_rings(&rctx->b, r600_resource(dst),
606 PIPE_TRANSFER_WRITE);
607 map += offset / 4;
608 size /= 4;
609 for (unsigned i = 0; i < size; i++)
610 *map++ = value;
611 }
612 }
613
614 void r600_resource_copy_region(struct pipe_context *ctx,
615 struct pipe_resource *dst,
616 unsigned dst_level,
617 unsigned dstx, unsigned dsty, unsigned dstz,
618 struct pipe_resource *src,
619 unsigned src_level,
620 const struct pipe_box *src_box)
621 {
622 struct r600_context *rctx = (struct r600_context *)ctx;
623 struct pipe_surface *dst_view, dst_templ;
624 struct pipe_sampler_view src_templ, *src_view;
625 unsigned dst_width, dst_height, src_width0, src_height0, src_widthFL, src_heightFL;
626 unsigned src_force_level = 0;
627 struct pipe_box sbox, dstbox;
628
629 /* Handle buffers first. */
630 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
631 if ((src->bind & PIPE_BIND_GLOBAL) ||
632 (dst->bind & PIPE_BIND_GLOBAL)) {
633 r600_copy_global_buffer(ctx, dst, dstx, src, src_box);
634 } else {
635 r600_copy_buffer(ctx, dst, dstx, src, src_box);
636 }
637 return;
638 }
639
640 assert(u_max_sample(dst) == u_max_sample(src));
641
642 /* The driver doesn't decompress resources automatically while
643 * u_blitter is rendering. */
644 if (!r600_decompress_subresource(ctx, src, src_level,
645 src_box->z, src_box->z + src_box->depth - 1)) {
646 return; /* error */
647 }
648
649 dst_width = u_minify(dst->width0, dst_level);
650 dst_height = u_minify(dst->height0, dst_level);
651 src_width0 = src->width0;
652 src_height0 = src->height0;
653 src_widthFL = u_minify(src->width0, src_level);
654 src_heightFL = u_minify(src->height0, src_level);
655
656 util_blitter_default_dst_texture(&dst_templ, dst, dst_level, dstz);
657 util_blitter_default_src_texture(&src_templ, src, src_level);
658
659 if (util_format_is_compressed(src->format) ||
660 util_format_is_compressed(dst->format)) {
661 unsigned blocksize = util_format_get_blocksize(src->format);
662
663 if (blocksize == 8)
664 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT; /* 64-bit block */
665 else
666 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT; /* 128-bit block */
667 dst_templ.format = src_templ.format;
668
669 dst_width = util_format_get_nblocksx(dst->format, dst_width);
670 dst_height = util_format_get_nblocksy(dst->format, dst_height);
671 src_width0 = util_format_get_nblocksx(src->format, src_width0);
672 src_height0 = util_format_get_nblocksy(src->format, src_height0);
673 src_widthFL = util_format_get_nblocksx(src->format, src_widthFL);
674 src_heightFL = util_format_get_nblocksy(src->format, src_heightFL);
675
676 dstx = util_format_get_nblocksx(dst->format, dstx);
677 dsty = util_format_get_nblocksy(dst->format, dsty);
678
679 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
680 sbox.y = util_format_get_nblocksy(src->format, src_box->y);
681 sbox.z = src_box->z;
682 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
683 sbox.height = util_format_get_nblocksy(src->format, src_box->height);
684 sbox.depth = src_box->depth;
685 src_box = &sbox;
686
687 src_force_level = src_level;
688 } else if (!util_blitter_is_copy_supported(rctx->blitter, dst, src)) {
689 if (util_format_is_subsampled_422(src->format)) {
690
691 src_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
692 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
693
694 dst_width = util_format_get_nblocksx(dst->format, dst_width);
695 src_width0 = util_format_get_nblocksx(src->format, src_width0);
696 src_widthFL = util_format_get_nblocksx(src->format, src_widthFL);
697
698 dstx = util_format_get_nblocksx(dst->format, dstx);
699
700 sbox = *src_box;
701 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
702 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
703 src_box = &sbox;
704 } else {
705 unsigned blocksize = util_format_get_blocksize(src->format);
706
707 switch (blocksize) {
708 case 1:
709 dst_templ.format = PIPE_FORMAT_R8_UNORM;
710 src_templ.format = PIPE_FORMAT_R8_UNORM;
711 break;
712 case 2:
713 dst_templ.format = PIPE_FORMAT_R8G8_UNORM;
714 src_templ.format = PIPE_FORMAT_R8G8_UNORM;
715 break;
716 case 4:
717 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
718 src_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
719 break;
720 case 8:
721 dst_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
722 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
723 break;
724 case 16:
725 dst_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
726 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
727 break;
728 default:
729 fprintf(stderr, "Unhandled format %s with blocksize %u\n",
730 util_format_short_name(src->format), blocksize);
731 assert(0);
732 }
733 }
734 }
735
736 dst_view = r600_create_surface_custom(ctx, dst, &dst_templ, dst_width, dst_height);
737
738 if (rctx->b.chip_class >= EVERGREEN) {
739 src_view = evergreen_create_sampler_view_custom(ctx, src, &src_templ,
740 src_width0, src_height0,
741 src_force_level);
742 } else {
743 src_view = r600_create_sampler_view_custom(ctx, src, &src_templ,
744 src_widthFL, src_heightFL);
745 }
746
747 u_box_3d(dstx, dsty, dstz, abs(src_box->width), abs(src_box->height),
748 abs(src_box->depth), &dstbox);
749
750 /* Copy. */
751 r600_blitter_begin(ctx, R600_COPY_TEXTURE);
752 util_blitter_blit_generic(rctx->blitter, dst_view, &dstbox,
753 src_view, src_box, src_width0, src_height0,
754 PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL,
755 FALSE);
756 r600_blitter_end(ctx);
757
758 pipe_surface_reference(&dst_view, NULL);
759 pipe_sampler_view_reference(&src_view, NULL);
760 }
761
762 /* For MSAA integer resolving to work, we change the format to NORM using this function. */
763 static enum pipe_format int_to_norm_format(enum pipe_format format)
764 {
765 switch (format) {
766 #define REPLACE_FORMAT_SIGN(format,sign) \
767 case PIPE_FORMAT_##format##_##sign##INT: \
768 return PIPE_FORMAT_##format##_##sign##NORM
769 #define REPLACE_FORMAT(format) \
770 REPLACE_FORMAT_SIGN(format, U); \
771 REPLACE_FORMAT_SIGN(format, S)
772
773 REPLACE_FORMAT_SIGN(B10G10R10A2, U);
774 REPLACE_FORMAT(R8);
775 REPLACE_FORMAT(R8G8);
776 REPLACE_FORMAT(R8G8B8X8);
777 REPLACE_FORMAT(R8G8B8A8);
778 REPLACE_FORMAT(A8);
779 REPLACE_FORMAT(I8);
780 REPLACE_FORMAT(L8);
781 REPLACE_FORMAT(L8A8);
782 REPLACE_FORMAT(R16);
783 REPLACE_FORMAT(R16G16);
784 REPLACE_FORMAT(R16G16B16X16);
785 REPLACE_FORMAT(R16G16B16A16);
786 REPLACE_FORMAT(A16);
787 REPLACE_FORMAT(I16);
788 REPLACE_FORMAT(L16);
789 REPLACE_FORMAT(L16A16);
790
791 #undef REPLACE_FORMAT
792 #undef REPLACE_FORMAT_SIGN
793 default:
794 return format;
795 }
796 }
797
798 static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
799 const struct pipe_blit_info *info)
800 {
801 struct r600_context *rctx = (struct r600_context*)ctx;
802 struct r600_texture *dst = (struct r600_texture*)info->dst.resource;
803 unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level);
804 unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level);
805 enum pipe_format format = int_to_norm_format(info->dst.format);
806 unsigned sample_mask =
807 rctx->b.chip_class == CAYMAN ? ~0 :
808 ((1ull << MAX2(1, info->src.resource->nr_samples)) - 1);
809
810 if (info->src.resource->nr_samples > 1 &&
811 info->dst.resource->nr_samples <= 1 &&
812 util_max_layer(info->src.resource, 0) == 0 &&
813 util_max_layer(info->dst.resource, info->dst.level) == 0 &&
814 info->dst.format == info->src.format &&
815 !util_format_is_pure_integer(format) &&
816 !util_format_is_depth_or_stencil(format) &&
817 !info->scissor_enable &&
818 (info->mask & PIPE_MASK_RGBA) == PIPE_MASK_RGBA &&
819 dst_width == info->src.resource->width0 &&
820 dst_height == info->src.resource->height0 &&
821 info->dst.box.x == 0 &&
822 info->dst.box.y == 0 &&
823 info->dst.box.width == dst_width &&
824 info->dst.box.height == dst_height &&
825 info->dst.box.depth == 1 &&
826 info->src.box.x == 0 &&
827 info->src.box.y == 0 &&
828 info->src.box.width == dst_width &&
829 info->src.box.height == dst_height &&
830 info->src.box.depth == 1 &&
831 dst->surface.level[info->dst.level].mode >= RADEON_SURF_MODE_1D &&
832 (!dst->cmask.size || !dst->dirty_level_mask) /* dst cannot be fast-cleared */) {
833 r600_blitter_begin(ctx, R600_COLOR_RESOLVE |
834 (info->render_condition_enable ? 0 : R600_DISABLE_RENDER_COND));
835 util_blitter_custom_resolve_color(rctx->blitter,
836 info->dst.resource, info->dst.level,
837 info->dst.box.z,
838 info->src.resource, info->src.box.z,
839 sample_mask, rctx->custom_blend_resolve,
840 format);
841 r600_blitter_end(ctx);
842 return true;
843 }
844 return false;
845 }
846
847 static void r600_blit(struct pipe_context *ctx,
848 const struct pipe_blit_info *info)
849 {
850 struct r600_context *rctx = (struct r600_context*)ctx;
851
852 if (do_hardware_msaa_resolve(ctx, info)) {
853 return;
854 }
855
856 assert(util_blitter_is_blit_supported(rctx->blitter, info));
857
858 /* The driver doesn't decompress resources automatically while
859 * u_blitter is rendering. */
860 if (!r600_decompress_subresource(ctx, info->src.resource, info->src.level,
861 info->src.box.z,
862 info->src.box.z + info->src.box.depth - 1)) {
863 return; /* error */
864 }
865
866 if (rctx->screen->b.debug_flags & DBG_FORCE_DMA &&
867 util_try_blit_via_copy_region(ctx, info))
868 return;
869
870 r600_blitter_begin(ctx, R600_BLIT |
871 (info->render_condition_enable ? 0 : R600_DISABLE_RENDER_COND));
872 util_blitter_blit(rctx->blitter, info);
873 r600_blitter_end(ctx);
874 }
875
876 static void r600_flush_resource(struct pipe_context *ctx,
877 struct pipe_resource *res)
878 {
879 struct r600_texture *rtex = (struct r600_texture*)res;
880
881 assert(res->target != PIPE_BUFFER);
882
883 if (!rtex->is_depth && rtex->cmask.size) {
884 r600_blit_decompress_color(ctx, rtex, 0, res->last_level,
885 0, util_max_layer(res, 0));
886 }
887 }
888
889 void r600_init_blit_functions(struct r600_context *rctx)
890 {
891 rctx->b.b.clear = r600_clear;
892 rctx->b.b.clear_render_target = r600_clear_render_target;
893 rctx->b.b.clear_depth_stencil = r600_clear_depth_stencil;
894 rctx->b.b.resource_copy_region = r600_resource_copy_region;
895 rctx->b.b.blit = r600_blit;
896 rctx->b.b.flush_resource = r600_flush_resource;
897 rctx->b.clear_buffer = r600_clear_buffer;
898 rctx->b.blit_decompress_depth = r600_blit_decompress_depth;
899 }