src/gallium/drivers/r600/r600_buffer.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  *      Corbin Simpson <MostAwesomeDude@gmail.com>
  26  */
  27 #include <pipe/p_screen.h>
  28 #include <util/u_format.h>
  29 #include <util/u_math.h>
  30 #include <util/u_inlines.h>
  31 #include <util/u_memory.h>
  32 #include <util/u_upload_mgr.h>
  33 #include "state_tracker/drm_driver.h"
  34 #include <xf86drm.h>
  35 #include "radeon_drm.h"
  36 #include "r600.h"
  37 #include "r600_pipe.h"
  38
  39 extern struct u_resource_vtbl r600_buffer_vtbl;
  40
  41 u32 r600_domain_from_usage(unsigned usage)
  42 {
  43         u32 domain = RADEON_GEM_DOMAIN_GTT;
  44
  45         if (usage & PIPE_BIND_RENDER_TARGET) {
  46                 domain |= RADEON_GEM_DOMAIN_VRAM;
  47         }
  48         if (usage & PIPE_BIND_DEPTH_STENCIL) {
  49                 domain |= RADEON_GEM_DOMAIN_VRAM;
  50         }
  51         if (usage & PIPE_BIND_SAMPLER_VIEW) {
  52                 domain |= RADEON_GEM_DOMAIN_VRAM;
  53         }
  54         /* also need BIND_BLIT_SOURCE/DESTINATION ? */
  55         if (usage & PIPE_BIND_VERTEX_BUFFER) {
  56                 domain |= RADEON_GEM_DOMAIN_GTT;
  57         }
  58         if (usage & PIPE_BIND_INDEX_BUFFER) {
  59                 domain |= RADEON_GEM_DOMAIN_GTT;
  60         }
  61         if (usage & PIPE_BIND_CONSTANT_BUFFER) {
  62                 domain |= RADEON_GEM_DOMAIN_VRAM;
  63         }
  64
  65         return domain;
  66 }
  67
  68 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
  69                                          const struct pipe_resource *templ)
  70 {
  71         struct r600_resource_buffer *rbuffer;
  72         struct r600_bo *bo;
  73         /* XXX We probably want a different alignment for buffers and textures. */
  74         unsigned alignment = 4096;
  75
  76         rbuffer = CALLOC_STRUCT(r600_resource_buffer);
  77         if (rbuffer == NULL)
  78                 return NULL;
  79
  80         rbuffer->magic = R600_BUFFER_MAGIC;
  81         rbuffer->user_buffer = NULL;
  82         rbuffer->num_ranges = 0;
  83         rbuffer->r.base.b = *templ;
  84         pipe_reference_init(&rbuffer->r.base.b.reference, 1);
  85         rbuffer->r.base.b.screen = screen;
  86         rbuffer->r.base.vtbl = &r600_buffer_vtbl;
  87         rbuffer->r.size = rbuffer->r.base.b.width0;
  88         rbuffer->r.domain = r600_domain_from_usage(rbuffer->r.base.b.bind);
  89         bo = r600_bo((struct radeon*)screen->winsys, rbuffer->r.base.b.width0, alignment, rbuffer->r.base.b.bind, rbuffer->r.base.b.usage);
  90         if (bo == NULL) {
  91                 FREE(rbuffer);
  92                 return NULL;
  93         }
  94         rbuffer->r.bo = bo;
  95         return &rbuffer->r.base.b;
  96 }
  97
  98 struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen,
  99                                               void *ptr, unsigned bytes,
 100                                               unsigned bind)
 101 {
 102         struct r600_resource_buffer *rbuffer;
 103
 104         rbuffer = CALLOC_STRUCT(r600_resource_buffer);
 105         if (rbuffer == NULL)
 106                 return NULL;
 107
 108         rbuffer->magic = R600_BUFFER_MAGIC;
 109         pipe_reference_init(&rbuffer->r.base.b.reference, 1);
 110         rbuffer->r.base.vtbl = &r600_buffer_vtbl;
 111         rbuffer->r.base.b.screen = screen;
 112         rbuffer->r.base.b.target = PIPE_BUFFER;
 113         rbuffer->r.base.b.format = PIPE_FORMAT_R8_UNORM;
 114         rbuffer->r.base.b.usage = PIPE_USAGE_IMMUTABLE;
 115         rbuffer->r.base.b.bind = bind;
 116         rbuffer->r.base.b.width0 = bytes;
 117         rbuffer->r.base.b.height0 = 1;
 118         rbuffer->r.base.b.depth0 = 1;
 119         rbuffer->r.base.b.flags = 0;
 120         rbuffer->num_ranges = 0;
 121         rbuffer->r.bo = NULL;
 122         rbuffer->user_buffer = ptr;
 123         return &rbuffer->r.base.b;
 124 }
 125
 126 static void r600_buffer_destroy(struct pipe_screen *screen,
 127                                 struct pipe_resource *buf)
 128 {
 129         struct r600_resource_buffer *rbuffer = r600_buffer(buf);
 130
 131         if (rbuffer->r.bo) {
 132                 r600_bo_reference((struct radeon*)screen->winsys, &rbuffer->r.bo, NULL);
 133         }
 134         FREE(rbuffer);
 135 }
 136
 137 static void *r600_buffer_transfer_map(struct pipe_context *pipe,
 138                                       struct pipe_transfer *transfer)
 139 {
 140         struct r600_resource_buffer *rbuffer = r600_buffer(transfer->resource);
 141         int write = 0;
 142         uint8_t *data;
 143         int i;
 144         boolean flush = FALSE;
 145
 146         if (rbuffer->user_buffer)
 147                 return (uint8_t*)rbuffer->user_buffer + transfer->box.x;
 148
 149         if (transfer->usage & PIPE_TRANSFER_DISCARD) {
 150                 for (i = 0; i < rbuffer->num_ranges; i++) {
 151                         if ((transfer->box.x >= rbuffer->ranges[i].start) &&
 152                             (transfer->box.x < rbuffer->ranges[i].end))
 153                                 flush = TRUE;
 154
 155                         if (flush) {
 156                                 r600_bo_reference((struct radeon*)pipe->winsys, &rbuffer->r.bo, NULL);
 157                                 rbuffer->num_ranges = 0;
 158                                 rbuffer->r.bo = r600_bo((struct radeon*)pipe->winsys,
 159                                                         rbuffer->r.base.b.width0, 0,
 160                                                         rbuffer->r.base.b.bind,
 161                                                         rbuffer->r.base.b.usage);
 162                                 break;
 163                         }
 164                 }
 165         }
 166         if (transfer->usage & PIPE_TRANSFER_DONTBLOCK) {
 167                 /* FIXME */
 168         }
 169         if (transfer->usage & PIPE_TRANSFER_WRITE) {
 170                 write = 1;
 171         }
 172         data = r600_bo_map((struct radeon*)pipe->winsys, rbuffer->r.bo, transfer->usage, pipe);
 173         if (!data)
 174                 return NULL;
 175
 176         return (uint8_t*)data + transfer->box.x;
 177 }
 178
 179 static void r600_buffer_transfer_unmap(struct pipe_context *pipe,
 180                                         struct pipe_transfer *transfer)
 181 {
 182         struct r600_resource_buffer *rbuffer = r600_buffer(transfer->resource);
 183
 184         if (rbuffer->r.bo)
 185                 r600_bo_unmap((struct radeon*)pipe->winsys, rbuffer->r.bo);
 186 }
 187
 188 static void r600_buffer_transfer_flush_region(struct pipe_context *pipe,
 189                                               struct pipe_transfer *transfer,
 190                                               const struct pipe_box *box)
 191 {
 192         struct r600_resource_buffer *rbuffer = r600_buffer(transfer->resource);
 193         unsigned i;
 194         unsigned offset = transfer->box.x + box->x;
 195         unsigned length = box->width;
 196
 197         assert(box->x + box->width <= transfer->box.width);
 198
 199         if (rbuffer->user_buffer)
 200                 return;
 201
 202         /* mark the range as used */
 203         for(i = 0; i < rbuffer->num_ranges; ++i) {
 204                 if(offset <= rbuffer->ranges[i].end && rbuffer->ranges[i].start <= (offset+box->width)) {
 205                         rbuffer->ranges[i].start = MIN2(rbuffer->ranges[i].start, offset);
 206                         rbuffer->ranges[i].end   = MAX2(rbuffer->ranges[i].end, (offset+length));
 207                         return;
 208                 }
 209         }
 210
 211         rbuffer->ranges[rbuffer->num_ranges].start = offset;
 212         rbuffer->ranges[rbuffer->num_ranges].end = offset+length;
 213         rbuffer->num_ranges++;
 214 }
 215
 216 unsigned r600_buffer_is_referenced_by_cs(struct pipe_context *context,
 217                                          struct pipe_resource *buf,
 218                                          unsigned face, unsigned level)
 219 {
 220         /* FIXME */
 221         return PIPE_REFERENCED_FOR_READ | PIPE_REFERENCED_FOR_WRITE;
 222 }
 223
 224 struct pipe_resource *r600_buffer_from_handle(struct pipe_screen *screen,
 225                                               struct winsys_handle *whandle)
 226 {
 227         struct radeon *rw = (struct radeon*)screen->winsys;
 228         struct r600_resource *rbuffer;
 229         struct r600_bo *bo = NULL;
 230
 231         bo = r600_bo_handle(rw, whandle->handle, NULL);
 232         if (bo == NULL) {
 233                 return NULL;
 234         }
 235
 236         rbuffer = CALLOC_STRUCT(r600_resource);
 237         if (rbuffer == NULL) {
 238                 r600_bo_reference(rw, &bo, NULL);
 239                 return NULL;
 240         }
 241
 242         pipe_reference_init(&rbuffer->base.b.reference, 1);
 243         rbuffer->base.b.target = PIPE_BUFFER;
 244         rbuffer->base.b.screen = screen;
 245         rbuffer->base.vtbl = &r600_buffer_vtbl;
 246         rbuffer->bo = bo;
 247         return &rbuffer->base.b;
 248 }
 249
 250 struct u_resource_vtbl r600_buffer_vtbl =
 251 {
 252         u_default_resource_get_handle,          /* get_handle */
 253         r600_buffer_destroy,                    /* resource_destroy */
 254         r600_buffer_is_referenced_by_cs,        /* is_buffer_referenced */
 255         u_default_get_transfer,                 /* get_transfer */
 256         u_default_transfer_destroy,             /* transfer_destroy */
 257         r600_buffer_transfer_map,               /* transfer_map */
 258         r600_buffer_transfer_flush_region,      /* transfer_flush_region */
 259         r600_buffer_transfer_unmap,             /* transfer_unmap */
 260         u_default_transfer_inline_write         /* transfer_inline_write */
 261 };
 262
 263 int r600_upload_index_buffer(struct r600_pipe_context *rctx, struct r600_drawl *draw)
 264 {
 265         struct pipe_resource *upload_buffer = NULL;
 266         unsigned index_offset = draw->index_buffer_offset;
 267         int ret = 0;
 268
 269         if (r600_buffer_is_user_buffer(draw->index_buffer)) {
 270                 ret = u_upload_buffer(rctx->upload_ib,
 271                                       index_offset,
 272                                       draw->count * draw->index_size,
 273                                       draw->index_buffer,
 274                                       &index_offset,
 275                                       &upload_buffer);
 276                 if (ret) {
 277                         goto done;
 278                 }
 279                 draw->index_buffer_offset = index_offset;
 280
 281                 /* Transfer ownership. */
 282                 pipe_resource_reference(&draw->index_buffer, upload_buffer);
 283                 pipe_resource_reference(&upload_buffer, NULL);
 284         }
 285
 286 done:
 287         return ret;
 288 }
 289
 290 int r600_upload_user_buffers(struct r600_pipe_context *rctx)
 291 {
 292         enum pipe_error ret = PIPE_OK;
 293         int i, nr;
 294
 295         nr = rctx->vertex_elements->count;
 296
 297         for (i = 0; i < nr; i++) {
 298                 struct pipe_vertex_buffer *vb =
 299                         &rctx->vertex_buffer[rctx->vertex_elements->elements[i].vertex_buffer_index];
 300
 301                 if (r600_buffer_is_user_buffer(vb->buffer)) {
 302                         struct pipe_resource *upload_buffer = NULL;
 303                         unsigned offset = 0; /*vb->buffer_offset * 4;*/
 304                         unsigned size = vb->buffer->width0;
 305                         unsigned upload_offset;
 306                         ret = u_upload_buffer(rctx->upload_vb,
 307                                               offset, size,
 308                                               vb->buffer,
 309                                               &upload_offset, &upload_buffer);
 310                         if (ret)
 311                                 return ret;
 312
 313                         pipe_resource_reference(&vb->buffer, NULL);
 314                         vb->buffer = upload_buffer;
 315                         vb->buffer_offset = upload_offset;
 316                 }
 317         }
 318         return ret;
 319 }