71b47e1b0569299d0ebab2c9555dfd1b8b29f5c4
[mesa.git] / src / gallium / drivers / r600 / r600_buffer.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson <MostAwesomeDude@gmail.com>
26 */
27 #include <byteswap.h>
28
29 #include <pipe/p_screen.h>
30 #include <util/u_format.h>
31 #include <util/u_math.h>
32 #include <util/u_inlines.h>
33 #include <util/u_memory.h>
34 #include "util/u_upload_mgr.h"
35
36 #include "state_tracker/drm_driver.h"
37
38 #include <xf86drm.h>
39 #include "radeon_drm.h"
40
41 #include "r600.h"
42 #include "r600_pipe.h"
43
44 static void r600_buffer_destroy(struct pipe_screen *screen,
45 struct pipe_resource *buf)
46 {
47 struct r600_screen *rscreen = (struct r600_screen*)screen;
48 struct r600_resource_buffer *rbuffer = r600_buffer(buf);
49
50 if (rbuffer->r.bo) {
51 r600_bo_reference((struct radeon*)screen->winsys, &rbuffer->r.bo, NULL);
52 }
53 rbuffer->r.bo = NULL;
54 util_slab_free(&rscreen->pool_buffers, rbuffer);
55 }
56
57 static struct pipe_transfer *r600_get_transfer(struct pipe_context *ctx,
58 struct pipe_resource *resource,
59 unsigned level,
60 unsigned usage,
61 const struct pipe_box *box)
62 {
63 struct r600_pipe_context *rctx = (struct r600_pipe_context*)ctx;
64 struct pipe_transfer *transfer = util_slab_alloc(&rctx->pool_transfers);
65
66 transfer->resource = resource;
67 transfer->level = level;
68 transfer->usage = usage;
69 transfer->box = *box;
70 transfer->stride = 0;
71 transfer->layer_stride = 0;
72 transfer->data = NULL;
73
74 /* Note strides are zero, this is ok for buffers, but not for
75 * textures 2d & higher at least.
76 */
77 return transfer;
78 }
79
80 static void *r600_buffer_transfer_map(struct pipe_context *pipe,
81 struct pipe_transfer *transfer)
82 {
83 struct r600_resource_buffer *rbuffer = r600_buffer(transfer->resource);
84 int write = 0;
85 uint8_t *data;
86
87 if (rbuffer->r.b.user_ptr)
88 return (uint8_t*)rbuffer->r.b.user_ptr + transfer->box.x;
89
90 if (transfer->usage & PIPE_TRANSFER_DONTBLOCK) {
91 /* FIXME */
92 }
93 if (transfer->usage & PIPE_TRANSFER_WRITE) {
94 write = 1;
95 }
96 data = r600_bo_map((struct radeon*)pipe->winsys, rbuffer->r.bo, transfer->usage, pipe);
97 if (!data)
98 return NULL;
99
100 return (uint8_t*)data + transfer->box.x;
101 }
102
103 static void r600_buffer_transfer_unmap(struct pipe_context *pipe,
104 struct pipe_transfer *transfer)
105 {
106 struct r600_resource_buffer *rbuffer = r600_buffer(transfer->resource);
107
108 if (rbuffer->r.b.user_ptr)
109 return;
110
111 if (rbuffer->r.bo)
112 r600_bo_unmap((struct radeon*)pipe->winsys, rbuffer->r.bo);
113 }
114
115 static void r600_buffer_transfer_flush_region(struct pipe_context *pipe,
116 struct pipe_transfer *transfer,
117 const struct pipe_box *box)
118 {
119 }
120
121 static void r600_transfer_destroy(struct pipe_context *ctx,
122 struct pipe_transfer *transfer)
123 {
124 struct r600_pipe_context *rctx = (struct r600_pipe_context*)ctx;
125 util_slab_free(&rctx->pool_transfers, transfer);
126 }
127
128 static void r600_buffer_transfer_inline_write(struct pipe_context *pipe,
129 struct pipe_resource *resource,
130 unsigned level,
131 unsigned usage,
132 const struct pipe_box *box,
133 const void *data,
134 unsigned stride,
135 unsigned layer_stride)
136 {
137 struct radeon *ws = (struct radeon*)pipe->winsys;
138 struct r600_resource_buffer *rbuffer = r600_buffer(resource);
139 uint8_t *map = NULL;
140
141 assert(rbuffer->r.b.user_ptr == NULL);
142
143 map = r600_bo_map(ws, rbuffer->r.bo,
144 PIPE_TRANSFER_WRITE | PIPE_TRANSFER_DISCARD | usage,
145 pipe);
146
147 memcpy(map + box->x, data, box->width);
148
149 if (rbuffer->r.bo)
150 r600_bo_unmap(ws, rbuffer->r.bo);
151 }
152
153 static const struct u_resource_vtbl r600_buffer_vtbl =
154 {
155 u_default_resource_get_handle, /* get_handle */
156 r600_buffer_destroy, /* resource_destroy */
157 r600_get_transfer, /* get_transfer */
158 r600_transfer_destroy, /* transfer_destroy */
159 r600_buffer_transfer_map, /* transfer_map */
160 r600_buffer_transfer_flush_region, /* transfer_flush_region */
161 r600_buffer_transfer_unmap, /* transfer_unmap */
162 r600_buffer_transfer_inline_write /* transfer_inline_write */
163 };
164
165 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
166 const struct pipe_resource *templ)
167 {
168 struct r600_screen *rscreen = (struct r600_screen*)screen;
169 struct r600_resource_buffer *rbuffer;
170 struct r600_bo *bo;
171 /* XXX We probably want a different alignment for buffers and textures. */
172 unsigned alignment = 4096;
173
174 rbuffer = util_slab_alloc(&rscreen->pool_buffers);
175
176 rbuffer->magic = R600_BUFFER_MAGIC;
177 rbuffer->r.b.b.b = *templ;
178 pipe_reference_init(&rbuffer->r.b.b.b.reference, 1);
179 rbuffer->r.b.b.b.screen = screen;
180 rbuffer->r.b.b.vtbl = &r600_buffer_vtbl;
181 rbuffer->r.b.user_ptr = NULL;
182 rbuffer->r.size = rbuffer->r.b.b.b.width0;
183 rbuffer->r.bo_size = rbuffer->r.size;
184
185 bo = r600_bo((struct radeon*)screen->winsys,
186 rbuffer->r.b.b.b.width0,
187 alignment, rbuffer->r.b.b.b.bind,
188 rbuffer->r.b.b.b.usage);
189
190 if (bo == NULL) {
191 FREE(rbuffer);
192 return NULL;
193 }
194 rbuffer->r.bo = bo;
195 return &rbuffer->r.b.b.b;
196 }
197
198 struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen,
199 void *ptr, unsigned bytes,
200 unsigned bind)
201 {
202 struct r600_screen *rscreen = (struct r600_screen*)screen;
203 struct r600_resource_buffer *rbuffer;
204
205 rbuffer = util_slab_alloc(&rscreen->pool_buffers);
206
207 rbuffer->magic = R600_BUFFER_MAGIC;
208 pipe_reference_init(&rbuffer->r.b.b.b.reference, 1);
209 rbuffer->r.b.b.vtbl = &r600_buffer_vtbl;
210 rbuffer->r.b.b.b.screen = screen;
211 rbuffer->r.b.b.b.target = PIPE_BUFFER;
212 rbuffer->r.b.b.b.format = PIPE_FORMAT_R8_UNORM;
213 rbuffer->r.b.b.b.usage = PIPE_USAGE_IMMUTABLE;
214 rbuffer->r.b.b.b.bind = bind;
215 rbuffer->r.b.b.b.width0 = bytes;
216 rbuffer->r.b.b.b.height0 = 1;
217 rbuffer->r.b.b.b.depth0 = 1;
218 rbuffer->r.b.b.b.array_size = 1;
219 rbuffer->r.b.b.b.flags = 0;
220 rbuffer->r.b.user_ptr = ptr;
221 rbuffer->r.bo = NULL;
222 rbuffer->r.bo_size = 0;
223 return &rbuffer->r.b.b.b;
224 }
225
226 struct pipe_resource *r600_buffer_from_handle(struct pipe_screen *screen,
227 struct winsys_handle *whandle)
228 {
229 struct radeon *rw = (struct radeon*)screen->winsys;
230 struct r600_resource *rbuffer;
231 struct r600_bo *bo = NULL;
232
233 bo = r600_bo_handle(rw, whandle->handle, NULL);
234 if (bo == NULL) {
235 return NULL;
236 }
237
238 rbuffer = CALLOC_STRUCT(r600_resource);
239 if (rbuffer == NULL) {
240 r600_bo_reference(rw, &bo, NULL);
241 return NULL;
242 }
243
244 pipe_reference_init(&rbuffer->b.b.b.reference, 1);
245 rbuffer->b.b.b.target = PIPE_BUFFER;
246 rbuffer->b.b.b.screen = screen;
247 rbuffer->b.b.vtbl = &r600_buffer_vtbl;
248 rbuffer->bo = bo;
249 return &rbuffer->b.b.b;
250 }
251
252 void r600_upload_index_buffer(struct r600_pipe_context *rctx, struct r600_drawl *draw)
253 {
254 struct r600_resource_buffer *rbuffer = r600_buffer(draw->index_buffer);
255 boolean flushed;
256
257 u_upload_data(rctx->vbuf_mgr->uploader, 0,
258 draw->info.count * draw->index_size,
259 rbuffer->r.b.user_ptr,
260 &draw->index_buffer_offset,
261 &draw->index_buffer, &flushed);
262 }
263
264 void r600_upload_const_buffer(struct r600_pipe_context *rctx, struct r600_resource_buffer **rbuffer,
265 uint32_t *const_offset)
266 {
267 if ((*rbuffer)->r.b.user_ptr) {
268 uint8_t *ptr = (*rbuffer)->r.b.user_ptr;
269 unsigned size = (*rbuffer)->r.b.b.b.width0;
270 boolean flushed;
271 #ifdef PIPE_ARCH_BIG_ENDIAN
272 int i;
273 uint32_t *tmpPtr;
274
275 *rbuffer = NULL;
276
277 tmpPtr = (uint32_t *)malloc(size);
278 /* big endian swap */
279 if(tmpPtr == NULL) {
280 return;
281 }
282 for(i = 0; i < size / 4; i++) {
283 tmpPtr[i] = bswap_32(*((uint32_t *)ptr + i));
284 }
285
286 u_upload_data(rctx->vbuf_mgr->uploader, 0, size, tmpPtr, const_offset,
287 (struct pipe_resource**)rbuffer, &flushed);
288
289 free(tmpPtr);
290 #else
291 *rbuffer = NULL;
292
293 u_upload_data(rctx->vbuf_mgr->uploader, 0, size, ptr, const_offset,
294 (struct pipe_resource**)rbuffer, &flushed);
295 #endif
296 } else {
297 *const_offset = 0;
298 }
299 }