969803fe9514f844df949795c3eb691c4ec7b5f7
[mesa.git] / src / gallium / drivers / r600 / r600_buffer.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson <MostAwesomeDude@gmail.com>
26 */
27 #include "r600_pipe.h"
28 #include "util/u_upload_mgr.h"
29 #include "util/u_memory.h"
30 #include "util/u_surface.h"
31
32 static void r600_buffer_destroy(struct pipe_screen *screen,
33 struct pipe_resource *buf)
34 {
35 struct r600_resource *rbuffer = r600_resource(buf);
36
37 util_range_destroy(&rbuffer->valid_buffer_range);
38 pb_reference(&rbuffer->buf, NULL);
39 FREE(rbuffer);
40 }
41
42 static void *r600_buffer_get_transfer(struct pipe_context *ctx,
43 struct pipe_resource *resource,
44 unsigned level,
45 unsigned usage,
46 const struct pipe_box *box,
47 struct pipe_transfer **ptransfer,
48 void *data, struct r600_resource *staging,
49 unsigned offset)
50 {
51 struct r600_context *rctx = (struct r600_context*)ctx;
52 struct r600_transfer *transfer = util_slab_alloc(&rctx->pool_transfers);
53
54 transfer->transfer.resource = resource;
55 transfer->transfer.level = level;
56 transfer->transfer.usage = usage;
57 transfer->transfer.box = *box;
58 transfer->transfer.stride = 0;
59 transfer->transfer.layer_stride = 0;
60 transfer->offset = offset;
61 transfer->staging = staging;
62 *ptransfer = &transfer->transfer;
63 return data;
64 }
65
66 static void *r600_buffer_transfer_map(struct pipe_context *ctx,
67 struct pipe_resource *resource,
68 unsigned level,
69 unsigned usage,
70 const struct pipe_box *box,
71 struct pipe_transfer **ptransfer)
72 {
73 struct r600_context *rctx = (struct r600_context*)ctx;
74 struct r600_resource *rbuffer = r600_resource(resource);
75 uint8_t *data;
76
77 assert(box->x + box->width <= resource->width0);
78
79 /* See if the buffer range being mapped has never been initialized,
80 * in which case it can be mapped unsynchronized. */
81 if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED) &&
82 usage & PIPE_TRANSFER_WRITE &&
83 !util_ranges_intersect(&rbuffer->valid_buffer_range, box->x, box->x + box->width)) {
84 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
85 }
86
87 if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE &&
88 !(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
89 assert(usage & PIPE_TRANSFER_WRITE);
90
91 /* Check if mapping this buffer would cause waiting for the GPU. */
92 if (r600_rings_is_buffer_referenced(&rctx->b, rbuffer->cs_buf, RADEON_USAGE_READWRITE) ||
93 rctx->b.ws->buffer_is_busy(rbuffer->buf, RADEON_USAGE_READWRITE)) {
94 rctx->b.invalidate_buffer(&rctx->b.b, &rbuffer->b.b);
95 }
96 }
97 else if ((usage & PIPE_TRANSFER_DISCARD_RANGE) &&
98 !(usage & PIPE_TRANSFER_UNSYNCHRONIZED) &&
99 !(rctx->screen->b.debug_flags & DBG_NO_DISCARD_RANGE) &&
100 (rctx->screen->b.has_cp_dma ||
101 (rctx->screen->b.has_streamout &&
102 /* The buffer range must be aligned to 4 with streamout. */
103 box->x % 4 == 0 && box->width % 4 == 0))) {
104 assert(usage & PIPE_TRANSFER_WRITE);
105
106 /* Check if mapping this buffer would cause waiting for the GPU. */
107 if (r600_rings_is_buffer_referenced(&rctx->b, rbuffer->cs_buf, RADEON_USAGE_READWRITE) ||
108 rctx->b.ws->buffer_is_busy(rbuffer->buf, RADEON_USAGE_READWRITE)) {
109 /* Do a wait-free write-only transfer using a temporary buffer. */
110 unsigned offset;
111 struct r600_resource *staging = NULL;
112
113 u_upload_alloc(rctx->uploader, 0, box->width + (box->x % R600_MAP_BUFFER_ALIGNMENT),
114 &offset, (struct pipe_resource**)&staging, (void**)&data);
115
116 if (staging) {
117 data += box->x % R600_MAP_BUFFER_ALIGNMENT;
118 return r600_buffer_get_transfer(ctx, resource, level, usage, box,
119 ptransfer, data, staging, offset);
120 }
121 }
122 }
123
124 /* mmap and synchronize with rings */
125 data = r600_buffer_map_sync_with_rings(&rctx->b, rbuffer, usage);
126 if (!data) {
127 return NULL;
128 }
129 data += box->x;
130
131 return r600_buffer_get_transfer(ctx, resource, level, usage, box,
132 ptransfer, data, NULL, 0);
133 }
134
135 static void r600_buffer_transfer_unmap(struct pipe_context *pipe,
136 struct pipe_transfer *transfer)
137 {
138 struct r600_context *rctx = (struct r600_context*)pipe;
139 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
140 struct r600_resource *rbuffer = r600_resource(transfer->resource);
141
142 if (rtransfer->staging) {
143 struct pipe_resource *dst, *src;
144 unsigned soffset, doffset, size;
145 struct pipe_box box;
146
147 dst = transfer->resource;
148 src = &rtransfer->staging->b.b;
149 size = transfer->box.width;
150 doffset = transfer->box.x;
151 soffset = rtransfer->offset + transfer->box.x % R600_MAP_BUFFER_ALIGNMENT;
152
153 u_box_1d(soffset, size, &box);
154
155 /* Copy the staging buffer into the original one. */
156 if (!(size % 4) && !(doffset % 4) && !(soffset % 4) &&
157 rctx->b.dma_copy(pipe, dst, 0, doffset, 0, 0, src, 0, &box)) {
158 /* DONE. */
159 } else {
160 pipe->resource_copy_region(pipe, dst, 0, doffset, 0, 0, src, 0, &box);
161 }
162 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
163 }
164
165 if (transfer->usage & PIPE_TRANSFER_WRITE) {
166 util_range_add(&rbuffer->valid_buffer_range, transfer->box.x,
167 transfer->box.x + transfer->box.width);
168 }
169 util_slab_free(&rctx->pool_transfers, transfer);
170 }
171
172 static const struct u_resource_vtbl r600_buffer_vtbl =
173 {
174 u_default_resource_get_handle, /* get_handle */
175 r600_buffer_destroy, /* resource_destroy */
176 r600_buffer_transfer_map, /* transfer_map */
177 NULL, /* transfer_flush_region */
178 r600_buffer_transfer_unmap, /* transfer_unmap */
179 NULL /* transfer_inline_write */
180 };
181
182 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
183 const struct pipe_resource *templ,
184 unsigned alignment)
185 {
186 struct r600_screen *rscreen = (struct r600_screen*)screen;
187 struct r600_resource *rbuffer;
188
189 rbuffer = MALLOC_STRUCT(r600_resource);
190
191 rbuffer->b.b = *templ;
192 pipe_reference_init(&rbuffer->b.b.reference, 1);
193 rbuffer->b.b.screen = screen;
194 rbuffer->b.vtbl = &r600_buffer_vtbl;
195 util_range_init(&rbuffer->valid_buffer_range);
196
197 if (!r600_init_resource(&rscreen->b, rbuffer, templ->width0, alignment, TRUE, templ->usage)) {
198 FREE(rbuffer);
199 return NULL;
200 }
201 return &rbuffer->b.b;
202 }