r600g: indentation fix
[mesa.git] / src / gallium / drivers / r600 / r600_buffer.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson <MostAwesomeDude@gmail.com>
26 */
27 #include <pipe/p_screen.h>
28 #include <util/u_format.h>
29 #include <util/u_math.h>
30 #include <util/u_inlines.h>
31 #include <util/u_memory.h>
32 #include <util/u_upload_mgr.h>
33 #include "state_tracker/drm_driver.h"
34 #include <xf86drm.h>
35 #include "radeon_drm.h"
36 #include "r600.h"
37 #include "r600_pipe.h"
38
39 extern struct u_resource_vtbl r600_buffer_vtbl;
40
41
42 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
43 const struct pipe_resource *templ)
44 {
45 struct r600_resource_buffer *rbuffer;
46 struct r600_bo *bo;
47 /* XXX We probably want a different alignment for buffers and textures. */
48 unsigned alignment = 4096;
49
50 rbuffer = CALLOC_STRUCT(r600_resource_buffer);
51 if (rbuffer == NULL)
52 return NULL;
53
54 rbuffer->magic = R600_BUFFER_MAGIC;
55 rbuffer->user_buffer = NULL;
56 rbuffer->num_ranges = 0;
57 rbuffer->r.base.b = *templ;
58 pipe_reference_init(&rbuffer->r.base.b.reference, 1);
59 rbuffer->r.base.b.screen = screen;
60 rbuffer->r.base.vtbl = &r600_buffer_vtbl;
61 rbuffer->r.size = rbuffer->r.base.b.width0;
62 bo = r600_bo((struct radeon*)screen->winsys, rbuffer->r.base.b.width0, alignment, rbuffer->r.base.b.bind, rbuffer->r.base.b.usage);
63 if (bo == NULL) {
64 FREE(rbuffer);
65 return NULL;
66 }
67 rbuffer->r.bo = bo;
68 return &rbuffer->r.base.b;
69 }
70
71 struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen,
72 void *ptr, unsigned bytes,
73 unsigned bind)
74 {
75 struct r600_resource_buffer *rbuffer;
76
77 rbuffer = CALLOC_STRUCT(r600_resource_buffer);
78 if (rbuffer == NULL)
79 return NULL;
80
81 rbuffer->magic = R600_BUFFER_MAGIC;
82 pipe_reference_init(&rbuffer->r.base.b.reference, 1);
83 rbuffer->r.base.vtbl = &r600_buffer_vtbl;
84 rbuffer->r.base.b.screen = screen;
85 rbuffer->r.base.b.target = PIPE_BUFFER;
86 rbuffer->r.base.b.format = PIPE_FORMAT_R8_UNORM;
87 rbuffer->r.base.b.usage = PIPE_USAGE_IMMUTABLE;
88 rbuffer->r.base.b.bind = bind;
89 rbuffer->r.base.b.width0 = bytes;
90 rbuffer->r.base.b.height0 = 1;
91 rbuffer->r.base.b.depth0 = 1;
92 rbuffer->r.base.b.array_size = 1;
93 rbuffer->r.base.b.flags = 0;
94 rbuffer->num_ranges = 0;
95 rbuffer->r.bo = NULL;
96 rbuffer->user_buffer = ptr;
97 return &rbuffer->r.base.b;
98 }
99
100 static void r600_buffer_destroy(struct pipe_screen *screen,
101 struct pipe_resource *buf)
102 {
103 struct r600_resource_buffer *rbuffer = r600_buffer(buf);
104
105 if (rbuffer->r.bo) {
106 r600_bo_reference((struct radeon*)screen->winsys, &rbuffer->r.bo, NULL);
107 }
108 FREE(rbuffer);
109 }
110
111 static void *r600_buffer_transfer_map(struct pipe_context *pipe,
112 struct pipe_transfer *transfer)
113 {
114 struct r600_resource_buffer *rbuffer = r600_buffer(transfer->resource);
115 int write = 0;
116 uint8_t *data;
117 int i;
118 boolean flush = FALSE;
119
120 if (rbuffer->user_buffer)
121 return (uint8_t*)rbuffer->user_buffer + transfer->box.x;
122
123 if (transfer->usage & PIPE_TRANSFER_DISCARD) {
124 for (i = 0; i < rbuffer->num_ranges; i++) {
125 if ((transfer->box.x >= rbuffer->ranges[i].start) &&
126 (transfer->box.x < rbuffer->ranges[i].end))
127 flush = TRUE;
128
129 if (flush) {
130 r600_bo_reference((struct radeon*)pipe->winsys, &rbuffer->r.bo, NULL);
131 rbuffer->num_ranges = 0;
132 rbuffer->r.bo = r600_bo((struct radeon*)pipe->winsys,
133 rbuffer->r.base.b.width0, 0,
134 rbuffer->r.base.b.bind,
135 rbuffer->r.base.b.usage);
136 break;
137 }
138 }
139 }
140 if (transfer->usage & PIPE_TRANSFER_DONTBLOCK) {
141 /* FIXME */
142 }
143 if (transfer->usage & PIPE_TRANSFER_WRITE) {
144 write = 1;
145 }
146 data = r600_bo_map((struct radeon*)pipe->winsys, rbuffer->r.bo, transfer->usage, pipe);
147 if (!data)
148 return NULL;
149
150 return (uint8_t*)data + transfer->box.x;
151 }
152
153 static void r600_buffer_transfer_unmap(struct pipe_context *pipe,
154 struct pipe_transfer *transfer)
155 {
156 struct r600_resource_buffer *rbuffer = r600_buffer(transfer->resource);
157
158 if (rbuffer->r.bo)
159 r600_bo_unmap((struct radeon*)pipe->winsys, rbuffer->r.bo);
160 }
161
162 static void r600_buffer_transfer_flush_region(struct pipe_context *pipe,
163 struct pipe_transfer *transfer,
164 const struct pipe_box *box)
165 {
166 struct r600_resource_buffer *rbuffer = r600_buffer(transfer->resource);
167 unsigned i;
168 unsigned offset = transfer->box.x + box->x;
169 unsigned length = box->width;
170
171 assert(box->x + box->width <= transfer->box.width);
172
173 if (rbuffer->user_buffer)
174 return;
175
176 /* mark the range as used */
177 for(i = 0; i < rbuffer->num_ranges; ++i) {
178 if(offset <= rbuffer->ranges[i].end && rbuffer->ranges[i].start <= (offset+box->width)) {
179 rbuffer->ranges[i].start = MIN2(rbuffer->ranges[i].start, offset);
180 rbuffer->ranges[i].end = MAX2(rbuffer->ranges[i].end, (offset+length));
181 return;
182 }
183 }
184
185 rbuffer->ranges[rbuffer->num_ranges].start = offset;
186 rbuffer->ranges[rbuffer->num_ranges].end = offset+length;
187 rbuffer->num_ranges++;
188 }
189
190 unsigned r600_buffer_is_referenced_by_cs(struct pipe_context *context,
191 struct pipe_resource *buf,
192 unsigned level, int layer)
193 {
194 /* FIXME */
195 return PIPE_REFERENCED_FOR_READ | PIPE_REFERENCED_FOR_WRITE;
196 }
197
198 struct pipe_resource *r600_buffer_from_handle(struct pipe_screen *screen,
199 struct winsys_handle *whandle)
200 {
201 struct radeon *rw = (struct radeon*)screen->winsys;
202 struct r600_resource *rbuffer;
203 struct r600_bo *bo = NULL;
204
205 bo = r600_bo_handle(rw, whandle->handle, NULL);
206 if (bo == NULL) {
207 return NULL;
208 }
209
210 rbuffer = CALLOC_STRUCT(r600_resource);
211 if (rbuffer == NULL) {
212 r600_bo_reference(rw, &bo, NULL);
213 return NULL;
214 }
215
216 pipe_reference_init(&rbuffer->base.b.reference, 1);
217 rbuffer->base.b.target = PIPE_BUFFER;
218 rbuffer->base.b.screen = screen;
219 rbuffer->base.vtbl = &r600_buffer_vtbl;
220 rbuffer->bo = bo;
221 return &rbuffer->base.b;
222 }
223
224 struct u_resource_vtbl r600_buffer_vtbl =
225 {
226 u_default_resource_get_handle, /* get_handle */
227 r600_buffer_destroy, /* resource_destroy */
228 r600_buffer_is_referenced_by_cs, /* is_buffer_referenced */
229 u_default_get_transfer, /* get_transfer */
230 u_default_transfer_destroy, /* transfer_destroy */
231 r600_buffer_transfer_map, /* transfer_map */
232 r600_buffer_transfer_flush_region, /* transfer_flush_region */
233 r600_buffer_transfer_unmap, /* transfer_unmap */
234 u_default_transfer_inline_write /* transfer_inline_write */
235 };
236
237 int r600_upload_index_buffer(struct r600_pipe_context *rctx, struct r600_drawl *draw)
238 {
239 struct pipe_resource *upload_buffer = NULL;
240 unsigned index_offset = draw->index_buffer_offset;
241 int ret = 0;
242
243 if (r600_buffer_is_user_buffer(draw->index_buffer)) {
244 ret = u_upload_buffer(rctx->upload_ib,
245 index_offset,
246 draw->count * draw->index_size,
247 draw->index_buffer,
248 &index_offset,
249 &upload_buffer);
250 if (ret) {
251 goto done;
252 }
253 draw->index_buffer_offset = index_offset;
254
255 /* Transfer ownership. */
256 pipe_resource_reference(&draw->index_buffer, upload_buffer);
257 pipe_resource_reference(&upload_buffer, NULL);
258 }
259
260 done:
261 return ret;
262 }
263
264 int r600_upload_user_buffers(struct r600_pipe_context *rctx)
265 {
266 enum pipe_error ret = PIPE_OK;
267 int i, nr;
268
269 nr = rctx->vertex_elements->count;
270
271 for (i = 0; i < nr; i++) {
272 struct pipe_vertex_buffer *vb =
273 &rctx->vertex_buffer[rctx->vertex_elements->elements[i].vertex_buffer_index];
274
275 if (r600_buffer_is_user_buffer(vb->buffer)) {
276 struct pipe_resource *upload_buffer = NULL;
277 unsigned offset = 0; /*vb->buffer_offset * 4;*/
278 unsigned size = vb->buffer->width0;
279 unsigned upload_offset;
280 ret = u_upload_buffer(rctx->upload_vb,
281 offset, size,
282 vb->buffer,
283 &upload_offset, &upload_buffer);
284 if (ret)
285 return ret;
286
287 pipe_resource_reference(&vb->buffer, NULL);
288 vb->buffer = upload_buffer;
289 vb->buffer_offset = upload_offset;
290 }
291 }
292 return ret;
293 }