src/gallium/drivers/r600/r600_buffer_common.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Marek Olšák
  25  */
  26
  27 #include "r600_cs.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_upload_mgr.h"
  30 #include <inttypes.h>
  31 #include <stdio.h>
  32
  33 bool r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
  34                                      struct pb_buffer *buf,
  35                                      enum radeon_bo_usage usage)
  36 {
  37         if (ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, buf, usage)) {
  38                 return true;
  39         }
  40         if (radeon_emitted(ctx->dma.cs, 0) &&
  41             ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, buf, usage)) {
  42                 return true;
  43         }
  44         return false;
  45 }
  46
  47 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
  48                                       struct r600_resource *resource,
  49                                       unsigned usage)
  50 {
  51         enum radeon_bo_usage rusage = RADEON_USAGE_READWRITE;
  52         bool busy = false;
  53
  54         assert(!(resource->flags & RADEON_FLAG_SPARSE));
  55
  56         if (usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
  57                 return ctx->ws->buffer_map(resource->buf, NULL, usage);
  58         }
  59
  60         if (!(usage & PIPE_TRANSFER_WRITE)) {
  61                 /* have to wait for the last write */
  62                 rusage = RADEON_USAGE_WRITE;
  63         }
  64
  65         if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
  66             ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs,
  67                                              resource->buf, rusage)) {
  68                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  69                         ctx->gfx.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
  70                         return NULL;
  71                 } else {
  72                         ctx->gfx.flush(ctx, 0, NULL);
  73                         busy = true;
  74                 }
  75         }
  76         if (radeon_emitted(ctx->dma.cs, 0) &&
  77             ctx->ws->cs_is_buffer_referenced(ctx->dma.cs,
  78                                              resource->buf, rusage)) {
  79                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  80                         ctx->dma.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
  81                         return NULL;
  82                 } else {
  83                         ctx->dma.flush(ctx, 0, NULL);
  84                         busy = true;
  85                 }
  86         }
  87
  88         if (busy || !ctx->ws->buffer_wait(resource->buf, 0, rusage)) {
  89                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  90                         return NULL;
  91                 } else {
  92                         /* We will be wait for the GPU. Wait for any offloaded
  93                          * CS flush to complete to avoid busy-waiting in the winsys. */
  94                         ctx->ws->cs_sync_flush(ctx->gfx.cs);
  95                         if (ctx->dma.cs)
  96                                 ctx->ws->cs_sync_flush(ctx->dma.cs);
  97                 }
  98         }
  99
 100         /* Setting the CS to NULL will prevent doing checks we have done already. */
 101         return ctx->ws->buffer_map(resource->buf, NULL, usage);
 102 }
 103
 104 void r600_init_resource_fields(struct r600_common_screen *rscreen,
 105                                struct r600_resource *res,
 106                                uint64_t size, unsigned alignment)
 107 {
 108         struct r600_texture *rtex = (struct r600_texture*)res;
 109
 110         res->bo_size = size;
 111         res->bo_alignment = alignment;
 112         res->flags = 0;
 113         res->texture_handle_allocated = false;
 114         res->image_handle_allocated = false;
 115
 116         switch (res->b.b.usage) {
 117         case PIPE_USAGE_STREAM:
 118                 res->flags = RADEON_FLAG_GTT_WC;
 119                 /* fall through */
 120         case PIPE_USAGE_STAGING:
 121                 /* Transfers are likely to occur more often with these
 122                  * resources. */
 123                 res->domains = RADEON_DOMAIN_GTT;
 124                 break;
 125         case PIPE_USAGE_DYNAMIC:
 126                 /* Older kernels didn't always flush the HDP cache before
 127                  * CS execution
 128                  */
 129                 if (rscreen->info.drm_major == 2 &&
 130                     rscreen->info.drm_minor < 40) {
 131                         res->domains = RADEON_DOMAIN_GTT;
 132                         res->flags |= RADEON_FLAG_GTT_WC;
 133                         break;
 134                 }
 135                 /* fall through */
 136         case PIPE_USAGE_DEFAULT:
 137         case PIPE_USAGE_IMMUTABLE:
 138         default:
 139                 /* Not listing GTT here improves performance in some
 140                  * apps. */
 141                 res->domains = RADEON_DOMAIN_VRAM;
 142                 res->flags |= RADEON_FLAG_GTT_WC;
 143                 break;
 144         }
 145
 146         if (res->b.b.target == PIPE_BUFFER &&
 147             res->b.b.flags & (PIPE_RESOURCE_FLAG_MAP_PERSISTENT |
 148                               PIPE_RESOURCE_FLAG_MAP_COHERENT)) {
 149                 /* Use GTT for all persistent mappings with older
 150                  * kernels, because they didn't always flush the HDP
 151                  * cache before CS execution.
 152                  *
 153                  * Write-combined CPU mappings are fine, the kernel
 154                  * ensures all CPU writes finish before the GPU
 155                  * executes a command stream.
 156                  */
 157                 if (rscreen->info.drm_major == 2 &&
 158                     rscreen->info.drm_minor < 40)
 159                         res->domains = RADEON_DOMAIN_GTT;
 160         }
 161
 162         /* Tiled textures are unmappable. Always put them in VRAM. */
 163         if ((res->b.b.target != PIPE_BUFFER && !rtex->surface.is_linear) ||
 164             res->flags & R600_RESOURCE_FLAG_UNMAPPABLE) {
 165                 res->domains = RADEON_DOMAIN_VRAM;
 166                 res->flags |= RADEON_FLAG_NO_CPU_ACCESS |
 167                          RADEON_FLAG_GTT_WC;
 168         }
 169
 170         /* Displayable and shareable surfaces are not suballocated. */
 171         if (res->b.b.bind & (PIPE_BIND_SHARED | PIPE_BIND_SCANOUT))
 172                 res->flags |= RADEON_FLAG_NO_SUBALLOC; /* shareable */
 173         else
 174                 res->flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
 175
 176         if (rscreen->debug_flags & DBG_NO_WC)
 177                 res->flags &= ~RADEON_FLAG_GTT_WC;
 178
 179         /* Set expected VRAM and GART usage for the buffer. */
 180         res->vram_usage = 0;
 181         res->gart_usage = 0;
 182
 183         if (res->domains & RADEON_DOMAIN_VRAM)
 184                 res->vram_usage = size;
 185         else if (res->domains & RADEON_DOMAIN_GTT)
 186                 res->gart_usage = size;
 187 }
 188
 189 bool r600_alloc_resource(struct r600_common_screen *rscreen,
 190                          struct r600_resource *res)
 191 {
 192         struct pb_buffer *old_buf, *new_buf;
 193
 194         /* Allocate a new resource. */
 195         new_buf = rscreen->ws->buffer_create(rscreen->ws, res->bo_size,
 196                                              res->bo_alignment,
 197                                              res->domains, res->flags);
 198         if (!new_buf) {
 199                 return false;
 200         }
 201
 202         /* Replace the pointer such that if res->buf wasn't NULL, it won't be
 203          * NULL. This should prevent crashes with multiple contexts using
 204          * the same buffer where one of the contexts invalidates it while
 205          * the others are using it. */
 206         old_buf = res->buf;
 207         res->buf = new_buf; /* should be atomic */
 208
 209         if (rscreen->info.r600_has_virtual_memory)
 210                 res->gpu_address = rscreen->ws->buffer_get_virtual_address(res->buf);
 211         else
 212                 res->gpu_address = 0;
 213
 214         pb_reference(&old_buf, NULL);
 215
 216         util_range_set_empty(&res->valid_buffer_range);
 217
 218         /* Print debug information. */
 219         if (rscreen->debug_flags & DBG_VM && res->b.b.target == PIPE_BUFFER) {
 220                 fprintf(stderr, "VM start=0x%"PRIX64"  end=0x%"PRIX64" | Buffer %"PRIu64" bytes\n",
 221                         res->gpu_address, res->gpu_address + res->buf->size,
 222                         res->buf->size);
 223         }
 224         return true;
 225 }
 226
 227 static void r600_buffer_destroy(struct pipe_screen *screen,
 228                                 struct pipe_resource *buf)
 229 {
 230         struct r600_resource *rbuffer = r600_resource(buf);
 231
 232         threaded_resource_deinit(buf);
 233         util_range_destroy(&rbuffer->valid_buffer_range);
 234         pipe_resource_reference((struct pipe_resource**)&rbuffer->immed_buffer, NULL);
 235         pb_reference(&rbuffer->buf, NULL);
 236         FREE(rbuffer);
 237 }
 238
 239 static bool
 240 r600_invalidate_buffer(struct r600_common_context *rctx,
 241                        struct r600_resource *rbuffer)
 242 {
 243         /* Shared buffers can't be reallocated. */
 244         if (rbuffer->b.is_shared)
 245                 return false;
 246
 247         /* Sparse buffers can't be reallocated. */
 248         if (rbuffer->flags & RADEON_FLAG_SPARSE)
 249                 return false;
 250
 251         /* In AMD_pinned_memory, the user pointer association only gets
 252          * broken when the buffer is explicitly re-allocated.
 253          */
 254         if (rbuffer->b.is_user_ptr)
 255                 return false;
 256
 257         /* Check if mapping this buffer would cause waiting for the GPU. */
 258         if (r600_rings_is_buffer_referenced(rctx, rbuffer->buf, RADEON_USAGE_READWRITE) ||
 259             !rctx->ws->buffer_wait(rbuffer->buf, 0, RADEON_USAGE_READWRITE)) {
 260                 rctx->invalidate_buffer(&rctx->b, &rbuffer->b.b);
 261         } else {
 262                 util_range_set_empty(&rbuffer->valid_buffer_range);
 263         }
 264
 265         return true;
 266 }
 267
 268 /* Replace the storage of dst with src. */
 269 void r600_replace_buffer_storage(struct pipe_context *ctx,
 270                                  struct pipe_resource *dst,
 271                                  struct pipe_resource *src)
 272 {
 273         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 274         struct r600_resource *rdst = r600_resource(dst);
 275         struct r600_resource *rsrc = r600_resource(src);
 276         uint64_t old_gpu_address = rdst->gpu_address;
 277
 278         pb_reference(&rdst->buf, rsrc->buf);
 279         rdst->gpu_address = rsrc->gpu_address;
 280         rdst->b.b.bind = rsrc->b.b.bind;
 281         rdst->flags = rsrc->flags;
 282
 283         assert(rdst->vram_usage == rsrc->vram_usage);
 284         assert(rdst->gart_usage == rsrc->gart_usage);
 285         assert(rdst->bo_size == rsrc->bo_size);
 286         assert(rdst->bo_alignment == rsrc->bo_alignment);
 287         assert(rdst->domains == rsrc->domains);
 288
 289         rctx->rebind_buffer(ctx, dst, old_gpu_address);
 290 }
 291
 292 void r600_invalidate_resource(struct pipe_context *ctx,
 293                               struct pipe_resource *resource)
 294 {
 295         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 296         struct r600_resource *rbuffer = r600_resource(resource);
 297
 298         /* We currently only do anyting here for buffers */
 299         if (resource->target == PIPE_BUFFER)
 300                 (void)r600_invalidate_buffer(rctx, rbuffer);
 301 }
 302
 303 static void *r600_buffer_get_transfer(struct pipe_context *ctx,
 304                                       struct pipe_resource *resource,
 305                                       unsigned usage,
 306                                       const struct pipe_box *box,
 307                                       struct pipe_transfer **ptransfer,
 308                                       void *data, struct r600_resource *staging,
 309                                       unsigned offset)
 310 {
 311         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 312         struct r600_transfer *transfer;
 313
 314         if (usage & TC_TRANSFER_MAP_THREADED_UNSYNC)
 315                 transfer = slab_alloc(&rctx->pool_transfers_unsync);
 316         else
 317                 transfer = slab_alloc(&rctx->pool_transfers);
 318
 319         transfer->b.b.resource = NULL;
 320         pipe_resource_reference(&transfer->b.b.resource, resource);
 321         transfer->b.b.level = 0;
 322         transfer->b.b.usage = usage;
 323         transfer->b.b.box = *box;
 324         transfer->b.b.stride = 0;
 325         transfer->b.b.layer_stride = 0;
 326         transfer->b.staging = NULL;
 327         transfer->offset = offset;
 328         transfer->staging = staging;
 329         *ptransfer = &transfer->b.b;
 330         return data;
 331 }
 332
 333 static bool r600_can_dma_copy_buffer(struct r600_common_context *rctx,
 334                                      unsigned dstx, unsigned srcx, unsigned size)
 335 {
 336         bool dword_aligned = !(dstx % 4) && !(srcx % 4) && !(size % 4);
 337
 338         return rctx->screen->has_cp_dma ||
 339                (dword_aligned && (rctx->dma.cs ||
 340                                   rctx->screen->has_streamout));
 341
 342 }
 343
 344 static void *r600_buffer_transfer_map(struct pipe_context *ctx,
 345                                       struct pipe_resource *resource,
 346                                       unsigned level,
 347                                       unsigned usage,
 348                                       const struct pipe_box *box,
 349                                       struct pipe_transfer **ptransfer)
 350 {
 351         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 352         struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
 353         struct r600_resource *rbuffer = r600_resource(resource);
 354         uint8_t *data;
 355
 356         assert(box->x + box->width <= resource->width0);
 357
 358         /* From GL_AMD_pinned_memory issues:
 359          *
 360          *     4) Is glMapBuffer on a shared buffer guaranteed to return the
 361          *        same system address which was specified at creation time?
 362          *
 363          *        RESOLVED: NO. The GL implementation might return a different
 364          *        virtual mapping of that memory, although the same physical
 365          *        page will be used.
 366          *
 367          * So don't ever use staging buffers.
 368          */
 369         if (rbuffer->b.is_user_ptr)
 370                 usage |= PIPE_TRANSFER_PERSISTENT;
 371
 372         /* See if the buffer range being mapped has never been initialized,
 373          * in which case it can be mapped unsynchronized. */
 374         if (!(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
 375                        TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED)) &&
 376             usage & PIPE_TRANSFER_WRITE &&
 377             !rbuffer->b.is_shared &&
 378             !util_ranges_intersect(&rbuffer->valid_buffer_range, box->x, box->x + box->width)) {
 379                 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 380         }
 381
 382         /* If discarding the entire range, discard the whole resource instead. */
 383         if (usage & PIPE_TRANSFER_DISCARD_RANGE &&
 384             box->x == 0 && box->width == resource->width0) {
 385                 usage |= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE;
 386         }
 387
 388         if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE &&
 389             !(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
 390                        TC_TRANSFER_MAP_NO_INVALIDATE))) {
 391                 assert(usage & PIPE_TRANSFER_WRITE);
 392
 393                 if (r600_invalidate_buffer(rctx, rbuffer)) {
 394                         /* At this point, the buffer is always idle. */
 395                         usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 396                 } else {
 397                         /* Fall back to a temporary buffer. */
 398                         usage |= PIPE_TRANSFER_DISCARD_RANGE;
 399                 }
 400         }
 401
 402         if ((usage & PIPE_TRANSFER_DISCARD_RANGE) &&
 403             !(rscreen->debug_flags & DBG_NO_DISCARD_RANGE) &&
 404             ((!(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
 405                          PIPE_TRANSFER_PERSISTENT)) &&
 406               r600_can_dma_copy_buffer(rctx, box->x, 0, box->width)) ||
 407              (rbuffer->flags & RADEON_FLAG_SPARSE))) {
 408                 assert(usage & PIPE_TRANSFER_WRITE);
 409
 410                 /* Check if mapping this buffer would cause waiting for the GPU.
 411                  */
 412                 if (rbuffer->flags & RADEON_FLAG_SPARSE ||
 413                     r600_rings_is_buffer_referenced(rctx, rbuffer->buf, RADEON_USAGE_READWRITE) ||
 414                     !rctx->ws->buffer_wait(rbuffer->buf, 0, RADEON_USAGE_READWRITE)) {
 415                         /* Do a wait-free write-only transfer using a temporary buffer. */
 416                         unsigned offset;
 417                         struct r600_resource *staging = NULL;
 418
 419                         u_upload_alloc(ctx->stream_uploader, 0,
 420                                        box->width + (box->x % R600_MAP_BUFFER_ALIGNMENT),
 421                                        rctx->screen->info.tcc_cache_line_size,
 422                                        &offset, (struct pipe_resource**)&staging,
 423                                        (void**)&data);
 424
 425                         if (staging) {
 426                                 data += box->x % R600_MAP_BUFFER_ALIGNMENT;
 427                                 return r600_buffer_get_transfer(ctx, resource, usage, box,
 428                                                                 ptransfer, data, staging, offset);
 429                         } else if (rbuffer->flags & RADEON_FLAG_SPARSE) {
 430                                 return NULL;
 431                         }
 432                 } else {
 433                         /* At this point, the buffer is always idle (we checked it above). */
 434                         usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 435                 }
 436         }
 437         /* Use a staging buffer in cached GTT for reads. */
 438         else if (((usage & PIPE_TRANSFER_READ) &&
 439                   !(usage & PIPE_TRANSFER_PERSISTENT) &&
 440                   (rbuffer->domains & RADEON_DOMAIN_VRAM ||
 441                    rbuffer->flags & RADEON_FLAG_GTT_WC) &&
 442                   r600_can_dma_copy_buffer(rctx, 0, box->x, box->width)) ||
 443                  (rbuffer->flags & RADEON_FLAG_SPARSE)) {
 444                 struct r600_resource *staging;
 445
 446                 assert(!(usage & TC_TRANSFER_MAP_THREADED_UNSYNC));
 447                 staging = (struct r600_resource*) pipe_buffer_create(
 448                                 ctx->screen, 0, PIPE_USAGE_STAGING,
 449                                 box->width + (box->x % R600_MAP_BUFFER_ALIGNMENT));
 450                 if (staging) {
 451                         /* Copy the VRAM buffer to the staging buffer. */
 452                         rctx->dma_copy(ctx, &staging->b.b, 0,
 453                                        box->x % R600_MAP_BUFFER_ALIGNMENT,
 454                                        0, 0, resource, 0, box);
 455
 456                         data = r600_buffer_map_sync_with_rings(rctx, staging,
 457                                                                usage & ~PIPE_TRANSFER_UNSYNCHRONIZED);
 458                         if (!data) {
 459                                 r600_resource_reference(&staging, NULL);
 460                                 return NULL;
 461                         }
 462                         data += box->x % R600_MAP_BUFFER_ALIGNMENT;
 463
 464                         return r600_buffer_get_transfer(ctx, resource, usage, box,
 465                                                         ptransfer, data, staging, 0);
 466                 } else if (rbuffer->flags & RADEON_FLAG_SPARSE) {
 467                         return NULL;
 468                 }
 469         }
 470
 471         data = r600_buffer_map_sync_with_rings(rctx, rbuffer, usage);
 472         if (!data) {
 473                 return NULL;
 474         }
 475         data += box->x;
 476
 477         return r600_buffer_get_transfer(ctx, resource, usage, box,
 478                                         ptransfer, data, NULL, 0);
 479 }
 480
 481 static void r600_buffer_do_flush_region(struct pipe_context *ctx,
 482                                         struct pipe_transfer *transfer,
 483                                         const struct pipe_box *box)
 484 {
 485         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 486         struct r600_resource *rbuffer = r600_resource(transfer->resource);
 487
 488         if (rtransfer->staging) {
 489                 struct pipe_resource *dst, *src;
 490                 unsigned soffset;
 491                 struct pipe_box dma_box;
 492
 493                 dst = transfer->resource;
 494                 src = &rtransfer->staging->b.b;
 495                 soffset = rtransfer->offset + box->x % R600_MAP_BUFFER_ALIGNMENT;
 496
 497                 u_box_1d(soffset, box->width, &dma_box);
 498
 499                 /* Copy the staging buffer into the original one. */
 500                 ctx->resource_copy_region(ctx, dst, 0, box->x, 0, 0, src, 0, &dma_box);
 501         }
 502
 503         util_range_add(&rbuffer->valid_buffer_range, box->x,
 504                        box->x + box->width);
 505 }
 506
 507 static void r600_buffer_flush_region(struct pipe_context *ctx,
 508                                      struct pipe_transfer *transfer,
 509                                      const struct pipe_box *rel_box)
 510 {
 511         unsigned required_usage = PIPE_TRANSFER_WRITE |
 512                                   PIPE_TRANSFER_FLUSH_EXPLICIT;
 513
 514         if ((transfer->usage & required_usage) == required_usage) {
 515                 struct pipe_box box;
 516
 517                 u_box_1d(transfer->box.x + rel_box->x, rel_box->width, &box);
 518                 r600_buffer_do_flush_region(ctx, transfer, &box);
 519         }
 520 }
 521
 522 static void r600_buffer_transfer_unmap(struct pipe_context *ctx,
 523                                        struct pipe_transfer *transfer)
 524 {
 525         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 526         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 527
 528         if (transfer->usage & PIPE_TRANSFER_WRITE &&
 529             !(transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT))
 530                 r600_buffer_do_flush_region(ctx, transfer, &transfer->box);
 531
 532         r600_resource_reference(&rtransfer->staging, NULL);
 533         assert(rtransfer->b.staging == NULL); /* for threaded context only */
 534         pipe_resource_reference(&transfer->resource, NULL);
 535
 536         /* Don't use pool_transfers_unsync. We are always in the driver
 537          * thread. */
 538         slab_free(&rctx->pool_transfers, transfer);
 539 }
 540
 541 void r600_buffer_subdata(struct pipe_context *ctx,
 542                          struct pipe_resource *buffer,
 543                          unsigned usage, unsigned offset,
 544                          unsigned size, const void *data)
 545 {
 546         struct pipe_transfer *transfer = NULL;
 547         struct pipe_box box;
 548         uint8_t *map = NULL;
 549
 550         u_box_1d(offset, size, &box);
 551         map = r600_buffer_transfer_map(ctx, buffer, 0,
 552                                        PIPE_TRANSFER_WRITE |
 553                                        PIPE_TRANSFER_DISCARD_RANGE |
 554                                        usage,
 555                                        &box, &transfer);
 556         if (!map)
 557                 return;
 558
 559         memcpy(map, data, size);
 560         r600_buffer_transfer_unmap(ctx, transfer);
 561 }
 562
 563 static const struct u_resource_vtbl r600_buffer_vtbl =
 564 {
 565         NULL,                           /* get_handle */
 566         r600_buffer_destroy,            /* resource_destroy */
 567         r600_buffer_transfer_map,       /* transfer_map */
 568         r600_buffer_flush_region,       /* transfer_flush_region */
 569         r600_buffer_transfer_unmap,     /* transfer_unmap */
 570 };
 571
 572 static struct r600_resource *
 573 r600_alloc_buffer_struct(struct pipe_screen *screen,
 574                          const struct pipe_resource *templ)
 575 {
 576         struct r600_resource *rbuffer;
 577
 578         rbuffer = MALLOC_STRUCT(r600_resource);
 579
 580         rbuffer->b.b = *templ;
 581         rbuffer->b.b.next = NULL;
 582         pipe_reference_init(&rbuffer->b.b.reference, 1);
 583         rbuffer->b.b.screen = screen;
 584
 585         rbuffer->b.vtbl = &r600_buffer_vtbl;
 586         threaded_resource_init(&rbuffer->b.b);
 587
 588         rbuffer->buf = NULL;
 589         rbuffer->bind_history = 0;
 590         rbuffer->immed_buffer = NULL;
 591         util_range_init(&rbuffer->valid_buffer_range);
 592         return rbuffer;
 593 }
 594
 595 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 596                                          const struct pipe_resource *templ,
 597                                          unsigned alignment)
 598 {
 599         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 600         struct r600_resource *rbuffer = r600_alloc_buffer_struct(screen, templ);
 601
 602         r600_init_resource_fields(rscreen, rbuffer, templ->width0, alignment);
 603
 604         if (templ->flags & PIPE_RESOURCE_FLAG_SPARSE)
 605                 rbuffer->flags |= RADEON_FLAG_SPARSE;
 606
 607         if (!r600_alloc_resource(rscreen, rbuffer)) {
 608                 FREE(rbuffer);
 609                 return NULL;
 610         }
 611         return &rbuffer->b.b;
 612 }
 613
 614 struct pipe_resource *r600_aligned_buffer_create(struct pipe_screen *screen,
 615                                                  unsigned flags,
 616                                                  unsigned usage,
 617                                                  unsigned size,
 618                                                  unsigned alignment)
 619 {
 620         struct pipe_resource buffer;
 621
 622         memset(&buffer, 0, sizeof buffer);
 623         buffer.target = PIPE_BUFFER;
 624         buffer.format = PIPE_FORMAT_R8_UNORM;
 625         buffer.bind = 0;
 626         buffer.usage = usage;
 627         buffer.flags = flags;
 628         buffer.width0 = size;
 629         buffer.height0 = 1;
 630         buffer.depth0 = 1;
 631         buffer.array_size = 1;
 632         return r600_buffer_create(screen, &buffer, alignment);
 633 }
 634
 635 struct pipe_resource *
 636 r600_buffer_from_user_memory(struct pipe_screen *screen,
 637                              const struct pipe_resource *templ,
 638                              void *user_memory)
 639 {
 640         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 641         struct radeon_winsys *ws = rscreen->ws;
 642         struct r600_resource *rbuffer = r600_alloc_buffer_struct(screen, templ);
 643
 644         rbuffer->domains = RADEON_DOMAIN_GTT;
 645         rbuffer->flags = 0;
 646         rbuffer->b.is_user_ptr = true;
 647         util_range_add(&rbuffer->valid_buffer_range, 0, templ->width0);
 648         util_range_add(&rbuffer->b.valid_buffer_range, 0, templ->width0);
 649
 650         /* Convert a user pointer to a buffer. */
 651         rbuffer->buf = ws->buffer_from_ptr(ws, user_memory, templ->width0);
 652         if (!rbuffer->buf) {
 653                 FREE(rbuffer);
 654                 return NULL;
 655         }
 656
 657         if (rscreen->info.r600_has_virtual_memory)
 658                 rbuffer->gpu_address =
 659                         ws->buffer_get_virtual_address(rbuffer->buf);
 660         else
 661                 rbuffer->gpu_address = 0;
 662
 663         rbuffer->vram_usage = 0;
 664         rbuffer->gart_usage = templ->width0;
 665
 666         return &rbuffer->b.b;
 667 }