2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include <util/u_inlines.h>
29 #include <util/u_format.h>
30 #include <util/u_memory.h>
31 #include <util/u_blitter.h>
32 #include "r600_resource.h"
33 #include "r600_screen.h"
34 #include "r600_context.h"
36 static void r600_destroy_context(struct pipe_context
*context
)
38 struct r600_context
*rctx
= r600_context(context
);
43 static void r600_flush(struct pipe_context
*ctx
, unsigned flags
,
44 struct pipe_fence_handle
**fence
)
46 struct r600_context
*rctx
= r600_context(ctx
);
47 struct r600_screen
*rscreen
= rctx
->screen
;
50 if (radeon_ctx_pm4(rctx
->ctx
))
52 /* FIXME dumping should be removed once shader support instructions
53 * without throwing bad code
56 radeon_ctx_dump_bof(rctx
->ctx
, "gallium.bof");
58 radeon_ctx_submit(rctx
->ctx
);
60 rctx
->ctx
= radeon_ctx_decref(rctx
->ctx
);
61 rctx
->ctx
= radeon_ctx(rscreen
->rw
);
65 struct pipe_context
*r600_create_context(struct pipe_screen
*screen
, void *priv
)
67 struct r600_context
*rctx
= CALLOC_STRUCT(r600_context
);
68 struct r600_screen
* rscreen
= r600_screen(screen
);
72 rctx
->context
.winsys
= rscreen
->screen
.winsys
;
73 rctx
->context
.screen
= screen
;
74 rctx
->context
.priv
= priv
;
75 rctx
->context
.destroy
= r600_destroy_context
;
76 rctx
->context
.draw_arrays
= r600_draw_arrays
;
77 rctx
->context
.draw_elements
= r600_draw_elements
;
78 rctx
->context
.draw_range_elements
= r600_draw_range_elements
;
79 rctx
->context
.flush
= r600_flush
;
81 /* Easy accessing of screen/winsys. */
82 rctx
->screen
= rscreen
;
83 rctx
->rw
= rscreen
->rw
;
85 r600_init_blit_functions(rctx
);
86 r600_init_query_functions(rctx
);
87 r600_init_state_functions(rctx
);
88 r600_init_context_resource_functions(rctx
);
90 rctx
->blitter
= util_blitter_create(&rctx
->context
);
91 if (rctx
->blitter
== NULL
) {
96 rctx
->cb_cntl
= radeon_state(rscreen
->rw
, R600_CB_CNTL_TYPE
, R600_CB_CNTL
);
97 rctx
->cb_cntl
->states
[R600_CB_CNTL__CB_SHADER_MASK
] = 0x0000000F;
98 rctx
->cb_cntl
->states
[R600_CB_CNTL__CB_TARGET_MASK
] = 0x0000000F;
99 rctx
->cb_cntl
->states
[R600_CB_CNTL__CB_COLOR_CONTROL
] = 0x00CC0000;
100 rctx
->cb_cntl
->states
[R600_CB_CNTL__PA_SC_AA_CONFIG
] = 0x00000000;
101 rctx
->cb_cntl
->states
[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX
] = 0x00000000;
102 rctx
->cb_cntl
->states
[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX
] = 0x00000000;
103 rctx
->cb_cntl
->states
[R600_CB_CNTL__CB_CLRCMP_CONTROL
] = 0x01000000;
104 rctx
->cb_cntl
->states
[R600_CB_CNTL__CB_CLRCMP_SRC
] = 0x00000000;
105 rctx
->cb_cntl
->states
[R600_CB_CNTL__CB_CLRCMP_DST
] = 0x000000FF;
106 rctx
->cb_cntl
->states
[R600_CB_CNTL__CB_CLRCMP_MSK
] = 0xFFFFFFFF;
107 rctx
->cb_cntl
->states
[R600_CB_CNTL__PA_SC_AA_MASK
] = 0xFFFFFFFF;
108 radeon_state_pm4(rctx
->cb_cntl
);
110 rctx
->config
= radeon_state(rscreen
->rw
, R600_CONFIG_TYPE
, R600_CONFIG
);
111 rctx
->config
->states
[R600_CONFIG__SQ_CONFIG
] = 0xE400000C;
112 rctx
->config
->states
[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1
] = 0x403800C0;
113 rctx
->config
->states
[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2
] = 0x00000000;
114 rctx
->config
->states
[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT
] = 0x00003090;
115 rctx
->config
->states
[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1
] = 0x00800080;
116 rctx
->config
->states
[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2
] = 0x00000000;
117 rctx
->config
->states
[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
] = 0x00004000;
118 rctx
->config
->states
[R600_CONFIG__TA_CNTL_AUX
] = 0x07000002;
119 rctx
->config
->states
[R600_CONFIG__VC_ENHANCE
] = 0x00000000;
120 rctx
->config
->states
[R600_CONFIG__DB_DEBUG
] = 0x00000000;
121 rctx
->config
->states
[R600_CONFIG__DB_WATERMARKS
] = 0x00420204;
122 rctx
->config
->states
[R600_CONFIG__SX_MISC
] = 0x00000000;
123 rctx
->config
->states
[R600_CONFIG__SPI_THREAD_GROUPING
] = 0x00000001;
124 rctx
->config
->states
[R600_CONFIG__CB_SHADER_CONTROL
] = 0x00000003;
125 rctx
->config
->states
[R600_CONFIG__SQ_ESGS_RING_ITEMSIZE
] = 0x00000000;
126 rctx
->config
->states
[R600_CONFIG__SQ_GSVS_RING_ITEMSIZE
] = 0x00000000;
127 rctx
->config
->states
[R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE
] = 0x00000000;
128 rctx
->config
->states
[R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE
] = 0x00000000;
129 rctx
->config
->states
[R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE
] = 0x00000000;
130 rctx
->config
->states
[R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE
] = 0x00000000;
131 rctx
->config
->states
[R600_CONFIG__SQ_FBUF_RING_ITEMSIZE
] = 0x00000000;
132 rctx
->config
->states
[R600_CONFIG__SQ_REDUC_RING_ITEMSIZE
] = 0x00000000;
133 rctx
->config
->states
[R600_CONFIG__SQ_GS_VERT_ITEMSIZE
] = 0x00000000;
134 rctx
->config
->states
[R600_CONFIG__VGT_OUTPUT_PATH_CNTL
] = 0x00000000;
135 rctx
->config
->states
[R600_CONFIG__VGT_HOS_CNTL
] = 0x00000000;
136 rctx
->config
->states
[R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL
] = 0x00000000;
137 rctx
->config
->states
[R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL
] = 0x00000000;
138 rctx
->config
->states
[R600_CONFIG__VGT_HOS_REUSE_DEPTH
] = 0x00000000;
139 rctx
->config
->states
[R600_CONFIG__VGT_GROUP_PRIM_TYPE
] = 0x00000000;
140 rctx
->config
->states
[R600_CONFIG__VGT_GROUP_FIRST_DECR
] = 0x00000000;
141 rctx
->config
->states
[R600_CONFIG__VGT_GROUP_DECR
] = 0x00000000;
142 rctx
->config
->states
[R600_CONFIG__VGT_GROUP_VECT_0_CNTL
] = 0x00000000;
143 rctx
->config
->states
[R600_CONFIG__VGT_GROUP_VECT_1_CNTL
] = 0x00000000;
144 rctx
->config
->states
[R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL
] = 0x00000000;
145 rctx
->config
->states
[R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL
] = 0x00000000;
146 rctx
->config
->states
[R600_CONFIG__VGT_GS_MODE
] = 0x00000000;
147 rctx
->config
->states
[R600_CONFIG__PA_SC_MODE_CNTL
] = 0x00514000;
148 rctx
->config
->states
[R600_CONFIG__VGT_STRMOUT_EN
] = 0x00000000;
149 rctx
->config
->states
[R600_CONFIG__VGT_REUSE_OFF
] = 0x00000001;
150 rctx
->config
->states
[R600_CONFIG__VGT_VTX_CNT_EN
] = 0x00000000;
151 rctx
->config
->states
[R600_CONFIG__VGT_STRMOUT_BUFFER_EN
] = 0x00000000;
152 radeon_state_pm4(rctx
->config
);
154 rctx
->ctx
= radeon_ctx(rscreen
->rw
);
155 rctx
->draw
= radeon_draw(rscreen
->rw
);
156 return &rctx
->context
;