src/gallium/drivers/r600/r600_context.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  *      Corbin Simpson
  26  */
  27 #include <stdio.h>
  28 #include <util/u_inlines.h>
  29 #include <util/u_format.h>
  30 #include <util/u_memory.h>
  31 #include <util/u_blitter.h>
  32 #include "r600_screen.h"
  33 #include "r600_context.h"
  34 #include "r600_resource.h"
  35 #include "r600d.h"
  36
  37
  38 static void r600_destroy_context(struct pipe_context *context)
  39 {
  40         struct r600_context *rctx = r600_context(context);
  41
  42         rctx->rasterizer = r600_context_state_decref(rctx->rasterizer);
  43         rctx->poly_stipple = r600_context_state_decref(rctx->poly_stipple);
  44         rctx->scissor = r600_context_state_decref(rctx->scissor);
  45         rctx->clip = r600_context_state_decref(rctx->clip);
  46         rctx->ps_shader = r600_context_state_decref(rctx->ps_shader);
  47         rctx->vs_shader = r600_context_state_decref(rctx->vs_shader);
  48         rctx->depth = r600_context_state_decref(rctx->depth);
  49         rctx->stencil = r600_context_state_decref(rctx->stencil);
  50         rctx->alpha = r600_context_state_decref(rctx->alpha);
  51         rctx->dsa = r600_context_state_decref(rctx->dsa);
  52         rctx->blend = r600_context_state_decref(rctx->blend);
  53         rctx->stencil_ref = r600_context_state_decref(rctx->stencil_ref);
  54         rctx->viewport = r600_context_state_decref(rctx->viewport);
  55         rctx->framebuffer = r600_context_state_decref(rctx->framebuffer);
  56
  57         free(rctx->ps_constant);
  58         free(rctx->vs_constant);
  59         free(rctx->vs_resource);
  60
  61         radeon_ctx_fini(&rctx->ctx);
  62         FREE(rctx);
  63 }
  64
  65 void r600_flush(struct pipe_context *ctx, unsigned flags,
  66                         struct pipe_fence_handle **fence)
  67 {
  68         struct r600_context *rctx = r600_context(ctx);
  69         struct r600_query *rquery;
  70         static int dc = 0;
  71         char dname[256];
  72
  73         /* suspend queries */
  74         r600_queries_suspend(ctx);
  75         /* FIXME dumping should be removed once shader support instructions
  76          * without throwing bad code
  77          */
  78         if (!rctx->ctx.cdwords)
  79                 goto out;
  80 #if 0
  81         sprintf(dname, "gallium-%08d.bof", dc);
  82         if (dc < 2) {
  83                 radeon_ctx_dump_bof(&rctx->ctx, dname);
  84                 R600_ERR("dumped %s\n", dname);
  85         }
  86 #endif
  87 #if 1
  88         radeon_ctx_submit(&rctx->ctx);
  89 #endif
  90         LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) {
  91                 rquery->flushed = true;
  92         }
  93         dc++;
  94 out:
  95         radeon_ctx_clear(&rctx->ctx);
  96         /* resume queries */
  97         r600_queries_resume(ctx);
  98 }
  99
 100 static void r600_init_config(struct r600_context *rctx)
 101 {
 102         int ps_prio;
 103         int vs_prio;
 104         int gs_prio;
 105         int es_prio;
 106         int num_ps_gprs;
 107         int num_vs_gprs;
 108         int num_gs_gprs;
 109         int num_es_gprs;
 110         int num_temp_gprs;
 111         int num_ps_threads;
 112         int num_vs_threads;
 113         int num_gs_threads;
 114         int num_es_threads;
 115         int num_ps_stack_entries;
 116         int num_vs_stack_entries;
 117         int num_gs_stack_entries;
 118         int num_es_stack_entries;
 119         enum radeon_family family;
 120
 121         family = radeon_get_family(rctx->rw);
 122         ps_prio = 0;
 123         vs_prio = 1;
 124         gs_prio = 2;
 125         es_prio = 3;
 126         switch (family) {
 127         case CHIP_R600:
 128                 num_ps_gprs = 192;
 129                 num_vs_gprs = 56;
 130                 num_temp_gprs = 4;
 131                 num_gs_gprs = 0;
 132                 num_es_gprs = 0;
 133                 num_ps_threads = 136;
 134                 num_vs_threads = 48;
 135                 num_gs_threads = 4;
 136                 num_es_threads = 4;
 137                 num_ps_stack_entries = 128;
 138                 num_vs_stack_entries = 128;
 139                 num_gs_stack_entries = 0;
 140                 num_es_stack_entries = 0;
 141                 break;
 142         case CHIP_RV630:
 143         case CHIP_RV635:
 144                 num_ps_gprs = 84;
 145                 num_vs_gprs = 36;
 146                 num_temp_gprs = 4;
 147                 num_gs_gprs = 0;
 148                 num_es_gprs = 0;
 149                 num_ps_threads = 144;
 150                 num_vs_threads = 40;
 151                 num_gs_threads = 4;
 152                 num_es_threads = 4;
 153                 num_ps_stack_entries = 40;
 154                 num_vs_stack_entries = 40;
 155                 num_gs_stack_entries = 32;
 156                 num_es_stack_entries = 16;
 157                 break;
 158         case CHIP_RV610:
 159         case CHIP_RV620:
 160         case CHIP_RS780:
 161         case CHIP_RS880:
 162         default:
 163                 num_ps_gprs = 84;
 164                 num_vs_gprs = 36;
 165                 num_temp_gprs = 4;
 166                 num_gs_gprs = 0;
 167                 num_es_gprs = 0;
 168                 num_ps_threads = 136;
 169                 num_vs_threads = 48;
 170                 num_gs_threads = 4;
 171                 num_es_threads = 4;
 172                 num_ps_stack_entries = 40;
 173                 num_vs_stack_entries = 40;
 174                 num_gs_stack_entries = 32;
 175                 num_es_stack_entries = 16;
 176                 break;
 177         case CHIP_RV670:
 178                 num_ps_gprs = 144;
 179                 num_vs_gprs = 40;
 180                 num_temp_gprs = 4;
 181                 num_gs_gprs = 0;
 182                 num_es_gprs = 0;
 183                 num_ps_threads = 136;
 184                 num_vs_threads = 48;
 185                 num_gs_threads = 4;
 186                 num_es_threads = 4;
 187                 num_ps_stack_entries = 40;
 188                 num_vs_stack_entries = 40;
 189                 num_gs_stack_entries = 32;
 190                 num_es_stack_entries = 16;
 191                 break;
 192         case CHIP_RV770:
 193                 num_ps_gprs = 192;
 194                 num_vs_gprs = 56;
 195                 num_temp_gprs = 4;
 196                 num_gs_gprs = 0;
 197                 num_es_gprs = 0;
 198                 num_ps_threads = 188;
 199                 num_vs_threads = 60;
 200                 num_gs_threads = 0;
 201                 num_es_threads = 0;
 202                 num_ps_stack_entries = 256;
 203                 num_vs_stack_entries = 256;
 204                 num_gs_stack_entries = 0;
 205                 num_es_stack_entries = 0;
 206                 break;
 207         case CHIP_RV730:
 208         case CHIP_RV740:
 209                 num_ps_gprs = 84;
 210                 num_vs_gprs = 36;
 211                 num_temp_gprs = 4;
 212                 num_gs_gprs = 0;
 213                 num_es_gprs = 0;
 214                 num_ps_threads = 188;
 215                 num_vs_threads = 60;
 216                 num_gs_threads = 0;
 217                 num_es_threads = 0;
 218                 num_ps_stack_entries = 128;
 219                 num_vs_stack_entries = 128;
 220                 num_gs_stack_entries = 0;
 221                 num_es_stack_entries = 0;
 222                 break;
 223         case CHIP_RV710:
 224                 num_ps_gprs = 192;
 225                 num_vs_gprs = 56;
 226                 num_temp_gprs = 4;
 227                 num_gs_gprs = 0;
 228                 num_es_gprs = 0;
 229                 num_ps_threads = 144;
 230                 num_vs_threads = 48;
 231                 num_gs_threads = 0;
 232                 num_es_threads = 0;
 233                 num_ps_stack_entries = 128;
 234                 num_vs_stack_entries = 128;
 235                 num_gs_stack_entries = 0;
 236                 num_es_stack_entries = 0;
 237                 break;
 238         }
 239         radeon_state_init(&rctx->config, rctx->rw, R600_STATE_CONFIG, 0, 0);
 240
 241         rctx->config.states[R600_CONFIG__SQ_CONFIG] = 0x00000000;
 242         switch (family) {
 243         case CHIP_RV610:
 244         case CHIP_RV620:
 245         case CHIP_RS780:
 246         case CHIP_RS880:
 247         case CHIP_RV710:
 248                 break;
 249         default:
 250                 rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VC_ENABLE(1);
 251                 break;
 252         }
 253         rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_DX9_CONSTS(1);
 254         rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ALU_INST_PREFER_VECTOR(1);
 255         rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_PS_PRIO(ps_prio);
 256         rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VS_PRIO(vs_prio);
 257         rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_GS_PRIO(gs_prio);
 258         rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ES_PRIO(es_prio);
 259
 260         rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] = 0;
 261         rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
 262         rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
 263         rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
 264
 265         rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] = 0;
 266         rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
 267         rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_es_gprs);
 268
 269         rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] = 0;
 270         rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
 271         rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
 272         rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
 273         rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_ES_THREADS(num_es_threads);
 274
 275         rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] = 0;
 276         rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
 277         rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
 278
 279         rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] = 0;
 280         rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
 281         rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
 282
 283         rctx->config.states[R600_CONFIG__VC_ENHANCE] = 0x00000000;
 284         rctx->config.states[R600_CONFIG__SX_MISC] = 0x00000000;
 285
 286         if (family >= CHIP_RV770) {
 287                 rctx->config.states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00004000;
 288                 rctx->config.states[R600_CONFIG__TA_CNTL_AUX] = 0x07000002;
 289                 rctx->config.states[R600_CONFIG__DB_DEBUG] = 0x00000000;
 290                 rctx->config.states[R600_CONFIG__DB_WATERMARKS] = 0x00420204;
 291                 rctx->config.states[R600_CONFIG__SPI_THREAD_GROUPING] = 0x00000000;
 292                 rctx->config.states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00514000;
 293         } else {
 294                 rctx->config.states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00000000;
 295                 rctx->config.states[R600_CONFIG__TA_CNTL_AUX] = 0x07000003;
 296                 rctx->config.states[R600_CONFIG__DB_DEBUG] = 0x82000000;
 297                 rctx->config.states[R600_CONFIG__DB_WATERMARKS] = 0x01020204;
 298                 rctx->config.states[R600_CONFIG__SPI_THREAD_GROUPING] = 0x00000001;
 299                 rctx->config.states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00004010;
 300         }
 301         rctx->config.states[R600_CONFIG__CB_SHADER_CONTROL] = 0x00000003;
 302         rctx->config.states[R600_CONFIG__SQ_ESGS_RING_ITEMSIZE] = 0x00000000;
 303         rctx->config.states[R600_CONFIG__SQ_GSVS_RING_ITEMSIZE] = 0x00000000;
 304         rctx->config.states[R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE] = 0x00000000;
 305         rctx->config.states[R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE] = 0x00000000;
 306         rctx->config.states[R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE] = 0x00000000;
 307         rctx->config.states[R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE] = 0x00000000;
 308         rctx->config.states[R600_CONFIG__SQ_FBUF_RING_ITEMSIZE] = 0x00000000;
 309         rctx->config.states[R600_CONFIG__SQ_REDUC_RING_ITEMSIZE] = 0x00000000;
 310         rctx->config.states[R600_CONFIG__SQ_GS_VERT_ITEMSIZE] = 0x00000000;
 311         rctx->config.states[R600_CONFIG__VGT_OUTPUT_PATH_CNTL] = 0x00000000;
 312         rctx->config.states[R600_CONFIG__VGT_HOS_CNTL] = 0x00000000;
 313         rctx->config.states[R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL] = 0x00000000;
 314         rctx->config.states[R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL] = 0x00000000;
 315         rctx->config.states[R600_CONFIG__VGT_HOS_REUSE_DEPTH] = 0x00000000;
 316         rctx->config.states[R600_CONFIG__VGT_GROUP_PRIM_TYPE] = 0x00000000;
 317         rctx->config.states[R600_CONFIG__VGT_GROUP_FIRST_DECR] = 0x00000000;
 318         rctx->config.states[R600_CONFIG__VGT_GROUP_DECR] = 0x00000000;
 319         rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_0_CNTL] = 0x00000000;
 320         rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_1_CNTL] = 0x00000000;
 321         rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL] = 0x00000000;
 322         rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL] = 0x00000000;
 323         rctx->config.states[R600_CONFIG__VGT_GS_MODE] = 0x00000000;
 324         rctx->config.states[R600_CONFIG__VGT_STRMOUT_EN] = 0x00000000;
 325         rctx->config.states[R600_CONFIG__VGT_REUSE_OFF] = 0x00000001;
 326         rctx->config.states[R600_CONFIG__VGT_VTX_CNT_EN] = 0x00000000;
 327         rctx->config.states[R600_CONFIG__VGT_STRMOUT_BUFFER_EN] = 0x00000000;
 328         radeon_state_pm4(&rctx->config);
 329 }
 330
 331 struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 332 {
 333         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 334         struct r600_screen* rscreen = r600_screen(screen);
 335
 336         if (rctx == NULL)
 337                 return NULL;
 338         rctx->context.winsys = rscreen->screen.winsys;
 339         rctx->context.screen = screen;
 340         rctx->context.priv = priv;
 341         rctx->context.destroy = r600_destroy_context;
 342         rctx->context.draw_vbo = r600_draw_vbo;
 343         rctx->context.flush = r600_flush;
 344
 345         /* Easy accessing of screen/winsys. */
 346         rctx->screen = rscreen;
 347         rctx->rw = rscreen->rw;
 348
 349         r600_init_blit_functions(rctx);
 350         r600_init_query_functions(rctx);
 351         r600_init_state_functions(rctx);
 352         r600_init_context_resource_functions(rctx);
 353
 354         rctx->blitter = util_blitter_create(&rctx->context);
 355         if (rctx->blitter == NULL) {
 356                 FREE(rctx);
 357                 return NULL;
 358         }
 359
 360         r600_init_config(rctx);
 361
 362         rctx->vs_constant = (struct radeon_state *)calloc(R600_MAX_CONSTANT, sizeof(struct radeon_state));
 363         if (!rctx->vs_constant) {
 364                 FREE(rctx);
 365                 return NULL;
 366         }
 367
 368         rctx->ps_constant = (struct radeon_state *)calloc(R600_MAX_CONSTANT, sizeof(struct radeon_state));
 369         if (!rctx->ps_constant) {
 370                 FREE(rctx);
 371                 return NULL;
 372         }
 373
 374         rctx->vs_resource = (struct radeon_state *)calloc(R600_MAX_RESOURCE, sizeof(struct radeon_state));
 375         if (!rctx->vs_resource) {
 376                 FREE(rctx);
 377                 return NULL;
 378         }
 379
 380         radeon_ctx_init(&rctx->ctx, rscreen->rw);
 381         radeon_draw_init(&rctx->draw, rscreen->rw);
 382         return &rctx->context;
 383 }