2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include <util/u_inlines.h>
29 #include <util/u_format.h>
30 #include <util/u_memory.h>
31 #include <util/u_blitter.h>
32 #include "r600_screen.h"
33 #include "r600_context.h"
34 #include "r600_resource.h"
37 static void r600_destroy_context(struct pipe_context
*context
)
39 struct r600_context
*rctx
= r600_context(context
);
44 static void r600_flush(struct pipe_context
*ctx
, unsigned flags
,
45 struct pipe_fence_handle
**fence
)
47 struct r600_context
*rctx
= r600_context(ctx
);
48 struct r600_screen
*rscreen
= rctx
->screen
;
51 if (radeon_ctx_pm4(rctx
->ctx
))
53 /* FIXME dumping should be removed once shader support instructions
54 * without throwing bad code
57 radeon_ctx_dump_bof(rctx
->ctx
, "gallium.bof");
59 radeon_ctx_submit(rctx
->ctx
);
61 rctx
->ctx
= radeon_ctx_decref(rctx
->ctx
);
62 rctx
->ctx
= radeon_ctx(rscreen
->rw
);
66 static void r600_init_config(struct r600_context
*rctx
)
81 int num_ps_stack_entries
;
82 int num_vs_stack_entries
;
83 int num_gs_stack_entries
;
84 int num_es_stack_entries
;
85 enum radeon_family family
;
87 family
= radeon_get_family(rctx
->rw
);
103 num_ps_stack_entries
= 128;
104 num_vs_stack_entries
= 128;
105 num_gs_stack_entries
= 0;
106 num_es_stack_entries
= 0;
115 num_ps_threads
= 144;
119 num_ps_stack_entries
= 40;
120 num_vs_stack_entries
= 40;
121 num_gs_stack_entries
= 32;
122 num_es_stack_entries
= 16;
134 num_ps_threads
= 136;
138 num_ps_stack_entries
= 40;
139 num_vs_stack_entries
= 40;
140 num_gs_stack_entries
= 32;
141 num_es_stack_entries
= 16;
149 num_ps_threads
= 136;
153 num_ps_stack_entries
= 40;
154 num_vs_stack_entries
= 40;
155 num_gs_stack_entries
= 32;
156 num_es_stack_entries
= 16;
164 num_ps_threads
= 188;
168 num_ps_stack_entries
= 256;
169 num_vs_stack_entries
= 256;
170 num_gs_stack_entries
= 0;
171 num_es_stack_entries
= 0;
180 num_ps_threads
= 188;
184 num_ps_stack_entries
= 128;
185 num_vs_stack_entries
= 128;
186 num_gs_stack_entries
= 0;
187 num_es_stack_entries
= 0;
195 num_ps_threads
= 144;
199 num_ps_stack_entries
= 128;
200 num_vs_stack_entries
= 128;
201 num_gs_stack_entries
= 0;
202 num_es_stack_entries
= 0;
205 printf("ps_prio : %d\n", ps_prio
);
206 printf("vs_prio : %d\n", vs_prio
);
207 printf("gs_prio : %d\n", gs_prio
);
208 printf("es_prio : %d\n", es_prio
);
209 printf("num_ps_gprs : %d\n", num_ps_gprs
);
210 printf("num_vs_gprs : %d\n", num_vs_gprs
);
211 printf("num_gs_gprs : %d\n", num_gs_gprs
);
212 printf("num_es_gprs : %d\n", num_es_gprs
);
213 printf("num_temp_gprs : %d\n", num_temp_gprs
);
214 printf("num_ps_threads : %d\n", num_ps_threads
);
215 printf("num_vs_threads : %d\n", num_vs_threads
);
216 printf("num_gs_threads : %d\n", num_gs_threads
);
217 printf("num_es_threads : %d\n", num_es_threads
);
218 printf("num_ps_stack_entries : %d\n", num_ps_stack_entries
);
219 printf("num_vs_stack_entries : %d\n", num_vs_stack_entries
);
220 printf("num_gs_stack_entries : %d\n", num_gs_stack_entries
);
221 printf("num_es_stack_entries : %d\n", num_es_stack_entries
);
223 rctx
->hw_states
.config
= radeon_state(rctx
->rw
, R600_CONFIG_TYPE
, R600_CONFIG
);
225 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_CONFIG
] = 0x00000000;
234 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_CONFIG
] |= S_008C00_VC_ENABLE(1);
237 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_CONFIG
] |= S_008C00_DX9_CONSTS(1);
238 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_CONFIG
] |= S_008C00_ALU_INST_PREFER_VECTOR(1);
239 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_CONFIG
] |= S_008C00_PS_PRIO(ps_prio
);
240 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_CONFIG
] |= S_008C00_VS_PRIO(vs_prio
);
241 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_CONFIG
] |= S_008C00_GS_PRIO(gs_prio
);
242 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_CONFIG
] |= S_008C00_ES_PRIO(es_prio
);
244 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1
] = 0;
245 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1
] |= S_008C04_NUM_PS_GPRS(num_ps_gprs
);
246 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1
] |= S_008C04_NUM_VS_GPRS(num_vs_gprs
);
247 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1
] |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs
);
249 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2
] = 0;
250 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2
] |= S_008C08_NUM_GS_GPRS(num_gs_gprs
);
251 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2
] |= S_008C08_NUM_GS_GPRS(num_es_gprs
);
253 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT
] = 0;
254 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT
] |= S_008C0C_NUM_PS_THREADS(num_ps_threads
);
255 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT
] |= S_008C0C_NUM_VS_THREADS(num_vs_threads
);
256 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT
] |= S_008C0C_NUM_GS_THREADS(num_gs_threads
);
257 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT
] |= S_008C0C_NUM_ES_THREADS(num_es_threads
);
259 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1
] = 0;
260 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1
] |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries
);
261 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1
] |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries
);
263 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2
] = 0;
264 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2
] |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries
);
265 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2
] |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries
);
267 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
] = 0x00004000;
268 rctx
->hw_states
.config
->states
[R600_CONFIG__TA_CNTL_AUX
] = 0x07000002;
269 rctx
->hw_states
.config
->states
[R600_CONFIG__VC_ENHANCE
] = 0x00000000;
270 rctx
->hw_states
.config
->states
[R600_CONFIG__DB_DEBUG
] = 0x00000000;
271 rctx
->hw_states
.config
->states
[R600_CONFIG__DB_WATERMARKS
] = 0x00420204;
272 rctx
->hw_states
.config
->states
[R600_CONFIG__SX_MISC
] = 0x00000000;
273 rctx
->hw_states
.config
->states
[R600_CONFIG__SPI_THREAD_GROUPING
] = 0x00000001;
274 rctx
->hw_states
.config
->states
[R600_CONFIG__CB_SHADER_CONTROL
] = 0x00000003;
275 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_ESGS_RING_ITEMSIZE
] = 0x00000000;
276 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_GSVS_RING_ITEMSIZE
] = 0x00000000;
277 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE
] = 0x00000000;
278 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE
] = 0x00000000;
279 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE
] = 0x00000000;
280 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE
] = 0x00000000;
281 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_FBUF_RING_ITEMSIZE
] = 0x00000000;
282 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_REDUC_RING_ITEMSIZE
] = 0x00000000;
283 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_GS_VERT_ITEMSIZE
] = 0x00000000;
284 rctx
->hw_states
.config
->states
[R600_CONFIG__VGT_OUTPUT_PATH_CNTL
] = 0x00000000;
285 rctx
->hw_states
.config
->states
[R600_CONFIG__VGT_HOS_CNTL
] = 0x00000000;
286 rctx
->hw_states
.config
->states
[R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL
] = 0x00000000;
287 rctx
->hw_states
.config
->states
[R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL
] = 0x00000000;
288 rctx
->hw_states
.config
->states
[R600_CONFIG__VGT_HOS_REUSE_DEPTH
] = 0x00000000;
289 rctx
->hw_states
.config
->states
[R600_CONFIG__VGT_GROUP_PRIM_TYPE
] = 0x00000000;
290 rctx
->hw_states
.config
->states
[R600_CONFIG__VGT_GROUP_FIRST_DECR
] = 0x00000000;
291 rctx
->hw_states
.config
->states
[R600_CONFIG__VGT_GROUP_DECR
] = 0x00000000;
292 rctx
->hw_states
.config
->states
[R600_CONFIG__VGT_GROUP_VECT_0_CNTL
] = 0x00000000;
293 rctx
->hw_states
.config
->states
[R600_CONFIG__VGT_GROUP_VECT_1_CNTL
] = 0x00000000;
294 rctx
->hw_states
.config
->states
[R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL
] = 0x00000000;
295 rctx
->hw_states
.config
->states
[R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL
] = 0x00000000;
296 rctx
->hw_states
.config
->states
[R600_CONFIG__VGT_GS_MODE
] = 0x00000000;
297 rctx
->hw_states
.config
->states
[R600_CONFIG__PA_SC_MODE_CNTL
] = 0x00514000;
298 rctx
->hw_states
.config
->states
[R600_CONFIG__VGT_STRMOUT_EN
] = 0x00000000;
299 rctx
->hw_states
.config
->states
[R600_CONFIG__VGT_REUSE_OFF
] = 0x00000001;
300 rctx
->hw_states
.config
->states
[R600_CONFIG__VGT_VTX_CNT_EN
] = 0x00000000;
301 rctx
->hw_states
.config
->states
[R600_CONFIG__VGT_STRMOUT_BUFFER_EN
] = 0x00000000;
302 radeon_state_pm4(rctx
->hw_states
.config
);
305 struct pipe_context
*r600_create_context(struct pipe_screen
*screen
, void *priv
)
307 struct r600_context
*rctx
= CALLOC_STRUCT(r600_context
);
308 struct r600_screen
* rscreen
= r600_screen(screen
);
312 rctx
->context
.winsys
= rscreen
->screen
.winsys
;
313 rctx
->context
.screen
= screen
;
314 rctx
->context
.priv
= priv
;
315 rctx
->context
.destroy
= r600_destroy_context
;
316 rctx
->context
.draw_vbo
= r600_draw_vbo
;
317 rctx
->context
.flush
= r600_flush
;
319 /* Easy accessing of screen/winsys. */
320 rctx
->screen
= rscreen
;
321 rctx
->rw
= rscreen
->rw
;
323 r600_init_blit_functions(rctx
);
324 r600_init_query_functions(rctx
);
325 r600_init_state_functions(rctx
);
326 r600_init_context_resource_functions(rctx
);
328 rctx
->blitter
= util_blitter_create(&rctx
->context
);
329 if (rctx
->blitter
== NULL
) {
334 rctx
->hw_states
.cb_cntl
= radeon_state(rscreen
->rw
, R600_CB_CNTL_TYPE
, R600_CB_CNTL
);
335 rctx
->hw_states
.cb_cntl
->states
[R600_CB_CNTL__CB_SHADER_MASK
] = 0x0000000F;
336 rctx
->hw_states
.cb_cntl
->states
[R600_CB_CNTL__CB_TARGET_MASK
] = 0x0000000F;
337 rctx
->hw_states
.cb_cntl
->states
[R600_CB_CNTL__CB_COLOR_CONTROL
] = 0x00CC0000;
338 rctx
->hw_states
.cb_cntl
->states
[R600_CB_CNTL__PA_SC_AA_CONFIG
] = 0x00000000;
339 rctx
->hw_states
.cb_cntl
->states
[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX
] = 0x00000000;
340 rctx
->hw_states
.cb_cntl
->states
[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX
] = 0x00000000;
341 rctx
->hw_states
.cb_cntl
->states
[R600_CB_CNTL__CB_CLRCMP_CONTROL
] = 0x01000000;
342 rctx
->hw_states
.cb_cntl
->states
[R600_CB_CNTL__CB_CLRCMP_SRC
] = 0x00000000;
343 rctx
->hw_states
.cb_cntl
->states
[R600_CB_CNTL__CB_CLRCMP_DST
] = 0x000000FF;
344 rctx
->hw_states
.cb_cntl
->states
[R600_CB_CNTL__CB_CLRCMP_MSK
] = 0xFFFFFFFF;
345 rctx
->hw_states
.cb_cntl
->states
[R600_CB_CNTL__PA_SC_AA_MASK
] = 0xFFFFFFFF;
346 radeon_state_pm4(rctx
->hw_states
.cb_cntl
);
348 r600_init_config(rctx
);
350 rctx
->ctx
= radeon_ctx(rscreen
->rw
);
351 rctx
->draw
= radeon_draw(rscreen
->rw
);
352 return &rctx
->context
;