src/gallium/drivers/r600/r600_context.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  *      Corbin Simpson
  26  */
  27 #include <stdio.h>
  28 #include <util/u_inlines.h>
  29 #include <util/u_format.h>
  30 #include <util/u_memory.h>
  31 #include <util/u_blitter.h>
  32 #include "r600_resource.h"
  33 #include "r600_screen.h"
  34 #include "r600_context.h"
  35 #include "r600d.h"
  36
  37 static void r600_destroy_context(struct pipe_context *context)
  38 {
  39         struct r600_context *rctx = r600_context(context);
  40
  41         FREE(rctx);
  42 }
  43
  44 static void r600_flush(struct pipe_context *ctx, unsigned flags,
  45                         struct pipe_fence_handle **fence)
  46 {
  47         struct r600_context *rctx = r600_context(ctx);
  48         struct r600_screen *rscreen = rctx->screen;
  49         static int dc = 0;
  50
  51         if (radeon_ctx_pm4(rctx->ctx))
  52                 return;
  53         /* FIXME dumping should be removed once shader support instructions
  54          * without throwing bad code
  55          */
  56         if (!dc)
  57                 radeon_ctx_dump_bof(rctx->ctx, "gallium.bof");
  58 #if 1
  59         radeon_ctx_submit(rctx->ctx);
  60 #endif
  61         rctx->ctx = radeon_ctx_decref(rctx->ctx);
  62         rctx->ctx = radeon_ctx(rscreen->rw);
  63         dc++;
  64 }
  65
  66 static void r600_init_config(struct r600_context *rctx)
  67 {
  68         int ps_prio;
  69         int vs_prio;
  70         int gs_prio;
  71         int es_prio;
  72         int num_ps_gprs;
  73         int num_vs_gprs;
  74         int num_gs_gprs;
  75         int num_es_gprs;
  76         int num_temp_gprs;
  77         int num_ps_threads;
  78         int num_vs_threads;
  79         int num_gs_threads;
  80         int num_es_threads;
  81         int num_ps_stack_entries;
  82         int num_vs_stack_entries;
  83         int num_gs_stack_entries;
  84         int num_es_stack_entries;
  85         enum radeon_family family;
  86
  87         family = radeon_get_family(rctx->rw);
  88         ps_prio = 0;
  89         vs_prio = 1;
  90         gs_prio = 2;
  91         es_prio = 3;
  92         switch (family) {
  93         case CHIP_R600:
  94                 num_ps_gprs = 192;
  95                 num_vs_gprs = 56;
  96                 num_temp_gprs = 4;
  97                 num_gs_gprs = 0;
  98                 num_es_gprs = 0;
  99                 num_ps_threads = 136;
 100                 num_vs_threads = 48;
 101                 num_gs_threads = 4;
 102                 num_es_threads = 4;
 103                 num_ps_stack_entries = 128;
 104                 num_vs_stack_entries = 128;
 105                 num_gs_stack_entries = 0;
 106                 num_es_stack_entries = 0;
 107                 break;
 108         case CHIP_RV630:
 109         case CHIP_RV635:
 110                 num_ps_gprs = 84;
 111                 num_vs_gprs = 36;
 112                 num_temp_gprs = 4;
 113                 num_gs_gprs = 0;
 114                 num_es_gprs = 0;
 115                 num_ps_threads = 144;
 116                 num_vs_threads = 40;
 117                 num_gs_threads = 4;
 118                 num_es_threads = 4;
 119                 num_ps_stack_entries = 40;
 120                 num_vs_stack_entries = 40;
 121                 num_gs_stack_entries = 32;
 122                 num_es_stack_entries = 16;
 123                 break;
 124         case CHIP_RV610:
 125         case CHIP_RV620:
 126         case CHIP_RS780:
 127         case CHIP_RS880:
 128         default:
 129                 num_ps_gprs = 84;
 130                 num_vs_gprs = 36;
 131                 num_temp_gprs = 4;
 132                 num_gs_gprs = 0;
 133                 num_es_gprs = 0;
 134                 num_ps_threads = 136;
 135                 num_vs_threads = 48;
 136                 num_gs_threads = 4;
 137                 num_es_threads = 4;
 138                 num_ps_stack_entries = 40;
 139                 num_vs_stack_entries = 40;
 140                 num_gs_stack_entries = 32;
 141                 num_es_stack_entries = 16;
 142                 break;
 143         case CHIP_RV670:
 144                 num_ps_gprs = 144;
 145                 num_vs_gprs = 40;
 146                 num_temp_gprs = 4;
 147                 num_gs_gprs = 0;
 148                 num_es_gprs = 0;
 149                 num_ps_threads = 136;
 150                 num_vs_threads = 48;
 151                 num_gs_threads = 4;
 152                 num_es_threads = 4;
 153                 num_ps_stack_entries = 40;
 154                 num_vs_stack_entries = 40;
 155                 num_gs_stack_entries = 32;
 156                 num_es_stack_entries = 16;
 157                 break;
 158         case CHIP_RV770:
 159                 num_ps_gprs = 192;
 160                 num_vs_gprs = 56;
 161                 num_temp_gprs = 4;
 162                 num_gs_gprs = 0;
 163                 num_es_gprs = 0;
 164                 num_ps_threads = 188;
 165                 num_vs_threads = 60;
 166                 num_gs_threads = 0;
 167                 num_es_threads = 0;
 168                 num_ps_stack_entries = 256;
 169                 num_vs_stack_entries = 256;
 170                 num_gs_stack_entries = 0;
 171                 num_es_stack_entries = 0;
 172                 break;
 173         case CHIP_RV730:
 174         case CHIP_RV740:
 175                 num_ps_gprs = 84;
 176                 num_vs_gprs = 36;
 177                 num_temp_gprs = 4;
 178                 num_gs_gprs = 0;
 179                 num_es_gprs = 0;
 180                 num_ps_threads = 188;
 181                 num_vs_threads = 60;
 182                 num_gs_threads = 0;
 183                 num_es_threads = 0;
 184                 num_ps_stack_entries = 128;
 185                 num_vs_stack_entries = 128;
 186                 num_gs_stack_entries = 0;
 187                 num_es_stack_entries = 0;
 188                 break;
 189         case CHIP_RV710:
 190                 num_ps_gprs = 192;
 191                 num_vs_gprs = 56;
 192                 num_temp_gprs = 4;
 193                 num_gs_gprs = 0;
 194                 num_es_gprs = 0;
 195                 num_ps_threads = 144;
 196                 num_vs_threads = 48;
 197                 num_gs_threads = 0;
 198                 num_es_threads = 0;
 199                 num_ps_stack_entries = 128;
 200                 num_vs_stack_entries = 128;
 201                 num_gs_stack_entries = 0;
 202                 num_es_stack_entries = 0;
 203                 break;
 204         }
 205         printf("ps_prio : %d\n", ps_prio);
 206         printf("vs_prio : %d\n", vs_prio);
 207         printf("gs_prio : %d\n", gs_prio);
 208         printf("es_prio : %d\n", es_prio);
 209         printf("num_ps_gprs : %d\n", num_ps_gprs);
 210         printf("num_vs_gprs : %d\n", num_vs_gprs);
 211         printf("num_gs_gprs : %d\n", num_gs_gprs);
 212         printf("num_es_gprs : %d\n", num_es_gprs);
 213         printf("num_temp_gprs : %d\n", num_temp_gprs);
 214         printf("num_ps_threads : %d\n", num_ps_threads);
 215         printf("num_vs_threads : %d\n", num_vs_threads);
 216         printf("num_gs_threads : %d\n", num_gs_threads);
 217         printf("num_es_threads : %d\n", num_es_threads);
 218         printf("num_ps_stack_entries : %d\n", num_ps_stack_entries);
 219         printf("num_vs_stack_entries : %d\n", num_vs_stack_entries);
 220         printf("num_gs_stack_entries : %d\n", num_gs_stack_entries);
 221         printf("num_es_stack_entries : %d\n", num_es_stack_entries);
 222
 223         rctx->config = radeon_state(rctx->rw, R600_CONFIG_TYPE, R600_CONFIG);
 224
 225         rctx->config->states[R600_CONFIG__SQ_CONFIG] = 0x00000000;
 226         switch (family) {
 227         case CHIP_RV610:
 228         case CHIP_RV620:
 229         case CHIP_RS780:
 230         case CHIP_RS880:
 231         case CHIP_RV710:
 232                 break;
 233         default:
 234                 rctx->config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VC_ENABLE(1);
 235                 break;
 236         }
 237         rctx->config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_DX9_CONSTS(1);
 238         rctx->config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ALU_INST_PREFER_VECTOR(1);
 239         rctx->config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_PS_PRIO(ps_prio);
 240         rctx->config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VS_PRIO(vs_prio);
 241         rctx->config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_GS_PRIO(gs_prio);
 242         rctx->config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ES_PRIO(es_prio);
 243
 244         rctx->config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] = 0;
 245         rctx->config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
 246         rctx->config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
 247         rctx->config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
 248
 249         rctx->config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] = 0;
 250         rctx->config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
 251         rctx->config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_es_gprs);
 252
 253         rctx->config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] = 0;
 254         rctx->config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
 255         rctx->config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
 256         rctx->config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
 257         rctx->config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_ES_THREADS(num_es_threads);
 258
 259         rctx->config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] = 0;
 260         rctx->config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
 261         rctx->config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
 262
 263         rctx->config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] = 0;
 264         rctx->config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
 265         rctx->config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
 266
 267         rctx->config->states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00004000;
 268         rctx->config->states[R600_CONFIG__TA_CNTL_AUX] = 0x07000002;
 269         rctx->config->states[R600_CONFIG__VC_ENHANCE] = 0x00000000;
 270         rctx->config->states[R600_CONFIG__DB_DEBUG] = 0x00000000;
 271         rctx->config->states[R600_CONFIG__DB_WATERMARKS] = 0x00420204;
 272         rctx->config->states[R600_CONFIG__SX_MISC] = 0x00000000;
 273         rctx->config->states[R600_CONFIG__SPI_THREAD_GROUPING] = 0x00000001;
 274         rctx->config->states[R600_CONFIG__CB_SHADER_CONTROL] = 0x00000003;
 275         rctx->config->states[R600_CONFIG__SQ_ESGS_RING_ITEMSIZE] = 0x00000000;
 276         rctx->config->states[R600_CONFIG__SQ_GSVS_RING_ITEMSIZE] = 0x00000000;
 277         rctx->config->states[R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE] = 0x00000000;
 278         rctx->config->states[R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE] = 0x00000000;
 279         rctx->config->states[R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE] = 0x00000000;
 280         rctx->config->states[R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE] = 0x00000000;
 281         rctx->config->states[R600_CONFIG__SQ_FBUF_RING_ITEMSIZE] = 0x00000000;
 282         rctx->config->states[R600_CONFIG__SQ_REDUC_RING_ITEMSIZE] = 0x00000000;
 283         rctx->config->states[R600_CONFIG__SQ_GS_VERT_ITEMSIZE] = 0x00000000;
 284         rctx->config->states[R600_CONFIG__VGT_OUTPUT_PATH_CNTL] = 0x00000000;
 285         rctx->config->states[R600_CONFIG__VGT_HOS_CNTL] = 0x00000000;
 286         rctx->config->states[R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL] = 0x00000000;
 287         rctx->config->states[R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL] = 0x00000000;
 288         rctx->config->states[R600_CONFIG__VGT_HOS_REUSE_DEPTH] = 0x00000000;
 289         rctx->config->states[R600_CONFIG__VGT_GROUP_PRIM_TYPE] = 0x00000000;
 290         rctx->config->states[R600_CONFIG__VGT_GROUP_FIRST_DECR] = 0x00000000;
 291         rctx->config->states[R600_CONFIG__VGT_GROUP_DECR] = 0x00000000;
 292         rctx->config->states[R600_CONFIG__VGT_GROUP_VECT_0_CNTL] = 0x00000000;
 293         rctx->config->states[R600_CONFIG__VGT_GROUP_VECT_1_CNTL] = 0x00000000;
 294         rctx->config->states[R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL] = 0x00000000;
 295         rctx->config->states[R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL] = 0x00000000;
 296         rctx->config->states[R600_CONFIG__VGT_GS_MODE] = 0x00000000;
 297         rctx->config->states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00514000;
 298         rctx->config->states[R600_CONFIG__VGT_STRMOUT_EN] = 0x00000000;
 299         rctx->config->states[R600_CONFIG__VGT_REUSE_OFF] = 0x00000001;
 300         rctx->config->states[R600_CONFIG__VGT_VTX_CNT_EN] = 0x00000000;
 301         rctx->config->states[R600_CONFIG__VGT_STRMOUT_BUFFER_EN] = 0x00000000;
 302         radeon_state_pm4(rctx->config);
 303 }
 304
 305 struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 306 {
 307         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 308         struct r600_screen* rscreen = r600_screen(screen);
 309
 310         if (rctx == NULL)
 311                 return NULL;
 312         rctx->context.winsys = rscreen->screen.winsys;
 313         rctx->context.screen = screen;
 314         rctx->context.priv = priv;
 315         rctx->context.destroy = r600_destroy_context;
 316         rctx->context.draw_arrays = r600_draw_arrays;
 317         rctx->context.draw_elements = r600_draw_elements;
 318         rctx->context.draw_range_elements = r600_draw_range_elements;
 319         rctx->context.flush = r600_flush;
 320
 321         /* Easy accessing of screen/winsys. */
 322         rctx->screen = rscreen;
 323         rctx->rw = rscreen->rw;
 324
 325         r600_init_blit_functions(rctx);
 326         r600_init_query_functions(rctx);
 327         r600_init_state_functions(rctx);
 328         r600_init_context_resource_functions(rctx);
 329
 330         rctx->blitter = util_blitter_create(&rctx->context);
 331         if (rctx->blitter == NULL) {
 332                 FREE(rctx);
 333                 return NULL;
 334         }
 335
 336         rctx->cb_cntl = radeon_state(rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL);
 337         rctx->cb_cntl->states[R600_CB_CNTL__CB_SHADER_MASK] = 0x0000000F;
 338         rctx->cb_cntl->states[R600_CB_CNTL__CB_TARGET_MASK] = 0x0000000F;
 339         rctx->cb_cntl->states[R600_CB_CNTL__CB_COLOR_CONTROL] = 0x00CC0000;
 340         rctx->cb_cntl->states[R600_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000;
 341         rctx->cb_cntl->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX] = 0x00000000;
 342         rctx->cb_cntl->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX] = 0x00000000;
 343         rctx->cb_cntl->states[R600_CB_CNTL__CB_CLRCMP_CONTROL] = 0x01000000;
 344         rctx->cb_cntl->states[R600_CB_CNTL__CB_CLRCMP_SRC] = 0x00000000;
 345         rctx->cb_cntl->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF;
 346         rctx->cb_cntl->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF;
 347         rctx->cb_cntl->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
 348         radeon_state_pm4(rctx->cb_cntl);
 349
 350         r600_init_config(rctx);
 351
 352         rctx->ctx = radeon_ctx(rscreen->rw);
 353         rctx->draw = radeon_draw(rscreen->rw);
 354         return &rctx->context;
 355 }