2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include <util/u_inlines.h>
29 #include <util/u_format.h>
30 #include <util/u_memory.h>
31 #include <util/u_blitter.h>
32 #include "r600_screen.h"
33 #include "r600_context.h"
34 #include "r600_resource.h"
38 static void r600_destroy_context(struct pipe_context
*context
)
40 struct r600_context
*rctx
= r600_context(context
);
45 void r600_flush(struct pipe_context
*ctx
, unsigned flags
,
46 struct pipe_fence_handle
**fence
)
48 struct r600_context
*rctx
= r600_context(ctx
);
49 struct r600_query
*rquery
;
54 r600_queries_suspend(ctx
);
55 /* FIXME dumping should be removed once shader support instructions
56 * without throwing bad code
58 if (!rctx
->ctx
.cdwords
)
61 sprintf(dname
, "gallium-%08d.bof", dc
);
63 radeon_ctx_dump_bof(&rctx
->ctx
, dname
);
64 R600_ERR("dumped %s\n", dname
);
68 radeon_ctx_submit(&rctx
->ctx
);
70 LIST_FOR_EACH_ENTRY(rquery
, &rctx
->query_list
, list
) {
71 rquery
->flushed
= true;
75 radeon_ctx_clear(&rctx
->ctx
);
77 r600_queries_resume(ctx
);
80 static void r600_init_config(struct r600_context
*rctx
)
95 int num_ps_stack_entries
;
96 int num_vs_stack_entries
;
97 int num_gs_stack_entries
;
98 int num_es_stack_entries
;
99 enum radeon_family family
;
101 family
= radeon_get_family(rctx
->rw
);
113 num_ps_threads
= 136;
117 num_ps_stack_entries
= 128;
118 num_vs_stack_entries
= 128;
119 num_gs_stack_entries
= 0;
120 num_es_stack_entries
= 0;
129 num_ps_threads
= 144;
133 num_ps_stack_entries
= 40;
134 num_vs_stack_entries
= 40;
135 num_gs_stack_entries
= 32;
136 num_es_stack_entries
= 16;
148 num_ps_threads
= 136;
152 num_ps_stack_entries
= 40;
153 num_vs_stack_entries
= 40;
154 num_gs_stack_entries
= 32;
155 num_es_stack_entries
= 16;
163 num_ps_threads
= 136;
167 num_ps_stack_entries
= 40;
168 num_vs_stack_entries
= 40;
169 num_gs_stack_entries
= 32;
170 num_es_stack_entries
= 16;
178 num_ps_threads
= 188;
182 num_ps_stack_entries
= 256;
183 num_vs_stack_entries
= 256;
184 num_gs_stack_entries
= 0;
185 num_es_stack_entries
= 0;
194 num_ps_threads
= 188;
198 num_ps_stack_entries
= 128;
199 num_vs_stack_entries
= 128;
200 num_gs_stack_entries
= 0;
201 num_es_stack_entries
= 0;
209 num_ps_threads
= 144;
213 num_ps_stack_entries
= 128;
214 num_vs_stack_entries
= 128;
215 num_gs_stack_entries
= 0;
216 num_es_stack_entries
= 0;
219 radeon_state_init(&rctx
->config
, rctx
->rw
, R600_STATE_CONFIG
, 0, 0);
221 rctx
->config
.states
[R600_CONFIG__SQ_CONFIG
] = 0x00000000;
230 rctx
->config
.states
[R600_CONFIG__SQ_CONFIG
] |= S_008C00_VC_ENABLE(1);
233 rctx
->config
.states
[R600_CONFIG__SQ_CONFIG
] |= S_008C00_DX9_CONSTS(1);
234 rctx
->config
.states
[R600_CONFIG__SQ_CONFIG
] |= S_008C00_ALU_INST_PREFER_VECTOR(1);
235 rctx
->config
.states
[R600_CONFIG__SQ_CONFIG
] |= S_008C00_PS_PRIO(ps_prio
);
236 rctx
->config
.states
[R600_CONFIG__SQ_CONFIG
] |= S_008C00_VS_PRIO(vs_prio
);
237 rctx
->config
.states
[R600_CONFIG__SQ_CONFIG
] |= S_008C00_GS_PRIO(gs_prio
);
238 rctx
->config
.states
[R600_CONFIG__SQ_CONFIG
] |= S_008C00_ES_PRIO(es_prio
);
240 rctx
->config
.states
[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1
] = 0;
241 rctx
->config
.states
[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1
] |= S_008C04_NUM_PS_GPRS(num_ps_gprs
);
242 rctx
->config
.states
[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1
] |= S_008C04_NUM_VS_GPRS(num_vs_gprs
);
243 rctx
->config
.states
[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1
] |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs
);
245 rctx
->config
.states
[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2
] = 0;
246 rctx
->config
.states
[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2
] |= S_008C08_NUM_GS_GPRS(num_gs_gprs
);
247 rctx
->config
.states
[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2
] |= S_008C08_NUM_GS_GPRS(num_es_gprs
);
249 rctx
->config
.states
[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT
] = 0;
250 rctx
->config
.states
[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT
] |= S_008C0C_NUM_PS_THREADS(num_ps_threads
);
251 rctx
->config
.states
[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT
] |= S_008C0C_NUM_VS_THREADS(num_vs_threads
);
252 rctx
->config
.states
[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT
] |= S_008C0C_NUM_GS_THREADS(num_gs_threads
);
253 rctx
->config
.states
[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT
] |= S_008C0C_NUM_ES_THREADS(num_es_threads
);
255 rctx
->config
.states
[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1
] = 0;
256 rctx
->config
.states
[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1
] |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries
);
257 rctx
->config
.states
[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1
] |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries
);
259 rctx
->config
.states
[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2
] = 0;
260 rctx
->config
.states
[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2
] |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries
);
261 rctx
->config
.states
[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2
] |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries
);
263 rctx
->config
.states
[R600_CONFIG__VC_ENHANCE
] = 0x00000000;
264 rctx
->config
.states
[R600_CONFIG__SX_MISC
] = 0x00000000;
266 if (family
>= CHIP_RV770
) {
267 rctx
->config
.states
[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
] = 0x00004000;
268 rctx
->config
.states
[R600_CONFIG__TA_CNTL_AUX
] = 0x07000002;
269 rctx
->config
.states
[R600_CONFIG__DB_DEBUG
] = 0x00000000;
270 rctx
->config
.states
[R600_CONFIG__DB_WATERMARKS
] = 0x00420204;
271 rctx
->config
.states
[R600_CONFIG__SPI_THREAD_GROUPING
] = 0x00000000;
272 rctx
->config
.states
[R600_CONFIG__PA_SC_MODE_CNTL
] = 0x00514000;
274 rctx
->config
.states
[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
] = 0x00000000;
275 rctx
->config
.states
[R600_CONFIG__TA_CNTL_AUX
] = 0x07000003;
276 rctx
->config
.states
[R600_CONFIG__DB_DEBUG
] = 0x82000000;
277 rctx
->config
.states
[R600_CONFIG__DB_WATERMARKS
] = 0x01020204;
278 rctx
->config
.states
[R600_CONFIG__SPI_THREAD_GROUPING
] = 0x00000001;
279 rctx
->config
.states
[R600_CONFIG__PA_SC_MODE_CNTL
] = 0x00004010;
281 rctx
->config
.states
[R600_CONFIG__CB_SHADER_CONTROL
] = 0x00000003;
282 rctx
->config
.states
[R600_CONFIG__SQ_ESGS_RING_ITEMSIZE
] = 0x00000000;
283 rctx
->config
.states
[R600_CONFIG__SQ_GSVS_RING_ITEMSIZE
] = 0x00000000;
284 rctx
->config
.states
[R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE
] = 0x00000000;
285 rctx
->config
.states
[R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE
] = 0x00000000;
286 rctx
->config
.states
[R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE
] = 0x00000000;
287 rctx
->config
.states
[R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE
] = 0x00000000;
288 rctx
->config
.states
[R600_CONFIG__SQ_FBUF_RING_ITEMSIZE
] = 0x00000000;
289 rctx
->config
.states
[R600_CONFIG__SQ_REDUC_RING_ITEMSIZE
] = 0x00000000;
290 rctx
->config
.states
[R600_CONFIG__SQ_GS_VERT_ITEMSIZE
] = 0x00000000;
291 rctx
->config
.states
[R600_CONFIG__VGT_OUTPUT_PATH_CNTL
] = 0x00000000;
292 rctx
->config
.states
[R600_CONFIG__VGT_HOS_CNTL
] = 0x00000000;
293 rctx
->config
.states
[R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL
] = 0x00000000;
294 rctx
->config
.states
[R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL
] = 0x00000000;
295 rctx
->config
.states
[R600_CONFIG__VGT_HOS_REUSE_DEPTH
] = 0x00000000;
296 rctx
->config
.states
[R600_CONFIG__VGT_GROUP_PRIM_TYPE
] = 0x00000000;
297 rctx
->config
.states
[R600_CONFIG__VGT_GROUP_FIRST_DECR
] = 0x00000000;
298 rctx
->config
.states
[R600_CONFIG__VGT_GROUP_DECR
] = 0x00000000;
299 rctx
->config
.states
[R600_CONFIG__VGT_GROUP_VECT_0_CNTL
] = 0x00000000;
300 rctx
->config
.states
[R600_CONFIG__VGT_GROUP_VECT_1_CNTL
] = 0x00000000;
301 rctx
->config
.states
[R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL
] = 0x00000000;
302 rctx
->config
.states
[R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL
] = 0x00000000;
303 rctx
->config
.states
[R600_CONFIG__VGT_GS_MODE
] = 0x00000000;
304 rctx
->config
.states
[R600_CONFIG__VGT_STRMOUT_EN
] = 0x00000000;
305 rctx
->config
.states
[R600_CONFIG__VGT_REUSE_OFF
] = 0x00000001;
306 rctx
->config
.states
[R600_CONFIG__VGT_VTX_CNT_EN
] = 0x00000000;
307 rctx
->config
.states
[R600_CONFIG__VGT_STRMOUT_BUFFER_EN
] = 0x00000000;
308 radeon_state_pm4(&rctx
->config
);
311 struct pipe_context
*r600_create_context(struct pipe_screen
*screen
, void *priv
)
313 struct r600_context
*rctx
= CALLOC_STRUCT(r600_context
);
314 struct r600_screen
* rscreen
= r600_screen(screen
);
318 rctx
->context
.winsys
= rscreen
->screen
.winsys
;
319 rctx
->context
.screen
= screen
;
320 rctx
->context
.priv
= priv
;
321 rctx
->context
.destroy
= r600_destroy_context
;
322 rctx
->context
.draw_vbo
= r600_draw_vbo
;
323 rctx
->context
.flush
= r600_flush
;
325 /* Easy accessing of screen/winsys. */
326 rctx
->screen
= rscreen
;
327 rctx
->rw
= rscreen
->rw
;
329 r600_init_blit_functions(rctx
);
330 r600_init_query_functions(rctx
);
331 r600_init_state_functions(rctx
);
332 r600_init_context_resource_functions(rctx
);
334 rctx
->blitter
= util_blitter_create(&rctx
->context
);
335 if (rctx
->blitter
== NULL
) {
340 r600_init_config(rctx
);
342 radeon_ctx_init(&rctx
->ctx
, rscreen
->rw
);
343 radeon_draw_init(&rctx
->draw
, rscreen
->rw
);
344 return &rctx
->context
;