src/gallium/drivers/r600/r600_context.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  *      Corbin Simpson
  26  */
  27 #include <stdio.h>
  28 #include <util/u_inlines.h>
  29 #include <util/u_format.h>
  30 #include <util/u_memory.h>
  31 #include <util/u_blitter.h>
  32 #include "r600_screen.h"
  33 #include "r600_context.h"
  34 #include "r600_resource.h"
  35 #include "r600d.h"
  36
  37
  38 static void r600_destroy_context(struct pipe_context *context)
  39 {
  40         struct r600_context *rctx = r600_context(context);
  41
  42         FREE(rctx);
  43 }
  44
  45 void r600_flush(struct pipe_context *ctx, unsigned flags,
  46                         struct pipe_fence_handle **fence)
  47 {
  48         struct r600_context *rctx = r600_context(ctx);
  49         struct r600_screen *rscreen = rctx->screen;
  50         struct r600_query *rquery;
  51         static int dc = 0;
  52         char dname[256];
  53
  54         /* suspend queries */
  55         r600_queries_suspend(ctx);
  56         if (radeon_ctx_pm4(rctx->ctx))
  57                 goto out;
  58         /* FIXME dumping should be removed once shader support instructions
  59          * without throwing bad code
  60          */
  61         if (!rctx->ctx->cpm4)
  62                 goto out;
  63         sprintf(dname, "gallium-%08d.bof", dc);
  64         if (dc < 2) {
  65                 radeon_ctx_dump_bof(rctx->ctx, dname);
  66                 R600_ERR("dumped %s\n", dname);
  67         }
  68 #if 1
  69         radeon_ctx_submit(rctx->ctx);
  70 #endif
  71         LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) {
  72                 rquery->flushed = true;
  73         }
  74         dc++;
  75 out:
  76         rctx->ctx = radeon_ctx_decref(rctx->ctx);
  77         rctx->ctx = radeon_ctx(rscreen->rw);
  78         /* resume queries */
  79         r600_queries_resume(ctx);
  80 }
  81
  82 static void r600_init_config(struct r600_context *rctx)
  83 {
  84         int ps_prio;
  85         int vs_prio;
  86         int gs_prio;
  87         int es_prio;
  88         int num_ps_gprs;
  89         int num_vs_gprs;
  90         int num_gs_gprs;
  91         int num_es_gprs;
  92         int num_temp_gprs;
  93         int num_ps_threads;
  94         int num_vs_threads;
  95         int num_gs_threads;
  96         int num_es_threads;
  97         int num_ps_stack_entries;
  98         int num_vs_stack_entries;
  99         int num_gs_stack_entries;
 100         int num_es_stack_entries;
 101         enum radeon_family family;
 102
 103         family = radeon_get_family(rctx->rw);
 104         ps_prio = 0;
 105         vs_prio = 1;
 106         gs_prio = 2;
 107         es_prio = 3;
 108         switch (family) {
 109         case CHIP_R600:
 110                 num_ps_gprs = 192;
 111                 num_vs_gprs = 56;
 112                 num_temp_gprs = 4;
 113                 num_gs_gprs = 0;
 114                 num_es_gprs = 0;
 115                 num_ps_threads = 136;
 116                 num_vs_threads = 48;
 117                 num_gs_threads = 4;
 118                 num_es_threads = 4;
 119                 num_ps_stack_entries = 128;
 120                 num_vs_stack_entries = 128;
 121                 num_gs_stack_entries = 0;
 122                 num_es_stack_entries = 0;
 123                 break;
 124         case CHIP_RV630:
 125         case CHIP_RV635:
 126                 num_ps_gprs = 84;
 127                 num_vs_gprs = 36;
 128                 num_temp_gprs = 4;
 129                 num_gs_gprs = 0;
 130                 num_es_gprs = 0;
 131                 num_ps_threads = 144;
 132                 num_vs_threads = 40;
 133                 num_gs_threads = 4;
 134                 num_es_threads = 4;
 135                 num_ps_stack_entries = 40;
 136                 num_vs_stack_entries = 40;
 137                 num_gs_stack_entries = 32;
 138                 num_es_stack_entries = 16;
 139                 break;
 140         case CHIP_RV610:
 141         case CHIP_RV620:
 142         case CHIP_RS780:
 143         case CHIP_RS880:
 144         default:
 145                 num_ps_gprs = 84;
 146                 num_vs_gprs = 36;
 147                 num_temp_gprs = 4;
 148                 num_gs_gprs = 0;
 149                 num_es_gprs = 0;
 150                 num_ps_threads = 136;
 151                 num_vs_threads = 48;
 152                 num_gs_threads = 4;
 153                 num_es_threads = 4;
 154                 num_ps_stack_entries = 40;
 155                 num_vs_stack_entries = 40;
 156                 num_gs_stack_entries = 32;
 157                 num_es_stack_entries = 16;
 158                 break;
 159         case CHIP_RV670:
 160                 num_ps_gprs = 144;
 161                 num_vs_gprs = 40;
 162                 num_temp_gprs = 4;
 163                 num_gs_gprs = 0;
 164                 num_es_gprs = 0;
 165                 num_ps_threads = 136;
 166                 num_vs_threads = 48;
 167                 num_gs_threads = 4;
 168                 num_es_threads = 4;
 169                 num_ps_stack_entries = 40;
 170                 num_vs_stack_entries = 40;
 171                 num_gs_stack_entries = 32;
 172                 num_es_stack_entries = 16;
 173                 break;
 174         case CHIP_RV770:
 175                 num_ps_gprs = 192;
 176                 num_vs_gprs = 56;
 177                 num_temp_gprs = 4;
 178                 num_gs_gprs = 0;
 179                 num_es_gprs = 0;
 180                 num_ps_threads = 188;
 181                 num_vs_threads = 60;
 182                 num_gs_threads = 0;
 183                 num_es_threads = 0;
 184                 num_ps_stack_entries = 256;
 185                 num_vs_stack_entries = 256;
 186                 num_gs_stack_entries = 0;
 187                 num_es_stack_entries = 0;
 188                 break;
 189         case CHIP_RV730:
 190         case CHIP_RV740:
 191                 num_ps_gprs = 84;
 192                 num_vs_gprs = 36;
 193                 num_temp_gprs = 4;
 194                 num_gs_gprs = 0;
 195                 num_es_gprs = 0;
 196                 num_ps_threads = 188;
 197                 num_vs_threads = 60;
 198                 num_gs_threads = 0;
 199                 num_es_threads = 0;
 200                 num_ps_stack_entries = 128;
 201                 num_vs_stack_entries = 128;
 202                 num_gs_stack_entries = 0;
 203                 num_es_stack_entries = 0;
 204                 break;
 205         case CHIP_RV710:
 206                 num_ps_gprs = 192;
 207                 num_vs_gprs = 56;
 208                 num_temp_gprs = 4;
 209                 num_gs_gprs = 0;
 210                 num_es_gprs = 0;
 211                 num_ps_threads = 144;
 212                 num_vs_threads = 48;
 213                 num_gs_threads = 0;
 214                 num_es_threads = 0;
 215                 num_ps_stack_entries = 128;
 216                 num_vs_stack_entries = 128;
 217                 num_gs_stack_entries = 0;
 218                 num_es_stack_entries = 0;
 219                 break;
 220         }
 221         rctx->hw_states.config = radeon_state(rctx->rw, R600_STATE_CONFIG, 0);
 222
 223         rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] = 0x00000000;
 224         switch (family) {
 225         case CHIP_RV610:
 226         case CHIP_RV620:
 227         case CHIP_RS780:
 228         case CHIP_RS880:
 229         case CHIP_RV710:
 230                 break;
 231         default:
 232                 rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VC_ENABLE(1);
 233                 break;
 234         }
 235         rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_DX9_CONSTS(1);
 236         rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ALU_INST_PREFER_VECTOR(1);
 237         rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_PS_PRIO(ps_prio);
 238         rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VS_PRIO(vs_prio);
 239         rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_GS_PRIO(gs_prio);
 240         rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ES_PRIO(es_prio);
 241
 242         rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] = 0;
 243         rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
 244         rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
 245         rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
 246
 247         rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] = 0;
 248         rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
 249         rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_es_gprs);
 250
 251         rctx->hw_states.config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] = 0;
 252         rctx->hw_states.config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
 253         rctx->hw_states.config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
 254         rctx->hw_states.config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
 255         rctx->hw_states.config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_ES_THREADS(num_es_threads);
 256
 257         rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] = 0;
 258         rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
 259         rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
 260
 261         rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] = 0;
 262         rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
 263         rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
 264
 265         rctx->hw_states.config->states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00004000;
 266         rctx->hw_states.config->states[R600_CONFIG__TA_CNTL_AUX] = 0x07000002;
 267         rctx->hw_states.config->states[R600_CONFIG__VC_ENHANCE] = 0x00000000;
 268         rctx->hw_states.config->states[R600_CONFIG__DB_DEBUG] = 0x00000000;
 269         rctx->hw_states.config->states[R600_CONFIG__DB_WATERMARKS] = 0x00420204;
 270         rctx->hw_states.config->states[R600_CONFIG__SX_MISC] = 0x00000000;
 271         rctx->hw_states.config->states[R600_CONFIG__SPI_THREAD_GROUPING] = 0x00000001;
 272         rctx->hw_states.config->states[R600_CONFIG__CB_SHADER_CONTROL] = 0x00000003;
 273         rctx->hw_states.config->states[R600_CONFIG__SQ_ESGS_RING_ITEMSIZE] = 0x00000000;
 274         rctx->hw_states.config->states[R600_CONFIG__SQ_GSVS_RING_ITEMSIZE] = 0x00000000;
 275         rctx->hw_states.config->states[R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE] = 0x00000000;
 276         rctx->hw_states.config->states[R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE] = 0x00000000;
 277         rctx->hw_states.config->states[R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE] = 0x00000000;
 278         rctx->hw_states.config->states[R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE] = 0x00000000;
 279         rctx->hw_states.config->states[R600_CONFIG__SQ_FBUF_RING_ITEMSIZE] = 0x00000000;
 280         rctx->hw_states.config->states[R600_CONFIG__SQ_REDUC_RING_ITEMSIZE] = 0x00000000;
 281         rctx->hw_states.config->states[R600_CONFIG__SQ_GS_VERT_ITEMSIZE] = 0x00000000;
 282         rctx->hw_states.config->states[R600_CONFIG__VGT_OUTPUT_PATH_CNTL] = 0x00000000;
 283         rctx->hw_states.config->states[R600_CONFIG__VGT_HOS_CNTL] = 0x00000000;
 284         rctx->hw_states.config->states[R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL] = 0x00000000;
 285         rctx->hw_states.config->states[R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL] = 0x00000000;
 286         rctx->hw_states.config->states[R600_CONFIG__VGT_HOS_REUSE_DEPTH] = 0x00000000;
 287         rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_PRIM_TYPE] = 0x00000000;
 288         rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_FIRST_DECR] = 0x00000000;
 289         rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_DECR] = 0x00000000;
 290         rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_VECT_0_CNTL] = 0x00000000;
 291         rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_VECT_1_CNTL] = 0x00000000;
 292         rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL] = 0x00000000;
 293         rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL] = 0x00000000;
 294         rctx->hw_states.config->states[R600_CONFIG__VGT_GS_MODE] = 0x00000000;
 295         rctx->hw_states.config->states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00514000;
 296         rctx->hw_states.config->states[R600_CONFIG__VGT_STRMOUT_EN] = 0x00000000;
 297         rctx->hw_states.config->states[R600_CONFIG__VGT_REUSE_OFF] = 0x00000001;
 298         rctx->hw_states.config->states[R600_CONFIG__VGT_VTX_CNT_EN] = 0x00000000;
 299         rctx->hw_states.config->states[R600_CONFIG__VGT_STRMOUT_BUFFER_EN] = 0x00000000;
 300         radeon_state_pm4(rctx->hw_states.config);
 301 }
 302
 303 struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 304 {
 305         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 306         struct r600_screen* rscreen = r600_screen(screen);
 307
 308         if (rctx == NULL)
 309                 return NULL;
 310         rctx->context.winsys = rscreen->screen.winsys;
 311         rctx->context.screen = screen;
 312         rctx->context.priv = priv;
 313         rctx->context.destroy = r600_destroy_context;
 314         rctx->context.draw_vbo = r600_draw_vbo;
 315         rctx->context.flush = r600_flush;
 316
 317         /* Easy accessing of screen/winsys. */
 318         rctx->screen = rscreen;
 319         rctx->rw = rscreen->rw;
 320
 321         r600_init_blit_functions(rctx);
 322         r600_init_query_functions(rctx);
 323         r600_init_state_functions(rctx);
 324         r600_init_context_resource_functions(rctx);
 325
 326         rctx->blitter = util_blitter_create(&rctx->context);
 327         if (rctx->blitter == NULL) {
 328                 FREE(rctx);
 329                 return NULL;
 330         }
 331
 332         r600_init_config(rctx);
 333
 334         rctx->ctx = radeon_ctx(rscreen->rw);
 335         rctx->draw = radeon_draw(rscreen->rw);
 336         return &rctx->context;
 337 }