2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include <util/u_inlines.h>
29 #include <util/u_format.h>
30 #include <util/u_memory.h>
31 #include <util/u_blitter.h>
32 #include "r600_screen.h"
33 #include "r600_context.h"
34 #include "r600_resource.h"
37 static void r600_destroy_context(struct pipe_context
*context
)
39 struct r600_context
*rctx
= r600_context(context
);
44 void r600_flush(struct pipe_context
*ctx
, unsigned flags
,
45 struct pipe_fence_handle
**fence
)
47 struct r600_context
*rctx
= r600_context(ctx
);
48 struct r600_screen
*rscreen
= rctx
->screen
;
52 if (radeon_ctx_pm4(rctx
->ctx
))
54 /* FIXME dumping should be removed once shader support instructions
55 * without throwing bad code
59 sprintf(dname
, "gallium-%08d.bof", dc
);
61 radeon_ctx_dump_bof(rctx
->ctx
, dname
);
63 radeon_ctx_submit(rctx
->ctx
);
67 rctx
->ctx
= radeon_ctx_decref(rctx
->ctx
);
68 rctx
->ctx
= radeon_ctx(rscreen
->rw
);
71 static void r600_init_config(struct r600_context
*rctx
)
86 int num_ps_stack_entries
;
87 int num_vs_stack_entries
;
88 int num_gs_stack_entries
;
89 int num_es_stack_entries
;
90 enum radeon_family family
;
92 family
= radeon_get_family(rctx
->rw
);
104 num_ps_threads
= 136;
108 num_ps_stack_entries
= 128;
109 num_vs_stack_entries
= 128;
110 num_gs_stack_entries
= 0;
111 num_es_stack_entries
= 0;
120 num_ps_threads
= 144;
124 num_ps_stack_entries
= 40;
125 num_vs_stack_entries
= 40;
126 num_gs_stack_entries
= 32;
127 num_es_stack_entries
= 16;
139 num_ps_threads
= 136;
143 num_ps_stack_entries
= 40;
144 num_vs_stack_entries
= 40;
145 num_gs_stack_entries
= 32;
146 num_es_stack_entries
= 16;
154 num_ps_threads
= 136;
158 num_ps_stack_entries
= 40;
159 num_vs_stack_entries
= 40;
160 num_gs_stack_entries
= 32;
161 num_es_stack_entries
= 16;
169 num_ps_threads
= 188;
173 num_ps_stack_entries
= 256;
174 num_vs_stack_entries
= 256;
175 num_gs_stack_entries
= 0;
176 num_es_stack_entries
= 0;
185 num_ps_threads
= 188;
189 num_ps_stack_entries
= 128;
190 num_vs_stack_entries
= 128;
191 num_gs_stack_entries
= 0;
192 num_es_stack_entries
= 0;
200 num_ps_threads
= 144;
204 num_ps_stack_entries
= 128;
205 num_vs_stack_entries
= 128;
206 num_gs_stack_entries
= 0;
207 num_es_stack_entries
= 0;
210 rctx
->hw_states
.config
= radeon_state(rctx
->rw
, R600_CONFIG_TYPE
, R600_CONFIG
);
212 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_CONFIG
] = 0x00000000;
221 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_CONFIG
] |= S_008C00_VC_ENABLE(1);
224 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_CONFIG
] |= S_008C00_DX9_CONSTS(1);
225 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_CONFIG
] |= S_008C00_ALU_INST_PREFER_VECTOR(1);
226 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_CONFIG
] |= S_008C00_PS_PRIO(ps_prio
);
227 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_CONFIG
] |= S_008C00_VS_PRIO(vs_prio
);
228 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_CONFIG
] |= S_008C00_GS_PRIO(gs_prio
);
229 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_CONFIG
] |= S_008C00_ES_PRIO(es_prio
);
231 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1
] = 0;
232 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1
] |= S_008C04_NUM_PS_GPRS(num_ps_gprs
);
233 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1
] |= S_008C04_NUM_VS_GPRS(num_vs_gprs
);
234 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1
] |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs
);
236 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2
] = 0;
237 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2
] |= S_008C08_NUM_GS_GPRS(num_gs_gprs
);
238 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2
] |= S_008C08_NUM_GS_GPRS(num_es_gprs
);
240 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT
] = 0;
241 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT
] |= S_008C0C_NUM_PS_THREADS(num_ps_threads
);
242 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT
] |= S_008C0C_NUM_VS_THREADS(num_vs_threads
);
243 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT
] |= S_008C0C_NUM_GS_THREADS(num_gs_threads
);
244 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT
] |= S_008C0C_NUM_ES_THREADS(num_es_threads
);
246 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1
] = 0;
247 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1
] |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries
);
248 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1
] |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries
);
250 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2
] = 0;
251 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2
] |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries
);
252 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2
] |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries
);
254 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
] = 0x00004000;
255 rctx
->hw_states
.config
->states
[R600_CONFIG__TA_CNTL_AUX
] = 0x07000002;
256 rctx
->hw_states
.config
->states
[R600_CONFIG__VC_ENHANCE
] = 0x00000000;
257 rctx
->hw_states
.config
->states
[R600_CONFIG__DB_DEBUG
] = 0x00000000;
258 rctx
->hw_states
.config
->states
[R600_CONFIG__DB_WATERMARKS
] = 0x00420204;
259 rctx
->hw_states
.config
->states
[R600_CONFIG__SX_MISC
] = 0x00000000;
260 rctx
->hw_states
.config
->states
[R600_CONFIG__SPI_THREAD_GROUPING
] = 0x00000001;
261 rctx
->hw_states
.config
->states
[R600_CONFIG__CB_SHADER_CONTROL
] = 0x00000003;
262 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_ESGS_RING_ITEMSIZE
] = 0x00000000;
263 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_GSVS_RING_ITEMSIZE
] = 0x00000000;
264 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE
] = 0x00000000;
265 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE
] = 0x00000000;
266 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE
] = 0x00000000;
267 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE
] = 0x00000000;
268 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_FBUF_RING_ITEMSIZE
] = 0x00000000;
269 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_REDUC_RING_ITEMSIZE
] = 0x00000000;
270 rctx
->hw_states
.config
->states
[R600_CONFIG__SQ_GS_VERT_ITEMSIZE
] = 0x00000000;
271 rctx
->hw_states
.config
->states
[R600_CONFIG__VGT_OUTPUT_PATH_CNTL
] = 0x00000000;
272 rctx
->hw_states
.config
->states
[R600_CONFIG__VGT_HOS_CNTL
] = 0x00000000;
273 rctx
->hw_states
.config
->states
[R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL
] = 0x00000000;
274 rctx
->hw_states
.config
->states
[R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL
] = 0x00000000;
275 rctx
->hw_states
.config
->states
[R600_CONFIG__VGT_HOS_REUSE_DEPTH
] = 0x00000000;
276 rctx
->hw_states
.config
->states
[R600_CONFIG__VGT_GROUP_PRIM_TYPE
] = 0x00000000;
277 rctx
->hw_states
.config
->states
[R600_CONFIG__VGT_GROUP_FIRST_DECR
] = 0x00000000;
278 rctx
->hw_states
.config
->states
[R600_CONFIG__VGT_GROUP_DECR
] = 0x00000000;
279 rctx
->hw_states
.config
->states
[R600_CONFIG__VGT_GROUP_VECT_0_CNTL
] = 0x00000000;
280 rctx
->hw_states
.config
->states
[R600_CONFIG__VGT_GROUP_VECT_1_CNTL
] = 0x00000000;
281 rctx
->hw_states
.config
->states
[R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL
] = 0x00000000;
282 rctx
->hw_states
.config
->states
[R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL
] = 0x00000000;
283 rctx
->hw_states
.config
->states
[R600_CONFIG__VGT_GS_MODE
] = 0x00000000;
284 rctx
->hw_states
.config
->states
[R600_CONFIG__PA_SC_MODE_CNTL
] = 0x00514000;
285 rctx
->hw_states
.config
->states
[R600_CONFIG__VGT_STRMOUT_EN
] = 0x00000000;
286 rctx
->hw_states
.config
->states
[R600_CONFIG__VGT_REUSE_OFF
] = 0x00000001;
287 rctx
->hw_states
.config
->states
[R600_CONFIG__VGT_VTX_CNT_EN
] = 0x00000000;
288 rctx
->hw_states
.config
->states
[R600_CONFIG__VGT_STRMOUT_BUFFER_EN
] = 0x00000000;
289 radeon_state_pm4(rctx
->hw_states
.config
);
292 struct pipe_context
*r600_create_context(struct pipe_screen
*screen
, void *priv
)
294 struct r600_context
*rctx
= CALLOC_STRUCT(r600_context
);
295 struct r600_screen
* rscreen
= r600_screen(screen
);
299 rctx
->context
.winsys
= rscreen
->screen
.winsys
;
300 rctx
->context
.screen
= screen
;
301 rctx
->context
.priv
= priv
;
302 rctx
->context
.destroy
= r600_destroy_context
;
303 rctx
->context
.draw_vbo
= r600_draw_vbo
;
304 rctx
->context
.flush
= r600_flush
;
306 /* Easy accessing of screen/winsys. */
307 rctx
->screen
= rscreen
;
308 rctx
->rw
= rscreen
->rw
;
310 r600_init_blit_functions(rctx
);
311 r600_init_query_functions(rctx
);
312 r600_init_state_functions(rctx
);
313 r600_init_context_resource_functions(rctx
);
315 rctx
->blitter
= util_blitter_create(&rctx
->context
);
316 if (rctx
->blitter
== NULL
) {
321 r600_init_config(rctx
);
323 rctx
->ctx
= radeon_ctx(rscreen
->rw
);
324 rctx
->draw
= radeon_draw(rscreen
->rw
);
325 return &rctx
->context
;