Merge branch 'gallium-newclear'
[mesa.git] / src / gallium / drivers / r600 / r600_context.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include <stdio.h>
28 #include <util/u_inlines.h>
29 #include <util/u_format.h>
30 #include <util/u_memory.h>
31 #include <util/u_blitter.h>
32 #include "r600_resource.h"
33 #include "r600_screen.h"
34 #include "r600_context.h"
35
36 static void r600_destroy_context(struct pipe_context *context)
37 {
38 struct r600_context *rctx = (struct r600_context*)context;
39
40 FREE(rctx);
41 }
42
43 static void r600_flush(struct pipe_context *ctx, unsigned flags,
44 struct pipe_fence_handle **fence)
45 {
46 struct r600_context *rctx = (struct r600_context*)ctx;
47 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
48 static int dc = 0;
49
50 if (radeon_ctx_pm4(rctx->ctx))
51 return;
52 /* FIXME dumping should be removed once shader support instructions
53 * without throwing bad code
54 */
55 if (!dc)
56 radeon_ctx_dump_bof(rctx->ctx, "gallium.bof");
57 #if 0
58 radeon_ctx_submit(rctx->ctx);
59 #endif
60 rctx->ctx = radeon_ctx_decref(rctx->ctx);
61 rctx->ctx = radeon_ctx(rscreen->rw);
62 dc++;
63 }
64
65 struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
66 {
67 struct r600_context *rctx = CALLOC_STRUCT(r600_context);
68 struct r600_screen* rscreen = r600_screen(screen);
69
70 if (rctx == NULL)
71 return NULL;
72 rctx->context.winsys = rscreen->screen.winsys;
73 rctx->context.screen = screen;
74 rctx->context.priv = priv;
75 rctx->context.destroy = r600_destroy_context;
76 rctx->context.clear = r600_clear;
77 rctx->context.draw_arrays = r600_draw_arrays;
78 rctx->context.draw_elements = r600_draw_elements;
79 rctx->context.draw_range_elements = r600_draw_range_elements;
80 rctx->context.flush = r600_flush;
81 r600_init_query_functions(rctx);
82 r600_init_state_functions(rctx);
83 r600_init_context_resource_functions(rctx);
84
85 rctx->blitter = util_blitter_create(&rctx->context);
86 if (rctx->blitter == NULL) {
87 FREE(rctx);
88 return NULL;
89 }
90
91 rctx->cb_cntl = radeon_state(rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL);
92 rctx->cb_cntl->states[R600_CB_CNTL__CB_SHADER_MASK] = 0x0000000F;
93 rctx->cb_cntl->states[R600_CB_CNTL__CB_TARGET_MASK] = 0x0000000F;
94 rctx->cb_cntl->states[R600_CB_CNTL__CB_COLOR_CONTROL] = 0x00CC0000;
95 rctx->cb_cntl->states[R600_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000;
96 rctx->cb_cntl->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX] = 0x00000000;
97 rctx->cb_cntl->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX] = 0x00000000;
98 rctx->cb_cntl->states[R600_CB_CNTL__CB_CLRCMP_CONTROL] = 0x01000000;
99 rctx->cb_cntl->states[R600_CB_CNTL__CB_CLRCMP_SRC] = 0x00000000;
100 rctx->cb_cntl->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF;
101 rctx->cb_cntl->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF;
102 rctx->cb_cntl->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
103 radeon_state_pm4(rctx->cb_cntl);
104
105 rctx->config = radeon_state(rscreen->rw, R600_CONFIG_TYPE, R600_CONFIG);
106 rctx->config->states[R600_CONFIG__SQ_CONFIG] = 0xE400000C;
107 rctx->config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] = 0x403800C0;
108 rctx->config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] = 0x00000000;
109 rctx->config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] = 0x00003090;
110 rctx->config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] = 0x00800080;
111 rctx->config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] = 0x00000000;
112 rctx->config->states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00004000;
113 rctx->config->states[R600_CONFIG__TA_CNTL_AUX] = 0x07000002;
114 rctx->config->states[R600_CONFIG__VC_ENHANCE] = 0x00000000;
115 rctx->config->states[R600_CONFIG__DB_DEBUG] = 0x00000000;
116 rctx->config->states[R600_CONFIG__DB_WATERMARKS] = 0x00420204;
117 rctx->config->states[R600_CONFIG__SX_MISC] = 0x00000000;
118 rctx->config->states[R600_CONFIG__SPI_THREAD_GROUPING] = 0x00000001;
119 rctx->config->states[R600_CONFIG__CB_SHADER_CONTROL] = 0x00000003;
120 rctx->config->states[R600_CONFIG__SQ_ESGS_RING_ITEMSIZE] = 0x00000000;
121 rctx->config->states[R600_CONFIG__SQ_GSVS_RING_ITEMSIZE] = 0x00000000;
122 rctx->config->states[R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE] = 0x00000000;
123 rctx->config->states[R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE] = 0x00000000;
124 rctx->config->states[R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE] = 0x00000000;
125 rctx->config->states[R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE] = 0x00000000;
126 rctx->config->states[R600_CONFIG__SQ_FBUF_RING_ITEMSIZE] = 0x00000000;
127 rctx->config->states[R600_CONFIG__SQ_REDUC_RING_ITEMSIZE] = 0x00000000;
128 rctx->config->states[R600_CONFIG__SQ_GS_VERT_ITEMSIZE] = 0x00000000;
129 rctx->config->states[R600_CONFIG__VGT_OUTPUT_PATH_CNTL] = 0x00000000;
130 rctx->config->states[R600_CONFIG__VGT_HOS_CNTL] = 0x00000000;
131 rctx->config->states[R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL] = 0x00000000;
132 rctx->config->states[R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL] = 0x00000000;
133 rctx->config->states[R600_CONFIG__VGT_HOS_REUSE_DEPTH] = 0x00000000;
134 rctx->config->states[R600_CONFIG__VGT_GROUP_PRIM_TYPE] = 0x00000000;
135 rctx->config->states[R600_CONFIG__VGT_GROUP_FIRST_DECR] = 0x00000000;
136 rctx->config->states[R600_CONFIG__VGT_GROUP_DECR] = 0x00000000;
137 rctx->config->states[R600_CONFIG__VGT_GROUP_VECT_0_CNTL] = 0x00000000;
138 rctx->config->states[R600_CONFIG__VGT_GROUP_VECT_1_CNTL] = 0x00000000;
139 rctx->config->states[R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL] = 0x00000000;
140 rctx->config->states[R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL] = 0x00000000;
141 rctx->config->states[R600_CONFIG__VGT_GS_MODE] = 0x00000000;
142 rctx->config->states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00514000;
143 rctx->config->states[R600_CONFIG__VGT_STRMOUT_EN] = 0x00000000;
144 rctx->config->states[R600_CONFIG__VGT_REUSE_OFF] = 0x00000001;
145 rctx->config->states[R600_CONFIG__VGT_VTX_CNT_EN] = 0x00000000;
146 rctx->config->states[R600_CONFIG__VGT_STRMOUT_BUFFER_EN] = 0x00000000;
147 radeon_state_pm4(rctx->config);
148
149 rctx->ctx = radeon_ctx(rscreen->rw);
150 rctx->draw = radeon_draw(rscreen->rw);
151 return &rctx->context;
152 }