src/gallium/drivers/r600/r600_draw.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  *      Corbin Simpson
  26  */
  27 #include <stdio.h>
  28 #include <errno.h>
  29 #include <pipe/p_screen.h>
  30 #include <util/u_format.h>
  31 #include <util/u_math.h>
  32 #include <util/u_inlines.h>
  33 #include <util/u_memory.h>
  34 #include "r600_screen.h"
  35 #include "r600_context.h"
  36 #include "r600_resource.h"
  37 #include "r600_state_inlines.h"
  38
  39 struct r600_draw {
  40         struct pipe_context     *ctx;
  41         struct radeon_state     *draw;
  42         struct radeon_state     *vgt;
  43         unsigned                mode;
  44         unsigned                start;
  45         unsigned                count;
  46         unsigned                index_size;
  47         struct pipe_resource    *index_buffer;
  48 };
  49
  50 static int r600_draw_common(struct r600_draw *draw)
  51 {
  52         struct r600_context *rctx = r600_context(draw->ctx);
  53         struct r600_screen *rscreen = rctx->screen;
  54         struct radeon_state *vs_resource;
  55         struct r600_resource *rbuffer;
  56         unsigned i, j, offset, format, prim;
  57         u32 vgt_dma_index_type, vgt_draw_initiator;
  58         struct pipe_vertex_buffer *vertex_buffer;
  59         int r;
  60
  61         r = r600_context_hw_states(draw->ctx);
  62         if (r)
  63                 return r;
  64         switch (draw->index_size) {
  65         case 2:
  66                 vgt_draw_initiator = 0;
  67                 vgt_dma_index_type = 0;
  68                 break;
  69         case 4:
  70                 vgt_draw_initiator = 0;
  71                 vgt_dma_index_type = 1;
  72                 break;
  73         case 0:
  74                 vgt_draw_initiator = 2;
  75                 vgt_dma_index_type = 0;
  76                 break;
  77         default:
  78                 fprintf(stderr, "%s %d unsupported index size %d\n", __func__, __LINE__, draw->index_size);
  79                 return -EINVAL;
  80         }
  81         r = r600_conv_pipe_prim(draw->mode, &prim);
  82         if (r)
  83                 return r;
  84         /* rebuild vertex shader if input format changed */
  85         r = r600_pipe_shader_update(draw->ctx, rctx->vs_shader);
  86         if (r)
  87                 return r;
  88         r = r600_pipe_shader_update(draw->ctx, rctx->ps_shader);
  89         if (r)
  90                 return r;
  91         r = radeon_draw_set(rctx->draw, rctx->vs_shader->rstate);
  92         if (r)
  93                 return r;
  94         r = radeon_draw_set(rctx->draw, rctx->ps_shader->rstate);
  95         if (r)
  96                 return r;
  97
  98         for (i = 0 ; i < rctx->vertex_elements->count; i++) {
  99                 j = rctx->vertex_elements->elements[i].vertex_buffer_index;
 100                 vertex_buffer = &rctx->vertex_buffer[j];
 101                 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
 102                 offset = rctx->vertex_elements->elements[i].src_offset + vertex_buffer->buffer_offset;
 103                 format = r600_translate_colorformat(rctx->vertex_elements->elements[i].src_format);
 104                 vs_resource = radeon_state(rscreen->rw, R600_VS_RESOURCE0 + i);
 105                 if (vs_resource == NULL)
 106                         return -ENOMEM;
 107                 vs_resource->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 108                 vs_resource->nbo = 1;
 109                 vs_resource->reloc_pm4_id[0] = R600_RESOURCE__RESOURCE_BO0_ID;
 110                 vs_resource->reloc_pm4_id[1] = R600_RESOURCE__RESOURCE_BO1_ID;
 111                 vs_resource->states[R600_RESOURCE__RESOURCE_WORD0] = offset;
 112                 vs_resource->states[R600_RESOURCE__RESOURCE_WORD1] = rbuffer->bo->size - offset;
 113                 vs_resource->states[R600_RESOURCE__RESOURCE_WORD2] = S_038008_STRIDE(vertex_buffer->stride) |
 114                                                                 S_038008_DATA_FORMAT(format);
 115                 vs_resource->states[R600_RESOURCE__RESOURCE_WORD3] = 0x00000000;
 116                 vs_resource->states[R600_RESOURCE__RESOURCE_WORD4] = 0x00000000;
 117                 vs_resource->states[R600_RESOURCE__RESOURCE_WORD5] = 0x00000000;
 118                 vs_resource->states[R600_RESOURCE__RESOURCE_WORD6] = 0xC0000000;
 119                 vs_resource->placement[0] = RADEON_GEM_DOMAIN_GTT;
 120                 vs_resource->placement[1] = RADEON_GEM_DOMAIN_GTT;
 121                 r = radeon_draw_set_new(rctx->draw, vs_resource);
 122                 if (r)
 123                         return r;
 124         }
 125         /* FIXME start need to change winsys */
 126         if (draw->index_buffer) {
 127                 draw->draw = radeon_state(rscreen->rw, R600_DRAW);
 128                 if (draw->draw == NULL)
 129                         return -ENOMEM;
 130                 draw->draw->states[R600_DRAW__VGT_NUM_INDICES] = draw->count;
 131                 draw->draw->states[R600_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
 132                 rbuffer = (struct r600_resource*)draw->index_buffer;
 133                 draw->draw->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 134                 draw->draw->placement[0] = RADEON_GEM_DOMAIN_GTT;
 135                 draw->draw->placement[1] = RADEON_GEM_DOMAIN_GTT;
 136                 draw->draw->nbo = 1;
 137                 draw->draw->reloc_pm4_id[0] = R600_DRAW__INDICES_BO_ID;
 138         } else {
 139                 draw->draw = radeon_state(rscreen->rw, R600_DRAW_AUTO);
 140                 if (draw->draw == NULL)
 141                         return -ENOMEM;
 142                 draw->draw->states[R600_DRAW_AUTO__VGT_NUM_INDICES] = draw->count;
 143                 draw->draw->states[R600_DRAW_AUTO__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
 144         }
 145         r = radeon_draw_set_new(rctx->draw, draw->draw);
 146         if (r)
 147                 return r;
 148         draw->vgt = radeon_state(rscreen->rw, R600_VGT);
 149         if (draw->vgt == NULL)
 150                 return -ENOMEM;
 151         draw->vgt->states[R600_VGT__VGT_PRIMITIVE_TYPE] = prim;
 152         draw->vgt->states[R600_VGT__VGT_MAX_VTX_INDX] = 0x00FFFFFF;
 153         draw->vgt->states[R600_VGT__VGT_MIN_VTX_INDX] = 0x00000000;
 154         draw->vgt->states[R600_VGT__VGT_INDX_OFFSET] = draw->start;
 155         draw->vgt->states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX] = 0x00000000;
 156         draw->vgt->states[R600_VGT__VGT_DMA_INDEX_TYPE] = vgt_dma_index_type;
 157         draw->vgt->states[R600_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001;
 158         r = radeon_draw_set_new(rctx->draw, draw->vgt);
 159         if (r)
 160                 return r;
 161         /* FIXME */
 162         r = radeon_ctx_set_draw(rctx->ctx, rctx->draw);
 163         if (r == -EBUSY) {
 164                 r600_flush(draw->ctx, 0, NULL);
 165                 r = radeon_ctx_set_draw(rctx->ctx, rctx->draw);
 166         }
 167         if (r)
 168                 return r;
 169         return 0;
 170 }
 171
 172 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
 173 {
 174         struct r600_context *rctx = r600_context(ctx);
 175         struct r600_draw draw;
 176
 177         assert(info->index_bias == 0);
 178
 179         draw.ctx = ctx;
 180         draw.mode = info->mode;
 181         draw.start = info->start;
 182         draw.count = info->count;
 183         if (info->indexed && rctx->index_buffer.buffer) {
 184                 draw.index_size = rctx->index_buffer.index_size;
 185                 draw.index_buffer = rctx->index_buffer.buffer;
 186
 187                 assert(rctx->index_buffer.offset %
 188                                 rctx->index_buffer.index_size == 0);
 189                 draw.start += rctx->index_buffer.offset /
 190                         rctx->index_buffer.index_size;
 191         }
 192         else {
 193                 draw.index_size = 0;
 194                 draw.index_buffer = NULL;
 195         }
 196         r600_draw_common(&draw);
 197 }