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gallium: Add a pipe cap for whether primitive restart works for patches.
[mesa.git] / src / gallium / drivers / r600 / r600_hw_context.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include "r600_pipe.h"
27 #include "r600d.h"
28 #include "util/u_memory.h"
29 #include <errno.h>
30 #include <unistd.h>
31
32
33 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
34 boolean count_draw_in)
35 {
36 /* Flush the DMA IB if it's not empty. */
37 if (radeon_emitted(ctx->b.dma.cs, 0))
38 ctx->b.dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
39
40 if (!ctx->b.ws->cs_memory_below_limit(ctx->b.gfx.cs, ctx->b.vram, ctx->b.gtt)) {
41 ctx->b.gtt = 0;
42 ctx->b.vram = 0;
43 ctx->b.gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
44 return;
45 }
46 /* all will be accounted once relocation are emited */
47 ctx->b.gtt = 0;
48 ctx->b.vram = 0;
49
50 /* The number of dwords we already used in the CS so far. */
51 num_dw += ctx->b.gfx.cs->cdw;
52
53 if (count_draw_in) {
54 uint64_t mask;
55
56 /* The number of dwords all the dirty states would take. */
57 mask = ctx->dirty_atoms;
58 while (mask != 0)
59 num_dw += ctx->atoms[u_bit_scan64(&mask)]->num_dw;
60
61 /* The upper-bound of how much space a draw command would take. */
62 num_dw += R600_MAX_FLUSH_CS_DWORDS + R600_MAX_DRAW_CS_DWORDS;
63 }
64
65 /* Count in r600_suspend_queries. */
66 num_dw += ctx->b.num_cs_dw_queries_suspend;
67
68 /* Count in streamout_end at the end of CS. */
69 if (ctx->b.streamout.begin_emitted) {
70 num_dw += ctx->b.streamout.num_dw_for_end;
71 }
72
73 /* SX_MISC */
74 if (ctx->b.chip_class == R600) {
75 num_dw += 3;
76 }
77
78 /* Count in framebuffer cache flushes at the end of CS. */
79 num_dw += R600_MAX_FLUSH_CS_DWORDS;
80
81 /* The fence at the end of CS. */
82 num_dw += 10;
83
84 /* Flush if there's not enough space. */
85 if (num_dw > ctx->b.gfx.cs->max_dw) {
86 ctx->b.gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
87 }
88 }
89
90 void r600_flush_emit(struct r600_context *rctx)
91 {
92 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
93 unsigned cp_coher_cntl = 0;
94 unsigned wait_until = 0;
95
96 if (!rctx->b.flags) {
97 return;
98 }
99
100 if (rctx->b.flags & R600_CONTEXT_WAIT_3D_IDLE) {
101 wait_until |= S_008040_WAIT_3D_IDLE(1);
102 }
103 if (rctx->b.flags & R600_CONTEXT_WAIT_CP_DMA_IDLE) {
104 wait_until |= S_008040_WAIT_CP_DMA_IDLE(1);
105 }
106
107 if (wait_until) {
108 /* Use of WAIT_UNTIL is deprecated on Cayman+ */
109 if (rctx->b.family >= CHIP_CAYMAN) {
110 /* emit a PS partial flush on Cayman/TN */
111 rctx->b.flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
112 }
113 }
114
115 if (rctx->b.flags & R600_CONTEXT_PS_PARTIAL_FLUSH) {
116 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
117 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
118 }
119
120 if (rctx->b.chip_class >= R700 &&
121 (rctx->b.flags & R600_CONTEXT_FLUSH_AND_INV_CB_META)) {
122 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
123 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
124 }
125
126 if (rctx->b.chip_class >= R700 &&
127 (rctx->b.flags & R600_CONTEXT_FLUSH_AND_INV_DB_META)) {
128 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
129 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
130
131 /* Set FULL_CACHE_ENA for DB META flushes on r7xx and later.
132 *
133 * This hack predates use of FLUSH_AND_INV_DB_META, so it's
134 * unclear whether it's still needed or even whether it has
135 * any effect.
136 */
137 cp_coher_cntl |= S_0085F0_FULL_CACHE_ENA(1);
138 }
139
140 if (rctx->b.flags & R600_CONTEXT_FLUSH_AND_INV ||
141 (rctx->b.chip_class == R600 && rctx->b.flags & R600_CONTEXT_STREAMOUT_FLUSH)) {
142 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
143 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
144 }
145
146 if (rctx->b.flags & R600_CONTEXT_INV_CONST_CACHE) {
147 /* Direct constant addressing uses the shader cache.
148 * Indirect contant addressing uses the vertex cache. */
149 cp_coher_cntl |= S_0085F0_SH_ACTION_ENA(1) |
150 (rctx->has_vertex_cache ? S_0085F0_VC_ACTION_ENA(1)
151 : S_0085F0_TC_ACTION_ENA(1));
152 }
153 if (rctx->b.flags & R600_CONTEXT_INV_VERTEX_CACHE) {
154 cp_coher_cntl |= rctx->has_vertex_cache ? S_0085F0_VC_ACTION_ENA(1)
155 : S_0085F0_TC_ACTION_ENA(1);
156 }
157 if (rctx->b.flags & R600_CONTEXT_INV_TEX_CACHE) {
158 /* Textures use the texture cache.
159 * Texture buffer objects use the vertex cache. */
160 cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1) |
161 (rctx->has_vertex_cache ? S_0085F0_VC_ACTION_ENA(1) : 0);
162 }
163
164 /* Don't use the DB CP COHER logic on r6xx.
165 * There are hw bugs.
166 */
167 if (rctx->b.chip_class >= R700 &&
168 (rctx->b.flags & R600_CONTEXT_FLUSH_AND_INV_DB)) {
169 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
170 S_0085F0_DB_DEST_BASE_ENA(1) |
171 S_0085F0_SMX_ACTION_ENA(1);
172 }
173
174 /* Don't use the CB CP COHER logic on r6xx.
175 * There are hw bugs.
176 */
177 if (rctx->b.chip_class >= R700 &&
178 (rctx->b.flags & R600_CONTEXT_FLUSH_AND_INV_CB)) {
179 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
180 S_0085F0_CB0_DEST_BASE_ENA(1) |
181 S_0085F0_CB1_DEST_BASE_ENA(1) |
182 S_0085F0_CB2_DEST_BASE_ENA(1) |
183 S_0085F0_CB3_DEST_BASE_ENA(1) |
184 S_0085F0_CB4_DEST_BASE_ENA(1) |
185 S_0085F0_CB5_DEST_BASE_ENA(1) |
186 S_0085F0_CB6_DEST_BASE_ENA(1) |
187 S_0085F0_CB7_DEST_BASE_ENA(1) |
188 S_0085F0_SMX_ACTION_ENA(1);
189 if (rctx->b.chip_class >= EVERGREEN)
190 cp_coher_cntl |= S_0085F0_CB8_DEST_BASE_ENA(1) |
191 S_0085F0_CB9_DEST_BASE_ENA(1) |
192 S_0085F0_CB10_DEST_BASE_ENA(1) |
193 S_0085F0_CB11_DEST_BASE_ENA(1);
194 }
195
196 if (rctx->b.chip_class >= R700 &&
197 rctx->b.flags & R600_CONTEXT_STREAMOUT_FLUSH) {
198 cp_coher_cntl |= S_0085F0_SO0_DEST_BASE_ENA(1) |
199 S_0085F0_SO1_DEST_BASE_ENA(1) |
200 S_0085F0_SO2_DEST_BASE_ENA(1) |
201 S_0085F0_SO3_DEST_BASE_ENA(1) |
202 S_0085F0_SMX_ACTION_ENA(1);
203 }
204
205 /* Workaround for buggy flushing on some R6xx chipsets. */
206 if ((rctx->b.flags & (R600_CONTEXT_FLUSH_AND_INV |
207 R600_CONTEXT_STREAMOUT_FLUSH)) &&
208 (rctx->b.family == CHIP_RV670 ||
209 rctx->b.family == CHIP_RS780 ||
210 rctx->b.family == CHIP_RS880)) {
211 cp_coher_cntl |= S_0085F0_CB1_DEST_BASE_ENA(1) |
212 S_0085F0_DEST_BASE_0_ENA(1);
213 }
214
215 if (cp_coher_cntl) {
216 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
217 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
218 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
219 radeon_emit(cs, 0); /* CP_COHER_BASE */
220 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
221 }
222
223 if (rctx->b.flags & R600_CONTEXT_START_PIPELINE_STATS) {
224 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
225 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) |
226 EVENT_INDEX(0));
227 } else if (rctx->b.flags & R600_CONTEXT_STOP_PIPELINE_STATS) {
228 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
229 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_STOP) |
230 EVENT_INDEX(0));
231 }
232
233 if (wait_until) {
234 /* Use of WAIT_UNTIL is deprecated on Cayman+ */
235 if (rctx->b.family < CHIP_CAYMAN) {
236 /* wait for things to settle */
237 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, wait_until);
238 }
239 }
240
241 /* everything is properly flushed */
242 rctx->b.flags = 0;
243 }
244
245 void r600_context_gfx_flush(void *context, unsigned flags,
246 struct pipe_fence_handle **fence)
247 {
248 struct r600_context *ctx = context;
249 struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
250
251 if (!radeon_emitted(cs, ctx->b.initial_gfx_cs_size) && !fence)
252 return;
253
254 r600_preflush_suspend_features(&ctx->b);
255
256 /* flush the framebuffer cache */
257 ctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV |
258 R600_CONTEXT_FLUSH_AND_INV_CB |
259 R600_CONTEXT_FLUSH_AND_INV_DB |
260 R600_CONTEXT_FLUSH_AND_INV_CB_META |
261 R600_CONTEXT_FLUSH_AND_INV_DB_META |
262 R600_CONTEXT_WAIT_3D_IDLE |
263 R600_CONTEXT_WAIT_CP_DMA_IDLE;
264
265 r600_flush_emit(ctx);
266
267 /* old kernels and userspace don't set SX_MISC, so we must reset it to 0 here */
268 if (ctx->b.chip_class == R600) {
269 radeon_set_context_reg(cs, R_028350_SX_MISC, 0);
270 }
271
272 /* force to keep tiling flags */
273 flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
274
275 /* Flush the CS. */
276 ctx->b.ws->cs_flush(cs, flags, fence);
277
278 r600_begin_new_cs(ctx);
279 }
280
281 void r600_begin_new_cs(struct r600_context *ctx)
282 {
283 unsigned shader;
284
285 ctx->b.flags = 0;
286 ctx->b.gtt = 0;
287 ctx->b.vram = 0;
288
289 /* Begin a new CS. */
290 r600_emit_command_buffer(ctx->b.gfx.cs, &ctx->start_cs_cmd);
291
292 /* Re-emit states. */
293 r600_mark_atom_dirty(ctx, &ctx->alphatest_state.atom);
294 r600_mark_atom_dirty(ctx, &ctx->blend_color.atom);
295 r600_mark_atom_dirty(ctx, &ctx->cb_misc_state.atom);
296 r600_mark_atom_dirty(ctx, &ctx->clip_misc_state.atom);
297 r600_mark_atom_dirty(ctx, &ctx->clip_state.atom);
298 r600_mark_atom_dirty(ctx, &ctx->db_misc_state.atom);
299 r600_mark_atom_dirty(ctx, &ctx->db_state.atom);
300 r600_mark_atom_dirty(ctx, &ctx->framebuffer.atom);
301 r600_mark_atom_dirty(ctx, &ctx->hw_shader_stages[R600_HW_STAGE_PS].atom);
302 r600_mark_atom_dirty(ctx, &ctx->poly_offset_state.atom);
303 r600_mark_atom_dirty(ctx, &ctx->vgt_state.atom);
304 r600_mark_atom_dirty(ctx, &ctx->sample_mask.atom);
305 ctx->b.scissors.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
306 r600_mark_atom_dirty(ctx, &ctx->b.scissors.atom);
307 ctx->b.viewports.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
308 r600_mark_atom_dirty(ctx, &ctx->b.viewports.atom);
309 if (ctx->b.chip_class <= EVERGREEN) {
310 r600_mark_atom_dirty(ctx, &ctx->config_state.atom);
311 }
312 r600_mark_atom_dirty(ctx, &ctx->stencil_ref.atom);
313 r600_mark_atom_dirty(ctx, &ctx->vertex_fetch_shader.atom);
314 r600_mark_atom_dirty(ctx, &ctx->hw_shader_stages[R600_HW_STAGE_ES].atom);
315 r600_mark_atom_dirty(ctx, &ctx->shader_stages.atom);
316 if (ctx->gs_shader) {
317 r600_mark_atom_dirty(ctx, &ctx->hw_shader_stages[R600_HW_STAGE_GS].atom);
318 r600_mark_atom_dirty(ctx, &ctx->gs_rings.atom);
319 }
320 if (ctx->tes_shader) {
321 r600_mark_atom_dirty(ctx, &ctx->hw_shader_stages[EG_HW_STAGE_HS].atom);
322 r600_mark_atom_dirty(ctx, &ctx->hw_shader_stages[EG_HW_STAGE_LS].atom);
323 }
324 r600_mark_atom_dirty(ctx, &ctx->hw_shader_stages[R600_HW_STAGE_VS].atom);
325 r600_mark_atom_dirty(ctx, &ctx->b.streamout.enable_atom);
326 r600_mark_atom_dirty(ctx, &ctx->b.render_cond_atom);
327
328 if (ctx->blend_state.cso)
329 r600_mark_atom_dirty(ctx, &ctx->blend_state.atom);
330 if (ctx->dsa_state.cso)
331 r600_mark_atom_dirty(ctx, &ctx->dsa_state.atom);
332 if (ctx->rasterizer_state.cso)
333 r600_mark_atom_dirty(ctx, &ctx->rasterizer_state.atom);
334
335 if (ctx->b.chip_class <= R700) {
336 r600_mark_atom_dirty(ctx, &ctx->seamless_cube_map.atom);
337 }
338
339 ctx->vertex_buffer_state.dirty_mask = ctx->vertex_buffer_state.enabled_mask;
340 r600_vertex_buffers_dirty(ctx);
341
342 /* Re-emit shader resources. */
343 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
344 struct r600_constbuf_state *constbuf = &ctx->constbuf_state[shader];
345 struct r600_textures_info *samplers = &ctx->samplers[shader];
346
347 constbuf->dirty_mask = constbuf->enabled_mask;
348 samplers->views.dirty_mask = samplers->views.enabled_mask;
349 samplers->states.dirty_mask = samplers->states.enabled_mask;
350
351 r600_constant_buffers_dirty(ctx, constbuf);
352 r600_sampler_views_dirty(ctx, &samplers->views);
353 r600_sampler_states_dirty(ctx, &samplers->states);
354 }
355
356 r600_postflush_resume_features(&ctx->b);
357
358 /* Re-emit the draw state. */
359 ctx->last_primitive_type = -1;
360 ctx->last_start_instance = -1;
361
362 ctx->b.initial_gfx_cs_size = ctx->b.gfx.cs->cdw;
363 }
364
365 /* The max number of bytes to copy per packet. */
366 #define CP_DMA_MAX_BYTE_COUNT ((1 << 21) - 8)
367
368 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
369 struct pipe_resource *dst, uint64_t dst_offset,
370 struct pipe_resource *src, uint64_t src_offset,
371 unsigned size)
372 {
373 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
374
375 assert(size);
376 assert(rctx->screen->b.has_cp_dma);
377
378 /* Mark the buffer range of destination as valid (initialized),
379 * so that transfer_map knows it should wait for the GPU when mapping
380 * that range. */
381 util_range_add(&r600_resource(dst)->valid_buffer_range, dst_offset,
382 dst_offset + size);
383
384 dst_offset += r600_resource(dst)->gpu_address;
385 src_offset += r600_resource(src)->gpu_address;
386
387 /* Flush the caches where the resources are bound. */
388 rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE |
389 R600_CONTEXT_INV_VERTEX_CACHE |
390 R600_CONTEXT_INV_TEX_CACHE |
391 R600_CONTEXT_FLUSH_AND_INV |
392 R600_CONTEXT_FLUSH_AND_INV_CB |
393 R600_CONTEXT_FLUSH_AND_INV_DB |
394 R600_CONTEXT_FLUSH_AND_INV_CB_META |
395 R600_CONTEXT_FLUSH_AND_INV_DB_META |
396 R600_CONTEXT_STREAMOUT_FLUSH |
397 R600_CONTEXT_WAIT_3D_IDLE;
398
399 /* There are differences between R700 and EG in CP DMA,
400 * but we only use the common bits here. */
401 while (size) {
402 unsigned sync = 0;
403 unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
404 unsigned src_reloc, dst_reloc;
405
406 r600_need_cs_space(rctx, 10 + (rctx->b.flags ? R600_MAX_FLUSH_CS_DWORDS : 0), FALSE);
407
408 /* Flush the caches for the first copy only. */
409 if (rctx->b.flags) {
410 r600_flush_emit(rctx);
411 }
412
413 /* Do the synchronization after the last copy, so that all data is written to memory. */
414 if (size == byte_count) {
415 sync = PKT3_CP_DMA_CP_SYNC;
416 }
417
418 /* This must be done after r600_need_cs_space. */
419 src_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, (struct r600_resource*)src,
420 RADEON_USAGE_READ, RADEON_PRIO_CP_DMA);
421 dst_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, (struct r600_resource*)dst,
422 RADEON_USAGE_WRITE, RADEON_PRIO_CP_DMA);
423
424 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
425 radeon_emit(cs, src_offset); /* SRC_ADDR_LO [31:0] */
426 radeon_emit(cs, sync | ((src_offset >> 32) & 0xff)); /* CP_SYNC [31] | SRC_ADDR_HI [7:0] */
427 radeon_emit(cs, dst_offset); /* DST_ADDR_LO [31:0] */
428 radeon_emit(cs, (dst_offset >> 32) & 0xff); /* DST_ADDR_HI [7:0] */
429 radeon_emit(cs, byte_count); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
430
431 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
432 radeon_emit(cs, src_reloc);
433 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
434 radeon_emit(cs, dst_reloc);
435
436 size -= byte_count;
437 src_offset += byte_count;
438 dst_offset += byte_count;
439 }
440
441 /* Invalidate the read caches. */
442 rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE |
443 R600_CONTEXT_INV_VERTEX_CACHE |
444 R600_CONTEXT_INV_TEX_CACHE;
445 }
446
447 void r600_dma_copy_buffer(struct r600_context *rctx,
448 struct pipe_resource *dst,
449 struct pipe_resource *src,
450 uint64_t dst_offset,
451 uint64_t src_offset,
452 uint64_t size)
453 {
454 struct radeon_winsys_cs *cs = rctx->b.dma.cs;
455 unsigned i, ncopy, csize;
456 struct r600_resource *rdst = (struct r600_resource*)dst;
457 struct r600_resource *rsrc = (struct r600_resource*)src;
458
459 /* Mark the buffer range of destination as valid (initialized),
460 * so that transfer_map knows it should wait for the GPU when mapping
461 * that range. */
462 util_range_add(&rdst->valid_buffer_range, dst_offset,
463 dst_offset + size);
464
465 size >>= 2; /* convert to dwords */
466 ncopy = (size / R600_DMA_COPY_MAX_SIZE_DW) + !!(size % R600_DMA_COPY_MAX_SIZE_DW);
467
468 r600_need_dma_space(&rctx->b, ncopy * 5, rdst, rsrc);
469 for (i = 0; i < ncopy; i++) {
470 csize = size < R600_DMA_COPY_MAX_SIZE_DW ? size : R600_DMA_COPY_MAX_SIZE_DW;
471 /* emit reloc before writing cs so that cs is always in consistent state */
472 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, rsrc, RADEON_USAGE_READ,
473 RADEON_PRIO_SDMA_BUFFER);
474 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, rdst, RADEON_USAGE_WRITE,
475 RADEON_PRIO_SDMA_BUFFER);
476 radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, 0, 0, csize));
477 radeon_emit(cs, dst_offset & 0xfffffffc);
478 radeon_emit(cs, src_offset & 0xfffffffc);
479 radeon_emit(cs, (dst_offset >> 32UL) & 0xff);
480 radeon_emit(cs, (src_offset >> 32UL) & 0xff);
481 dst_offset += csize << 2;
482 src_offset += csize << 2;
483 size -= csize;
484 }
485 r600_dma_emit_wait_idle(&rctx->b);
486 }