2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "r600_hw_context_priv.h"
28 #include "util/u_memory.h"
31 /* Get backends mask */
32 void r600_get_backend_mask(struct r600_context
*ctx
)
34 struct radeon_winsys_cs
*cs
= ctx
->cs
;
35 struct r600_resource
*buffer
;
37 unsigned num_backends
= ctx
->screen
->info
.r600_num_backends
;
41 /* if backend_map query is supported by the kernel */
42 if (ctx
->screen
->info
.r600_backend_map_valid
) {
43 unsigned num_tile_pipes
= ctx
->screen
->info
.r600_num_tile_pipes
;
44 unsigned backend_map
= ctx
->screen
->info
.r600_backend_map
;
45 unsigned item_width
, item_mask
;
47 if (ctx
->chip_class
>= EVERGREEN
) {
55 while(num_tile_pipes
--) {
56 i
= backend_map
& item_mask
;
58 backend_map
>>= item_width
;
61 ctx
->backend_mask
= mask
;
66 /* otherwise backup path for older kernels */
68 /* create buffer for event data */
69 buffer
= (struct r600_resource
*)
70 pipe_buffer_create(&ctx
->screen
->screen
, PIPE_BIND_CUSTOM
,
71 PIPE_USAGE_STAGING
, ctx
->max_db
*16);
75 va
= r600_resource_va(&ctx
->screen
->screen
, (void*)buffer
);
77 /* initialize buffer with zeroes */
78 results
= ctx
->ws
->buffer_map(buffer
->cs_buf
, ctx
->cs
, PIPE_TRANSFER_WRITE
);
80 memset(results
, 0, ctx
->max_db
* 4 * 4);
81 ctx
->ws
->buffer_unmap(buffer
->cs_buf
);
83 /* emit EVENT_WRITE for ZPASS_DONE */
84 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_EVENT_WRITE
, 2, 0);
85 cs
->buf
[cs
->cdw
++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE
) | EVENT_INDEX(1);
86 cs
->buf
[cs
->cdw
++] = va
;
87 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFF;
89 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
90 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(ctx
, buffer
, RADEON_USAGE_WRITE
);
93 results
= ctx
->ws
->buffer_map(buffer
->cs_buf
, ctx
->cs
, PIPE_TRANSFER_READ
);
95 for(i
= 0; i
< ctx
->max_db
; i
++) {
96 /* at least highest bit will be set if backend is used */
100 ctx
->ws
->buffer_unmap(buffer
->cs_buf
);
104 pipe_resource_reference((struct pipe_resource
**)&buffer
, NULL
);
107 ctx
->backend_mask
= mask
;
112 /* fallback to old method - set num_backends lower bits to 1 */
113 ctx
->backend_mask
= (~((uint32_t)0))>>(32-num_backends
);
117 static void r600_init_block(struct r600_context
*ctx
,
118 struct r600_block
*block
,
119 const struct r600_reg
*reg
, int index
, int nreg
,
120 unsigned opcode
, unsigned offset_base
)
125 /* initialize block */
127 block
->status
|= R600_BLOCK_STATUS_DIRTY
; /* dirty all blocks at start */
128 block
->start_offset
= reg
[i
].offset
;
129 block
->pm4
[block
->pm4_ndwords
++] = PKT3(opcode
, n
, 0);
130 block
->pm4
[block
->pm4_ndwords
++] = (block
->start_offset
- offset_base
) >> 2;
131 block
->reg
= &block
->pm4
[block
->pm4_ndwords
];
132 block
->pm4_ndwords
+= n
;
134 block
->nreg_dirty
= n
;
135 LIST_INITHEAD(&block
->list
);
136 LIST_INITHEAD(&block
->enable_list
);
138 for (j
= 0; j
< n
; j
++) {
139 if (reg
[i
+j
].flags
& REG_FLAG_DIRTY_ALWAYS
) {
140 block
->flags
|= REG_FLAG_DIRTY_ALWAYS
;
142 if (reg
[i
+j
].flags
& REG_FLAG_ENABLE_ALWAYS
) {
143 if (!(block
->status
& R600_BLOCK_STATUS_ENABLED
)) {
144 block
->status
|= R600_BLOCK_STATUS_ENABLED
;
145 LIST_ADDTAIL(&block
->enable_list
, &ctx
->enable_list
);
146 LIST_ADDTAIL(&block
->list
,&ctx
->dirty
);
149 if (reg
[i
+j
].flags
& REG_FLAG_FLUSH_CHANGE
) {
150 block
->flags
|= REG_FLAG_FLUSH_CHANGE
;
153 if (reg
[i
+j
].flags
& REG_FLAG_NEED_BO
) {
155 assert(block
->nbo
< R600_BLOCK_MAX_BO
);
156 block
->pm4_bo_index
[j
] = block
->nbo
;
157 block
->pm4
[block
->pm4_ndwords
++] = PKT3(PKT3_NOP
, 0, 0);
158 block
->pm4
[block
->pm4_ndwords
++] = 0x00000000;
159 block
->reloc
[block
->nbo
].bo_pm4_index
= block
->pm4_ndwords
- 1;
161 if ((ctx
->family
> CHIP_R600
) &&
162 (ctx
->family
< CHIP_RV770
) && reg
[i
+j
].flags
& REG_FLAG_RV6XX_SBU
) {
163 block
->pm4
[block
->pm4_ndwords
++] = PKT3(PKT3_SURFACE_BASE_UPDATE
, 0, 0);
164 block
->pm4
[block
->pm4_ndwords
++] = reg
[i
+j
].sbu_flags
;
167 /* check that we stay in limit */
168 assert(block
->pm4_ndwords
< R600_BLOCK_MAX_REG
);
171 int r600_context_add_block(struct r600_context
*ctx
, const struct r600_reg
*reg
, unsigned nreg
,
172 unsigned opcode
, unsigned offset_base
)
174 struct r600_block
*block
;
175 struct r600_range
*range
;
178 for (unsigned i
= 0, n
= 0; i
< nreg
; i
+= n
) {
179 /* ignore new block balise */
180 if (reg
[i
].offset
== GROUP_FORCE_NEW_BLOCK
) {
185 /* ignore regs not on R600 on R600 */
186 if ((reg
[i
].flags
& REG_FLAG_NOT_R600
) && ctx
->family
== CHIP_R600
) {
191 /* register that need relocation are in their own group */
192 /* find number of consecutive registers */
194 offset
= reg
[i
].offset
;
195 while (reg
[i
+ n
].offset
== offset
) {
200 if (n
>= (R600_BLOCK_MAX_REG
- 2))
204 /* allocate new block */
205 block
= calloc(1, sizeof(struct r600_block
));
210 for (int j
= 0; j
< n
; j
++) {
211 range
= &ctx
->range
[CTX_RANGE_ID(reg
[i
+ j
].offset
)];
212 /* create block table if it doesn't exist */
214 range
->blocks
= calloc(1 << HASH_SHIFT
, sizeof(void *));
218 range
->blocks
[CTX_BLOCK_ID(reg
[i
+ j
].offset
)] = block
;
221 r600_init_block(ctx
, block
, reg
, i
, n
, opcode
, offset_base
);
227 /* R600/R700 configuration */
228 static const struct r600_reg r600_config_reg_list
[] = {
229 {R_008958_VGT_PRIMITIVE_TYPE
, 0, 0},
230 {R_008B40_PA_SC_AA_SAMPLE_LOCS_2S
, 0, 0},
231 {R_008B44_PA_SC_AA_SAMPLE_LOCS_4S
, 0, 0},
232 {R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0
, 0, 0},
233 {R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1
, 0, 0},
234 {R_008C04_SQ_GPR_RESOURCE_MGMT_1
, REG_FLAG_ENABLE_ALWAYS
| REG_FLAG_FLUSH_CHANGE
, 0},
237 static const struct r600_reg r600_ctl_const_list
[] = {
238 {R_03CFF4_SQ_VTX_START_INST_LOC
, 0, 0},
241 static const struct r600_reg r600_context_reg_list
[] = {
242 {R_028A4C_PA_SC_MODE_CNTL
, 0, 0},
243 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
244 {R_028040_CB_COLOR0_BASE
, REG_FLAG_NEED_BO
|REG_FLAG_RV6XX_SBU
, SURFACE_BASE_UPDATE_COLOR(0)},
245 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
246 {R_0280A0_CB_COLOR0_INFO
, REG_FLAG_NEED_BO
, 0},
247 {R_028060_CB_COLOR0_SIZE
, 0, 0},
248 {R_028080_CB_COLOR0_VIEW
, 0, 0},
249 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
250 {R_0280E0_CB_COLOR0_FRAG
, REG_FLAG_NEED_BO
, 0},
251 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
252 {R_0280C0_CB_COLOR0_TILE
, REG_FLAG_NEED_BO
, 0},
253 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
254 {R_028100_CB_COLOR0_MASK
, 0, 0},
255 {R_028044_CB_COLOR1_BASE
, REG_FLAG_NEED_BO
|REG_FLAG_RV6XX_SBU
, SURFACE_BASE_UPDATE_COLOR(1)},
256 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
257 {R_0280A4_CB_COLOR1_INFO
, REG_FLAG_NEED_BO
, 0},
258 {R_028064_CB_COLOR1_SIZE
, 0, 0},
259 {R_028084_CB_COLOR1_VIEW
, 0, 0},
260 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
261 {R_0280E4_CB_COLOR1_FRAG
, REG_FLAG_NEED_BO
, 0},
262 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
263 {R_0280C4_CB_COLOR1_TILE
, REG_FLAG_NEED_BO
, 0},
264 {R_028104_CB_COLOR1_MASK
, 0, 0},
265 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
266 {R_028048_CB_COLOR2_BASE
, REG_FLAG_NEED_BO
|REG_FLAG_RV6XX_SBU
, SURFACE_BASE_UPDATE_COLOR(2)},
267 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
268 {R_0280A8_CB_COLOR2_INFO
, REG_FLAG_NEED_BO
, 0},
269 {R_028068_CB_COLOR2_SIZE
, 0, 0},
270 {R_028088_CB_COLOR2_VIEW
, 0, 0},
271 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
272 {R_0280E8_CB_COLOR2_FRAG
, REG_FLAG_NEED_BO
, 0},
273 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
274 {R_0280C8_CB_COLOR2_TILE
, REG_FLAG_NEED_BO
, 0},
275 {R_028108_CB_COLOR2_MASK
, 0, 0},
276 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
277 {R_02804C_CB_COLOR3_BASE
, REG_FLAG_NEED_BO
|REG_FLAG_RV6XX_SBU
, SURFACE_BASE_UPDATE_COLOR(3)},
278 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
279 {R_0280AC_CB_COLOR3_INFO
, REG_FLAG_NEED_BO
, 0},
280 {R_02806C_CB_COLOR3_SIZE
, 0, 0},
281 {R_02808C_CB_COLOR3_VIEW
, 0, 0},
282 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
283 {R_0280EC_CB_COLOR3_FRAG
, REG_FLAG_NEED_BO
, 0},
284 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
285 {R_0280CC_CB_COLOR3_TILE
, REG_FLAG_NEED_BO
, 0},
286 {R_02810C_CB_COLOR3_MASK
, 0, 0},
287 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
288 {R_028050_CB_COLOR4_BASE
, REG_FLAG_NEED_BO
|REG_FLAG_RV6XX_SBU
, SURFACE_BASE_UPDATE_COLOR(4)},
289 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
290 {R_0280B0_CB_COLOR4_INFO
, REG_FLAG_NEED_BO
, 0},
291 {R_028070_CB_COLOR4_SIZE
, 0, 0},
292 {R_028090_CB_COLOR4_VIEW
, 0, 0},
293 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
294 {R_0280F0_CB_COLOR4_FRAG
, REG_FLAG_NEED_BO
, 0},
295 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
296 {R_0280D0_CB_COLOR4_TILE
, REG_FLAG_NEED_BO
, 0},
297 {R_028110_CB_COLOR4_MASK
, 0, 0},
298 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
299 {R_028054_CB_COLOR5_BASE
, REG_FLAG_NEED_BO
|REG_FLAG_RV6XX_SBU
, SURFACE_BASE_UPDATE_COLOR(5)},
300 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
301 {R_0280B4_CB_COLOR5_INFO
, REG_FLAG_NEED_BO
, 0},
302 {R_028074_CB_COLOR5_SIZE
, 0, 0},
303 {R_028094_CB_COLOR5_VIEW
, 0, 0},
304 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
305 {R_0280F4_CB_COLOR5_FRAG
, REG_FLAG_NEED_BO
, 0},
306 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
307 {R_0280D4_CB_COLOR5_TILE
, REG_FLAG_NEED_BO
, 0},
308 {R_028114_CB_COLOR5_MASK
, 0, 0},
309 {R_028058_CB_COLOR6_BASE
, REG_FLAG_NEED_BO
|REG_FLAG_RV6XX_SBU
, SURFACE_BASE_UPDATE_COLOR(6)},
310 {R_0280B8_CB_COLOR6_INFO
, REG_FLAG_NEED_BO
, 0},
311 {R_028078_CB_COLOR6_SIZE
, 0, 0},
312 {R_028098_CB_COLOR6_VIEW
, 0, 0},
313 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
314 {R_0280F8_CB_COLOR6_FRAG
, REG_FLAG_NEED_BO
, 0},
315 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
316 {R_0280D8_CB_COLOR6_TILE
, REG_FLAG_NEED_BO
, 0},
317 {R_028118_CB_COLOR6_MASK
, 0, 0},
318 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
319 {R_02805C_CB_COLOR7_BASE
, REG_FLAG_NEED_BO
|REG_FLAG_RV6XX_SBU
, SURFACE_BASE_UPDATE_COLOR(7)},
320 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
321 {R_0280BC_CB_COLOR7_INFO
, REG_FLAG_NEED_BO
, 0},
322 {R_02807C_CB_COLOR7_SIZE
, 0, 0},
323 {R_02809C_CB_COLOR7_VIEW
, 0, 0},
324 {R_0280FC_CB_COLOR7_FRAG
, REG_FLAG_NEED_BO
, 0},
325 {R_0280DC_CB_COLOR7_TILE
, REG_FLAG_NEED_BO
, 0},
326 {R_02811C_CB_COLOR7_MASK
, 0, 0},
327 {R_028120_CB_CLEAR_RED
, 0, 0},
328 {R_028124_CB_CLEAR_GREEN
, 0, 0},
329 {R_028128_CB_CLEAR_BLUE
, 0, 0},
330 {R_02812C_CB_CLEAR_ALPHA
, 0, 0},
331 {R_028414_CB_BLEND_RED
, 0, 0},
332 {R_028418_CB_BLEND_GREEN
, 0, 0},
333 {R_02841C_CB_BLEND_BLUE
, 0, 0},
334 {R_028420_CB_BLEND_ALPHA
, 0, 0},
335 {R_028424_CB_FOG_RED
, 0, 0},
336 {R_028428_CB_FOG_GREEN
, 0, 0},
337 {R_02842C_CB_FOG_BLUE
, 0, 0},
338 {R_028430_DB_STENCILREFMASK
, 0, 0},
339 {R_028434_DB_STENCILREFMASK_BF
, 0, 0},
340 {R_028780_CB_BLEND0_CONTROL
, REG_FLAG_NOT_R600
, 0},
341 {R_028784_CB_BLEND1_CONTROL
, REG_FLAG_NOT_R600
, 0},
342 {R_028788_CB_BLEND2_CONTROL
, REG_FLAG_NOT_R600
, 0},
343 {R_02878C_CB_BLEND3_CONTROL
, REG_FLAG_NOT_R600
, 0},
344 {R_028790_CB_BLEND4_CONTROL
, REG_FLAG_NOT_R600
, 0},
345 {R_028794_CB_BLEND5_CONTROL
, REG_FLAG_NOT_R600
, 0},
346 {R_028798_CB_BLEND6_CONTROL
, REG_FLAG_NOT_R600
, 0},
347 {R_02879C_CB_BLEND7_CONTROL
, REG_FLAG_NOT_R600
, 0},
348 {R_0287A0_CB_SHADER_CONTROL
, 0, 0},
349 {R_028800_DB_DEPTH_CONTROL
, 0, 0},
350 {R_028804_CB_BLEND_CONTROL
, 0, 0},
351 {R_02880C_DB_SHADER_CONTROL
, 0, 0},
352 {R_02800C_DB_DEPTH_BASE
, REG_FLAG_NEED_BO
|REG_FLAG_RV6XX_SBU
, SURFACE_BASE_UPDATE_DEPTH
},
353 {R_028000_DB_DEPTH_SIZE
, 0, 0},
354 {R_028004_DB_DEPTH_VIEW
, 0, 0},
355 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
356 {R_028010_DB_DEPTH_INFO
, REG_FLAG_NEED_BO
, 0},
357 {R_028A6C_VGT_GS_OUT_PRIM_TYPE
, 0, 0},
358 {R_028D24_DB_HTILE_SURFACE
, 0, 0},
359 {R_028D34_DB_PREFETCH_LIMIT
, 0, 0},
360 {R_028D44_DB_ALPHA_TO_MASK
, 0, 0},
361 {R_028204_PA_SC_WINDOW_SCISSOR_TL
, 0, 0},
362 {R_028208_PA_SC_WINDOW_SCISSOR_BR
, 0, 0},
363 {R_028250_PA_SC_VPORT_SCISSOR_0_TL
, 0, 0},
364 {R_028254_PA_SC_VPORT_SCISSOR_0_BR
, 0, 0},
365 {R_02843C_PA_CL_VPORT_XSCALE_0
, 0, 0},
366 {R_028440_PA_CL_VPORT_XOFFSET_0
, 0, 0},
367 {R_028444_PA_CL_VPORT_YSCALE_0
, 0, 0},
368 {R_028448_PA_CL_VPORT_YOFFSET_0
, 0, 0},
369 {R_02844C_PA_CL_VPORT_ZSCALE_0
, 0, 0},
370 {R_028450_PA_CL_VPORT_ZOFFSET_0
, 0, 0},
371 {R_0286D4_SPI_INTERP_CONTROL_0
, 0, 0},
372 {R_028810_PA_CL_CLIP_CNTL
, 0, 0},
373 {R_028814_PA_SU_SC_MODE_CNTL
, 0, 0},
374 {R_02881C_PA_CL_VS_OUT_CNTL
, 0, 0},
375 {R_028A00_PA_SU_POINT_SIZE
, 0, 0},
376 {R_028A04_PA_SU_POINT_MINMAX
, 0, 0},
377 {R_028A08_PA_SU_LINE_CNTL
, 0, 0},
378 {R_028A0C_PA_SC_LINE_STIPPLE
, 0, 0},
379 {R_028C00_PA_SC_LINE_CNTL
, 0, 0},
380 {R_028C04_PA_SC_AA_CONFIG
, 0, 0},
381 {R_028C08_PA_SU_VTX_CNTL
, 0, 0},
382 {R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL
, 0, 0},
383 {R_028DFC_PA_SU_POLY_OFFSET_CLAMP
, 0, 0},
384 {R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE
, 0, 0},
385 {R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET
, 0, 0},
386 {R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE
, 0, 0},
387 {R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET
, 0, 0},
388 {R_028E20_PA_CL_UCP0_X
, 0, 0},
389 {R_028E24_PA_CL_UCP0_Y
, 0, 0},
390 {R_028E28_PA_CL_UCP0_Z
, 0, 0},
391 {R_028E2C_PA_CL_UCP0_W
, 0, 0},
392 {R_028E30_PA_CL_UCP1_X
, 0, 0},
393 {R_028E34_PA_CL_UCP1_Y
, 0, 0},
394 {R_028E38_PA_CL_UCP1_Z
, 0, 0},
395 {R_028E3C_PA_CL_UCP1_W
, 0, 0},
396 {R_028E40_PA_CL_UCP2_X
, 0, 0},
397 {R_028E44_PA_CL_UCP2_Y
, 0, 0},
398 {R_028E48_PA_CL_UCP2_Z
, 0, 0},
399 {R_028E4C_PA_CL_UCP2_W
, 0, 0},
400 {R_028E50_PA_CL_UCP3_X
, 0, 0},
401 {R_028E54_PA_CL_UCP3_Y
, 0, 0},
402 {R_028E58_PA_CL_UCP3_Z
, 0, 0},
403 {R_028E5C_PA_CL_UCP3_W
, 0, 0},
404 {R_028E60_PA_CL_UCP4_X
, 0, 0},
405 {R_028E64_PA_CL_UCP4_Y
, 0, 0},
406 {R_028E68_PA_CL_UCP4_Z
, 0, 0},
407 {R_028E6C_PA_CL_UCP4_W
, 0, 0},
408 {R_028E70_PA_CL_UCP5_X
, 0, 0},
409 {R_028E74_PA_CL_UCP5_Y
, 0, 0},
410 {R_028E78_PA_CL_UCP5_Z
, 0, 0},
411 {R_028E7C_PA_CL_UCP5_W
, 0, 0},
412 {R_028350_SX_MISC
, 0, 0},
413 {R_028380_SQ_VTX_SEMANTIC_0
, 0, 0},
414 {R_028384_SQ_VTX_SEMANTIC_1
, 0, 0},
415 {R_028388_SQ_VTX_SEMANTIC_2
, 0, 0},
416 {R_02838C_SQ_VTX_SEMANTIC_3
, 0, 0},
417 {R_028390_SQ_VTX_SEMANTIC_4
, 0, 0},
418 {R_028394_SQ_VTX_SEMANTIC_5
, 0, 0},
419 {R_028398_SQ_VTX_SEMANTIC_6
, 0, 0},
420 {R_02839C_SQ_VTX_SEMANTIC_7
, 0, 0},
421 {R_0283A0_SQ_VTX_SEMANTIC_8
, 0, 0},
422 {R_0283A4_SQ_VTX_SEMANTIC_9
, 0, 0},
423 {R_0283A8_SQ_VTX_SEMANTIC_10
, 0, 0},
424 {R_0283AC_SQ_VTX_SEMANTIC_11
, 0, 0},
425 {R_0283B0_SQ_VTX_SEMANTIC_12
, 0, 0},
426 {R_0283B4_SQ_VTX_SEMANTIC_13
, 0, 0},
427 {R_0283B8_SQ_VTX_SEMANTIC_14
, 0, 0},
428 {R_0283BC_SQ_VTX_SEMANTIC_15
, 0, 0},
429 {R_0283C0_SQ_VTX_SEMANTIC_16
, 0, 0},
430 {R_0283C4_SQ_VTX_SEMANTIC_17
, 0, 0},
431 {R_0283C8_SQ_VTX_SEMANTIC_18
, 0, 0},
432 {R_0283CC_SQ_VTX_SEMANTIC_19
, 0, 0},
433 {R_0283D0_SQ_VTX_SEMANTIC_20
, 0, 0},
434 {R_0283D4_SQ_VTX_SEMANTIC_21
, 0, 0},
435 {R_0283D8_SQ_VTX_SEMANTIC_22
, 0, 0},
436 {R_0283DC_SQ_VTX_SEMANTIC_23
, 0, 0},
437 {R_0283E0_SQ_VTX_SEMANTIC_24
, 0, 0},
438 {R_0283E4_SQ_VTX_SEMANTIC_25
, 0, 0},
439 {R_0283E8_SQ_VTX_SEMANTIC_26
, 0, 0},
440 {R_0283EC_SQ_VTX_SEMANTIC_27
, 0, 0},
441 {R_0283F0_SQ_VTX_SEMANTIC_28
, 0, 0},
442 {R_0283F4_SQ_VTX_SEMANTIC_29
, 0, 0},
443 {R_0283F8_SQ_VTX_SEMANTIC_30
, 0, 0},
444 {R_0283FC_SQ_VTX_SEMANTIC_31
, 0, 0},
445 {R_028614_SPI_VS_OUT_ID_0
, 0, 0},
446 {R_028618_SPI_VS_OUT_ID_1
, 0, 0},
447 {R_02861C_SPI_VS_OUT_ID_2
, 0, 0},
448 {R_028620_SPI_VS_OUT_ID_3
, 0, 0},
449 {R_028624_SPI_VS_OUT_ID_4
, 0, 0},
450 {R_028628_SPI_VS_OUT_ID_5
, 0, 0},
451 {R_02862C_SPI_VS_OUT_ID_6
, 0, 0},
452 {R_028630_SPI_VS_OUT_ID_7
, 0, 0},
453 {R_028634_SPI_VS_OUT_ID_8
, 0, 0},
454 {R_028638_SPI_VS_OUT_ID_9
, 0, 0},
455 {R_0286C4_SPI_VS_OUT_CONFIG
, 0, 0},
456 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
457 {R_028858_SQ_PGM_START_VS
, REG_FLAG_NEED_BO
, 0},
458 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
459 {R_028868_SQ_PGM_RESOURCES_VS
, 0, 0},
460 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
461 {R_028894_SQ_PGM_START_FS
, REG_FLAG_NEED_BO
, 0},
462 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
463 {R_0288A4_SQ_PGM_RESOURCES_FS
, 0, 0},
464 {R_0288DC_SQ_PGM_CF_OFFSET_FS
, 0, 0},
465 {R_028644_SPI_PS_INPUT_CNTL_0
, 0, 0},
466 {R_028648_SPI_PS_INPUT_CNTL_1
, 0, 0},
467 {R_02864C_SPI_PS_INPUT_CNTL_2
, 0, 0},
468 {R_028650_SPI_PS_INPUT_CNTL_3
, 0, 0},
469 {R_028654_SPI_PS_INPUT_CNTL_4
, 0, 0},
470 {R_028658_SPI_PS_INPUT_CNTL_5
, 0, 0},
471 {R_02865C_SPI_PS_INPUT_CNTL_6
, 0, 0},
472 {R_028660_SPI_PS_INPUT_CNTL_7
, 0, 0},
473 {R_028664_SPI_PS_INPUT_CNTL_8
, 0, 0},
474 {R_028668_SPI_PS_INPUT_CNTL_9
, 0, 0},
475 {R_02866C_SPI_PS_INPUT_CNTL_10
, 0, 0},
476 {R_028670_SPI_PS_INPUT_CNTL_11
, 0, 0},
477 {R_028674_SPI_PS_INPUT_CNTL_12
, 0, 0},
478 {R_028678_SPI_PS_INPUT_CNTL_13
, 0, 0},
479 {R_02867C_SPI_PS_INPUT_CNTL_14
, 0, 0},
480 {R_028680_SPI_PS_INPUT_CNTL_15
, 0, 0},
481 {R_028684_SPI_PS_INPUT_CNTL_16
, 0, 0},
482 {R_028688_SPI_PS_INPUT_CNTL_17
, 0, 0},
483 {R_02868C_SPI_PS_INPUT_CNTL_18
, 0, 0},
484 {R_028690_SPI_PS_INPUT_CNTL_19
, 0, 0},
485 {R_028694_SPI_PS_INPUT_CNTL_20
, 0, 0},
486 {R_028698_SPI_PS_INPUT_CNTL_21
, 0, 0},
487 {R_02869C_SPI_PS_INPUT_CNTL_22
, 0, 0},
488 {R_0286A0_SPI_PS_INPUT_CNTL_23
, 0, 0},
489 {R_0286A4_SPI_PS_INPUT_CNTL_24
, 0, 0},
490 {R_0286A8_SPI_PS_INPUT_CNTL_25
, 0, 0},
491 {R_0286AC_SPI_PS_INPUT_CNTL_26
, 0, 0},
492 {R_0286B0_SPI_PS_INPUT_CNTL_27
, 0, 0},
493 {R_0286B4_SPI_PS_INPUT_CNTL_28
, 0, 0},
494 {R_0286B8_SPI_PS_INPUT_CNTL_29
, 0, 0},
495 {R_0286BC_SPI_PS_INPUT_CNTL_30
, 0, 0},
496 {R_0286C0_SPI_PS_INPUT_CNTL_31
, 0, 0},
497 {R_0286CC_SPI_PS_IN_CONTROL_0
, 0, 0},
498 {R_0286D0_SPI_PS_IN_CONTROL_1
, 0, 0},
499 {R_0286D8_SPI_INPUT_Z
, 0, 0},
500 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
501 {R_028840_SQ_PGM_START_PS
, REG_FLAG_NEED_BO
, 0},
502 {GROUP_FORCE_NEW_BLOCK
, 0, 0},
503 {R_028850_SQ_PGM_RESOURCES_PS
, 0, 0},
504 {R_028854_SQ_PGM_EXPORTS_PS
, 0, 0},
505 {R_028408_VGT_INDX_OFFSET
, 0, 0},
506 {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
, 0, 0},
507 {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, 0, 0},
508 {R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 0, 0},
509 {R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX
, 0, 0},
512 static int r600_loop_const_init(struct r600_context
*ctx
, uint32_t offset
)
515 struct r600_reg r600_loop_consts
[32];
518 for (i
= 0; i
< nreg
; i
++) {
519 r600_loop_consts
[i
].offset
= R600_LOOP_CONST_OFFSET
+ ((offset
+ i
) * 4);
520 r600_loop_consts
[i
].flags
= REG_FLAG_DIRTY_ALWAYS
;
521 r600_loop_consts
[i
].sbu_flags
= 0;
523 return r600_context_add_block(ctx
, r600_loop_consts
, nreg
, PKT3_SET_LOOP_CONST
, R600_LOOP_CONST_OFFSET
);
527 void r600_context_fini(struct r600_context
*ctx
)
529 struct r600_block
*block
;
530 struct r600_range
*range
;
533 for (int i
= 0; i
< NUM_RANGES
; i
++) {
534 if (!ctx
->range
[i
].blocks
)
536 for (int j
= 0; j
< (1 << HASH_SHIFT
); j
++) {
537 block
= ctx
->range
[i
].blocks
[j
];
539 for (int k
= 0, offset
= block
->start_offset
; k
< block
->nreg
; k
++, offset
+= 4) {
540 range
= &ctx
->range
[CTX_RANGE_ID(offset
)];
541 range
->blocks
[CTX_BLOCK_ID(offset
)] = NULL
;
543 for (int k
= 1; k
<= block
->nbo
; k
++) {
544 pipe_resource_reference((struct pipe_resource
**)&block
->reloc
[k
].bo
, NULL
);
549 free(ctx
->range
[i
].blocks
);
555 int r600_setup_block_table(struct r600_context
*ctx
)
557 /* setup block table */
559 ctx
->blocks
= calloc(ctx
->nblocks
, sizeof(void*));
562 for (int i
= 0; i
< NUM_RANGES
; i
++) {
563 if (!ctx
->range
[i
].blocks
)
565 for (int j
= 0, add
; j
< (1 << HASH_SHIFT
); j
++) {
566 if (!ctx
->range
[i
].blocks
[j
])
570 for (int k
= 0; k
< c
; k
++) {
571 if (ctx
->blocks
[k
] == ctx
->range
[i
].blocks
[j
]) {
577 assert(c
< ctx
->nblocks
);
578 ctx
->blocks
[c
++] = ctx
->range
[i
].blocks
[j
];
579 j
+= (ctx
->range
[i
].blocks
[j
]->nreg
) - 1;
586 int r600_context_init(struct r600_context
*ctx
)
591 r
= r600_context_add_block(ctx
, r600_config_reg_list
,
592 Elements(r600_config_reg_list
), PKT3_SET_CONFIG_REG
, R600_CONFIG_REG_OFFSET
);
595 r
= r600_context_add_block(ctx
, r600_context_reg_list
,
596 Elements(r600_context_reg_list
), PKT3_SET_CONTEXT_REG
, R600_CONTEXT_REG_OFFSET
);
599 r
= r600_context_add_block(ctx
, r600_ctl_const_list
,
600 Elements(r600_ctl_const_list
), PKT3_SET_CTL_CONST
, R600_CTL_CONST_OFFSET
);
605 r600_loop_const_init(ctx
, 0);
607 r600_loop_const_init(ctx
, 32);
609 r
= r600_setup_block_table(ctx
);
616 r600_context_fini(ctx
);
620 void r600_need_cs_space(struct r600_context
*ctx
, unsigned num_dw
,
621 boolean count_draw_in
)
623 /* The number of dwords we already used in the CS so far. */
624 num_dw
+= ctx
->cs
->cdw
;
629 /* The number of dwords all the dirty states would take. */
630 for (i
= 0; i
< R600_MAX_ATOM
; i
++) {
631 if (ctx
->atoms
[i
] && ctx
->atoms
[i
]->dirty
) {
632 num_dw
+= ctx
->atoms
[i
]->num_dw
;
636 num_dw
+= ctx
->pm4_dirty_cdwords
;
638 /* The upper-bound of how much a draw command would take. */
639 num_dw
+= R600_MAX_DRAW_CS_DWORDS
;
642 /* Count in queries_suspend. */
643 num_dw
+= ctx
->num_cs_dw_nontimer_queries_suspend
;
644 num_dw
+= ctx
->num_cs_dw_timer_queries_suspend
;
646 /* Count in streamout_end at the end of CS. */
647 num_dw
+= ctx
->num_cs_dw_streamout_end
;
649 /* Count in render_condition(NULL) at the end of CS. */
650 if (ctx
->predicate_drawing
) {
654 /* Count in framebuffer cache flushes at the end of CS. */
655 num_dw
+= 44; /* one SURFACE_SYNC and CACHE_FLUSH_AND_INV (r6xx-only) */
657 /* Save 16 dwords for the fence mechanism. */
660 /* Flush if there's not enough space. */
661 if (num_dw
> RADEON_MAX_CMDBUF_DWORDS
) {
662 r600_flush(&ctx
->context
, NULL
, RADEON_FLUSH_ASYNC
);
666 void r600_context_dirty_block(struct r600_context
*ctx
,
667 struct r600_block
*block
,
668 int dirty
, int index
)
670 if ((index
+ 1) > block
->nreg_dirty
)
671 block
->nreg_dirty
= index
+ 1;
673 if ((dirty
!= (block
->status
& R600_BLOCK_STATUS_DIRTY
)) || !(block
->status
& R600_BLOCK_STATUS_ENABLED
)) {
674 block
->status
|= R600_BLOCK_STATUS_DIRTY
;
675 ctx
->pm4_dirty_cdwords
+= block
->pm4_ndwords
;
676 if (!(block
->status
& R600_BLOCK_STATUS_ENABLED
)) {
677 block
->status
|= R600_BLOCK_STATUS_ENABLED
;
678 LIST_ADDTAIL(&block
->enable_list
, &ctx
->enable_list
);
680 LIST_ADDTAIL(&block
->list
,&ctx
->dirty
);
682 if (block
->flags
& REG_FLAG_FLUSH_CHANGE
) {
683 ctx
->flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
689 * If reg needs a reloc, this function will add it to its block's reloc list.
690 * @return true if reg needs a reloc, false otherwise
692 static bool r600_reg_set_block_reloc(struct r600_pipe_reg
*reg
)
696 if (!reg
->block
->pm4_bo_index
[reg
->id
]) {
699 /* find relocation */
700 reloc_id
= reg
->block
->pm4_bo_index
[reg
->id
];
701 pipe_resource_reference(
702 (struct pipe_resource
**)®
->block
->reloc
[reloc_id
].bo
,
704 reg
->block
->reloc
[reloc_id
].bo_usage
= reg
->bo_usage
;
709 * This function will emit all the registers in state directly to the command
710 * stream allowing you to bypass the r600_context dirty list.
712 * This is used for dispatching compute shaders to avoid mixing compute and
713 * 3D states in the context's dirty list.
715 * @param pkt_flags Should be either 0 or RADEON_CP_PACKET3_COMPUTE_MODE. This
716 * value will be passed on to r600_context_block_emit_dirty an or'd against
719 void r600_context_pipe_state_emit(struct r600_context
*ctx
,
720 struct r600_pipe_state
*state
,
725 /* Mark all blocks as dirty:
726 * Since two registers can be in the same block, we need to make sure
727 * we mark all the blocks dirty before we emit any of them. If we were
728 * to mark blocks dirty and emit them in the same loop, like this:
730 * foreach (reg in state->regs) {
731 * mark_dirty(reg->block)
732 * emit_block(reg->block)
735 * Then if we have two registers in this state that are in the same
736 * block, we would end up emitting that block twice.
738 for (i
= 0; i
< state
->nregs
; i
++) {
739 struct r600_pipe_reg
*reg
= &state
->regs
[i
];
740 /* Mark all the registers in the block as dirty */
741 reg
->block
->nreg_dirty
= reg
->block
->nreg
;
742 reg
->block
->status
|= R600_BLOCK_STATUS_DIRTY
;
743 /* Update the reloc for this register if necessary. */
744 r600_reg_set_block_reloc(reg
);
747 /* Emit the registers writes */
748 for (i
= 0; i
< state
->nregs
; i
++) {
749 struct r600_pipe_reg
*reg
= &state
->regs
[i
];
750 if (reg
->block
->status
& R600_BLOCK_STATUS_DIRTY
) {
751 r600_context_block_emit_dirty(ctx
, reg
->block
, pkt_flags
);
756 void r600_context_pipe_state_set(struct r600_context
*ctx
, struct r600_pipe_state
*state
)
758 struct r600_block
*block
;
760 for (int i
= 0; i
< state
->nregs
; i
++) {
762 struct r600_pipe_reg
*reg
= &state
->regs
[i
];
767 dirty
= block
->status
& R600_BLOCK_STATUS_DIRTY
;
769 if (reg
->value
!= block
->reg
[id
]) {
770 block
->reg
[id
] = reg
->value
;
771 dirty
|= R600_BLOCK_STATUS_DIRTY
;
773 if (block
->flags
& REG_FLAG_DIRTY_ALWAYS
)
774 dirty
|= R600_BLOCK_STATUS_DIRTY
;
775 if (r600_reg_set_block_reloc(reg
)) {
776 /* always force dirty for relocs for now */
777 dirty
|= R600_BLOCK_STATUS_DIRTY
;
781 r600_context_dirty_block(ctx
, block
, dirty
, id
);
786 * @param pkt_flags should be set to RADEON_CP_PACKET3_COMPUTE_MODE if this
787 * block will be used for compute shaders.
789 void r600_context_block_emit_dirty(struct r600_context
*ctx
, struct r600_block
*block
,
792 struct radeon_winsys_cs
*cs
= ctx
->cs
;
793 int optional
= block
->nbo
== 0 && !(block
->flags
& REG_FLAG_DIRTY_ALWAYS
);
794 int cp_dwords
= block
->pm4_ndwords
, start_dword
= 0;
796 int nbo
= block
->nbo
;
798 if (block
->nreg_dirty
== 0 && optional
) {
803 for (int j
= 0; j
< block
->nreg
; j
++) {
804 if (block
->pm4_bo_index
[j
]) {
805 /* find relocation */
806 struct r600_block_reloc
*reloc
= &block
->reloc
[block
->pm4_bo_index
[j
]];
808 block
->pm4
[reloc
->bo_pm4_index
] =
809 r600_context_bo_reloc(ctx
, reloc
->bo
, reloc
->bo_usage
);
811 block
->pm4
[reloc
->bo_pm4_index
] = 0;
821 optional
&= (block
->nreg_dirty
!= block
->nreg
);
823 new_dwords
= block
->nreg_dirty
;
824 start_dword
= cs
->cdw
;
825 cp_dwords
= new_dwords
+ 2;
827 memcpy(&cs
->buf
[cs
->cdw
], block
->pm4
, cp_dwords
* 4);
829 /* We are applying the pkt_flags after copying the register block to
830 * the the command stream, because it is possible this block will be
831 * emitted with a different pkt_flags, and we don't want to store the
832 * pkt_flags in the block.
834 cs
->buf
[cs
->cdw
] |= pkt_flags
;
835 cs
->cdw
+= cp_dwords
;
840 newword
= cs
->buf
[start_dword
];
841 newword
&= PKT_COUNT_C
;
842 newword
|= PKT_COUNT_S(new_dwords
);
843 cs
->buf
[start_dword
] = newword
;
846 block
->status
^= R600_BLOCK_STATUS_DIRTY
;
847 block
->nreg_dirty
= 0;
848 LIST_DELINIT(&block
->list
);
851 void r600_flush_emit(struct r600_context
*rctx
)
853 struct radeon_winsys_cs
*cs
= rctx
->cs
;
859 if (rctx
->flags
& R600_CONTEXT_PS_PARTIAL_FLUSH
) {
860 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_EVENT_WRITE
, 0, 0);
861 cs
->buf
[cs
->cdw
++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4);
864 if (rctx
->flags
& R600_CONTEXT_FLUSH_AND_INV
) {
865 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_EVENT_WRITE
, 0, 0);
866 cs
->buf
[cs
->cdw
++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT
) | EVENT_INDEX(0);
868 /* DB flushes are special due to errata with hyperz, we need to
869 * insert a no-op, so that the cache has time to really flush.
871 if (rctx
->chip_class
<= R700
&&
872 rctx
->flags
& R600_CONTEXT_HTILE_ERRATA
) {
873 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 31, 0);
874 cs
->buf
[cs
->cdw
++] = 0xdeadcafe;
875 cs
->buf
[cs
->cdw
++] = 0xdeadcafe;
876 cs
->buf
[cs
->cdw
++] = 0xdeadcafe;
877 cs
->buf
[cs
->cdw
++] = 0xdeadcafe;
878 cs
->buf
[cs
->cdw
++] = 0xdeadcafe;
879 cs
->buf
[cs
->cdw
++] = 0xdeadcafe;
880 cs
->buf
[cs
->cdw
++] = 0xdeadcafe;
881 cs
->buf
[cs
->cdw
++] = 0xdeadcafe;
882 cs
->buf
[cs
->cdw
++] = 0xdeadcafe;
883 cs
->buf
[cs
->cdw
++] = 0xdeadcafe;
884 cs
->buf
[cs
->cdw
++] = 0xdeadcafe;
885 cs
->buf
[cs
->cdw
++] = 0xdeadcafe;
886 cs
->buf
[cs
->cdw
++] = 0xdeadcafe;
887 cs
->buf
[cs
->cdw
++] = 0xdeadcafe;
888 cs
->buf
[cs
->cdw
++] = 0xdeadcafe;
889 cs
->buf
[cs
->cdw
++] = 0xdeadcafe;
890 cs
->buf
[cs
->cdw
++] = 0xdeadcafe;
891 cs
->buf
[cs
->cdw
++] = 0xdeadcafe;
892 cs
->buf
[cs
->cdw
++] = 0xdeadcafe;
893 cs
->buf
[cs
->cdw
++] = 0xdeadcafe;
894 cs
->buf
[cs
->cdw
++] = 0xdeadcafe;
895 cs
->buf
[cs
->cdw
++] = 0xdeadcafe;
896 cs
->buf
[cs
->cdw
++] = 0xdeadcafe;
897 cs
->buf
[cs
->cdw
++] = 0xdeadcafe;
898 cs
->buf
[cs
->cdw
++] = 0xdeadcafe;
899 cs
->buf
[cs
->cdw
++] = 0xdeadcafe;
900 cs
->buf
[cs
->cdw
++] = 0xdeadcafe;
901 cs
->buf
[cs
->cdw
++] = 0xdeadcafe;
902 cs
->buf
[cs
->cdw
++] = 0xdeadcafe;
903 cs
->buf
[cs
->cdw
++] = 0xdeadcafe;
904 cs
->buf
[cs
->cdw
++] = 0xdeadcafe;
905 cs
->buf
[cs
->cdw
++] = 0xdeadcafe;
909 if (rctx
->flags
& (R600_CONTEXT_CB_FLUSH
|
910 R600_CONTEXT_DB_FLUSH
|
911 R600_CONTEXT_SHADERCONST_FLUSH
|
912 R600_CONTEXT_TEX_FLUSH
|
913 R600_CONTEXT_VTX_FLUSH
|
914 R600_CONTEXT_STREAMOUT_FLUSH
)) {
915 /* anything left (cb, vtx, shader, streamout) can be flushed
916 * using the surface sync packet
920 if (rctx
->flags
& R600_CONTEXT_CB_FLUSH
) {
921 flags
|= S_0085F0_CB_ACTION_ENA(1) |
922 S_0085F0_CB0_DEST_BASE_ENA(1) |
923 S_0085F0_CB1_DEST_BASE_ENA(1) |
924 S_0085F0_CB2_DEST_BASE_ENA(1) |
925 S_0085F0_CB3_DEST_BASE_ENA(1) |
926 S_0085F0_CB4_DEST_BASE_ENA(1) |
927 S_0085F0_CB5_DEST_BASE_ENA(1) |
928 S_0085F0_CB6_DEST_BASE_ENA(1) |
929 S_0085F0_CB7_DEST_BASE_ENA(1);
931 if (rctx
->chip_class
>= EVERGREEN
) {
932 flags
|= S_0085F0_CB8_DEST_BASE_ENA(1) |
933 S_0085F0_CB9_DEST_BASE_ENA(1) |
934 S_0085F0_CB10_DEST_BASE_ENA(1) |
935 S_0085F0_CB11_DEST_BASE_ENA(1);
939 * (CB1_DEST_BASE_ENA is also required, which is
940 * included unconditionally above). */
941 if (rctx
->family
== CHIP_RV670
||
942 rctx
->family
== CHIP_RS780
||
943 rctx
->family
== CHIP_RS880
) {
944 flags
|= S_0085F0_DEST_BASE_0_ENA(1);
948 if (rctx
->flags
& R600_CONTEXT_STREAMOUT_FLUSH
) {
949 flags
|= S_0085F0_SO0_DEST_BASE_ENA(1) |
950 S_0085F0_SO1_DEST_BASE_ENA(1) |
951 S_0085F0_SO2_DEST_BASE_ENA(1) |
952 S_0085F0_SO3_DEST_BASE_ENA(1) |
953 S_0085F0_SMX_ACTION_ENA(1);
956 if (rctx
->family
== CHIP_RV670
||
957 rctx
->family
== CHIP_RS780
||
958 rctx
->family
== CHIP_RS880
) {
959 flags
|= S_0085F0_DEST_BASE_0_ENA(1);
963 flags
|= (rctx
->flags
& R600_CONTEXT_DB_FLUSH
) ? S_0085F0_DB_ACTION_ENA(1) |
964 S_0085F0_DB_DEST_BASE_ENA(1): 0;
965 flags
|= (rctx
->flags
& R600_CONTEXT_SHADERCONST_FLUSH
) ? S_0085F0_SH_ACTION_ENA(1) : 0;
966 flags
|= (rctx
->flags
& R600_CONTEXT_TEX_FLUSH
) ? S_0085F0_TC_ACTION_ENA(1) : 0;
967 flags
|= (rctx
->flags
& R600_CONTEXT_VTX_FLUSH
) ? S_0085F0_VC_ACTION_ENA(1) : 0;
969 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SURFACE_SYNC
, 3, 0);
970 cs
->buf
[cs
->cdw
++] = flags
; /* CP_COHER_CNTL */
971 cs
->buf
[cs
->cdw
++] = 0xffffffff; /* CP_COHER_SIZE */
972 cs
->buf
[cs
->cdw
++] = 0; /* CP_COHER_BASE */
973 cs
->buf
[cs
->cdw
++] = 0x0000000A; /* POLL_INTERVAL */
976 if (rctx
->flags
& R600_CONTEXT_WAIT_IDLE
) {
977 /* wait for things to settle */
978 r600_write_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
981 /* everything is properly flushed */
985 void r600_context_flush(struct r600_context
*ctx
, unsigned flags
)
987 struct radeon_winsys_cs
*cs
= ctx
->cs
;
989 if (cs
->cdw
== ctx
->start_cs_cmd
.atom
.num_dw
)
992 ctx
->timer_queries_suspended
= false;
993 ctx
->nontimer_queries_suspended
= false;
994 ctx
->streamout_suspended
= false;
996 /* suspend queries */
997 if (ctx
->num_cs_dw_timer_queries_suspend
) {
998 r600_suspend_timer_queries(ctx
);
999 ctx
->timer_queries_suspended
= true;
1001 if (ctx
->num_cs_dw_nontimer_queries_suspend
) {
1002 r600_suspend_nontimer_queries(ctx
);
1003 ctx
->nontimer_queries_suspended
= true;
1006 if (ctx
->num_cs_dw_streamout_end
) {
1007 r600_context_streamout_end(ctx
);
1008 ctx
->streamout_suspended
= true;
1011 /* partial flush is needed to avoid lockups on some chips with user fences */
1012 ctx
->flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
1014 /* flush the framebuffer */
1015 ctx
->flags
|= R600_CONTEXT_CB_FLUSH
| R600_CONTEXT_DB_FLUSH
;
1018 if (ctx
->chip_class
== R600
) {
1019 ctx
->flags
|= R600_CONTEXT_FLUSH_AND_INV
;
1022 r600_flush_emit(ctx
);
1024 /* old kernels and userspace don't set SX_MISC, so we must reset it to 0 here */
1025 if (ctx
->chip_class
<= R700
) {
1026 r600_write_context_reg(cs
, R_028350_SX_MISC
, 0);
1029 /* force to keep tiling flags */
1030 flags
|= RADEON_FLUSH_KEEP_TILING_FLAGS
;
1033 ctx
->ws
->cs_flush(ctx
->cs
, flags
);
1035 r600_begin_new_cs(ctx
);
1038 void r600_begin_new_cs(struct r600_context
*ctx
)
1040 struct r600_block
*enable_block
= NULL
;
1043 ctx
->pm4_dirty_cdwords
= 0;
1046 /* Begin a new CS. */
1047 r600_emit_atom(ctx
, &ctx
->start_cs_cmd
.atom
);
1049 /* Re-emit states. */
1050 r600_atom_dirty(ctx
, &ctx
->alphatest_state
.atom
);
1051 r600_atom_dirty(ctx
, &ctx
->cb_misc_state
.atom
);
1052 r600_atom_dirty(ctx
, &ctx
->db_misc_state
.atom
);
1054 if (ctx
->chip_class
<= R700
) {
1055 r600_atom_dirty(ctx
, &ctx
->seamless_cube_map
.atom
);
1057 r600_atom_dirty(ctx
, &ctx
->sample_mask
.atom
);
1059 ctx
->vertex_buffer_state
.dirty_mask
= ctx
->vertex_buffer_state
.enabled_mask
;
1060 r600_vertex_buffers_dirty(ctx
);
1062 /* Re-emit shader resources. */
1063 for (shader
= 0; shader
< PIPE_SHADER_TYPES
; shader
++) {
1064 struct r600_constbuf_state
*constbuf
= &ctx
->constbuf_state
[shader
];
1065 struct r600_textures_info
*samplers
= &ctx
->samplers
[shader
];
1067 constbuf
->dirty_mask
= constbuf
->enabled_mask
;
1068 samplers
->views
.dirty_mask
= samplers
->views
.enabled_mask
;
1069 samplers
->states
.dirty_mask
= samplers
->states
.enabled_mask
;
1071 r600_constant_buffers_dirty(ctx
, constbuf
);
1072 r600_sampler_views_dirty(ctx
, &samplers
->views
);
1073 r600_sampler_states_dirty(ctx
, &samplers
->states
);
1076 if (ctx
->streamout_suspended
) {
1077 ctx
->streamout_start
= TRUE
;
1078 ctx
->streamout_append_bitmask
= ~0;
1081 /* resume queries */
1082 if (ctx
->timer_queries_suspended
) {
1083 r600_resume_timer_queries(ctx
);
1085 if (ctx
->nontimer_queries_suspended
) {
1086 r600_resume_nontimer_queries(ctx
);
1089 /* set all valid group as dirty so they get reemited on
1092 LIST_FOR_EACH_ENTRY(enable_block
, &ctx
->enable_list
, enable_list
) {
1093 if(!(enable_block
->status
& R600_BLOCK_STATUS_DIRTY
)) {
1094 LIST_ADDTAIL(&enable_block
->list
,&ctx
->dirty
);
1095 enable_block
->status
|= R600_BLOCK_STATUS_DIRTY
;
1097 ctx
->pm4_dirty_cdwords
+= enable_block
->pm4_ndwords
;
1098 enable_block
->nreg_dirty
= enable_block
->nreg
;
1102 void r600_context_emit_fence(struct r600_context
*ctx
, struct r600_resource
*fence_bo
, unsigned offset
, unsigned value
)
1104 struct radeon_winsys_cs
*cs
= ctx
->cs
;
1107 r600_need_cs_space(ctx
, 10, FALSE
);
1109 va
= r600_resource_va(&ctx
->screen
->screen
, (void*)fence_bo
);
1110 va
= va
+ (offset
<< 2);
1112 ctx
->flags
&= ~R600_CONTEXT_PS_PARTIAL_FLUSH
;
1113 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_EVENT_WRITE
, 0, 0);
1114 cs
->buf
[cs
->cdw
++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4);
1116 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_EVENT_WRITE_EOP
, 4, 0);
1117 cs
->buf
[cs
->cdw
++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT
) | EVENT_INDEX(5);
1118 cs
->buf
[cs
->cdw
++] = va
& 0xFFFFFFFFUL
; /* ADDRESS_LO */
1119 /* DATA_SEL | INT_EN | ADDRESS_HI */
1120 cs
->buf
[cs
->cdw
++] = (1 << 29) | (0 << 24) | ((va
>> 32UL) & 0xFF);
1121 cs
->buf
[cs
->cdw
++] = value
; /* DATA_LO */
1122 cs
->buf
[cs
->cdw
++] = 0; /* DATA_HI */
1123 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
1124 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(ctx
, fence_bo
, RADEON_USAGE_WRITE
);
1127 static void r600_flush_vgt_streamout(struct r600_context
*ctx
)
1129 struct radeon_winsys_cs
*cs
= ctx
->cs
;
1131 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CONFIG_REG
, 1, 0);
1132 cs
->buf
[cs
->cdw
++] = (R_008490_CP_STRMOUT_CNTL
- R600_CONFIG_REG_OFFSET
) >> 2;
1133 cs
->buf
[cs
->cdw
++] = 0;
1135 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_EVENT_WRITE
, 0, 0);
1136 cs
->buf
[cs
->cdw
++] = EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH
) | EVENT_INDEX(0);
1138 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_WAIT_REG_MEM
, 5, 0);
1139 cs
->buf
[cs
->cdw
++] = WAIT_REG_MEM_EQUAL
; /* wait until the register is equal to the reference value */
1140 cs
->buf
[cs
->cdw
++] = R_008490_CP_STRMOUT_CNTL
>> 2; /* register */
1141 cs
->buf
[cs
->cdw
++] = 0;
1142 cs
->buf
[cs
->cdw
++] = S_008490_OFFSET_UPDATE_DONE(1); /* reference value */
1143 cs
->buf
[cs
->cdw
++] = S_008490_OFFSET_UPDATE_DONE(1); /* mask */
1144 cs
->buf
[cs
->cdw
++] = 4; /* poll interval */
1147 static void r600_set_streamout_enable(struct r600_context
*ctx
, unsigned buffer_enable_bit
)
1149 struct radeon_winsys_cs
*cs
= ctx
->cs
;
1151 if (buffer_enable_bit
) {
1152 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CONTEXT_REG
, 1, 0);
1153 cs
->buf
[cs
->cdw
++] = (R_028AB0_VGT_STRMOUT_EN
- R600_CONTEXT_REG_OFFSET
) >> 2;
1154 cs
->buf
[cs
->cdw
++] = S_028AB0_STREAMOUT(1);
1156 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CONTEXT_REG
, 1, 0);
1157 cs
->buf
[cs
->cdw
++] = (R_028B20_VGT_STRMOUT_BUFFER_EN
- R600_CONTEXT_REG_OFFSET
) >> 2;
1158 cs
->buf
[cs
->cdw
++] = buffer_enable_bit
;
1160 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CONTEXT_REG
, 1, 0);
1161 cs
->buf
[cs
->cdw
++] = (R_028AB0_VGT_STRMOUT_EN
- R600_CONTEXT_REG_OFFSET
) >> 2;
1162 cs
->buf
[cs
->cdw
++] = S_028AB0_STREAMOUT(0);
1166 void r600_context_streamout_begin(struct r600_context
*ctx
)
1168 struct radeon_winsys_cs
*cs
= ctx
->cs
;
1169 struct r600_so_target
**t
= ctx
->so_targets
;
1170 unsigned *stride_in_dw
= ctx
->vs_shader
->so
.stride
;
1171 unsigned buffer_en
, i
, update_flags
= 0;
1174 buffer_en
= (ctx
->num_so_targets
>= 1 && t
[0] ? 1 : 0) |
1175 (ctx
->num_so_targets
>= 2 && t
[1] ? 2 : 0) |
1176 (ctx
->num_so_targets
>= 3 && t
[2] ? 4 : 0) |
1177 (ctx
->num_so_targets
>= 4 && t
[3] ? 8 : 0);
1179 ctx
->num_cs_dw_streamout_end
=
1180 12 + /* flush_vgt_streamout */
1181 util_bitcount(buffer_en
) * 8 + /* STRMOUT_BUFFER_UPDATE */
1182 3 /* set_streamout_enable(0) */;
1184 r600_need_cs_space(ctx
,
1185 12 + /* flush_vgt_streamout */
1186 6 + /* set_streamout_enable */
1187 util_bitcount(buffer_en
) * 7 + /* SET_CONTEXT_REG */
1188 (ctx
->chip_class
== R700
? util_bitcount(buffer_en
) * 5 : 0) + /* STRMOUT_BASE_UPDATE */
1189 util_bitcount(buffer_en
& ctx
->streamout_append_bitmask
) * 8 + /* STRMOUT_BUFFER_UPDATE */
1190 util_bitcount(buffer_en
& ~ctx
->streamout_append_bitmask
) * 6 + /* STRMOUT_BUFFER_UPDATE */
1191 (ctx
->family
> CHIP_R600
&& ctx
->family
< CHIP_RV770
? 2 : 0) + /* SURFACE_BASE_UPDATE */
1192 ctx
->num_cs_dw_streamout_end
, TRUE
);
1194 if (ctx
->chip_class
>= EVERGREEN
) {
1195 evergreen_flush_vgt_streamout(ctx
);
1196 evergreen_set_streamout_enable(ctx
, buffer_en
);
1198 r600_flush_vgt_streamout(ctx
);
1199 r600_set_streamout_enable(ctx
, buffer_en
);
1202 for (i
= 0; i
< ctx
->num_so_targets
; i
++) {
1204 t
[i
]->stride_in_dw
= stride_in_dw
[i
];
1206 va
= r600_resource_va(&ctx
->screen
->screen
,
1207 (void*)t
[i
]->b
.buffer
);
1209 update_flags
|= SURFACE_BASE_UPDATE_STRMOUT(i
);
1211 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CONTEXT_REG
, 3, 0);
1212 cs
->buf
[cs
->cdw
++] = (R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0
+
1213 16*i
- R600_CONTEXT_REG_OFFSET
) >> 2;
1214 cs
->buf
[cs
->cdw
++] = (t
[i
]->b
.buffer_offset
+
1215 t
[i
]->b
.buffer_size
) >> 2; /* BUFFER_SIZE (in DW) */
1216 cs
->buf
[cs
->cdw
++] = stride_in_dw
[i
]; /* VTX_STRIDE (in DW) */
1217 cs
->buf
[cs
->cdw
++] = va
>> 8; /* BUFFER_BASE */
1219 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
1220 cs
->buf
[cs
->cdw
++] =
1221 r600_context_bo_reloc(ctx
, r600_resource(t
[i
]->b
.buffer
),
1222 RADEON_USAGE_WRITE
);
1224 /* R7xx requires this packet after updating BUFFER_BASE.
1225 * Without this, R7xx locks up. */
1226 if (ctx
->chip_class
== R700
) {
1227 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_STRMOUT_BASE_UPDATE
, 1, 0);
1228 cs
->buf
[cs
->cdw
++] = i
;
1229 cs
->buf
[cs
->cdw
++] = va
>> 8;
1231 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
1232 cs
->buf
[cs
->cdw
++] =
1233 r600_context_bo_reloc(ctx
, r600_resource(t
[i
]->b
.buffer
),
1234 RADEON_USAGE_WRITE
);
1237 if (ctx
->streamout_append_bitmask
& (1 << i
)) {
1238 va
= r600_resource_va(&ctx
->screen
->screen
,
1239 (void*)t
[i
]->filled_size
);
1241 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0);
1242 cs
->buf
[cs
->cdw
++] = STRMOUT_SELECT_BUFFER(i
) |
1243 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM
); /* control */
1244 cs
->buf
[cs
->cdw
++] = 0; /* unused */
1245 cs
->buf
[cs
->cdw
++] = 0; /* unused */
1246 cs
->buf
[cs
->cdw
++] = va
& 0xFFFFFFFFUL
; /* src address lo */
1247 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFFUL
; /* src address hi */
1249 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
1250 cs
->buf
[cs
->cdw
++] =
1251 r600_context_bo_reloc(ctx
, t
[i
]->filled_size
,
1254 /* Start from the beginning. */
1255 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0);
1256 cs
->buf
[cs
->cdw
++] = STRMOUT_SELECT_BUFFER(i
) |
1257 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET
); /* control */
1258 cs
->buf
[cs
->cdw
++] = 0; /* unused */
1259 cs
->buf
[cs
->cdw
++] = 0; /* unused */
1260 cs
->buf
[cs
->cdw
++] = t
[i
]->b
.buffer_offset
>> 2; /* buffer offset in DW */
1261 cs
->buf
[cs
->cdw
++] = 0; /* unused */
1266 if (ctx
->family
> CHIP_R600
&& ctx
->family
< CHIP_RV770
) {
1267 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SURFACE_BASE_UPDATE
, 0, 0);
1268 cs
->buf
[cs
->cdw
++] = update_flags
;
1272 void r600_context_streamout_end(struct r600_context
*ctx
)
1274 struct radeon_winsys_cs
*cs
= ctx
->cs
;
1275 struct r600_so_target
**t
= ctx
->so_targets
;
1279 if (ctx
->chip_class
>= EVERGREEN
) {
1280 evergreen_flush_vgt_streamout(ctx
);
1282 r600_flush_vgt_streamout(ctx
);
1285 for (i
= 0; i
< ctx
->num_so_targets
; i
++) {
1287 va
= r600_resource_va(&ctx
->screen
->screen
,
1288 (void*)t
[i
]->filled_size
);
1289 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0);
1290 cs
->buf
[cs
->cdw
++] = STRMOUT_SELECT_BUFFER(i
) |
1291 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE
) |
1292 STRMOUT_STORE_BUFFER_FILLED_SIZE
; /* control */
1293 cs
->buf
[cs
->cdw
++] = va
& 0xFFFFFFFFUL
; /* dst address lo */
1294 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFFUL
; /* dst address hi */
1295 cs
->buf
[cs
->cdw
++] = 0; /* unused */
1296 cs
->buf
[cs
->cdw
++] = 0; /* unused */
1298 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
1299 cs
->buf
[cs
->cdw
++] =
1300 r600_context_bo_reloc(ctx
, t
[i
]->filled_size
,
1301 RADEON_USAGE_WRITE
);
1306 if (ctx
->chip_class
>= EVERGREEN
) {
1307 evergreen_set_streamout_enable(ctx
, 0);
1309 r600_set_streamout_enable(ctx
, 0);
1311 ctx
->flags
|= R600_CONTEXT_STREAMOUT_FLUSH
;
1314 if (ctx
->chip_class
== R600
) {
1315 ctx
->flags
|= R600_CONTEXT_FLUSH_AND_INV
;
1317 ctx
->num_cs_dw_streamout_end
= 0;