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r600g: Implement scratch buffer state management (v2)
[mesa.git] / src / gallium / drivers / r600 / r600_hw_context.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include "r600_pipe.h"
27 #include "r600d.h"
28 #include "util/u_memory.h"
29 #include <errno.h>
30 #include <unistd.h>
31
32
33 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
34 boolean count_draw_in)
35 {
36 /* Flush the DMA IB if it's not empty. */
37 if (radeon_emitted(ctx->b.dma.cs, 0))
38 ctx->b.dma.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
39
40 if (!radeon_cs_memory_below_limit(ctx->b.screen, ctx->b.gfx.cs,
41 ctx->b.vram, ctx->b.gtt)) {
42 ctx->b.gtt = 0;
43 ctx->b.vram = 0;
44 ctx->b.gfx.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
45 return;
46 }
47 /* all will be accounted once relocation are emited */
48 ctx->b.gtt = 0;
49 ctx->b.vram = 0;
50
51 /* Check available space in CS. */
52 if (count_draw_in) {
53 uint64_t mask;
54
55 /* The number of dwords all the dirty states would take. */
56 mask = ctx->dirty_atoms;
57 while (mask != 0)
58 num_dw += ctx->atoms[u_bit_scan64(&mask)]->num_dw;
59
60 /* The upper-bound of how much space a draw command would take. */
61 num_dw += R600_MAX_FLUSH_CS_DWORDS + R600_MAX_DRAW_CS_DWORDS;
62 }
63
64 /* Count in r600_suspend_queries. */
65 num_dw += ctx->b.num_cs_dw_queries_suspend;
66
67 /* Count in streamout_end at the end of CS. */
68 if (ctx->b.streamout.begin_emitted) {
69 num_dw += ctx->b.streamout.num_dw_for_end;
70 }
71
72 /* SX_MISC */
73 if (ctx->b.chip_class == R600) {
74 num_dw += 3;
75 }
76
77 /* Count in framebuffer cache flushes at the end of CS. */
78 num_dw += R600_MAX_FLUSH_CS_DWORDS;
79
80 /* The fence at the end of CS. */
81 num_dw += 10;
82
83 /* Flush if there's not enough space. */
84 if (!ctx->b.ws->cs_check_space(ctx->b.gfx.cs, num_dw)) {
85 ctx->b.gfx.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
86 }
87 }
88
89 void r600_flush_emit(struct r600_context *rctx)
90 {
91 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
92 unsigned cp_coher_cntl = 0;
93 unsigned wait_until = 0;
94
95 if (!rctx->b.flags) {
96 return;
97 }
98
99 /* Ensure coherency between streamout and shaders. */
100 if (rctx->b.flags & R600_CONTEXT_STREAMOUT_FLUSH)
101 rctx->b.flags |= r600_get_flush_flags(R600_COHERENCY_SHADER);
102
103 if (rctx->b.flags & R600_CONTEXT_WAIT_3D_IDLE) {
104 wait_until |= S_008040_WAIT_3D_IDLE(1);
105 }
106 if (rctx->b.flags & R600_CONTEXT_WAIT_CP_DMA_IDLE) {
107 wait_until |= S_008040_WAIT_CP_DMA_IDLE(1);
108 }
109
110 if (wait_until) {
111 /* Use of WAIT_UNTIL is deprecated on Cayman+ */
112 if (rctx->b.family >= CHIP_CAYMAN) {
113 /* emit a PS partial flush on Cayman/TN */
114 rctx->b.flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
115 }
116 }
117
118 /* Wait packets must be executed first, because SURFACE_SYNC doesn't
119 * wait for shaders if it's not flushing CB or DB.
120 */
121 if (rctx->b.flags & R600_CONTEXT_PS_PARTIAL_FLUSH) {
122 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
123 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
124 }
125
126 if (rctx->b.flags & R600_CONTEXT_CS_PARTIAL_FLUSH) {
127 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
128 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
129 }
130
131 if (wait_until) {
132 /* Use of WAIT_UNTIL is deprecated on Cayman+ */
133 if (rctx->b.family < CHIP_CAYMAN) {
134 /* wait for things to settle */
135 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, wait_until);
136 }
137 }
138
139 if (rctx->b.chip_class >= R700 &&
140 (rctx->b.flags & R600_CONTEXT_FLUSH_AND_INV_CB_META)) {
141 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
142 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
143 }
144
145 if (rctx->b.chip_class >= R700 &&
146 (rctx->b.flags & R600_CONTEXT_FLUSH_AND_INV_DB_META)) {
147 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
148 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
149
150 /* Set FULL_CACHE_ENA for DB META flushes on r7xx and later.
151 *
152 * This hack predates use of FLUSH_AND_INV_DB_META, so it's
153 * unclear whether it's still needed or even whether it has
154 * any effect.
155 */
156 cp_coher_cntl |= S_0085F0_FULL_CACHE_ENA(1);
157 }
158
159 if (rctx->b.flags & R600_CONTEXT_FLUSH_AND_INV ||
160 (rctx->b.chip_class == R600 && rctx->b.flags & R600_CONTEXT_STREAMOUT_FLUSH)) {
161 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
162 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
163 }
164
165 if (rctx->b.flags & R600_CONTEXT_INV_CONST_CACHE) {
166 /* Direct constant addressing uses the shader cache.
167 * Indirect contant addressing uses the vertex cache. */
168 cp_coher_cntl |= S_0085F0_SH_ACTION_ENA(1) |
169 (rctx->has_vertex_cache ? S_0085F0_VC_ACTION_ENA(1)
170 : S_0085F0_TC_ACTION_ENA(1));
171 }
172 if (rctx->b.flags & R600_CONTEXT_INV_VERTEX_CACHE) {
173 cp_coher_cntl |= rctx->has_vertex_cache ? S_0085F0_VC_ACTION_ENA(1)
174 : S_0085F0_TC_ACTION_ENA(1);
175 }
176 if (rctx->b.flags & R600_CONTEXT_INV_TEX_CACHE) {
177 /* Textures use the texture cache.
178 * Texture buffer objects use the vertex cache. */
179 cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1) |
180 (rctx->has_vertex_cache ? S_0085F0_VC_ACTION_ENA(1) : 0);
181 }
182
183 /* Don't use the DB CP COHER logic on r6xx.
184 * There are hw bugs.
185 */
186 if (rctx->b.chip_class >= R700 &&
187 (rctx->b.flags & R600_CONTEXT_FLUSH_AND_INV_DB)) {
188 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
189 S_0085F0_DB_DEST_BASE_ENA(1) |
190 S_0085F0_SMX_ACTION_ENA(1);
191 }
192
193 /* Don't use the CB CP COHER logic on r6xx.
194 * There are hw bugs.
195 */
196 if (rctx->b.chip_class >= R700 &&
197 (rctx->b.flags & R600_CONTEXT_FLUSH_AND_INV_CB)) {
198 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
199 S_0085F0_CB0_DEST_BASE_ENA(1) |
200 S_0085F0_CB1_DEST_BASE_ENA(1) |
201 S_0085F0_CB2_DEST_BASE_ENA(1) |
202 S_0085F0_CB3_DEST_BASE_ENA(1) |
203 S_0085F0_CB4_DEST_BASE_ENA(1) |
204 S_0085F0_CB5_DEST_BASE_ENA(1) |
205 S_0085F0_CB6_DEST_BASE_ENA(1) |
206 S_0085F0_CB7_DEST_BASE_ENA(1) |
207 S_0085F0_SMX_ACTION_ENA(1);
208 if (rctx->b.chip_class >= EVERGREEN)
209 cp_coher_cntl |= S_0085F0_CB8_DEST_BASE_ENA(1) |
210 S_0085F0_CB9_DEST_BASE_ENA(1) |
211 S_0085F0_CB10_DEST_BASE_ENA(1) |
212 S_0085F0_CB11_DEST_BASE_ENA(1);
213 }
214
215 if (rctx->b.chip_class >= R700 &&
216 rctx->b.flags & R600_CONTEXT_STREAMOUT_FLUSH) {
217 cp_coher_cntl |= S_0085F0_SO0_DEST_BASE_ENA(1) |
218 S_0085F0_SO1_DEST_BASE_ENA(1) |
219 S_0085F0_SO2_DEST_BASE_ENA(1) |
220 S_0085F0_SO3_DEST_BASE_ENA(1) |
221 S_0085F0_SMX_ACTION_ENA(1);
222 }
223
224 /* Workaround for buggy flushing on some R6xx chipsets. */
225 if ((rctx->b.flags & (R600_CONTEXT_FLUSH_AND_INV |
226 R600_CONTEXT_STREAMOUT_FLUSH)) &&
227 (rctx->b.family == CHIP_RV670 ||
228 rctx->b.family == CHIP_RS780 ||
229 rctx->b.family == CHIP_RS880)) {
230 cp_coher_cntl |= S_0085F0_CB1_DEST_BASE_ENA(1) |
231 S_0085F0_DEST_BASE_0_ENA(1);
232 }
233
234 if (cp_coher_cntl) {
235 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
236 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
237 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
238 radeon_emit(cs, 0); /* CP_COHER_BASE */
239 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
240 }
241
242 if (rctx->b.flags & R600_CONTEXT_START_PIPELINE_STATS) {
243 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
244 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) |
245 EVENT_INDEX(0));
246 } else if (rctx->b.flags & R600_CONTEXT_STOP_PIPELINE_STATS) {
247 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
248 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_STOP) |
249 EVENT_INDEX(0));
250 }
251
252 /* everything is properly flushed */
253 rctx->b.flags = 0;
254 }
255
256 void r600_context_gfx_flush(void *context, unsigned flags,
257 struct pipe_fence_handle **fence)
258 {
259 struct r600_context *ctx = context;
260 struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
261 struct radeon_winsys *ws = ctx->b.ws;
262
263 if (!radeon_emitted(cs, ctx->b.initial_gfx_cs_size))
264 return;
265
266 if (r600_check_device_reset(&ctx->b))
267 return;
268
269 r600_preflush_suspend_features(&ctx->b);
270
271 /* flush the framebuffer cache */
272 ctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV |
273 R600_CONTEXT_FLUSH_AND_INV_CB |
274 R600_CONTEXT_FLUSH_AND_INV_DB |
275 R600_CONTEXT_FLUSH_AND_INV_CB_META |
276 R600_CONTEXT_FLUSH_AND_INV_DB_META |
277 R600_CONTEXT_WAIT_3D_IDLE |
278 R600_CONTEXT_WAIT_CP_DMA_IDLE;
279
280 r600_flush_emit(ctx);
281
282 if (ctx->trace_buf)
283 eg_trace_emit(ctx);
284 /* old kernels and userspace don't set SX_MISC, so we must reset it to 0 here */
285 if (ctx->b.chip_class == R600) {
286 radeon_set_context_reg(cs, R_028350_SX_MISC, 0);
287 }
288
289 if (ctx->is_debug) {
290 /* Save the IB for debug contexts. */
291 radeon_clear_saved_cs(&ctx->last_gfx);
292 radeon_save_cs(ws, cs, &ctx->last_gfx, true);
293 r600_resource_reference(&ctx->last_trace_buf, ctx->trace_buf);
294 r600_resource_reference(&ctx->trace_buf, NULL);
295 }
296 /* Flush the CS. */
297 ws->cs_flush(cs, flags, &ctx->b.last_gfx_fence);
298 if (fence)
299 ws->fence_reference(fence, ctx->b.last_gfx_fence);
300 ctx->b.num_gfx_cs_flushes++;
301
302 if (ctx->is_debug) {
303 if (!ws->fence_wait(ws, ctx->b.last_gfx_fence, 10000000)) {
304 const char *fname = getenv("R600_TRACE");
305 if (!fname)
306 exit(-1);
307 FILE *fl = fopen(fname, "w+");
308 if (fl) {
309 eg_dump_debug_state(&ctx->b.b, fl, 0);
310 fclose(fl);
311 } else
312 perror(fname);
313 exit(-1);
314 }
315 }
316 r600_begin_new_cs(ctx);
317 }
318
319 void r600_begin_new_cs(struct r600_context *ctx)
320 {
321 unsigned shader;
322
323 if (ctx->is_debug) {
324 uint32_t zero = 0;
325
326 /* Create a buffer used for writing trace IDs and initialize it to 0. */
327 assert(!ctx->trace_buf);
328 ctx->trace_buf = (struct r600_resource*)
329 pipe_buffer_create(ctx->b.b.screen, 0,
330 PIPE_USAGE_STAGING, 4);
331 if (ctx->trace_buf)
332 pipe_buffer_write_nooverlap(&ctx->b.b, &ctx->trace_buf->b.b,
333 0, sizeof(zero), &zero);
334 ctx->trace_id = 0;
335 }
336
337 if (ctx->trace_buf)
338 eg_trace_emit(ctx);
339
340 ctx->b.flags = 0;
341 ctx->b.gtt = 0;
342 ctx->b.vram = 0;
343
344 /* Begin a new CS. */
345 r600_emit_command_buffer(ctx->b.gfx.cs, &ctx->start_cs_cmd);
346
347 /* Re-emit states. */
348 r600_mark_atom_dirty(ctx, &ctx->alphatest_state.atom);
349 r600_mark_atom_dirty(ctx, &ctx->blend_color.atom);
350 r600_mark_atom_dirty(ctx, &ctx->cb_misc_state.atom);
351 r600_mark_atom_dirty(ctx, &ctx->clip_misc_state.atom);
352 r600_mark_atom_dirty(ctx, &ctx->clip_state.atom);
353 r600_mark_atom_dirty(ctx, &ctx->db_misc_state.atom);
354 r600_mark_atom_dirty(ctx, &ctx->db_state.atom);
355 r600_mark_atom_dirty(ctx, &ctx->framebuffer.atom);
356 if (ctx->b.chip_class >= EVERGREEN) {
357 r600_mark_atom_dirty(ctx, &ctx->fragment_images.atom);
358 r600_mark_atom_dirty(ctx, &ctx->fragment_buffers.atom);
359 r600_mark_atom_dirty(ctx, &ctx->compute_images.atom);
360 r600_mark_atom_dirty(ctx, &ctx->compute_buffers.atom);
361 }
362 r600_mark_atom_dirty(ctx, &ctx->hw_shader_stages[R600_HW_STAGE_PS].atom);
363 r600_mark_atom_dirty(ctx, &ctx->poly_offset_state.atom);
364 r600_mark_atom_dirty(ctx, &ctx->vgt_state.atom);
365 r600_mark_atom_dirty(ctx, &ctx->sample_mask.atom);
366 ctx->b.scissors.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
367 r600_mark_atom_dirty(ctx, &ctx->b.scissors.atom);
368 ctx->b.viewports.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
369 ctx->b.viewports.depth_range_dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
370 r600_mark_atom_dirty(ctx, &ctx->b.viewports.atom);
371 if (ctx->b.chip_class <= EVERGREEN) {
372 r600_mark_atom_dirty(ctx, &ctx->config_state.atom);
373 }
374 r600_mark_atom_dirty(ctx, &ctx->stencil_ref.atom);
375 r600_mark_atom_dirty(ctx, &ctx->vertex_fetch_shader.atom);
376 r600_mark_atom_dirty(ctx, &ctx->hw_shader_stages[R600_HW_STAGE_ES].atom);
377 r600_mark_atom_dirty(ctx, &ctx->shader_stages.atom);
378 if (ctx->gs_shader) {
379 r600_mark_atom_dirty(ctx, &ctx->hw_shader_stages[R600_HW_STAGE_GS].atom);
380 r600_mark_atom_dirty(ctx, &ctx->gs_rings.atom);
381 }
382 if (ctx->tes_shader) {
383 r600_mark_atom_dirty(ctx, &ctx->hw_shader_stages[EG_HW_STAGE_HS].atom);
384 r600_mark_atom_dirty(ctx, &ctx->hw_shader_stages[EG_HW_STAGE_LS].atom);
385 }
386 r600_mark_atom_dirty(ctx, &ctx->hw_shader_stages[R600_HW_STAGE_VS].atom);
387 r600_mark_atom_dirty(ctx, &ctx->b.streamout.enable_atom);
388 r600_mark_atom_dirty(ctx, &ctx->b.render_cond_atom);
389
390 if (ctx->blend_state.cso)
391 r600_mark_atom_dirty(ctx, &ctx->blend_state.atom);
392 if (ctx->dsa_state.cso)
393 r600_mark_atom_dirty(ctx, &ctx->dsa_state.atom);
394 if (ctx->rasterizer_state.cso)
395 r600_mark_atom_dirty(ctx, &ctx->rasterizer_state.atom);
396
397 if (ctx->b.chip_class <= R700) {
398 r600_mark_atom_dirty(ctx, &ctx->seamless_cube_map.atom);
399 }
400
401 ctx->vertex_buffer_state.dirty_mask = ctx->vertex_buffer_state.enabled_mask;
402 r600_vertex_buffers_dirty(ctx);
403
404 /* Re-emit shader resources. */
405 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
406 struct r600_constbuf_state *constbuf = &ctx->constbuf_state[shader];
407 struct r600_textures_info *samplers = &ctx->samplers[shader];
408
409 constbuf->dirty_mask = constbuf->enabled_mask;
410 samplers->views.dirty_mask = samplers->views.enabled_mask;
411 samplers->states.dirty_mask = samplers->states.enabled_mask;
412
413 r600_constant_buffers_dirty(ctx, constbuf);
414 r600_sampler_views_dirty(ctx, &samplers->views);
415 r600_sampler_states_dirty(ctx, &samplers->states);
416 }
417
418 for (shader = 0; shader < ARRAY_SIZE(ctx->scratch_buffers); shader++) {
419 ctx->scratch_buffers[shader].dirty = true;
420 }
421
422 r600_postflush_resume_features(&ctx->b);
423
424 /* Re-emit the draw state. */
425 ctx->last_primitive_type = -1;
426 ctx->last_start_instance = -1;
427 ctx->last_rast_prim = -1;
428 ctx->current_rast_prim = -1;
429
430 assert(!ctx->b.gfx.cs->prev_dw);
431 ctx->b.initial_gfx_cs_size = ctx->b.gfx.cs->current.cdw;
432 }
433
434 void r600_emit_pfp_sync_me(struct r600_context *rctx)
435 {
436 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
437
438 if (rctx->b.chip_class >= EVERGREEN &&
439 rctx->b.screen->info.drm_minor >= 46) {
440 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
441 radeon_emit(cs, 0);
442 } else {
443 /* Emulate PFP_SYNC_ME by writing a value to memory in ME and
444 * waiting for it in PFP.
445 */
446 struct r600_resource *buf = NULL;
447 unsigned offset, reloc;
448 uint64_t va;
449
450 /* 16-byte address alignment is required by WAIT_REG_MEM. */
451 u_suballocator_alloc(rctx->b.allocator_zeroed_memory, 4, 16,
452 &offset, (struct pipe_resource**)&buf);
453 if (!buf) {
454 /* This is too heavyweight, but will work. */
455 rctx->b.gfx.flush(rctx, PIPE_FLUSH_ASYNC, NULL);
456 return;
457 }
458
459 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, buf,
460 RADEON_USAGE_READWRITE,
461 RADEON_PRIO_FENCE);
462
463 va = buf->gpu_address + offset;
464 assert(va % 16 == 0);
465
466 /* Write 1 to memory in ME. */
467 radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
468 radeon_emit(cs, va);
469 radeon_emit(cs, ((va >> 32) & 0xff) | MEM_WRITE_32_BITS);
470 radeon_emit(cs, 1);
471 radeon_emit(cs, 0);
472
473 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
474 radeon_emit(cs, reloc);
475
476 /* Wait in PFP (PFP can only do GEQUAL against memory). */
477 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
478 radeon_emit(cs, WAIT_REG_MEM_GEQUAL |
479 WAIT_REG_MEM_MEMORY |
480 WAIT_REG_MEM_PFP);
481 radeon_emit(cs, va);
482 radeon_emit(cs, va >> 32);
483 radeon_emit(cs, 1); /* reference value */
484 radeon_emit(cs, 0xffffffff); /* mask */
485 radeon_emit(cs, 4); /* poll interval */
486
487 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
488 radeon_emit(cs, reloc);
489
490 r600_resource_reference(&buf, NULL);
491 }
492 }
493
494 /* The max number of bytes to copy per packet. */
495 #define CP_DMA_MAX_BYTE_COUNT ((1 << 21) - 8)
496
497 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
498 struct pipe_resource *dst, uint64_t dst_offset,
499 struct pipe_resource *src, uint64_t src_offset,
500 unsigned size)
501 {
502 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
503
504 assert(size);
505 assert(rctx->screen->b.has_cp_dma);
506
507 /* Mark the buffer range of destination as valid (initialized),
508 * so that transfer_map knows it should wait for the GPU when mapping
509 * that range. */
510 util_range_add(&r600_resource(dst)->valid_buffer_range, dst_offset,
511 dst_offset + size);
512
513 dst_offset += r600_resource(dst)->gpu_address;
514 src_offset += r600_resource(src)->gpu_address;
515
516 /* Flush the caches where the resources are bound. */
517 rctx->b.flags |= r600_get_flush_flags(R600_COHERENCY_SHADER) |
518 R600_CONTEXT_WAIT_3D_IDLE;
519
520 /* There are differences between R700 and EG in CP DMA,
521 * but we only use the common bits here. */
522 while (size) {
523 unsigned sync = 0;
524 unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
525 unsigned src_reloc, dst_reloc;
526
527 r600_need_cs_space(rctx,
528 10 + (rctx->b.flags ? R600_MAX_FLUSH_CS_DWORDS : 0) +
529 3 + R600_MAX_PFP_SYNC_ME_DWORDS, FALSE);
530
531 /* Flush the caches for the first copy only. */
532 if (rctx->b.flags) {
533 r600_flush_emit(rctx);
534 }
535
536 /* Do the synchronization after the last copy, so that all data is written to memory. */
537 if (size == byte_count) {
538 sync = PKT3_CP_DMA_CP_SYNC;
539 }
540
541 /* This must be done after r600_need_cs_space. */
542 src_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, (struct r600_resource*)src,
543 RADEON_USAGE_READ, RADEON_PRIO_CP_DMA);
544 dst_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, (struct r600_resource*)dst,
545 RADEON_USAGE_WRITE, RADEON_PRIO_CP_DMA);
546
547 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
548 radeon_emit(cs, src_offset); /* SRC_ADDR_LO [31:0] */
549 radeon_emit(cs, sync | ((src_offset >> 32) & 0xff)); /* CP_SYNC [31] | SRC_ADDR_HI [7:0] */
550 radeon_emit(cs, dst_offset); /* DST_ADDR_LO [31:0] */
551 radeon_emit(cs, (dst_offset >> 32) & 0xff); /* DST_ADDR_HI [7:0] */
552 radeon_emit(cs, byte_count); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
553
554 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
555 radeon_emit(cs, src_reloc);
556 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
557 radeon_emit(cs, dst_reloc);
558
559 size -= byte_count;
560 src_offset += byte_count;
561 dst_offset += byte_count;
562 }
563
564 /* CP_DMA_CP_SYNC doesn't wait for idle on R6xx, but this does. */
565 if (rctx->b.chip_class == R600)
566 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL,
567 S_008040_WAIT_CP_DMA_IDLE(1));
568
569 /* CP DMA is executed in ME, but index buffers are read by PFP.
570 * This ensures that ME (CP DMA) is idle before PFP starts fetching
571 * indices. If we wanted to execute CP DMA in PFP, this packet
572 * should precede it.
573 */
574 r600_emit_pfp_sync_me(rctx);
575 }
576
577 void r600_dma_copy_buffer(struct r600_context *rctx,
578 struct pipe_resource *dst,
579 struct pipe_resource *src,
580 uint64_t dst_offset,
581 uint64_t src_offset,
582 uint64_t size)
583 {
584 struct radeon_winsys_cs *cs = rctx->b.dma.cs;
585 unsigned i, ncopy, csize;
586 struct r600_resource *rdst = (struct r600_resource*)dst;
587 struct r600_resource *rsrc = (struct r600_resource*)src;
588
589 /* Mark the buffer range of destination as valid (initialized),
590 * so that transfer_map knows it should wait for the GPU when mapping
591 * that range. */
592 util_range_add(&rdst->valid_buffer_range, dst_offset,
593 dst_offset + size);
594
595 size >>= 2; /* convert to dwords */
596 ncopy = (size / R600_DMA_COPY_MAX_SIZE_DW) + !!(size % R600_DMA_COPY_MAX_SIZE_DW);
597
598 r600_need_dma_space(&rctx->b, ncopy * 5, rdst, rsrc);
599 for (i = 0; i < ncopy; i++) {
600 csize = size < R600_DMA_COPY_MAX_SIZE_DW ? size : R600_DMA_COPY_MAX_SIZE_DW;
601 /* emit reloc before writing cs so that cs is always in consistent state */
602 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, rsrc, RADEON_USAGE_READ,
603 RADEON_PRIO_SDMA_BUFFER);
604 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, rdst, RADEON_USAGE_WRITE,
605 RADEON_PRIO_SDMA_BUFFER);
606 radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, 0, 0, csize));
607 radeon_emit(cs, dst_offset & 0xfffffffc);
608 radeon_emit(cs, src_offset & 0xfffffffc);
609 radeon_emit(cs, (dst_offset >> 32UL) & 0xff);
610 radeon_emit(cs, (src_offset >> 32UL) & 0xff);
611 dst_offset += csize << 2;
612 src_offset += csize << 2;
613 size -= csize;
614 }
615 }