2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "r600_pipe.h"
28 #include "util/u_memory.h"
33 void r600_need_cs_space(struct r600_context
*ctx
, unsigned num_dw
,
34 boolean count_draw_in
)
36 /* Flush the DMA IB if it's not empty. */
37 if (radeon_emitted(ctx
->b
.dma
.cs
, 0))
38 ctx
->b
.dma
.flush(ctx
, PIPE_FLUSH_ASYNC
, NULL
);
40 if (!radeon_cs_memory_below_limit(ctx
->b
.screen
, ctx
->b
.gfx
.cs
,
41 ctx
->b
.vram
, ctx
->b
.gtt
)) {
44 ctx
->b
.gfx
.flush(ctx
, PIPE_FLUSH_ASYNC
, NULL
);
47 /* all will be accounted once relocation are emited */
51 /* Check available space in CS. */
55 /* The number of dwords all the dirty states would take. */
56 mask
= ctx
->dirty_atoms
;
58 num_dw
+= ctx
->atoms
[u_bit_scan64(&mask
)]->num_dw
;
60 /* The upper-bound of how much space a draw command would take. */
61 num_dw
+= R600_MAX_FLUSH_CS_DWORDS
+ R600_MAX_DRAW_CS_DWORDS
;
64 /* Count in r600_suspend_queries. */
65 num_dw
+= ctx
->b
.num_cs_dw_queries_suspend
;
67 /* Count in streamout_end at the end of CS. */
68 if (ctx
->b
.streamout
.begin_emitted
) {
69 num_dw
+= ctx
->b
.streamout
.num_dw_for_end
;
73 if (ctx
->b
.chip_class
== R600
) {
77 /* Count in framebuffer cache flushes at the end of CS. */
78 num_dw
+= R600_MAX_FLUSH_CS_DWORDS
;
80 /* The fence at the end of CS. */
83 /* Flush if there's not enough space. */
84 if (!ctx
->b
.ws
->cs_check_space(ctx
->b
.gfx
.cs
, num_dw
)) {
85 ctx
->b
.gfx
.flush(ctx
, PIPE_FLUSH_ASYNC
, NULL
);
89 void r600_flush_emit(struct r600_context
*rctx
)
91 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
92 unsigned cp_coher_cntl
= 0;
93 unsigned wait_until
= 0;
99 /* Ensure coherency between streamout and shaders. */
100 if (rctx
->b
.flags
& R600_CONTEXT_STREAMOUT_FLUSH
)
101 rctx
->b
.flags
|= r600_get_flush_flags(R600_COHERENCY_SHADER
);
103 if (rctx
->b
.flags
& R600_CONTEXT_WAIT_3D_IDLE
) {
104 wait_until
|= S_008040_WAIT_3D_IDLE(1);
106 if (rctx
->b
.flags
& R600_CONTEXT_WAIT_CP_DMA_IDLE
) {
107 wait_until
|= S_008040_WAIT_CP_DMA_IDLE(1);
111 /* Use of WAIT_UNTIL is deprecated on Cayman+ */
112 if (rctx
->b
.family
>= CHIP_CAYMAN
) {
113 /* emit a PS partial flush on Cayman/TN */
114 rctx
->b
.flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
118 /* Wait packets must be executed first, because SURFACE_SYNC doesn't
119 * wait for shaders if it's not flushing CB or DB.
121 if (rctx
->b
.flags
& R600_CONTEXT_PS_PARTIAL_FLUSH
) {
122 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
123 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
127 /* Use of WAIT_UNTIL is deprecated on Cayman+ */
128 if (rctx
->b
.family
< CHIP_CAYMAN
) {
129 /* wait for things to settle */
130 radeon_set_config_reg(cs
, R_008040_WAIT_UNTIL
, wait_until
);
134 if (rctx
->b
.chip_class
>= R700
&&
135 (rctx
->b
.flags
& R600_CONTEXT_FLUSH_AND_INV_CB_META
)) {
136 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
137 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_CB_META
) | EVENT_INDEX(0));
140 if (rctx
->b
.chip_class
>= R700
&&
141 (rctx
->b
.flags
& R600_CONTEXT_FLUSH_AND_INV_DB_META
)) {
142 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
143 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_DB_META
) | EVENT_INDEX(0));
145 /* Set FULL_CACHE_ENA for DB META flushes on r7xx and later.
147 * This hack predates use of FLUSH_AND_INV_DB_META, so it's
148 * unclear whether it's still needed or even whether it has
151 cp_coher_cntl
|= S_0085F0_FULL_CACHE_ENA(1);
154 if (rctx
->b
.flags
& R600_CONTEXT_FLUSH_AND_INV
||
155 (rctx
->b
.chip_class
== R600
&& rctx
->b
.flags
& R600_CONTEXT_STREAMOUT_FLUSH
)) {
156 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
157 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT
) | EVENT_INDEX(0));
160 if (rctx
->b
.flags
& R600_CONTEXT_INV_CONST_CACHE
) {
161 /* Direct constant addressing uses the shader cache.
162 * Indirect contant addressing uses the vertex cache. */
163 cp_coher_cntl
|= S_0085F0_SH_ACTION_ENA(1) |
164 (rctx
->has_vertex_cache
? S_0085F0_VC_ACTION_ENA(1)
165 : S_0085F0_TC_ACTION_ENA(1));
167 if (rctx
->b
.flags
& R600_CONTEXT_INV_VERTEX_CACHE
) {
168 cp_coher_cntl
|= rctx
->has_vertex_cache
? S_0085F0_VC_ACTION_ENA(1)
169 : S_0085F0_TC_ACTION_ENA(1);
171 if (rctx
->b
.flags
& R600_CONTEXT_INV_TEX_CACHE
) {
172 /* Textures use the texture cache.
173 * Texture buffer objects use the vertex cache. */
174 cp_coher_cntl
|= S_0085F0_TC_ACTION_ENA(1) |
175 (rctx
->has_vertex_cache
? S_0085F0_VC_ACTION_ENA(1) : 0);
178 /* Don't use the DB CP COHER logic on r6xx.
181 if (rctx
->b
.chip_class
>= R700
&&
182 (rctx
->b
.flags
& R600_CONTEXT_FLUSH_AND_INV_DB
)) {
183 cp_coher_cntl
|= S_0085F0_DB_ACTION_ENA(1) |
184 S_0085F0_DB_DEST_BASE_ENA(1) |
185 S_0085F0_SMX_ACTION_ENA(1);
188 /* Don't use the CB CP COHER logic on r6xx.
191 if (rctx
->b
.chip_class
>= R700
&&
192 (rctx
->b
.flags
& R600_CONTEXT_FLUSH_AND_INV_CB
)) {
193 cp_coher_cntl
|= S_0085F0_CB_ACTION_ENA(1) |
194 S_0085F0_CB0_DEST_BASE_ENA(1) |
195 S_0085F0_CB1_DEST_BASE_ENA(1) |
196 S_0085F0_CB2_DEST_BASE_ENA(1) |
197 S_0085F0_CB3_DEST_BASE_ENA(1) |
198 S_0085F0_CB4_DEST_BASE_ENA(1) |
199 S_0085F0_CB5_DEST_BASE_ENA(1) |
200 S_0085F0_CB6_DEST_BASE_ENA(1) |
201 S_0085F0_CB7_DEST_BASE_ENA(1) |
202 S_0085F0_SMX_ACTION_ENA(1);
203 if (rctx
->b
.chip_class
>= EVERGREEN
)
204 cp_coher_cntl
|= S_0085F0_CB8_DEST_BASE_ENA(1) |
205 S_0085F0_CB9_DEST_BASE_ENA(1) |
206 S_0085F0_CB10_DEST_BASE_ENA(1) |
207 S_0085F0_CB11_DEST_BASE_ENA(1);
210 if (rctx
->b
.chip_class
>= R700
&&
211 rctx
->b
.flags
& R600_CONTEXT_STREAMOUT_FLUSH
) {
212 cp_coher_cntl
|= S_0085F0_SO0_DEST_BASE_ENA(1) |
213 S_0085F0_SO1_DEST_BASE_ENA(1) |
214 S_0085F0_SO2_DEST_BASE_ENA(1) |
215 S_0085F0_SO3_DEST_BASE_ENA(1) |
216 S_0085F0_SMX_ACTION_ENA(1);
219 /* Workaround for buggy flushing on some R6xx chipsets. */
220 if ((rctx
->b
.flags
& (R600_CONTEXT_FLUSH_AND_INV
|
221 R600_CONTEXT_STREAMOUT_FLUSH
)) &&
222 (rctx
->b
.family
== CHIP_RV670
||
223 rctx
->b
.family
== CHIP_RS780
||
224 rctx
->b
.family
== CHIP_RS880
)) {
225 cp_coher_cntl
|= S_0085F0_CB1_DEST_BASE_ENA(1) |
226 S_0085F0_DEST_BASE_0_ENA(1);
230 radeon_emit(cs
, PKT3(PKT3_SURFACE_SYNC
, 3, 0));
231 radeon_emit(cs
, cp_coher_cntl
); /* CP_COHER_CNTL */
232 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
233 radeon_emit(cs
, 0); /* CP_COHER_BASE */
234 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
237 if (rctx
->b
.flags
& R600_CONTEXT_START_PIPELINE_STATS
) {
238 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
239 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START
) |
241 } else if (rctx
->b
.flags
& R600_CONTEXT_STOP_PIPELINE_STATS
) {
242 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
243 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_STOP
) |
247 /* everything is properly flushed */
251 void r600_context_gfx_flush(void *context
, unsigned flags
,
252 struct pipe_fence_handle
**fence
)
254 struct r600_context
*ctx
= context
;
255 struct radeon_winsys_cs
*cs
= ctx
->b
.gfx
.cs
;
256 struct radeon_winsys
*ws
= ctx
->b
.ws
;
258 if (!radeon_emitted(cs
, ctx
->b
.initial_gfx_cs_size
))
261 if (r600_check_device_reset(&ctx
->b
))
264 r600_preflush_suspend_features(&ctx
->b
);
266 /* flush the framebuffer cache */
267 ctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV
|
268 R600_CONTEXT_FLUSH_AND_INV_CB
|
269 R600_CONTEXT_FLUSH_AND_INV_DB
|
270 R600_CONTEXT_FLUSH_AND_INV_CB_META
|
271 R600_CONTEXT_FLUSH_AND_INV_DB_META
|
272 R600_CONTEXT_WAIT_3D_IDLE
|
273 R600_CONTEXT_WAIT_CP_DMA_IDLE
;
275 r600_flush_emit(ctx
);
279 /* old kernels and userspace don't set SX_MISC, so we must reset it to 0 here */
280 if (ctx
->b
.chip_class
== R600
) {
281 radeon_set_context_reg(cs
, R_028350_SX_MISC
, 0);
285 /* Save the IB for debug contexts. */
286 radeon_clear_saved_cs(&ctx
->last_gfx
);
287 radeon_save_cs(ws
, cs
, &ctx
->last_gfx
, true);
288 r600_resource_reference(&ctx
->last_trace_buf
, ctx
->trace_buf
);
289 r600_resource_reference(&ctx
->trace_buf
, NULL
);
292 ws
->cs_flush(cs
, flags
, &ctx
->b
.last_gfx_fence
);
294 ws
->fence_reference(fence
, ctx
->b
.last_gfx_fence
);
295 ctx
->b
.num_gfx_cs_flushes
++;
298 if (!ws
->fence_wait(ws
, ctx
->b
.last_gfx_fence
, 10000000)) {
299 const char *fname
= getenv("R600_TRACE");
302 FILE *fl
= fopen(fname
, "w+");
304 eg_dump_debug_state(&ctx
->b
.b
, fl
, 0);
311 r600_begin_new_cs(ctx
);
314 void r600_begin_new_cs(struct r600_context
*ctx
)
321 /* Create a buffer used for writing trace IDs and initialize it to 0. */
322 assert(!ctx
->trace_buf
);
323 ctx
->trace_buf
= (struct r600_resource
*)
324 pipe_buffer_create(ctx
->b
.b
.screen
, 0,
325 PIPE_USAGE_STAGING
, 4);
327 pipe_buffer_write_nooverlap(&ctx
->b
.b
, &ctx
->trace_buf
->b
.b
,
328 0, sizeof(zero
), &zero
);
339 /* Begin a new CS. */
340 r600_emit_command_buffer(ctx
->b
.gfx
.cs
, &ctx
->start_cs_cmd
);
342 /* Re-emit states. */
343 r600_mark_atom_dirty(ctx
, &ctx
->alphatest_state
.atom
);
344 r600_mark_atom_dirty(ctx
, &ctx
->blend_color
.atom
);
345 r600_mark_atom_dirty(ctx
, &ctx
->cb_misc_state
.atom
);
346 r600_mark_atom_dirty(ctx
, &ctx
->clip_misc_state
.atom
);
347 r600_mark_atom_dirty(ctx
, &ctx
->clip_state
.atom
);
348 r600_mark_atom_dirty(ctx
, &ctx
->db_misc_state
.atom
);
349 r600_mark_atom_dirty(ctx
, &ctx
->db_state
.atom
);
350 r600_mark_atom_dirty(ctx
, &ctx
->framebuffer
.atom
);
351 if (ctx
->b
.chip_class
>= EVERGREEN
)
352 r600_mark_atom_dirty(ctx
, &ctx
->fragment_images
.atom
);
353 r600_mark_atom_dirty(ctx
, &ctx
->hw_shader_stages
[R600_HW_STAGE_PS
].atom
);
354 r600_mark_atom_dirty(ctx
, &ctx
->poly_offset_state
.atom
);
355 r600_mark_atom_dirty(ctx
, &ctx
->vgt_state
.atom
);
356 r600_mark_atom_dirty(ctx
, &ctx
->sample_mask
.atom
);
357 ctx
->b
.scissors
.dirty_mask
= (1 << R600_MAX_VIEWPORTS
) - 1;
358 r600_mark_atom_dirty(ctx
, &ctx
->b
.scissors
.atom
);
359 ctx
->b
.viewports
.dirty_mask
= (1 << R600_MAX_VIEWPORTS
) - 1;
360 ctx
->b
.viewports
.depth_range_dirty_mask
= (1 << R600_MAX_VIEWPORTS
) - 1;
361 r600_mark_atom_dirty(ctx
, &ctx
->b
.viewports
.atom
);
362 if (ctx
->b
.chip_class
<= EVERGREEN
) {
363 r600_mark_atom_dirty(ctx
, &ctx
->config_state
.atom
);
365 r600_mark_atom_dirty(ctx
, &ctx
->stencil_ref
.atom
);
366 r600_mark_atom_dirty(ctx
, &ctx
->vertex_fetch_shader
.atom
);
367 r600_mark_atom_dirty(ctx
, &ctx
->hw_shader_stages
[R600_HW_STAGE_ES
].atom
);
368 r600_mark_atom_dirty(ctx
, &ctx
->shader_stages
.atom
);
369 if (ctx
->gs_shader
) {
370 r600_mark_atom_dirty(ctx
, &ctx
->hw_shader_stages
[R600_HW_STAGE_GS
].atom
);
371 r600_mark_atom_dirty(ctx
, &ctx
->gs_rings
.atom
);
373 if (ctx
->tes_shader
) {
374 r600_mark_atom_dirty(ctx
, &ctx
->hw_shader_stages
[EG_HW_STAGE_HS
].atom
);
375 r600_mark_atom_dirty(ctx
, &ctx
->hw_shader_stages
[EG_HW_STAGE_LS
].atom
);
377 r600_mark_atom_dirty(ctx
, &ctx
->hw_shader_stages
[R600_HW_STAGE_VS
].atom
);
378 r600_mark_atom_dirty(ctx
, &ctx
->b
.streamout
.enable_atom
);
379 r600_mark_atom_dirty(ctx
, &ctx
->b
.render_cond_atom
);
381 if (ctx
->blend_state
.cso
)
382 r600_mark_atom_dirty(ctx
, &ctx
->blend_state
.atom
);
383 if (ctx
->dsa_state
.cso
)
384 r600_mark_atom_dirty(ctx
, &ctx
->dsa_state
.atom
);
385 if (ctx
->rasterizer_state
.cso
)
386 r600_mark_atom_dirty(ctx
, &ctx
->rasterizer_state
.atom
);
388 if (ctx
->b
.chip_class
<= R700
) {
389 r600_mark_atom_dirty(ctx
, &ctx
->seamless_cube_map
.atom
);
392 ctx
->vertex_buffer_state
.dirty_mask
= ctx
->vertex_buffer_state
.enabled_mask
;
393 r600_vertex_buffers_dirty(ctx
);
395 /* Re-emit shader resources. */
396 for (shader
= 0; shader
< PIPE_SHADER_TYPES
; shader
++) {
397 struct r600_constbuf_state
*constbuf
= &ctx
->constbuf_state
[shader
];
398 struct r600_textures_info
*samplers
= &ctx
->samplers
[shader
];
400 constbuf
->dirty_mask
= constbuf
->enabled_mask
;
401 samplers
->views
.dirty_mask
= samplers
->views
.enabled_mask
;
402 samplers
->states
.dirty_mask
= samplers
->states
.enabled_mask
;
404 r600_constant_buffers_dirty(ctx
, constbuf
);
405 r600_sampler_views_dirty(ctx
, &samplers
->views
);
406 r600_sampler_states_dirty(ctx
, &samplers
->states
);
409 r600_postflush_resume_features(&ctx
->b
);
411 /* Re-emit the draw state. */
412 ctx
->last_primitive_type
= -1;
413 ctx
->last_start_instance
= -1;
414 ctx
->last_rast_prim
= -1;
415 ctx
->current_rast_prim
= -1;
417 assert(!ctx
->b
.gfx
.cs
->prev_dw
);
418 ctx
->b
.initial_gfx_cs_size
= ctx
->b
.gfx
.cs
->current
.cdw
;
421 void r600_emit_pfp_sync_me(struct r600_context
*rctx
)
423 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
425 if (rctx
->b
.chip_class
>= EVERGREEN
&&
426 rctx
->b
.screen
->info
.drm_minor
>= 46) {
427 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
430 /* Emulate PFP_SYNC_ME by writing a value to memory in ME and
431 * waiting for it in PFP.
433 struct r600_resource
*buf
= NULL
;
434 unsigned offset
, reloc
;
437 /* 16-byte address alignment is required by WAIT_REG_MEM. */
438 u_suballocator_alloc(rctx
->b
.allocator_zeroed_memory
, 4, 16,
439 &offset
, (struct pipe_resource
**)&buf
);
441 /* This is too heavyweight, but will work. */
442 rctx
->b
.gfx
.flush(rctx
, PIPE_FLUSH_ASYNC
, NULL
);
446 reloc
= radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, buf
,
447 RADEON_USAGE_READWRITE
,
450 va
= buf
->gpu_address
+ offset
;
451 assert(va
% 16 == 0);
453 /* Write 1 to memory in ME. */
454 radeon_emit(cs
, PKT3(PKT3_MEM_WRITE
, 3, 0));
456 radeon_emit(cs
, ((va
>> 32) & 0xff) | MEM_WRITE_32_BITS
);
460 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
461 radeon_emit(cs
, reloc
);
463 /* Wait in PFP (PFP can only do GEQUAL against memory). */
464 radeon_emit(cs
, PKT3(PKT3_WAIT_REG_MEM
, 5, 0));
465 radeon_emit(cs
, WAIT_REG_MEM_GEQUAL
|
466 WAIT_REG_MEM_MEMORY
|
469 radeon_emit(cs
, va
>> 32);
470 radeon_emit(cs
, 1); /* reference value */
471 radeon_emit(cs
, 0xffffffff); /* mask */
472 radeon_emit(cs
, 4); /* poll interval */
474 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
475 radeon_emit(cs
, reloc
);
477 r600_resource_reference(&buf
, NULL
);
481 /* The max number of bytes to copy per packet. */
482 #define CP_DMA_MAX_BYTE_COUNT ((1 << 21) - 8)
484 void r600_cp_dma_copy_buffer(struct r600_context
*rctx
,
485 struct pipe_resource
*dst
, uint64_t dst_offset
,
486 struct pipe_resource
*src
, uint64_t src_offset
,
489 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
492 assert(rctx
->screen
->b
.has_cp_dma
);
494 /* Mark the buffer range of destination as valid (initialized),
495 * so that transfer_map knows it should wait for the GPU when mapping
497 util_range_add(&r600_resource(dst
)->valid_buffer_range
, dst_offset
,
500 dst_offset
+= r600_resource(dst
)->gpu_address
;
501 src_offset
+= r600_resource(src
)->gpu_address
;
503 /* Flush the caches where the resources are bound. */
504 rctx
->b
.flags
|= r600_get_flush_flags(R600_COHERENCY_SHADER
) |
505 R600_CONTEXT_WAIT_3D_IDLE
;
507 /* There are differences between R700 and EG in CP DMA,
508 * but we only use the common bits here. */
511 unsigned byte_count
= MIN2(size
, CP_DMA_MAX_BYTE_COUNT
);
512 unsigned src_reloc
, dst_reloc
;
514 r600_need_cs_space(rctx
,
515 10 + (rctx
->b
.flags
? R600_MAX_FLUSH_CS_DWORDS
: 0) +
516 3 + R600_MAX_PFP_SYNC_ME_DWORDS
, FALSE
);
518 /* Flush the caches for the first copy only. */
520 r600_flush_emit(rctx
);
523 /* Do the synchronization after the last copy, so that all data is written to memory. */
524 if (size
== byte_count
) {
525 sync
= PKT3_CP_DMA_CP_SYNC
;
528 /* This must be done after r600_need_cs_space. */
529 src_reloc
= radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, (struct r600_resource
*)src
,
530 RADEON_USAGE_READ
, RADEON_PRIO_CP_DMA
);
531 dst_reloc
= radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, (struct r600_resource
*)dst
,
532 RADEON_USAGE_WRITE
, RADEON_PRIO_CP_DMA
);
534 radeon_emit(cs
, PKT3(PKT3_CP_DMA
, 4, 0));
535 radeon_emit(cs
, src_offset
); /* SRC_ADDR_LO [31:0] */
536 radeon_emit(cs
, sync
| ((src_offset
>> 32) & 0xff)); /* CP_SYNC [31] | SRC_ADDR_HI [7:0] */
537 radeon_emit(cs
, dst_offset
); /* DST_ADDR_LO [31:0] */
538 radeon_emit(cs
, (dst_offset
>> 32) & 0xff); /* DST_ADDR_HI [7:0] */
539 radeon_emit(cs
, byte_count
); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
541 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
542 radeon_emit(cs
, src_reloc
);
543 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
544 radeon_emit(cs
, dst_reloc
);
547 src_offset
+= byte_count
;
548 dst_offset
+= byte_count
;
551 /* CP_DMA_CP_SYNC doesn't wait for idle on R6xx, but this does. */
552 if (rctx
->b
.chip_class
== R600
)
553 radeon_set_config_reg(cs
, R_008040_WAIT_UNTIL
,
554 S_008040_WAIT_CP_DMA_IDLE(1));
556 /* CP DMA is executed in ME, but index buffers are read by PFP.
557 * This ensures that ME (CP DMA) is idle before PFP starts fetching
558 * indices. If we wanted to execute CP DMA in PFP, this packet
561 r600_emit_pfp_sync_me(rctx
);
564 void r600_dma_copy_buffer(struct r600_context
*rctx
,
565 struct pipe_resource
*dst
,
566 struct pipe_resource
*src
,
571 struct radeon_winsys_cs
*cs
= rctx
->b
.dma
.cs
;
572 unsigned i
, ncopy
, csize
;
573 struct r600_resource
*rdst
= (struct r600_resource
*)dst
;
574 struct r600_resource
*rsrc
= (struct r600_resource
*)src
;
576 /* Mark the buffer range of destination as valid (initialized),
577 * so that transfer_map knows it should wait for the GPU when mapping
579 util_range_add(&rdst
->valid_buffer_range
, dst_offset
,
582 size
>>= 2; /* convert to dwords */
583 ncopy
= (size
/ R600_DMA_COPY_MAX_SIZE_DW
) + !!(size
% R600_DMA_COPY_MAX_SIZE_DW
);
585 r600_need_dma_space(&rctx
->b
, ncopy
* 5, rdst
, rsrc
);
586 for (i
= 0; i
< ncopy
; i
++) {
587 csize
= size
< R600_DMA_COPY_MAX_SIZE_DW
? size
: R600_DMA_COPY_MAX_SIZE_DW
;
588 /* emit reloc before writing cs so that cs is always in consistent state */
589 radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.dma
, rsrc
, RADEON_USAGE_READ
,
590 RADEON_PRIO_SDMA_BUFFER
);
591 radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.dma
, rdst
, RADEON_USAGE_WRITE
,
592 RADEON_PRIO_SDMA_BUFFER
);
593 radeon_emit(cs
, DMA_PACKET(DMA_PACKET_COPY
, 0, 0, csize
));
594 radeon_emit(cs
, dst_offset
& 0xfffffffc);
595 radeon_emit(cs
, src_offset
& 0xfffffffc);
596 radeon_emit(cs
, (dst_offset
>> 32UL) & 0xff);
597 radeon_emit(cs
, (src_offset
>> 32UL) & 0xff);
598 dst_offset
+= csize
<< 2;
599 src_offset
+= csize
<< 2;