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llvmpipe: Fix incorrect sizeof.
[mesa.git] / src / gallium / drivers / r600 / r600_hw_context.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include "r600_hw_context_priv.h"
27 #include "r600d.h"
28 #include "util/u_memory.h"
29 #include <errno.h>
30
31 /* Get backends mask */
32 void r600_get_backend_mask(struct r600_context *ctx)
33 {
34 struct radeon_winsys_cs *cs = ctx->cs;
35 struct r600_resource *buffer;
36 uint32_t *results;
37 unsigned num_backends = ctx->screen->info.r600_num_backends;
38 unsigned i, mask = 0;
39 uint64_t va;
40
41 /* if backend_map query is supported by the kernel */
42 if (ctx->screen->info.r600_backend_map_valid) {
43 unsigned num_tile_pipes = ctx->screen->info.r600_num_tile_pipes;
44 unsigned backend_map = ctx->screen->info.r600_backend_map;
45 unsigned item_width, item_mask;
46
47 if (ctx->chip_class >= EVERGREEN) {
48 item_width = 4;
49 item_mask = 0x7;
50 } else {
51 item_width = 2;
52 item_mask = 0x3;
53 }
54
55 while(num_tile_pipes--) {
56 i = backend_map & item_mask;
57 mask |= (1<<i);
58 backend_map >>= item_width;
59 }
60 if (mask != 0) {
61 ctx->backend_mask = mask;
62 return;
63 }
64 }
65
66 /* otherwise backup path for older kernels */
67
68 /* create buffer for event data */
69 buffer = (struct r600_resource*)
70 pipe_buffer_create(&ctx->screen->screen, PIPE_BIND_CUSTOM,
71 PIPE_USAGE_STAGING, ctx->max_db*16);
72 if (!buffer)
73 goto err;
74
75 va = r600_resource_va(&ctx->screen->screen, (void*)buffer);
76
77 /* initialize buffer with zeroes */
78 results = ctx->ws->buffer_map(buffer->cs_buf, ctx->cs, PIPE_TRANSFER_WRITE);
79 if (results) {
80 memset(results, 0, ctx->max_db * 4 * 4);
81 ctx->ws->buffer_unmap(buffer->cs_buf);
82
83 /* emit EVENT_WRITE for ZPASS_DONE */
84 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
85 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
86 cs->buf[cs->cdw++] = va;
87 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
88
89 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
90 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, buffer, RADEON_USAGE_WRITE);
91
92 /* analyze results */
93 results = ctx->ws->buffer_map(buffer->cs_buf, ctx->cs, PIPE_TRANSFER_READ);
94 if (results) {
95 for(i = 0; i < ctx->max_db; i++) {
96 /* at least highest bit will be set if backend is used */
97 if (results[i*4 + 1])
98 mask |= (1<<i);
99 }
100 ctx->ws->buffer_unmap(buffer->cs_buf);
101 }
102 }
103
104 pipe_resource_reference((struct pipe_resource**)&buffer, NULL);
105
106 if (mask != 0) {
107 ctx->backend_mask = mask;
108 return;
109 }
110
111 err:
112 /* fallback to old method - set num_backends lower bits to 1 */
113 ctx->backend_mask = (~((uint32_t)0))>>(32-num_backends);
114 return;
115 }
116
117 static void r600_init_block(struct r600_context *ctx,
118 struct r600_block *block,
119 const struct r600_reg *reg, int index, int nreg,
120 unsigned opcode, unsigned offset_base)
121 {
122 int i = index;
123 int j, n = nreg;
124
125 /* initialize block */
126 block->flags = 0;
127 block->status |= R600_BLOCK_STATUS_DIRTY; /* dirty all blocks at start */
128 block->start_offset = reg[i].offset;
129 block->pm4[block->pm4_ndwords++] = PKT3(opcode, n, 0);
130 block->pm4[block->pm4_ndwords++] = (block->start_offset - offset_base) >> 2;
131 block->reg = &block->pm4[block->pm4_ndwords];
132 block->pm4_ndwords += n;
133 block->nreg = n;
134 block->nreg_dirty = n;
135 LIST_INITHEAD(&block->list);
136 LIST_INITHEAD(&block->enable_list);
137
138 for (j = 0; j < n; j++) {
139 if (reg[i+j].flags & REG_FLAG_DIRTY_ALWAYS) {
140 block->flags |= REG_FLAG_DIRTY_ALWAYS;
141 }
142 if (reg[i+j].flags & REG_FLAG_ENABLE_ALWAYS) {
143 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
144 block->status |= R600_BLOCK_STATUS_ENABLED;
145 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
146 LIST_ADDTAIL(&block->list,&ctx->dirty);
147 }
148 }
149 if (reg[i+j].flags & REG_FLAG_FLUSH_CHANGE) {
150 block->flags |= REG_FLAG_FLUSH_CHANGE;
151 }
152
153 if (reg[i+j].flags & REG_FLAG_NEED_BO) {
154 block->nbo++;
155 assert(block->nbo < R600_BLOCK_MAX_BO);
156 block->pm4_bo_index[j] = block->nbo;
157 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0, 0);
158 block->pm4[block->pm4_ndwords++] = 0x00000000;
159 block->reloc[block->nbo].bo_pm4_index = block->pm4_ndwords - 1;
160 }
161 }
162 /* check that we stay in limit */
163 assert(block->pm4_ndwords < R600_BLOCK_MAX_REG);
164 }
165
166 int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg,
167 unsigned opcode, unsigned offset_base)
168 {
169 struct r600_block *block;
170 struct r600_range *range;
171 int offset;
172
173 for (unsigned i = 0, n = 0; i < nreg; i += n) {
174 /* ignore new block balise */
175 if (reg[i].offset == GROUP_FORCE_NEW_BLOCK) {
176 n = 1;
177 continue;
178 }
179
180 /* register that need relocation are in their own group */
181 /* find number of consecutive registers */
182 n = 0;
183 offset = reg[i].offset;
184 while (reg[i + n].offset == offset) {
185 n++;
186 offset += 4;
187 if ((n + i) >= nreg)
188 break;
189 if (n >= (R600_BLOCK_MAX_REG - 2))
190 break;
191 }
192
193 /* allocate new block */
194 block = calloc(1, sizeof(struct r600_block));
195 if (block == NULL) {
196 return -ENOMEM;
197 }
198 ctx->nblocks++;
199 for (int j = 0; j < n; j++) {
200 range = &ctx->range[CTX_RANGE_ID(reg[i + j].offset)];
201 /* create block table if it doesn't exist */
202 if (!range->blocks)
203 range->blocks = calloc(1 << HASH_SHIFT, sizeof(void *));
204 if (!range->blocks)
205 return -1;
206
207 range->blocks[CTX_BLOCK_ID(reg[i + j].offset)] = block;
208 }
209
210 r600_init_block(ctx, block, reg, i, n, opcode, offset_base);
211
212 }
213 return 0;
214 }
215
216 static const struct r600_reg r600_context_reg_list[] = {
217 {R_028D24_DB_HTILE_SURFACE, 0, 0},
218 {R_028614_SPI_VS_OUT_ID_0, 0, 0},
219 {R_028618_SPI_VS_OUT_ID_1, 0, 0},
220 {R_02861C_SPI_VS_OUT_ID_2, 0, 0},
221 {R_028620_SPI_VS_OUT_ID_3, 0, 0},
222 {R_028624_SPI_VS_OUT_ID_4, 0, 0},
223 {R_028628_SPI_VS_OUT_ID_5, 0, 0},
224 {R_02862C_SPI_VS_OUT_ID_6, 0, 0},
225 {R_028630_SPI_VS_OUT_ID_7, 0, 0},
226 {R_028634_SPI_VS_OUT_ID_8, 0, 0},
227 {R_028638_SPI_VS_OUT_ID_9, 0, 0},
228 {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0},
229 {GROUP_FORCE_NEW_BLOCK, 0, 0},
230 {R_028858_SQ_PGM_START_VS, REG_FLAG_NEED_BO, 0},
231 {GROUP_FORCE_NEW_BLOCK, 0, 0},
232 {R_028868_SQ_PGM_RESOURCES_VS, 0, 0},
233 {GROUP_FORCE_NEW_BLOCK, 0, 0},
234 {R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0},
235 {R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0},
236 {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0},
237 {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0},
238 {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0},
239 {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0},
240 {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0},
241 {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0},
242 {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0},
243 {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0},
244 {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0},
245 {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0},
246 {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0},
247 {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0},
248 {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0},
249 {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0},
250 {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0},
251 {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0},
252 {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0},
253 {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0},
254 {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0},
255 {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0},
256 {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0},
257 {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0},
258 {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0},
259 {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0},
260 {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0},
261 {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0},
262 {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0},
263 {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0},
264 {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0},
265 {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0},
266 {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0},
267 {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0},
268 {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0},
269 {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0},
270 {R_0286D8_SPI_INPUT_Z, 0, 0},
271 {GROUP_FORCE_NEW_BLOCK, 0, 0},
272 {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0},
273 {GROUP_FORCE_NEW_BLOCK, 0, 0},
274 {R_028850_SQ_PGM_RESOURCES_PS, 0, 0},
275 {R_028854_SQ_PGM_EXPORTS_PS, 0, 0},
276 };
277
278 /* initialize */
279 void r600_context_fini(struct r600_context *ctx)
280 {
281 struct r600_block *block;
282 struct r600_range *range;
283
284 if (ctx->range) {
285 for (int i = 0; i < NUM_RANGES; i++) {
286 if (!ctx->range[i].blocks)
287 continue;
288 for (int j = 0; j < (1 << HASH_SHIFT); j++) {
289 block = ctx->range[i].blocks[j];
290 if (block) {
291 for (int k = 0, offset = block->start_offset; k < block->nreg; k++, offset += 4) {
292 range = &ctx->range[CTX_RANGE_ID(offset)];
293 range->blocks[CTX_BLOCK_ID(offset)] = NULL;
294 }
295 for (int k = 1; k <= block->nbo; k++) {
296 pipe_resource_reference((struct pipe_resource**)&block->reloc[k].bo, NULL);
297 }
298 free(block);
299 }
300 }
301 free(ctx->range[i].blocks);
302 }
303 }
304 free(ctx->blocks);
305 }
306
307 int r600_setup_block_table(struct r600_context *ctx)
308 {
309 /* setup block table */
310 int c = 0;
311 ctx->blocks = calloc(ctx->nblocks, sizeof(void*));
312 if (!ctx->blocks)
313 return -ENOMEM;
314 for (int i = 0; i < NUM_RANGES; i++) {
315 if (!ctx->range[i].blocks)
316 continue;
317 for (int j = 0, add; j < (1 << HASH_SHIFT); j++) {
318 if (!ctx->range[i].blocks[j])
319 continue;
320
321 add = 1;
322 for (int k = 0; k < c; k++) {
323 if (ctx->blocks[k] == ctx->range[i].blocks[j]) {
324 add = 0;
325 break;
326 }
327 }
328 if (add) {
329 assert(c < ctx->nblocks);
330 ctx->blocks[c++] = ctx->range[i].blocks[j];
331 j += (ctx->range[i].blocks[j]->nreg) - 1;
332 }
333 }
334 }
335 return 0;
336 }
337
338 int r600_context_init(struct r600_context *ctx)
339 {
340 int r;
341
342 /* add blocks */
343 r = r600_context_add_block(ctx, r600_context_reg_list,
344 Elements(r600_context_reg_list), PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET);
345 if (r)
346 goto out_err;
347
348 r = r600_setup_block_table(ctx);
349 if (r)
350 goto out_err;
351
352 ctx->max_db = 4;
353 return 0;
354 out_err:
355 r600_context_fini(ctx);
356 return r;
357 }
358
359 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
360 boolean count_draw_in)
361 {
362 /* The number of dwords we already used in the CS so far. */
363 num_dw += ctx->cs->cdw;
364
365 if (count_draw_in) {
366 unsigned i;
367
368 /* The number of dwords all the dirty states would take. */
369 for (i = 0; i < R600_NUM_ATOMS; i++) {
370 if (ctx->atoms[i] && ctx->atoms[i]->dirty) {
371 num_dw += ctx->atoms[i]->num_dw;
372 }
373 }
374
375 num_dw += ctx->pm4_dirty_cdwords;
376
377 /* The upper-bound of how much space a draw command would take. */
378 num_dw += R600_MAX_FLUSH_CS_DWORDS + R600_MAX_DRAW_CS_DWORDS;
379 }
380
381 /* Count in queries_suspend. */
382 num_dw += ctx->num_cs_dw_nontimer_queries_suspend;
383 num_dw += ctx->num_cs_dw_timer_queries_suspend;
384
385 /* Count in streamout_end at the end of CS. */
386 num_dw += ctx->num_cs_dw_streamout_end;
387
388 /* Count in render_condition(NULL) at the end of CS. */
389 if (ctx->predicate_drawing) {
390 num_dw += 3;
391 }
392
393 /* SX_MISC */
394 if (ctx->chip_class <= R700) {
395 num_dw += 3;
396 }
397
398 /* Count in framebuffer cache flushes at the end of CS. */
399 num_dw += R600_MAX_FLUSH_CS_DWORDS;
400
401 /* The fence at the end of CS. */
402 num_dw += 10;
403
404 /* Flush if there's not enough space. */
405 if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
406 r600_flush(&ctx->context, NULL, RADEON_FLUSH_ASYNC);
407 }
408 }
409
410 void r600_context_dirty_block(struct r600_context *ctx,
411 struct r600_block *block,
412 int dirty, int index)
413 {
414 if ((index + 1) > block->nreg_dirty)
415 block->nreg_dirty = index + 1;
416
417 if ((dirty != (block->status & R600_BLOCK_STATUS_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) {
418 block->status |= R600_BLOCK_STATUS_DIRTY;
419 ctx->pm4_dirty_cdwords += block->pm4_ndwords;
420 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
421 block->status |= R600_BLOCK_STATUS_ENABLED;
422 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
423 }
424 LIST_ADDTAIL(&block->list,&ctx->dirty);
425
426 if (block->flags & REG_FLAG_FLUSH_CHANGE) {
427 ctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
428 }
429 }
430 }
431
432 /**
433 * If reg needs a reloc, this function will add it to its block's reloc list.
434 * @return true if reg needs a reloc, false otherwise
435 */
436 static bool r600_reg_set_block_reloc(struct r600_pipe_reg *reg)
437 {
438 unsigned reloc_id;
439
440 if (!reg->block->pm4_bo_index[reg->id]) {
441 return false;
442 }
443 /* find relocation */
444 reloc_id = reg->block->pm4_bo_index[reg->id];
445 pipe_resource_reference(
446 (struct pipe_resource**)&reg->block->reloc[reloc_id].bo,
447 &reg->bo->b.b);
448 reg->block->reloc[reloc_id].bo_usage = reg->bo_usage;
449 return true;
450 }
451
452 /**
453 * This function will emit all the registers in state directly to the command
454 * stream allowing you to bypass the r600_context dirty list.
455 *
456 * This is used for dispatching compute shaders to avoid mixing compute and
457 * 3D states in the context's dirty list.
458 *
459 * @param pkt_flags Should be either 0 or RADEON_CP_PACKET3_COMPUTE_MODE. This
460 * value will be passed on to r600_context_block_emit_dirty an or'd against
461 * the PKT3 headers.
462 */
463 void r600_context_pipe_state_emit(struct r600_context *ctx,
464 struct r600_pipe_state *state,
465 unsigned pkt_flags)
466 {
467 unsigned i;
468
469 /* Mark all blocks as dirty:
470 * Since two registers can be in the same block, we need to make sure
471 * we mark all the blocks dirty before we emit any of them. If we were
472 * to mark blocks dirty and emit them in the same loop, like this:
473 *
474 * foreach (reg in state->regs) {
475 * mark_dirty(reg->block)
476 * emit_block(reg->block)
477 * }
478 *
479 * Then if we have two registers in this state that are in the same
480 * block, we would end up emitting that block twice.
481 */
482 for (i = 0; i < state->nregs; i++) {
483 struct r600_pipe_reg *reg = &state->regs[i];
484 /* Mark all the registers in the block as dirty */
485 reg->block->nreg_dirty = reg->block->nreg;
486 reg->block->status |= R600_BLOCK_STATUS_DIRTY;
487 /* Update the reloc for this register if necessary. */
488 r600_reg_set_block_reloc(reg);
489 }
490
491 /* Emit the registers writes */
492 for (i = 0; i < state->nregs; i++) {
493 struct r600_pipe_reg *reg = &state->regs[i];
494 if (reg->block->status & R600_BLOCK_STATUS_DIRTY) {
495 r600_context_block_emit_dirty(ctx, reg->block, pkt_flags);
496 }
497 }
498 }
499
500 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state)
501 {
502 struct r600_block *block;
503 int dirty;
504 for (int i = 0; i < state->nregs; i++) {
505 unsigned id;
506 struct r600_pipe_reg *reg = &state->regs[i];
507
508 block = reg->block;
509 id = reg->id;
510
511 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
512
513 if (reg->value != block->reg[id]) {
514 block->reg[id] = reg->value;
515 dirty |= R600_BLOCK_STATUS_DIRTY;
516 }
517 if (block->flags & REG_FLAG_DIRTY_ALWAYS)
518 dirty |= R600_BLOCK_STATUS_DIRTY;
519 if (r600_reg_set_block_reloc(reg)) {
520 /* always force dirty for relocs for now */
521 dirty |= R600_BLOCK_STATUS_DIRTY;
522 }
523
524 if (dirty)
525 r600_context_dirty_block(ctx, block, dirty, id);
526 }
527 }
528
529 /**
530 * @param pkt_flags should be set to RADEON_CP_PACKET3_COMPUTE_MODE if this
531 * block will be used for compute shaders.
532 */
533 void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block,
534 unsigned pkt_flags)
535 {
536 struct radeon_winsys_cs *cs = ctx->cs;
537 int optional = block->nbo == 0 && !(block->flags & REG_FLAG_DIRTY_ALWAYS);
538 int cp_dwords = block->pm4_ndwords, start_dword = 0;
539 int new_dwords = 0;
540 int nbo = block->nbo;
541
542 if (block->nreg_dirty == 0 && optional) {
543 goto out;
544 }
545
546 if (nbo) {
547 for (int j = 0; j < block->nreg; j++) {
548 if (block->pm4_bo_index[j]) {
549 /* find relocation */
550 struct r600_block_reloc *reloc = &block->reloc[block->pm4_bo_index[j]];
551 if (reloc->bo) {
552 block->pm4[reloc->bo_pm4_index] =
553 r600_context_bo_reloc(ctx, reloc->bo, reloc->bo_usage);
554 } else {
555 block->pm4[reloc->bo_pm4_index] = 0;
556 }
557 nbo--;
558 if (nbo == 0)
559 break;
560
561 }
562 }
563 }
564
565 optional &= (block->nreg_dirty != block->nreg);
566 if (optional) {
567 new_dwords = block->nreg_dirty;
568 start_dword = cs->cdw;
569 cp_dwords = new_dwords + 2;
570 }
571 memcpy(&cs->buf[cs->cdw], block->pm4, cp_dwords * 4);
572
573 /* We are applying the pkt_flags after copying the register block to
574 * the the command stream, because it is possible this block will be
575 * emitted with a different pkt_flags, and we don't want to store the
576 * pkt_flags in the block.
577 */
578 cs->buf[cs->cdw] |= pkt_flags;
579 cs->cdw += cp_dwords;
580
581 if (optional) {
582 uint32_t newword;
583
584 newword = cs->buf[start_dword];
585 newword &= PKT_COUNT_C;
586 newword |= PKT_COUNT_S(new_dwords);
587 cs->buf[start_dword] = newword;
588 }
589 out:
590 block->status ^= R600_BLOCK_STATUS_DIRTY;
591 block->nreg_dirty = 0;
592 LIST_DELINIT(&block->list);
593 }
594
595 void r600_flush_emit(struct r600_context *rctx)
596 {
597 struct radeon_winsys_cs *cs = rctx->cs;
598
599 if (!rctx->flags) {
600 return;
601 }
602
603 if (rctx->flags & R600_CONTEXT_PS_PARTIAL_FLUSH) {
604 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
605 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
606 }
607
608 if (rctx->chip_class >= R700 &&
609 (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB_META)) {
610 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
611 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0);
612 }
613
614 if (rctx->flags & R600_CONTEXT_FLUSH_AND_INV) {
615 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
616 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
617
618 /* DB flushes are special due to errata with hyperz, we need to
619 * insert a no-op, so that the cache has time to really flush.
620 */
621 if (rctx->chip_class <= R700 &&
622 rctx->flags & R600_CONTEXT_HTILE_ERRATA) {
623 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 31, 0);
624 cs->buf[cs->cdw++] = 0xdeadcafe;
625 cs->buf[cs->cdw++] = 0xdeadcafe;
626 cs->buf[cs->cdw++] = 0xdeadcafe;
627 cs->buf[cs->cdw++] = 0xdeadcafe;
628 cs->buf[cs->cdw++] = 0xdeadcafe;
629 cs->buf[cs->cdw++] = 0xdeadcafe;
630 cs->buf[cs->cdw++] = 0xdeadcafe;
631 cs->buf[cs->cdw++] = 0xdeadcafe;
632 cs->buf[cs->cdw++] = 0xdeadcafe;
633 cs->buf[cs->cdw++] = 0xdeadcafe;
634 cs->buf[cs->cdw++] = 0xdeadcafe;
635 cs->buf[cs->cdw++] = 0xdeadcafe;
636 cs->buf[cs->cdw++] = 0xdeadcafe;
637 cs->buf[cs->cdw++] = 0xdeadcafe;
638 cs->buf[cs->cdw++] = 0xdeadcafe;
639 cs->buf[cs->cdw++] = 0xdeadcafe;
640 cs->buf[cs->cdw++] = 0xdeadcafe;
641 cs->buf[cs->cdw++] = 0xdeadcafe;
642 cs->buf[cs->cdw++] = 0xdeadcafe;
643 cs->buf[cs->cdw++] = 0xdeadcafe;
644 cs->buf[cs->cdw++] = 0xdeadcafe;
645 cs->buf[cs->cdw++] = 0xdeadcafe;
646 cs->buf[cs->cdw++] = 0xdeadcafe;
647 cs->buf[cs->cdw++] = 0xdeadcafe;
648 cs->buf[cs->cdw++] = 0xdeadcafe;
649 cs->buf[cs->cdw++] = 0xdeadcafe;
650 cs->buf[cs->cdw++] = 0xdeadcafe;
651 cs->buf[cs->cdw++] = 0xdeadcafe;
652 cs->buf[cs->cdw++] = 0xdeadcafe;
653 cs->buf[cs->cdw++] = 0xdeadcafe;
654 cs->buf[cs->cdw++] = 0xdeadcafe;
655 cs->buf[cs->cdw++] = 0xdeadcafe;
656 }
657 }
658
659 if (rctx->flags & (R600_CONTEXT_CB_FLUSH |
660 R600_CONTEXT_DB_FLUSH |
661 R600_CONTEXT_SHADERCONST_FLUSH |
662 R600_CONTEXT_TEX_FLUSH |
663 R600_CONTEXT_VTX_FLUSH |
664 R600_CONTEXT_STREAMOUT_FLUSH)) {
665 /* anything left (cb, vtx, shader, streamout) can be flushed
666 * using the surface sync packet
667 */
668 unsigned flags = 0;
669
670 if (rctx->flags & R600_CONTEXT_CB_FLUSH) {
671 flags |= S_0085F0_CB_ACTION_ENA(1) |
672 S_0085F0_CB0_DEST_BASE_ENA(1) |
673 S_0085F0_CB1_DEST_BASE_ENA(1) |
674 S_0085F0_CB2_DEST_BASE_ENA(1) |
675 S_0085F0_CB3_DEST_BASE_ENA(1) |
676 S_0085F0_CB4_DEST_BASE_ENA(1) |
677 S_0085F0_CB5_DEST_BASE_ENA(1) |
678 S_0085F0_CB6_DEST_BASE_ENA(1) |
679 S_0085F0_CB7_DEST_BASE_ENA(1);
680
681 if (rctx->chip_class >= EVERGREEN) {
682 flags |= S_0085F0_CB8_DEST_BASE_ENA(1) |
683 S_0085F0_CB9_DEST_BASE_ENA(1) |
684 S_0085F0_CB10_DEST_BASE_ENA(1) |
685 S_0085F0_CB11_DEST_BASE_ENA(1);
686 }
687
688 /* RV670 errata
689 * (CB1_DEST_BASE_ENA is also required, which is
690 * included unconditionally above). */
691 if (rctx->family == CHIP_RV670 ||
692 rctx->family == CHIP_RS780 ||
693 rctx->family == CHIP_RS880) {
694 flags |= S_0085F0_DEST_BASE_0_ENA(1);
695 }
696 }
697
698 if (rctx->flags & R600_CONTEXT_STREAMOUT_FLUSH) {
699 flags |= S_0085F0_SO0_DEST_BASE_ENA(1) |
700 S_0085F0_SO1_DEST_BASE_ENA(1) |
701 S_0085F0_SO2_DEST_BASE_ENA(1) |
702 S_0085F0_SO3_DEST_BASE_ENA(1) |
703 S_0085F0_SMX_ACTION_ENA(1);
704
705 /* RV670 errata */
706 if (rctx->family == CHIP_RV670 ||
707 rctx->family == CHIP_RS780 ||
708 rctx->family == CHIP_RS880) {
709 flags |= S_0085F0_DEST_BASE_0_ENA(1);
710 }
711 }
712
713 flags |= (rctx->flags & R600_CONTEXT_DB_FLUSH) ? S_0085F0_DB_ACTION_ENA(1) |
714 S_0085F0_DB_DEST_BASE_ENA(1): 0;
715 flags |= (rctx->flags & R600_CONTEXT_SHADERCONST_FLUSH) ? S_0085F0_SH_ACTION_ENA(1) : 0;
716 flags |= (rctx->flags & R600_CONTEXT_TEX_FLUSH) ? S_0085F0_TC_ACTION_ENA(1) : 0;
717 flags |= (rctx->flags & R600_CONTEXT_VTX_FLUSH) ? S_0085F0_VC_ACTION_ENA(1) : 0;
718
719 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
720 cs->buf[cs->cdw++] = flags; /* CP_COHER_CNTL */
721 cs->buf[cs->cdw++] = 0xffffffff; /* CP_COHER_SIZE */
722 cs->buf[cs->cdw++] = 0; /* CP_COHER_BASE */
723 cs->buf[cs->cdw++] = 0x0000000A; /* POLL_INTERVAL */
724 }
725
726 if (rctx->flags & R600_CONTEXT_WAIT_IDLE) {
727 /* wait for things to settle */
728 r600_write_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
729 }
730
731 /* everything is properly flushed */
732 rctx->flags = 0;
733 }
734
735 void r600_context_flush(struct r600_context *ctx, unsigned flags)
736 {
737 struct radeon_winsys_cs *cs = ctx->cs;
738
739 if (cs->cdw == ctx->start_cs_cmd.num_dw)
740 return;
741
742 ctx->timer_queries_suspended = false;
743 ctx->nontimer_queries_suspended = false;
744 ctx->streamout_suspended = false;
745
746 /* suspend queries */
747 if (ctx->num_cs_dw_timer_queries_suspend) {
748 r600_suspend_timer_queries(ctx);
749 ctx->timer_queries_suspended = true;
750 }
751 if (ctx->num_cs_dw_nontimer_queries_suspend) {
752 r600_suspend_nontimer_queries(ctx);
753 ctx->nontimer_queries_suspended = true;
754 }
755
756 if (ctx->num_cs_dw_streamout_end) {
757 r600_context_streamout_end(ctx);
758 ctx->streamout_suspended = true;
759 }
760
761 /* partial flush is needed to avoid lockups on some chips with user fences */
762 ctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
763
764 /* flush the framebuffer */
765 ctx->flags |= R600_CONTEXT_CB_FLUSH | R600_CONTEXT_DB_FLUSH;
766
767 /* R6xx errata */
768 if (ctx->chip_class == R600) {
769 ctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
770 }
771
772 r600_flush_emit(ctx);
773
774 /* old kernels and userspace don't set SX_MISC, so we must reset it to 0 here */
775 if (ctx->chip_class <= R700) {
776 r600_write_context_reg(cs, R_028350_SX_MISC, 0);
777 }
778
779 /* force to keep tiling flags */
780 if (ctx->keep_tiling_flags) {
781 flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
782 }
783
784 /* Flush the CS. */
785 ctx->ws->cs_flush(ctx->cs, flags);
786
787 r600_begin_new_cs(ctx);
788 }
789
790 void r600_begin_new_cs(struct r600_context *ctx)
791 {
792 struct r600_block *enable_block = NULL;
793 unsigned shader;
794
795 ctx->pm4_dirty_cdwords = 0;
796 ctx->flags = 0;
797
798 /* Begin a new CS. */
799 r600_emit_command_buffer(ctx->cs, &ctx->start_cs_cmd);
800
801 /* Re-emit states. */
802 ctx->alphatest_state.atom.dirty = true;
803 ctx->blend_color.atom.dirty = true;
804 ctx->cb_misc_state.atom.dirty = true;
805 ctx->clip_misc_state.atom.dirty = true;
806 ctx->clip_state.atom.dirty = true;
807 ctx->db_misc_state.atom.dirty = true;
808 ctx->framebuffer.atom.dirty = true;
809 ctx->poly_offset_state.atom.dirty = true;
810 ctx->vgt_state.atom.dirty = true;
811 ctx->vgt2_state.atom.dirty = true;
812 ctx->sample_mask.atom.dirty = true;
813 ctx->scissor.atom.dirty = true;
814 ctx->config_state.atom.dirty = true;
815 ctx->stencil_ref.atom.dirty = true;
816 ctx->vertex_fetch_shader.atom.dirty = true;
817 ctx->viewport.atom.dirty = true;
818
819 if (ctx->blend_state.cso)
820 ctx->blend_state.atom.dirty = true;
821 if (ctx->dsa_state.cso)
822 ctx->dsa_state.atom.dirty = true;
823 if (ctx->rasterizer_state.cso)
824 ctx->rasterizer_state.atom.dirty = true;
825
826 if (ctx->chip_class <= R700) {
827 ctx->seamless_cube_map.atom.dirty = true;
828 }
829
830 ctx->vertex_buffer_state.dirty_mask = ctx->vertex_buffer_state.enabled_mask;
831 r600_vertex_buffers_dirty(ctx);
832
833 /* Re-emit shader resources. */
834 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
835 struct r600_constbuf_state *constbuf = &ctx->constbuf_state[shader];
836 struct r600_textures_info *samplers = &ctx->samplers[shader];
837
838 constbuf->dirty_mask = constbuf->enabled_mask;
839 samplers->views.dirty_mask = samplers->views.enabled_mask;
840 samplers->states.dirty_mask = samplers->states.enabled_mask;
841
842 r600_constant_buffers_dirty(ctx, constbuf);
843 r600_sampler_views_dirty(ctx, &samplers->views);
844 r600_sampler_states_dirty(ctx, &samplers->states);
845 }
846
847 if (ctx->streamout_suspended) {
848 ctx->streamout_start = TRUE;
849 ctx->streamout_append_bitmask = ~0;
850 }
851
852 /* resume queries */
853 if (ctx->timer_queries_suspended) {
854 r600_resume_timer_queries(ctx);
855 }
856 if (ctx->nontimer_queries_suspended) {
857 r600_resume_nontimer_queries(ctx);
858 }
859
860 /* set all valid group as dirty so they get reemited on
861 * next draw command
862 */
863 LIST_FOR_EACH_ENTRY(enable_block, &ctx->enable_list, enable_list) {
864 if(!(enable_block->status & R600_BLOCK_STATUS_DIRTY)) {
865 LIST_ADDTAIL(&enable_block->list,&ctx->dirty);
866 enable_block->status |= R600_BLOCK_STATUS_DIRTY;
867 }
868 ctx->pm4_dirty_cdwords += enable_block->pm4_ndwords;
869 enable_block->nreg_dirty = enable_block->nreg;
870 }
871
872 /* Re-emit the draw state. */
873 ctx->last_primitive_type = -1;
874 ctx->last_start_instance = -1;
875 }
876
877 void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence_bo, unsigned offset, unsigned value)
878 {
879 struct radeon_winsys_cs *cs = ctx->cs;
880 uint64_t va;
881
882 r600_need_cs_space(ctx, 10, FALSE);
883
884 va = r600_resource_va(&ctx->screen->screen, (void*)fence_bo);
885 va = va + (offset << 2);
886
887 ctx->flags &= ~R600_CONTEXT_PS_PARTIAL_FLUSH;
888 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
889 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
890
891 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
892 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
893 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* ADDRESS_LO */
894 /* DATA_SEL | INT_EN | ADDRESS_HI */
895 cs->buf[cs->cdw++] = (1 << 29) | (0 << 24) | ((va >> 32UL) & 0xFF);
896 cs->buf[cs->cdw++] = value; /* DATA_LO */
897 cs->buf[cs->cdw++] = 0; /* DATA_HI */
898 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
899 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, fence_bo, RADEON_USAGE_WRITE);
900 }
901
902 static void r600_flush_vgt_streamout(struct r600_context *ctx)
903 {
904 struct radeon_winsys_cs *cs = ctx->cs;
905
906 r600_write_config_reg(cs, R_008490_CP_STRMOUT_CNTL, 0);
907
908 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
909 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0);
910
911 cs->buf[cs->cdw++] = PKT3(PKT3_WAIT_REG_MEM, 5, 0);
912 cs->buf[cs->cdw++] = WAIT_REG_MEM_EQUAL; /* wait until the register is equal to the reference value */
913 cs->buf[cs->cdw++] = R_008490_CP_STRMOUT_CNTL >> 2; /* register */
914 cs->buf[cs->cdw++] = 0;
915 cs->buf[cs->cdw++] = S_008490_OFFSET_UPDATE_DONE(1); /* reference value */
916 cs->buf[cs->cdw++] = S_008490_OFFSET_UPDATE_DONE(1); /* mask */
917 cs->buf[cs->cdw++] = 4; /* poll interval */
918 }
919
920 static void r600_set_streamout_enable(struct r600_context *ctx, unsigned buffer_enable_bit)
921 {
922 struct radeon_winsys_cs *cs = ctx->cs;
923
924 if (buffer_enable_bit) {
925 r600_write_context_reg(cs, R_028AB0_VGT_STRMOUT_EN, S_028AB0_STREAMOUT(1));
926 r600_write_context_reg(cs, R_028B20_VGT_STRMOUT_BUFFER_EN, buffer_enable_bit);
927 } else {
928 r600_write_context_reg(cs, R_028AB0_VGT_STRMOUT_EN, S_028AB0_STREAMOUT(0));
929 }
930 }
931
932 void r600_context_streamout_begin(struct r600_context *ctx)
933 {
934 struct radeon_winsys_cs *cs = ctx->cs;
935 struct r600_so_target **t = ctx->so_targets;
936 unsigned *stride_in_dw = ctx->vs_shader->so.stride;
937 unsigned buffer_en, i, update_flags = 0;
938 uint64_t va;
939 unsigned num_cs_dw_streamout_end;
940
941 buffer_en = (ctx->num_so_targets >= 1 && t[0] ? 1 : 0) |
942 (ctx->num_so_targets >= 2 && t[1] ? 2 : 0) |
943 (ctx->num_so_targets >= 3 && t[2] ? 4 : 0) |
944 (ctx->num_so_targets >= 4 && t[3] ? 8 : 0);
945
946 num_cs_dw_streamout_end =
947 12 + /* flush_vgt_streamout */
948 util_bitcount(buffer_en) * 8 + /* STRMOUT_BUFFER_UPDATE */
949 3 /* set_streamout_enable(0) */;
950
951 r600_need_cs_space(ctx,
952 12 + /* flush_vgt_streamout */
953 6 + /* set_streamout_enable */
954 util_bitcount(buffer_en) * 7 + /* SET_CONTEXT_REG */
955 (ctx->family >= CHIP_RS780 &&
956 ctx->family <= CHIP_RV740 ? util_bitcount(buffer_en) * 5 : 0) + /* STRMOUT_BASE_UPDATE */
957 util_bitcount(buffer_en & ctx->streamout_append_bitmask) * 8 + /* STRMOUT_BUFFER_UPDATE */
958 util_bitcount(buffer_en & ~ctx->streamout_append_bitmask) * 6 + /* STRMOUT_BUFFER_UPDATE */
959 (ctx->family > CHIP_R600 && ctx->family < CHIP_RS780 ? 2 : 0) + /* SURFACE_BASE_UPDATE */
960 num_cs_dw_streamout_end, TRUE);
961
962 /* This must be set after r600_need_cs_space. */
963 ctx->num_cs_dw_streamout_end = num_cs_dw_streamout_end;
964
965 if (ctx->chip_class >= EVERGREEN) {
966 evergreen_flush_vgt_streamout(ctx);
967 evergreen_set_streamout_enable(ctx, buffer_en);
968 } else {
969 r600_flush_vgt_streamout(ctx);
970 r600_set_streamout_enable(ctx, buffer_en);
971 }
972
973 for (i = 0; i < ctx->num_so_targets; i++) {
974 if (t[i]) {
975 t[i]->stride_in_dw = stride_in_dw[i];
976 t[i]->so_index = i;
977 va = r600_resource_va(&ctx->screen->screen,
978 (void*)t[i]->b.buffer);
979
980 update_flags |= SURFACE_BASE_UPDATE_STRMOUT(i);
981
982 r600_write_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 3);
983 r600_write_value(cs, (t[i]->b.buffer_offset +
984 t[i]->b.buffer_size) >> 2); /* BUFFER_SIZE (in DW) */
985 r600_write_value(cs, stride_in_dw[i]); /* VTX_STRIDE (in DW) */
986 r600_write_value(cs, va >> 8); /* BUFFER_BASE */
987
988 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
989 cs->buf[cs->cdw++] =
990 r600_context_bo_reloc(ctx, r600_resource(t[i]->b.buffer),
991 RADEON_USAGE_WRITE);
992
993 /* R7xx requires this packet after updating BUFFER_BASE.
994 * Without this, R7xx locks up. */
995 if (ctx->family >= CHIP_RS780 && ctx->family <= CHIP_RV740) {
996 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BASE_UPDATE, 1, 0);
997 cs->buf[cs->cdw++] = i;
998 cs->buf[cs->cdw++] = va >> 8;
999
1000 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1001 cs->buf[cs->cdw++] =
1002 r600_context_bo_reloc(ctx, r600_resource(t[i]->b.buffer),
1003 RADEON_USAGE_WRITE);
1004 }
1005
1006 if (ctx->streamout_append_bitmask & (1 << i)) {
1007 va = r600_resource_va(&ctx->screen->screen,
1008 (void*)t[i]->filled_size);
1009 /* Append. */
1010 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
1011 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
1012 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM); /* control */
1013 cs->buf[cs->cdw++] = 0; /* unused */
1014 cs->buf[cs->cdw++] = 0; /* unused */
1015 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */
1016 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
1017
1018 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1019 cs->buf[cs->cdw++] =
1020 r600_context_bo_reloc(ctx, t[i]->filled_size,
1021 RADEON_USAGE_READ);
1022 } else {
1023 /* Start from the beginning. */
1024 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
1025 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
1026 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET); /* control */
1027 cs->buf[cs->cdw++] = 0; /* unused */
1028 cs->buf[cs->cdw++] = 0; /* unused */
1029 cs->buf[cs->cdw++] = t[i]->b.buffer_offset >> 2; /* buffer offset in DW */
1030 cs->buf[cs->cdw++] = 0; /* unused */
1031 }
1032 }
1033 }
1034
1035 if (ctx->family > CHIP_R600 && ctx->family < CHIP_RS780) {
1036 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0);
1037 cs->buf[cs->cdw++] = update_flags;
1038 }
1039 }
1040
1041 void r600_context_streamout_end(struct r600_context *ctx)
1042 {
1043 struct radeon_winsys_cs *cs = ctx->cs;
1044 struct r600_so_target **t = ctx->so_targets;
1045 unsigned i;
1046 uint64_t va;
1047
1048 if (ctx->chip_class >= EVERGREEN) {
1049 evergreen_flush_vgt_streamout(ctx);
1050 } else {
1051 r600_flush_vgt_streamout(ctx);
1052 }
1053
1054 for (i = 0; i < ctx->num_so_targets; i++) {
1055 if (t[i]) {
1056 va = r600_resource_va(&ctx->screen->screen,
1057 (void*)t[i]->filled_size);
1058 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
1059 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
1060 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
1061 STRMOUT_STORE_BUFFER_FILLED_SIZE; /* control */
1062 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* dst address lo */
1063 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* dst address hi */
1064 cs->buf[cs->cdw++] = 0; /* unused */
1065 cs->buf[cs->cdw++] = 0; /* unused */
1066
1067 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1068 cs->buf[cs->cdw++] =
1069 r600_context_bo_reloc(ctx, t[i]->filled_size,
1070 RADEON_USAGE_WRITE);
1071
1072 }
1073 }
1074
1075 if (ctx->chip_class >= EVERGREEN) {
1076 evergreen_set_streamout_enable(ctx, 0);
1077 } else {
1078 r600_set_streamout_enable(ctx, 0);
1079 }
1080 ctx->flags |= R600_CONTEXT_STREAMOUT_FLUSH;
1081
1082 /* R6xx errata */
1083 if (ctx->chip_class == R600) {
1084 ctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
1085 }
1086 ctx->num_cs_dw_streamout_end = 0;
1087 }