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r600g: make F2U trans-only on r600-r700
[mesa.git] / src / gallium / drivers / r600 / r600_hw_context.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include "r600_hw_context_priv.h"
27 #include "r600d.h"
28 #include "util/u_memory.h"
29 #include <errno.h>
30
31 /* Get backends mask */
32 void r600_get_backend_mask(struct r600_context *ctx)
33 {
34 struct radeon_winsys_cs *cs = ctx->cs;
35 struct r600_resource *buffer;
36 uint32_t *results;
37 unsigned num_backends = ctx->screen->info.r600_num_backends;
38 unsigned i, mask = 0;
39 uint64_t va;
40
41 /* if backend_map query is supported by the kernel */
42 if (ctx->screen->info.r600_backend_map_valid) {
43 unsigned num_tile_pipes = ctx->screen->info.r600_num_tile_pipes;
44 unsigned backend_map = ctx->screen->info.r600_backend_map;
45 unsigned item_width, item_mask;
46
47 if (ctx->chip_class >= EVERGREEN) {
48 item_width = 4;
49 item_mask = 0x7;
50 } else {
51 item_width = 2;
52 item_mask = 0x3;
53 }
54
55 while(num_tile_pipes--) {
56 i = backend_map & item_mask;
57 mask |= (1<<i);
58 backend_map >>= item_width;
59 }
60 if (mask != 0) {
61 ctx->backend_mask = mask;
62 return;
63 }
64 }
65
66 /* otherwise backup path for older kernels */
67
68 /* create buffer for event data */
69 buffer = (struct r600_resource*)
70 pipe_buffer_create(&ctx->screen->screen, PIPE_BIND_CUSTOM,
71 PIPE_USAGE_STAGING, ctx->max_db*16);
72 if (!buffer)
73 goto err;
74
75 va = r600_resource_va(&ctx->screen->screen, (void*)buffer);
76
77 /* initialize buffer with zeroes */
78 results = ctx->ws->buffer_map(buffer->cs_buf, ctx->cs, PIPE_TRANSFER_WRITE);
79 if (results) {
80 memset(results, 0, ctx->max_db * 4 * 4);
81 ctx->ws->buffer_unmap(buffer->cs_buf);
82
83 /* emit EVENT_WRITE for ZPASS_DONE */
84 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
85 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
86 cs->buf[cs->cdw++] = va;
87 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
88
89 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
90 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, buffer, RADEON_USAGE_WRITE);
91
92 /* analyze results */
93 results = ctx->ws->buffer_map(buffer->cs_buf, ctx->cs, PIPE_TRANSFER_READ);
94 if (results) {
95 for(i = 0; i < ctx->max_db; i++) {
96 /* at least highest bit will be set if backend is used */
97 if (results[i*4 + 1])
98 mask |= (1<<i);
99 }
100 ctx->ws->buffer_unmap(buffer->cs_buf);
101 }
102 }
103
104 pipe_resource_reference((struct pipe_resource**)&buffer, NULL);
105
106 if (mask != 0) {
107 ctx->backend_mask = mask;
108 return;
109 }
110
111 err:
112 /* fallback to old method - set num_backends lower bits to 1 */
113 ctx->backend_mask = (~((uint32_t)0))>>(32-num_backends);
114 return;
115 }
116
117 void r600_context_ps_partial_flush(struct r600_context *ctx)
118 {
119 struct radeon_winsys_cs *cs = ctx->cs;
120
121 if (!(ctx->flags & R600_CONTEXT_DRAW_PENDING))
122 return;
123
124 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
125 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
126
127 ctx->flags &= ~R600_CONTEXT_DRAW_PENDING;
128 }
129
130 static void r600_init_block(struct r600_context *ctx,
131 struct r600_block *block,
132 const struct r600_reg *reg, int index, int nreg,
133 unsigned opcode, unsigned offset_base)
134 {
135 int i = index;
136 int j, n = nreg;
137
138 /* initialize block */
139 block->flags = 0;
140 block->status |= R600_BLOCK_STATUS_DIRTY; /* dirty all blocks at start */
141 block->start_offset = reg[i].offset;
142 block->pm4[block->pm4_ndwords++] = PKT3(opcode, n, 0);
143 block->pm4[block->pm4_ndwords++] = (block->start_offset - offset_base) >> 2;
144 block->reg = &block->pm4[block->pm4_ndwords];
145 block->pm4_ndwords += n;
146 block->nreg = n;
147 block->nreg_dirty = n;
148 LIST_INITHEAD(&block->list);
149 LIST_INITHEAD(&block->enable_list);
150
151 for (j = 0; j < n; j++) {
152 if (reg[i+j].flags & REG_FLAG_DIRTY_ALWAYS) {
153 block->flags |= REG_FLAG_DIRTY_ALWAYS;
154 }
155 if (reg[i+j].flags & REG_FLAG_ENABLE_ALWAYS) {
156 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
157 block->status |= R600_BLOCK_STATUS_ENABLED;
158 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
159 LIST_ADDTAIL(&block->list,&ctx->dirty);
160 }
161 }
162 if (reg[i+j].flags & REG_FLAG_FLUSH_CHANGE) {
163 block->flags |= REG_FLAG_FLUSH_CHANGE;
164 }
165
166 if (reg[i+j].flags & REG_FLAG_NEED_BO) {
167 block->nbo++;
168 assert(block->nbo < R600_BLOCK_MAX_BO);
169 block->pm4_bo_index[j] = block->nbo;
170 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0, 0);
171 block->pm4[block->pm4_ndwords++] = 0x00000000;
172 block->reloc[block->nbo].bo_pm4_index = block->pm4_ndwords - 1;
173 }
174 if ((ctx->family > CHIP_R600) &&
175 (ctx->family < CHIP_RV770) && reg[i+j].flags & REG_FLAG_RV6XX_SBU) {
176 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0);
177 block->pm4[block->pm4_ndwords++] = reg[i+j].sbu_flags;
178 }
179 }
180 /* check that we stay in limit */
181 assert(block->pm4_ndwords < R600_BLOCK_MAX_REG);
182 }
183
184 int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg,
185 unsigned opcode, unsigned offset_base)
186 {
187 struct r600_block *block;
188 struct r600_range *range;
189 int offset;
190
191 for (unsigned i = 0, n = 0; i < nreg; i += n) {
192 /* ignore new block balise */
193 if (reg[i].offset == GROUP_FORCE_NEW_BLOCK) {
194 n = 1;
195 continue;
196 }
197
198 /* ignore regs not on R600 on R600 */
199 if ((reg[i].flags & REG_FLAG_NOT_R600) && ctx->family == CHIP_R600) {
200 n = 1;
201 continue;
202 }
203
204 /* register that need relocation are in their own group */
205 /* find number of consecutive registers */
206 n = 0;
207 offset = reg[i].offset;
208 while (reg[i + n].offset == offset) {
209 n++;
210 offset += 4;
211 if ((n + i) >= nreg)
212 break;
213 if (n >= (R600_BLOCK_MAX_REG - 2))
214 break;
215 }
216
217 /* allocate new block */
218 block = calloc(1, sizeof(struct r600_block));
219 if (block == NULL) {
220 return -ENOMEM;
221 }
222 ctx->nblocks++;
223 for (int j = 0; j < n; j++) {
224 range = &ctx->range[CTX_RANGE_ID(reg[i + j].offset)];
225 /* create block table if it doesn't exist */
226 if (!range->blocks)
227 range->blocks = calloc(1 << HASH_SHIFT, sizeof(void *));
228 if (!range->blocks)
229 return -1;
230
231 range->blocks[CTX_BLOCK_ID(reg[i + j].offset)] = block;
232 }
233
234 r600_init_block(ctx, block, reg, i, n, opcode, offset_base);
235
236 }
237 return 0;
238 }
239
240 /* R600/R700 configuration */
241 static const struct r600_reg r600_config_reg_list[] = {
242 {R_008958_VGT_PRIMITIVE_TYPE, 0, 0},
243 {R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
244 };
245
246 static const struct r600_reg r600_ctl_const_list[] = {
247 {R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0},
248 };
249
250 static const struct r600_reg r600_context_reg_list[] = {
251 {R_028A4C_PA_SC_MODE_CNTL, 0, 0},
252 {GROUP_FORCE_NEW_BLOCK, 0, 0},
253 {R_028040_CB_COLOR0_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(0)},
254 {GROUP_FORCE_NEW_BLOCK, 0, 0},
255 {R_0280A0_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0},
256 {R_028060_CB_COLOR0_SIZE, 0, 0},
257 {R_028080_CB_COLOR0_VIEW, 0, 0},
258 {GROUP_FORCE_NEW_BLOCK, 0, 0},
259 {R_0280E0_CB_COLOR0_FRAG, REG_FLAG_NEED_BO, 0},
260 {GROUP_FORCE_NEW_BLOCK, 0, 0},
261 {R_0280C0_CB_COLOR0_TILE, REG_FLAG_NEED_BO, 0},
262 {GROUP_FORCE_NEW_BLOCK, 0, 0},
263 {R_028044_CB_COLOR1_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(1)},
264 {GROUP_FORCE_NEW_BLOCK, 0, 0},
265 {R_0280A4_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0},
266 {R_028064_CB_COLOR1_SIZE, 0, 0},
267 {R_028084_CB_COLOR1_VIEW, 0, 0},
268 {GROUP_FORCE_NEW_BLOCK, 0, 0},
269 {R_0280E4_CB_COLOR1_FRAG, REG_FLAG_NEED_BO, 0},
270 {GROUP_FORCE_NEW_BLOCK, 0, 0},
271 {R_0280C4_CB_COLOR1_TILE, REG_FLAG_NEED_BO, 0},
272 {GROUP_FORCE_NEW_BLOCK, 0, 0},
273 {R_028048_CB_COLOR2_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(2)},
274 {GROUP_FORCE_NEW_BLOCK, 0, 0},
275 {R_0280A8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0},
276 {R_028068_CB_COLOR2_SIZE, 0, 0},
277 {R_028088_CB_COLOR2_VIEW, 0, 0},
278 {GROUP_FORCE_NEW_BLOCK, 0, 0},
279 {R_0280E8_CB_COLOR2_FRAG, REG_FLAG_NEED_BO, 0},
280 {GROUP_FORCE_NEW_BLOCK, 0, 0},
281 {R_0280C8_CB_COLOR2_TILE, REG_FLAG_NEED_BO, 0},
282 {GROUP_FORCE_NEW_BLOCK, 0, 0},
283 {R_02804C_CB_COLOR3_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(3)},
284 {GROUP_FORCE_NEW_BLOCK, 0, 0},
285 {R_0280AC_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0},
286 {R_02806C_CB_COLOR3_SIZE, 0, 0},
287 {R_02808C_CB_COLOR3_VIEW, 0, 0},
288 {GROUP_FORCE_NEW_BLOCK, 0, 0},
289 {R_0280EC_CB_COLOR3_FRAG, REG_FLAG_NEED_BO, 0},
290 {GROUP_FORCE_NEW_BLOCK, 0, 0},
291 {R_0280CC_CB_COLOR3_TILE, REG_FLAG_NEED_BO, 0},
292 {GROUP_FORCE_NEW_BLOCK, 0, 0},
293 {R_028050_CB_COLOR4_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(4)},
294 {GROUP_FORCE_NEW_BLOCK, 0, 0},
295 {R_0280B0_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0},
296 {R_028070_CB_COLOR4_SIZE, 0, 0},
297 {R_028090_CB_COLOR4_VIEW, 0, 0},
298 {GROUP_FORCE_NEW_BLOCK, 0, 0},
299 {R_0280F0_CB_COLOR4_FRAG, REG_FLAG_NEED_BO, 0},
300 {GROUP_FORCE_NEW_BLOCK, 0, 0},
301 {R_0280D0_CB_COLOR4_TILE, REG_FLAG_NEED_BO, 0},
302 {GROUP_FORCE_NEW_BLOCK, 0, 0},
303 {R_028054_CB_COLOR5_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(5)},
304 {GROUP_FORCE_NEW_BLOCK, 0, 0},
305 {R_0280B4_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0},
306 {R_028074_CB_COLOR5_SIZE, 0, 0},
307 {R_028094_CB_COLOR5_VIEW, 0, 0},
308 {GROUP_FORCE_NEW_BLOCK, 0, 0},
309 {R_0280F4_CB_COLOR5_FRAG, REG_FLAG_NEED_BO, 0},
310 {GROUP_FORCE_NEW_BLOCK, 0, 0},
311 {R_0280D4_CB_COLOR5_TILE, REG_FLAG_NEED_BO, 0},
312 {R_028058_CB_COLOR6_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(6)},
313 {R_0280B8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0},
314 {R_028078_CB_COLOR6_SIZE, 0, 0},
315 {R_028098_CB_COLOR6_VIEW, 0, 0},
316 {GROUP_FORCE_NEW_BLOCK, 0, 0},
317 {R_0280F8_CB_COLOR6_FRAG, REG_FLAG_NEED_BO, 0},
318 {GROUP_FORCE_NEW_BLOCK, 0, 0},
319 {R_0280D8_CB_COLOR6_TILE, REG_FLAG_NEED_BO, 0},
320 {GROUP_FORCE_NEW_BLOCK, 0, 0},
321 {R_02805C_CB_COLOR7_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(7)},
322 {GROUP_FORCE_NEW_BLOCK, 0, 0},
323 {R_0280BC_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0},
324 {R_02807C_CB_COLOR7_SIZE, 0, 0},
325 {R_02809C_CB_COLOR7_VIEW, 0, 0},
326 {R_0280FC_CB_COLOR7_FRAG, REG_FLAG_NEED_BO, 0},
327 {R_0280DC_CB_COLOR7_TILE, REG_FLAG_NEED_BO, 0},
328 {R_028120_CB_CLEAR_RED, 0, 0},
329 {R_028124_CB_CLEAR_GREEN, 0, 0},
330 {R_028128_CB_CLEAR_BLUE, 0, 0},
331 {R_02812C_CB_CLEAR_ALPHA, 0, 0},
332 {R_028414_CB_BLEND_RED, 0, 0},
333 {R_028418_CB_BLEND_GREEN, 0, 0},
334 {R_02841C_CB_BLEND_BLUE, 0, 0},
335 {R_028420_CB_BLEND_ALPHA, 0, 0},
336 {R_028424_CB_FOG_RED, 0, 0},
337 {R_028428_CB_FOG_GREEN, 0, 0},
338 {R_02842C_CB_FOG_BLUE, 0, 0},
339 {R_028430_DB_STENCILREFMASK, 0, 0},
340 {R_028434_DB_STENCILREFMASK_BF, 0, 0},
341 {R_028780_CB_BLEND0_CONTROL, REG_FLAG_NOT_R600, 0},
342 {R_028784_CB_BLEND1_CONTROL, REG_FLAG_NOT_R600, 0},
343 {R_028788_CB_BLEND2_CONTROL, REG_FLAG_NOT_R600, 0},
344 {R_02878C_CB_BLEND3_CONTROL, REG_FLAG_NOT_R600, 0},
345 {R_028790_CB_BLEND4_CONTROL, REG_FLAG_NOT_R600, 0},
346 {R_028794_CB_BLEND5_CONTROL, REG_FLAG_NOT_R600, 0},
347 {R_028798_CB_BLEND6_CONTROL, REG_FLAG_NOT_R600, 0},
348 {R_02879C_CB_BLEND7_CONTROL, REG_FLAG_NOT_R600, 0},
349 {R_0287A0_CB_SHADER_CONTROL, 0, 0},
350 {R_028800_DB_DEPTH_CONTROL, 0, 0},
351 {R_028804_CB_BLEND_CONTROL, 0, 0},
352 {R_02880C_DB_SHADER_CONTROL, 0, 0},
353 {R_02800C_DB_DEPTH_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_DEPTH},
354 {R_028000_DB_DEPTH_SIZE, 0, 0},
355 {R_028004_DB_DEPTH_VIEW, 0, 0},
356 {GROUP_FORCE_NEW_BLOCK, 0, 0},
357 {R_028010_DB_DEPTH_INFO, REG_FLAG_NEED_BO, 0},
358 {R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0, 0},
359 {R_028D24_DB_HTILE_SURFACE, 0, 0},
360 {R_028D34_DB_PREFETCH_LIMIT, 0, 0},
361 {R_028D44_DB_ALPHA_TO_MASK, 0, 0},
362 {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
363 {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
364 {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0},
365 {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
366 {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0},
367 {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0},
368 {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0},
369 {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0},
370 {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0},
371 {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0},
372 {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0},
373 {R_028810_PA_CL_CLIP_CNTL, 0, 0},
374 {R_028814_PA_SU_SC_MODE_CNTL, 0, 0},
375 {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0},
376 {R_028A00_PA_SU_POINT_SIZE, 0, 0},
377 {R_028A04_PA_SU_POINT_MINMAX, 0, 0},
378 {R_028A08_PA_SU_LINE_CNTL, 0, 0},
379 {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0},
380 {R_028C08_PA_SU_VTX_CNTL, 0, 0},
381 {R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0},
382 {R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0},
383 {R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0},
384 {R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0},
385 {R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0},
386 {R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0},
387 {R_028E20_PA_CL_UCP0_X, 0, 0},
388 {R_028E24_PA_CL_UCP0_Y, 0, 0},
389 {R_028E28_PA_CL_UCP0_Z, 0, 0},
390 {R_028E2C_PA_CL_UCP0_W, 0, 0},
391 {R_028E30_PA_CL_UCP1_X, 0, 0},
392 {R_028E34_PA_CL_UCP1_Y, 0, 0},
393 {R_028E38_PA_CL_UCP1_Z, 0, 0},
394 {R_028E3C_PA_CL_UCP1_W, 0, 0},
395 {R_028E40_PA_CL_UCP2_X, 0, 0},
396 {R_028E44_PA_CL_UCP2_Y, 0, 0},
397 {R_028E48_PA_CL_UCP2_Z, 0, 0},
398 {R_028E4C_PA_CL_UCP2_W, 0, 0},
399 {R_028E50_PA_CL_UCP3_X, 0, 0},
400 {R_028E54_PA_CL_UCP3_Y, 0, 0},
401 {R_028E58_PA_CL_UCP3_Z, 0, 0},
402 {R_028E5C_PA_CL_UCP3_W, 0, 0},
403 {R_028E60_PA_CL_UCP4_X, 0, 0},
404 {R_028E64_PA_CL_UCP4_Y, 0, 0},
405 {R_028E68_PA_CL_UCP4_Z, 0, 0},
406 {R_028E6C_PA_CL_UCP4_W, 0, 0},
407 {R_028E70_PA_CL_UCP5_X, 0, 0},
408 {R_028E74_PA_CL_UCP5_Y, 0, 0},
409 {R_028E78_PA_CL_UCP5_Z, 0, 0},
410 {R_028E7C_PA_CL_UCP5_W, 0, 0},
411 {R_028350_SX_MISC, 0, 0},
412 {R_028380_SQ_VTX_SEMANTIC_0, 0, 0},
413 {R_028384_SQ_VTX_SEMANTIC_1, 0, 0},
414 {R_028388_SQ_VTX_SEMANTIC_2, 0, 0},
415 {R_02838C_SQ_VTX_SEMANTIC_3, 0, 0},
416 {R_028390_SQ_VTX_SEMANTIC_4, 0, 0},
417 {R_028394_SQ_VTX_SEMANTIC_5, 0, 0},
418 {R_028398_SQ_VTX_SEMANTIC_6, 0, 0},
419 {R_02839C_SQ_VTX_SEMANTIC_7, 0, 0},
420 {R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0},
421 {R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0},
422 {R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0},
423 {R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0},
424 {R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0},
425 {R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0},
426 {R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0},
427 {R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0},
428 {R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0},
429 {R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0},
430 {R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0},
431 {R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0},
432 {R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0},
433 {R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0},
434 {R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0},
435 {R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0},
436 {R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0},
437 {R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0},
438 {R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0},
439 {R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0},
440 {R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0},
441 {R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0},
442 {R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0},
443 {R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0},
444 {R_028614_SPI_VS_OUT_ID_0, 0, 0},
445 {R_028618_SPI_VS_OUT_ID_1, 0, 0},
446 {R_02861C_SPI_VS_OUT_ID_2, 0, 0},
447 {R_028620_SPI_VS_OUT_ID_3, 0, 0},
448 {R_028624_SPI_VS_OUT_ID_4, 0, 0},
449 {R_028628_SPI_VS_OUT_ID_5, 0, 0},
450 {R_02862C_SPI_VS_OUT_ID_6, 0, 0},
451 {R_028630_SPI_VS_OUT_ID_7, 0, 0},
452 {R_028634_SPI_VS_OUT_ID_8, 0, 0},
453 {R_028638_SPI_VS_OUT_ID_9, 0, 0},
454 {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0},
455 {GROUP_FORCE_NEW_BLOCK, 0, 0},
456 {R_028858_SQ_PGM_START_VS, REG_FLAG_NEED_BO, 0},
457 {GROUP_FORCE_NEW_BLOCK, 0, 0},
458 {R_028868_SQ_PGM_RESOURCES_VS, 0, 0},
459 {GROUP_FORCE_NEW_BLOCK, 0, 0},
460 {R_028894_SQ_PGM_START_FS, REG_FLAG_NEED_BO, 0},
461 {GROUP_FORCE_NEW_BLOCK, 0, 0},
462 {R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0},
463 {R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0},
464 {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0},
465 {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0},
466 {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0},
467 {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0},
468 {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0},
469 {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0},
470 {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0},
471 {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0},
472 {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0},
473 {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0},
474 {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0},
475 {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0},
476 {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0},
477 {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0},
478 {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0},
479 {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0},
480 {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0},
481 {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0},
482 {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0},
483 {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0},
484 {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0},
485 {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0},
486 {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0},
487 {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0},
488 {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0},
489 {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0},
490 {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0},
491 {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0},
492 {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0},
493 {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0},
494 {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0},
495 {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0},
496 {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0},
497 {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0},
498 {R_0286D8_SPI_INPUT_Z, 0, 0},
499 {GROUP_FORCE_NEW_BLOCK, 0, 0},
500 {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0},
501 {GROUP_FORCE_NEW_BLOCK, 0, 0},
502 {R_028850_SQ_PGM_RESOURCES_PS, 0, 0},
503 {R_028854_SQ_PGM_EXPORTS_PS, 0, 0},
504 {R_028408_VGT_INDX_OFFSET, 0, 0},
505 {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0},
506 {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0},
507 };
508
509 static int r600_loop_const_init(struct r600_context *ctx, uint32_t offset)
510 {
511 unsigned nreg = 32;
512 struct r600_reg r600_loop_consts[32];
513 int i;
514
515 for (i = 0; i < nreg; i++) {
516 r600_loop_consts[i].offset = R600_LOOP_CONST_OFFSET + ((offset + i) * 4);
517 r600_loop_consts[i].flags = REG_FLAG_DIRTY_ALWAYS;
518 r600_loop_consts[i].sbu_flags = 0;
519 }
520 return r600_context_add_block(ctx, r600_loop_consts, nreg, PKT3_SET_LOOP_CONST, R600_LOOP_CONST_OFFSET);
521 }
522
523 /* initialize */
524 void r600_context_fini(struct r600_context *ctx)
525 {
526 struct r600_block *block;
527 struct r600_range *range;
528
529 if (ctx->range) {
530 for (int i = 0; i < NUM_RANGES; i++) {
531 if (!ctx->range[i].blocks)
532 continue;
533 for (int j = 0; j < (1 << HASH_SHIFT); j++) {
534 block = ctx->range[i].blocks[j];
535 if (block) {
536 for (int k = 0, offset = block->start_offset; k < block->nreg; k++, offset += 4) {
537 range = &ctx->range[CTX_RANGE_ID(offset)];
538 range->blocks[CTX_BLOCK_ID(offset)] = NULL;
539 }
540 for (int k = 1; k <= block->nbo; k++) {
541 pipe_resource_reference((struct pipe_resource**)&block->reloc[k].bo, NULL);
542 }
543 free(block);
544 }
545 }
546 free(ctx->range[i].blocks);
547 }
548 }
549 free(ctx->blocks);
550 }
551
552 int r600_setup_block_table(struct r600_context *ctx)
553 {
554 /* setup block table */
555 int c = 0;
556 ctx->blocks = calloc(ctx->nblocks, sizeof(void*));
557 if (!ctx->blocks)
558 return -ENOMEM;
559 for (int i = 0; i < NUM_RANGES; i++) {
560 if (!ctx->range[i].blocks)
561 continue;
562 for (int j = 0, add; j < (1 << HASH_SHIFT); j++) {
563 if (!ctx->range[i].blocks[j])
564 continue;
565
566 add = 1;
567 for (int k = 0; k < c; k++) {
568 if (ctx->blocks[k] == ctx->range[i].blocks[j]) {
569 add = 0;
570 break;
571 }
572 }
573 if (add) {
574 assert(c < ctx->nblocks);
575 ctx->blocks[c++] = ctx->range[i].blocks[j];
576 j += (ctx->range[i].blocks[j]->nreg) - 1;
577 }
578 }
579 }
580 return 0;
581 }
582
583 int r600_context_init(struct r600_context *ctx)
584 {
585 int r;
586
587 /* add blocks */
588 r = r600_context_add_block(ctx, r600_config_reg_list,
589 Elements(r600_config_reg_list), PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET);
590 if (r)
591 goto out_err;
592 r = r600_context_add_block(ctx, r600_context_reg_list,
593 Elements(r600_context_reg_list), PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET);
594 if (r)
595 goto out_err;
596 r = r600_context_add_block(ctx, r600_ctl_const_list,
597 Elements(r600_ctl_const_list), PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET);
598 if (r)
599 goto out_err;
600
601 /* PS loop const */
602 r600_loop_const_init(ctx, 0);
603 /* VS loop const */
604 r600_loop_const_init(ctx, 32);
605
606 r = r600_setup_block_table(ctx);
607 if (r)
608 goto out_err;
609
610 ctx->max_db = 4;
611 return 0;
612 out_err:
613 r600_context_fini(ctx);
614 return r;
615 }
616
617 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
618 boolean count_draw_in)
619 {
620 struct r600_atom *state;
621
622 /* The number of dwords we already used in the CS so far. */
623 num_dw += ctx->cs->cdw;
624
625 if (count_draw_in) {
626 /* The number of dwords all the dirty states would take. */
627 LIST_FOR_EACH_ENTRY(state, &ctx->dirty_states, head) {
628 num_dw += state->num_dw;
629 }
630
631 num_dw += ctx->pm4_dirty_cdwords;
632
633 /* The upper-bound of how much a draw command would take. */
634 num_dw += R600_MAX_DRAW_CS_DWORDS;
635 }
636
637 /* Count in queries_suspend. */
638 num_dw += ctx->num_cs_dw_nontimer_queries_suspend;
639 num_dw += ctx->num_cs_dw_timer_queries_suspend;
640
641 /* Count in streamout_end at the end of CS. */
642 num_dw += ctx->num_cs_dw_streamout_end;
643
644 /* Count in render_condition(NULL) at the end of CS. */
645 if (ctx->predicate_drawing) {
646 num_dw += 3;
647 }
648
649 /* Count in framebuffer cache flushes at the end of CS. */
650 num_dw += 7; /* one SURFACE_SYNC and CACHE_FLUSH_AND_INV (r6xx-only) */
651
652 /* Save 16 dwords for the fence mechanism. */
653 num_dw += 16;
654
655 /* Flush if there's not enough space. */
656 if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
657 r600_flush(&ctx->context, NULL, RADEON_FLUSH_ASYNC);
658 }
659 }
660
661 void r600_context_dirty_block(struct r600_context *ctx,
662 struct r600_block *block,
663 int dirty, int index)
664 {
665 if ((index + 1) > block->nreg_dirty)
666 block->nreg_dirty = index + 1;
667
668 if ((dirty != (block->status & R600_BLOCK_STATUS_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) {
669 block->status |= R600_BLOCK_STATUS_DIRTY;
670 ctx->pm4_dirty_cdwords += block->pm4_ndwords;
671 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
672 block->status |= R600_BLOCK_STATUS_ENABLED;
673 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
674 }
675 LIST_ADDTAIL(&block->list,&ctx->dirty);
676
677 if (block->flags & REG_FLAG_FLUSH_CHANGE) {
678 r600_context_ps_partial_flush(ctx);
679 }
680 }
681 }
682
683 /**
684 * If reg needs a reloc, this function will add it to its block's reloc list.
685 * @return true if reg needs a reloc, false otherwise
686 */
687 static bool r600_reg_set_block_reloc(struct r600_pipe_reg *reg)
688 {
689 unsigned reloc_id;
690
691 if (!reg->block->pm4_bo_index[reg->id]) {
692 return false;
693 }
694 /* find relocation */
695 reloc_id = reg->block->pm4_bo_index[reg->id];
696 pipe_resource_reference(
697 (struct pipe_resource**)&reg->block->reloc[reloc_id].bo,
698 &reg->bo->b.b);
699 reg->block->reloc[reloc_id].bo_usage = reg->bo_usage;
700 return true;
701 }
702
703 /**
704 * This function will emit all the registers in state directly to the command
705 * stream allowing you to bypass the r600_context dirty list.
706 *
707 * This is used for dispatching compute shaders to avoid mixing compute and
708 * 3D states in the context's dirty list.
709 *
710 * @param pkt_flags Should be either 0 or RADEON_CP_PACKET3_COMPUTE_MODE. This
711 * value will be passed on to r600_context_block_emit_dirty an or'd against
712 * the PKT3 headers.
713 */
714 void r600_context_pipe_state_emit(struct r600_context *ctx,
715 struct r600_pipe_state *state,
716 unsigned pkt_flags)
717 {
718 unsigned i;
719
720 /* Mark all blocks as dirty:
721 * Since two registers can be in the same block, we need to make sure
722 * we mark all the blocks dirty before we emit any of them. If we were
723 * to mark blocks dirty and emit them in the same loop, like this:
724 *
725 * foreach (reg in state->regs) {
726 * mark_dirty(reg->block)
727 * emit_block(reg->block)
728 * }
729 *
730 * Then if we have two registers in this state that are in the same
731 * block, we would end up emitting that block twice.
732 */
733 for (i = 0; i < state->nregs; i++) {
734 struct r600_pipe_reg *reg = &state->regs[i];
735 /* Mark all the registers in the block as dirty */
736 reg->block->nreg_dirty = reg->block->nreg;
737 reg->block->status |= R600_BLOCK_STATUS_DIRTY;
738 /* Update the reloc for this register if necessary. */
739 r600_reg_set_block_reloc(reg);
740 }
741
742 /* Emit the registers writes */
743 for (i = 0; i < state->nregs; i++) {
744 struct r600_pipe_reg *reg = &state->regs[i];
745 if (reg->block->status & R600_BLOCK_STATUS_DIRTY) {
746 r600_context_block_emit_dirty(ctx, reg->block, pkt_flags);
747 }
748 }
749 }
750
751 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state)
752 {
753 struct r600_block *block;
754 int dirty;
755 for (int i = 0; i < state->nregs; i++) {
756 unsigned id;
757 struct r600_pipe_reg *reg = &state->regs[i];
758
759 block = reg->block;
760 id = reg->id;
761
762 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
763
764 if (reg->value != block->reg[id]) {
765 block->reg[id] = reg->value;
766 dirty |= R600_BLOCK_STATUS_DIRTY;
767 }
768 if (block->flags & REG_FLAG_DIRTY_ALWAYS)
769 dirty |= R600_BLOCK_STATUS_DIRTY;
770 if (r600_reg_set_block_reloc(reg)) {
771 /* always force dirty for relocs for now */
772 dirty |= R600_BLOCK_STATUS_DIRTY;
773 }
774
775 if (dirty)
776 r600_context_dirty_block(ctx, block, dirty, id);
777 }
778 }
779
780 /**
781 * @param pkt_flags should be set to RADEON_CP_PACKET3_COMPUTE_MODE if this
782 * block will be used for compute shaders.
783 */
784 void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block,
785 unsigned pkt_flags)
786 {
787 struct radeon_winsys_cs *cs = ctx->cs;
788 int optional = block->nbo == 0 && !(block->flags & REG_FLAG_DIRTY_ALWAYS);
789 int cp_dwords = block->pm4_ndwords, start_dword = 0;
790 int new_dwords = 0;
791 int nbo = block->nbo;
792
793 if (block->nreg_dirty == 0 && optional) {
794 goto out;
795 }
796
797 if (nbo) {
798 for (int j = 0; j < block->nreg; j++) {
799 if (block->pm4_bo_index[j]) {
800 /* find relocation */
801 struct r600_block_reloc *reloc = &block->reloc[block->pm4_bo_index[j]];
802 if (reloc->bo) {
803 block->pm4[reloc->bo_pm4_index] =
804 r600_context_bo_reloc(ctx, reloc->bo, reloc->bo_usage);
805 } else {
806 block->pm4[reloc->bo_pm4_index] = 0;
807 }
808 nbo--;
809 if (nbo == 0)
810 break;
811
812 }
813 }
814 }
815
816 optional &= (block->nreg_dirty != block->nreg);
817 if (optional) {
818 new_dwords = block->nreg_dirty;
819 start_dword = cs->cdw;
820 cp_dwords = new_dwords + 2;
821 }
822 memcpy(&cs->buf[cs->cdw], block->pm4, cp_dwords * 4);
823
824 /* We are applying the pkt_flags after copying the register block to
825 * the the command stream, because it is possible this block will be
826 * emitted with a different pkt_flags, and we don't want to store the
827 * pkt_flags in the block.
828 */
829 cs->buf[cs->cdw] |= pkt_flags;
830 cs->cdw += cp_dwords;
831
832 if (optional) {
833 uint32_t newword;
834
835 newword = cs->buf[start_dword];
836 newword &= PKT_COUNT_C;
837 newword |= PKT_COUNT_S(new_dwords);
838 cs->buf[start_dword] = newword;
839 }
840 out:
841 block->status ^= R600_BLOCK_STATUS_DIRTY;
842 block->nreg_dirty = 0;
843 LIST_DELINIT(&block->list);
844 }
845
846 void r600_inval_shader_cache(struct r600_context *ctx)
847 {
848 ctx->surface_sync_cmd.flush_flags |= S_0085F0_SH_ACTION_ENA(1);
849 r600_atom_dirty(ctx, &ctx->surface_sync_cmd.atom);
850 }
851
852 void r600_inval_texture_cache(struct r600_context *ctx)
853 {
854 ctx->surface_sync_cmd.flush_flags |= S_0085F0_TC_ACTION_ENA(1);
855 r600_atom_dirty(ctx, &ctx->surface_sync_cmd.atom);
856 }
857
858 void r600_inval_vertex_cache(struct r600_context *ctx)
859 {
860 if (ctx->has_vertex_cache) {
861 ctx->surface_sync_cmd.flush_flags |= S_0085F0_VC_ACTION_ENA(1);
862 } else {
863 /* Some GPUs don't have the vertex cache and must use the texture cache instead. */
864 ctx->surface_sync_cmd.flush_flags |= S_0085F0_TC_ACTION_ENA(1);
865 }
866 r600_atom_dirty(ctx, &ctx->surface_sync_cmd.atom);
867 }
868
869 void r600_flush_framebuffer(struct r600_context *ctx, bool flush_now)
870 {
871 if (!(ctx->flags & R600_CONTEXT_DST_CACHES_DIRTY))
872 return;
873
874 ctx->surface_sync_cmd.flush_flags |=
875 r600_get_cb_flush_flags(ctx) |
876 (ctx->framebuffer.zsbuf ? S_0085F0_DB_ACTION_ENA(1) | S_0085F0_DB_DEST_BASE_ENA(1) : 0);
877
878 if (flush_now) {
879 r600_emit_atom(ctx, &ctx->surface_sync_cmd.atom);
880 } else {
881 r600_atom_dirty(ctx, &ctx->surface_sync_cmd.atom);
882 }
883
884 /* Also add a complete cache flush to work around broken flushing on R6xx. */
885 if (ctx->chip_class == R600) {
886 if (flush_now) {
887 r600_emit_atom(ctx, &ctx->r6xx_flush_and_inv_cmd);
888 } else {
889 r600_atom_dirty(ctx, &ctx->r6xx_flush_and_inv_cmd);
890 }
891 }
892
893 ctx->flags &= ~R600_CONTEXT_DST_CACHES_DIRTY;
894 }
895
896 void r600_context_flush(struct r600_context *ctx, unsigned flags)
897 {
898 struct radeon_winsys_cs *cs = ctx->cs;
899 struct r600_block *enable_block = NULL;
900 bool timer_queries_suspended = false;
901 bool nontimer_queries_suspended = false;
902 bool streamout_suspended = false;
903
904 if (cs->cdw == ctx->start_cs_cmd.atom.num_dw)
905 return;
906
907 /* suspend queries */
908 if (ctx->num_cs_dw_timer_queries_suspend) {
909 r600_suspend_timer_queries(ctx);
910 timer_queries_suspended = true;
911 }
912 if (ctx->num_cs_dw_nontimer_queries_suspend) {
913 r600_suspend_nontimer_queries(ctx);
914 nontimer_queries_suspended = true;
915 }
916
917 if (ctx->num_cs_dw_streamout_end) {
918 r600_context_streamout_end(ctx);
919 streamout_suspended = true;
920 }
921
922 r600_flush_framebuffer(ctx, true);
923
924 /* partial flush is needed to avoid lockups on some chips with user fences */
925 r600_context_ps_partial_flush(ctx);
926
927 /* old kernels and userspace don't set SX_MISC, so we must reset it to 0 here */
928 if (ctx->chip_class <= R700) {
929 r600_write_context_reg(cs, R_028350_SX_MISC, 0);
930 }
931
932 /* force to keep tiling flags */
933 flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
934
935 /* Flush the CS. */
936 ctx->ws->cs_flush(ctx->cs, flags);
937
938 ctx->pm4_dirty_cdwords = 0;
939 ctx->flags = 0;
940
941 /* Begin a new CS. */
942 r600_emit_atom(ctx, &ctx->start_cs_cmd.atom);
943
944 /* Invalidate caches. */
945 r600_inval_texture_cache(ctx);
946 r600_flush_framebuffer(ctx, false);
947
948 /* Re-emit states. */
949 r600_atom_dirty(ctx, &ctx->alphatest_state.atom);
950 r600_atom_dirty(ctx, &ctx->cb_misc_state.atom);
951 r600_atom_dirty(ctx, &ctx->db_misc_state.atom);
952 /* reemit sampler, will only matter if atom_sampler.num_dw != 0 */
953 r600_atom_dirty(ctx, &ctx->vs_samplers.atom_sampler);
954 r600_atom_dirty(ctx, &ctx->ps_samplers.atom_sampler);
955 if (ctx->chip_class <= R700) {
956 r600_atom_dirty(ctx, &ctx->seamless_cube_map.atom);
957 }
958 r600_atom_dirty(ctx, &ctx->sample_mask.atom);
959
960 ctx->vertex_buffer_state.dirty_mask = ctx->vertex_buffer_state.enabled_mask;
961 r600_vertex_buffers_dirty(ctx);
962
963 ctx->vs_constbuf_state.dirty_mask = ctx->vs_constbuf_state.enabled_mask;
964 ctx->ps_constbuf_state.dirty_mask = ctx->ps_constbuf_state.enabled_mask;
965 r600_constant_buffers_dirty(ctx, &ctx->vs_constbuf_state);
966 r600_constant_buffers_dirty(ctx, &ctx->ps_constbuf_state);
967
968 ctx->vs_samplers.views.dirty_mask = ctx->vs_samplers.views.enabled_mask;
969 ctx->ps_samplers.views.dirty_mask = ctx->ps_samplers.views.enabled_mask;
970 r600_sampler_views_dirty(ctx, &ctx->vs_samplers.views);
971 r600_sampler_views_dirty(ctx, &ctx->ps_samplers.views);
972
973 if (streamout_suspended) {
974 ctx->streamout_start = TRUE;
975 ctx->streamout_append_bitmask = ~0;
976 }
977
978 /* resume queries */
979 if (timer_queries_suspended) {
980 r600_resume_timer_queries(ctx);
981 }
982 if (nontimer_queries_suspended) {
983 r600_resume_nontimer_queries(ctx);
984 }
985
986 /* set all valid group as dirty so they get reemited on
987 * next draw command
988 */
989 LIST_FOR_EACH_ENTRY(enable_block, &ctx->enable_list, enable_list) {
990 if(!(enable_block->status & R600_BLOCK_STATUS_DIRTY)) {
991 LIST_ADDTAIL(&enable_block->list,&ctx->dirty);
992 enable_block->status |= R600_BLOCK_STATUS_DIRTY;
993 }
994 ctx->pm4_dirty_cdwords += enable_block->pm4_ndwords;
995 enable_block->nreg_dirty = enable_block->nreg;
996 }
997 }
998
999 void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence_bo, unsigned offset, unsigned value)
1000 {
1001 struct radeon_winsys_cs *cs = ctx->cs;
1002 uint64_t va;
1003
1004 r600_need_cs_space(ctx, 10, FALSE);
1005
1006 va = r600_resource_va(&ctx->screen->screen, (void*)fence_bo);
1007 va = va + (offset << 2);
1008
1009 r600_context_ps_partial_flush(ctx);
1010 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1011 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1012 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* ADDRESS_LO */
1013 /* DATA_SEL | INT_EN | ADDRESS_HI */
1014 cs->buf[cs->cdw++] = (1 << 29) | (0 << 24) | ((va >> 32UL) & 0xFF);
1015 cs->buf[cs->cdw++] = value; /* DATA_LO */
1016 cs->buf[cs->cdw++] = 0; /* DATA_HI */
1017 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1018 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, fence_bo, RADEON_USAGE_WRITE);
1019 }
1020
1021 static void r600_flush_vgt_streamout(struct r600_context *ctx)
1022 {
1023 struct radeon_winsys_cs *cs = ctx->cs;
1024
1025 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, 1, 0);
1026 cs->buf[cs->cdw++] = (R_008490_CP_STRMOUT_CNTL - R600_CONFIG_REG_OFFSET) >> 2;
1027 cs->buf[cs->cdw++] = 0;
1028
1029 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
1030 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0);
1031
1032 cs->buf[cs->cdw++] = PKT3(PKT3_WAIT_REG_MEM, 5, 0);
1033 cs->buf[cs->cdw++] = WAIT_REG_MEM_EQUAL; /* wait until the register is equal to the reference value */
1034 cs->buf[cs->cdw++] = R_008490_CP_STRMOUT_CNTL >> 2; /* register */
1035 cs->buf[cs->cdw++] = 0;
1036 cs->buf[cs->cdw++] = S_008490_OFFSET_UPDATE_DONE(1); /* reference value */
1037 cs->buf[cs->cdw++] = S_008490_OFFSET_UPDATE_DONE(1); /* mask */
1038 cs->buf[cs->cdw++] = 4; /* poll interval */
1039 }
1040
1041 static void r600_set_streamout_enable(struct r600_context *ctx, unsigned buffer_enable_bit)
1042 {
1043 struct radeon_winsys_cs *cs = ctx->cs;
1044
1045 if (buffer_enable_bit) {
1046 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
1047 cs->buf[cs->cdw++] = (R_028AB0_VGT_STRMOUT_EN - R600_CONTEXT_REG_OFFSET) >> 2;
1048 cs->buf[cs->cdw++] = S_028AB0_STREAMOUT(1);
1049
1050 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
1051 cs->buf[cs->cdw++] = (R_028B20_VGT_STRMOUT_BUFFER_EN - R600_CONTEXT_REG_OFFSET) >> 2;
1052 cs->buf[cs->cdw++] = buffer_enable_bit;
1053 } else {
1054 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
1055 cs->buf[cs->cdw++] = (R_028AB0_VGT_STRMOUT_EN - R600_CONTEXT_REG_OFFSET) >> 2;
1056 cs->buf[cs->cdw++] = S_028AB0_STREAMOUT(0);
1057 }
1058 }
1059
1060 void r600_context_streamout_begin(struct r600_context *ctx)
1061 {
1062 struct radeon_winsys_cs *cs = ctx->cs;
1063 struct r600_so_target **t = ctx->so_targets;
1064 unsigned *stride_in_dw = ctx->vs_shader->so.stride;
1065 unsigned buffer_en, i, update_flags = 0;
1066 uint64_t va;
1067
1068 buffer_en = (ctx->num_so_targets >= 1 && t[0] ? 1 : 0) |
1069 (ctx->num_so_targets >= 2 && t[1] ? 2 : 0) |
1070 (ctx->num_so_targets >= 3 && t[2] ? 4 : 0) |
1071 (ctx->num_so_targets >= 4 && t[3] ? 8 : 0);
1072
1073 ctx->num_cs_dw_streamout_end =
1074 12 + /* flush_vgt_streamout */
1075 util_bitcount(buffer_en) * 8 + /* STRMOUT_BUFFER_UPDATE */
1076 3 /* set_streamout_enable(0) */;
1077
1078 r600_need_cs_space(ctx,
1079 12 + /* flush_vgt_streamout */
1080 6 + /* set_streamout_enable */
1081 util_bitcount(buffer_en) * 7 + /* SET_CONTEXT_REG */
1082 (ctx->chip_class == R700 ? util_bitcount(buffer_en) * 5 : 0) + /* STRMOUT_BASE_UPDATE */
1083 util_bitcount(buffer_en & ctx->streamout_append_bitmask) * 8 + /* STRMOUT_BUFFER_UPDATE */
1084 util_bitcount(buffer_en & ~ctx->streamout_append_bitmask) * 6 + /* STRMOUT_BUFFER_UPDATE */
1085 (ctx->family > CHIP_R600 && ctx->family < CHIP_RV770 ? 2 : 0) + /* SURFACE_BASE_UPDATE */
1086 ctx->num_cs_dw_streamout_end, TRUE);
1087
1088 if (ctx->chip_class >= EVERGREEN) {
1089 evergreen_flush_vgt_streamout(ctx);
1090 evergreen_set_streamout_enable(ctx, buffer_en);
1091 } else {
1092 r600_flush_vgt_streamout(ctx);
1093 r600_set_streamout_enable(ctx, buffer_en);
1094 }
1095
1096 for (i = 0; i < ctx->num_so_targets; i++) {
1097 if (t[i]) {
1098 t[i]->stride_in_dw = stride_in_dw[i];
1099 t[i]->so_index = i;
1100 va = r600_resource_va(&ctx->screen->screen,
1101 (void*)t[i]->b.buffer);
1102
1103 update_flags |= SURFACE_BASE_UPDATE_STRMOUT(i);
1104
1105 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 3, 0);
1106 cs->buf[cs->cdw++] = (R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 +
1107 16*i - R600_CONTEXT_REG_OFFSET) >> 2;
1108 cs->buf[cs->cdw++] = (t[i]->b.buffer_offset +
1109 t[i]->b.buffer_size) >> 2; /* BUFFER_SIZE (in DW) */
1110 cs->buf[cs->cdw++] = stride_in_dw[i]; /* VTX_STRIDE (in DW) */
1111 cs->buf[cs->cdw++] = va >> 8; /* BUFFER_BASE */
1112
1113 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1114 cs->buf[cs->cdw++] =
1115 r600_context_bo_reloc(ctx, r600_resource(t[i]->b.buffer),
1116 RADEON_USAGE_WRITE);
1117
1118 /* R7xx requires this packet after updating BUFFER_BASE.
1119 * Without this, R7xx locks up. */
1120 if (ctx->chip_class == R700) {
1121 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BASE_UPDATE, 1, 0);
1122 cs->buf[cs->cdw++] = i;
1123 cs->buf[cs->cdw++] = va >> 8;
1124
1125 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1126 cs->buf[cs->cdw++] =
1127 r600_context_bo_reloc(ctx, r600_resource(t[i]->b.buffer),
1128 RADEON_USAGE_WRITE);
1129 }
1130
1131 if (ctx->streamout_append_bitmask & (1 << i)) {
1132 va = r600_resource_va(&ctx->screen->screen,
1133 (void*)t[i]->filled_size);
1134 /* Append. */
1135 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
1136 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
1137 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM); /* control */
1138 cs->buf[cs->cdw++] = 0; /* unused */
1139 cs->buf[cs->cdw++] = 0; /* unused */
1140 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */
1141 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
1142
1143 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1144 cs->buf[cs->cdw++] =
1145 r600_context_bo_reloc(ctx, t[i]->filled_size,
1146 RADEON_USAGE_READ);
1147 } else {
1148 /* Start from the beginning. */
1149 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
1150 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
1151 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET); /* control */
1152 cs->buf[cs->cdw++] = 0; /* unused */
1153 cs->buf[cs->cdw++] = 0; /* unused */
1154 cs->buf[cs->cdw++] = t[i]->b.buffer_offset >> 2; /* buffer offset in DW */
1155 cs->buf[cs->cdw++] = 0; /* unused */
1156 }
1157 }
1158 }
1159
1160 if (ctx->family > CHIP_R600 && ctx->family < CHIP_RV770) {
1161 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0);
1162 cs->buf[cs->cdw++] = update_flags;
1163 }
1164 }
1165
1166 void r600_context_streamout_end(struct r600_context *ctx)
1167 {
1168 struct radeon_winsys_cs *cs = ctx->cs;
1169 struct r600_so_target **t = ctx->so_targets;
1170 unsigned i, flush_flags = 0;
1171 uint64_t va;
1172
1173 if (ctx->chip_class >= EVERGREEN) {
1174 evergreen_flush_vgt_streamout(ctx);
1175 } else {
1176 r600_flush_vgt_streamout(ctx);
1177 }
1178
1179 for (i = 0; i < ctx->num_so_targets; i++) {
1180 if (t[i]) {
1181 va = r600_resource_va(&ctx->screen->screen,
1182 (void*)t[i]->filled_size);
1183 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
1184 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
1185 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
1186 STRMOUT_STORE_BUFFER_FILLED_SIZE; /* control */
1187 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* dst address lo */
1188 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* dst address hi */
1189 cs->buf[cs->cdw++] = 0; /* unused */
1190 cs->buf[cs->cdw++] = 0; /* unused */
1191
1192 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1193 cs->buf[cs->cdw++] =
1194 r600_context_bo_reloc(ctx, t[i]->filled_size,
1195 RADEON_USAGE_WRITE);
1196
1197 flush_flags |= S_0085F0_SO0_DEST_BASE_ENA(1) << i;
1198 }
1199 }
1200
1201 if (ctx->chip_class >= EVERGREEN) {
1202 evergreen_set_streamout_enable(ctx, 0);
1203 } else {
1204 r600_set_streamout_enable(ctx, 0);
1205 }
1206
1207 /* This is needed to fix cache flushes on r600. */
1208 if (ctx->chip_class == R600) {
1209 if (ctx->family == CHIP_RV670 ||
1210 ctx->family == CHIP_RS780 ||
1211 ctx->family == CHIP_RS880) {
1212 flush_flags |= S_0085F0_DEST_BASE_0_ENA(1);
1213 }
1214
1215 r600_atom_dirty(ctx, &ctx->r6xx_flush_and_inv_cmd);
1216 }
1217
1218 /* Flush streamout caches. */
1219 ctx->surface_sync_cmd.flush_flags |=
1220 S_0085F0_SMX_ACTION_ENA(1) | flush_flags;
1221 r600_atom_dirty(ctx, &ctx->surface_sync_cmd.atom);
1222
1223 ctx->num_cs_dw_streamout_end = 0;
1224 }