projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
r600g: atomize scissor state
[mesa.git] / src / gallium / drivers / r600 / r600_hw_context.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include "r600_hw_context_priv.h"
27 #include "r600d.h"
28 #include "util/u_memory.h"
29 #include <errno.h>
30
31 /* Get backends mask */
32 void r600_get_backend_mask(struct r600_context *ctx)
33 {
34 struct radeon_winsys_cs *cs = ctx->cs;
35 struct r600_resource *buffer;
36 uint32_t *results;
37 unsigned num_backends = ctx->screen->info.r600_num_backends;
38 unsigned i, mask = 0;
39 uint64_t va;
40
41 /* if backend_map query is supported by the kernel */
42 if (ctx->screen->info.r600_backend_map_valid) {
43 unsigned num_tile_pipes = ctx->screen->info.r600_num_tile_pipes;
44 unsigned backend_map = ctx->screen->info.r600_backend_map;
45 unsigned item_width, item_mask;
46
47 if (ctx->chip_class >= EVERGREEN) {
48 item_width = 4;
49 item_mask = 0x7;
50 } else {
51 item_width = 2;
52 item_mask = 0x3;
53 }
54
55 while(num_tile_pipes--) {
56 i = backend_map & item_mask;
57 mask |= (1<<i);
58 backend_map >>= item_width;
59 }
60 if (mask != 0) {
61 ctx->backend_mask = mask;
62 return;
63 }
64 }
65
66 /* otherwise backup path for older kernels */
67
68 /* create buffer for event data */
69 buffer = (struct r600_resource*)
70 pipe_buffer_create(&ctx->screen->screen, PIPE_BIND_CUSTOM,
71 PIPE_USAGE_STAGING, ctx->max_db*16);
72 if (!buffer)
73 goto err;
74
75 va = r600_resource_va(&ctx->screen->screen, (void*)buffer);
76
77 /* initialize buffer with zeroes */
78 results = ctx->ws->buffer_map(buffer->cs_buf, ctx->cs, PIPE_TRANSFER_WRITE);
79 if (results) {
80 memset(results, 0, ctx->max_db * 4 * 4);
81 ctx->ws->buffer_unmap(buffer->cs_buf);
82
83 /* emit EVENT_WRITE for ZPASS_DONE */
84 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
85 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
86 cs->buf[cs->cdw++] = va;
87 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
88
89 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
90 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, buffer, RADEON_USAGE_WRITE);
91
92 /* analyze results */
93 results = ctx->ws->buffer_map(buffer->cs_buf, ctx->cs, PIPE_TRANSFER_READ);
94 if (results) {
95 for(i = 0; i < ctx->max_db; i++) {
96 /* at least highest bit will be set if backend is used */
97 if (results[i*4 + 1])
98 mask |= (1<<i);
99 }
100 ctx->ws->buffer_unmap(buffer->cs_buf);
101 }
102 }
103
104 pipe_resource_reference((struct pipe_resource**)&buffer, NULL);
105
106 if (mask != 0) {
107 ctx->backend_mask = mask;
108 return;
109 }
110
111 err:
112 /* fallback to old method - set num_backends lower bits to 1 */
113 ctx->backend_mask = (~((uint32_t)0))>>(32-num_backends);
114 return;
115 }
116
117 static void r600_init_block(struct r600_context *ctx,
118 struct r600_block *block,
119 const struct r600_reg *reg, int index, int nreg,
120 unsigned opcode, unsigned offset_base)
121 {
122 int i = index;
123 int j, n = nreg;
124
125 /* initialize block */
126 block->flags = 0;
127 block->status |= R600_BLOCK_STATUS_DIRTY; /* dirty all blocks at start */
128 block->start_offset = reg[i].offset;
129 block->pm4[block->pm4_ndwords++] = PKT3(opcode, n, 0);
130 block->pm4[block->pm4_ndwords++] = (block->start_offset - offset_base) >> 2;
131 block->reg = &block->pm4[block->pm4_ndwords];
132 block->pm4_ndwords += n;
133 block->nreg = n;
134 block->nreg_dirty = n;
135 LIST_INITHEAD(&block->list);
136 LIST_INITHEAD(&block->enable_list);
137
138 for (j = 0; j < n; j++) {
139 if (reg[i+j].flags & REG_FLAG_DIRTY_ALWAYS) {
140 block->flags |= REG_FLAG_DIRTY_ALWAYS;
141 }
142 if (reg[i+j].flags & REG_FLAG_ENABLE_ALWAYS) {
143 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
144 block->status |= R600_BLOCK_STATUS_ENABLED;
145 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
146 LIST_ADDTAIL(&block->list,&ctx->dirty);
147 }
148 }
149 if (reg[i+j].flags & REG_FLAG_FLUSH_CHANGE) {
150 block->flags |= REG_FLAG_FLUSH_CHANGE;
151 }
152
153 if (reg[i+j].flags & REG_FLAG_NEED_BO) {
154 block->nbo++;
155 assert(block->nbo < R600_BLOCK_MAX_BO);
156 block->pm4_bo_index[j] = block->nbo;
157 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0, 0);
158 block->pm4[block->pm4_ndwords++] = 0x00000000;
159 block->reloc[block->nbo].bo_pm4_index = block->pm4_ndwords - 1;
160 }
161 }
162 /* check that we stay in limit */
163 assert(block->pm4_ndwords < R600_BLOCK_MAX_REG);
164 }
165
166 int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg,
167 unsigned opcode, unsigned offset_base)
168 {
169 struct r600_block *block;
170 struct r600_range *range;
171 int offset;
172
173 for (unsigned i = 0, n = 0; i < nreg; i += n) {
174 /* ignore new block balise */
175 if (reg[i].offset == GROUP_FORCE_NEW_BLOCK) {
176 n = 1;
177 continue;
178 }
179
180 /* register that need relocation are in their own group */
181 /* find number of consecutive registers */
182 n = 0;
183 offset = reg[i].offset;
184 while (reg[i + n].offset == offset) {
185 n++;
186 offset += 4;
187 if ((n + i) >= nreg)
188 break;
189 if (n >= (R600_BLOCK_MAX_REG - 2))
190 break;
191 }
192
193 /* allocate new block */
194 block = calloc(1, sizeof(struct r600_block));
195 if (block == NULL) {
196 return -ENOMEM;
197 }
198 ctx->nblocks++;
199 for (int j = 0; j < n; j++) {
200 range = &ctx->range[CTX_RANGE_ID(reg[i + j].offset)];
201 /* create block table if it doesn't exist */
202 if (!range->blocks)
203 range->blocks = calloc(1 << HASH_SHIFT, sizeof(void *));
204 if (!range->blocks)
205 return -1;
206
207 range->blocks[CTX_BLOCK_ID(reg[i + j].offset)] = block;
208 }
209
210 r600_init_block(ctx, block, reg, i, n, opcode, offset_base);
211
212 }
213 return 0;
214 }
215
216 /* R600/R700 configuration */
217 static const struct r600_reg r600_config_reg_list[] = {
218 {R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
219 };
220
221 static const struct r600_reg r600_context_reg_list[] = {
222 {R_028A4C_PA_SC_MODE_CNTL, 0, 0},
223 {GROUP_FORCE_NEW_BLOCK, 0, 0},
224 {R_028800_DB_DEPTH_CONTROL, 0, 0},
225 {R_02880C_DB_SHADER_CONTROL, 0, 0},
226 {GROUP_FORCE_NEW_BLOCK, 0, 0},
227 {R_028D24_DB_HTILE_SURFACE, 0, 0},
228 {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0},
229 {R_028814_PA_SU_SC_MODE_CNTL, 0, 0},
230 {R_028A00_PA_SU_POINT_SIZE, 0, 0},
231 {R_028A04_PA_SU_POINT_MINMAX, 0, 0},
232 {R_028A08_PA_SU_LINE_CNTL, 0, 0},
233 {R_028C08_PA_SU_VTX_CNTL, 0, 0},
234 {R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0},
235 {R_028350_SX_MISC, 0, 0},
236 {R_028380_SQ_VTX_SEMANTIC_0, 0, 0},
237 {R_028384_SQ_VTX_SEMANTIC_1, 0, 0},
238 {R_028388_SQ_VTX_SEMANTIC_2, 0, 0},
239 {R_02838C_SQ_VTX_SEMANTIC_3, 0, 0},
240 {R_028390_SQ_VTX_SEMANTIC_4, 0, 0},
241 {R_028394_SQ_VTX_SEMANTIC_5, 0, 0},
242 {R_028398_SQ_VTX_SEMANTIC_6, 0, 0},
243 {R_02839C_SQ_VTX_SEMANTIC_7, 0, 0},
244 {R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0},
245 {R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0},
246 {R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0},
247 {R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0},
248 {R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0},
249 {R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0},
250 {R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0},
251 {R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0},
252 {R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0},
253 {R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0},
254 {R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0},
255 {R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0},
256 {R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0},
257 {R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0},
258 {R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0},
259 {R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0},
260 {R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0},
261 {R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0},
262 {R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0},
263 {R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0},
264 {R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0},
265 {R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0},
266 {R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0},
267 {R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0},
268 {R_028614_SPI_VS_OUT_ID_0, 0, 0},
269 {R_028618_SPI_VS_OUT_ID_1, 0, 0},
270 {R_02861C_SPI_VS_OUT_ID_2, 0, 0},
271 {R_028620_SPI_VS_OUT_ID_3, 0, 0},
272 {R_028624_SPI_VS_OUT_ID_4, 0, 0},
273 {R_028628_SPI_VS_OUT_ID_5, 0, 0},
274 {R_02862C_SPI_VS_OUT_ID_6, 0, 0},
275 {R_028630_SPI_VS_OUT_ID_7, 0, 0},
276 {R_028634_SPI_VS_OUT_ID_8, 0, 0},
277 {R_028638_SPI_VS_OUT_ID_9, 0, 0},
278 {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0},
279 {GROUP_FORCE_NEW_BLOCK, 0, 0},
280 {R_028858_SQ_PGM_START_VS, REG_FLAG_NEED_BO, 0},
281 {GROUP_FORCE_NEW_BLOCK, 0, 0},
282 {R_028868_SQ_PGM_RESOURCES_VS, 0, 0},
283 {GROUP_FORCE_NEW_BLOCK, 0, 0},
284 {R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0},
285 {R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0},
286 {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0},
287 {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0},
288 {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0},
289 {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0},
290 {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0},
291 {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0},
292 {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0},
293 {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0},
294 {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0},
295 {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0},
296 {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0},
297 {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0},
298 {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0},
299 {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0},
300 {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0},
301 {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0},
302 {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0},
303 {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0},
304 {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0},
305 {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0},
306 {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0},
307 {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0},
308 {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0},
309 {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0},
310 {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0},
311 {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0},
312 {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0},
313 {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0},
314 {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0},
315 {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0},
316 {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0},
317 {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0},
318 {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0},
319 {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0},
320 {R_0286D8_SPI_INPUT_Z, 0, 0},
321 {GROUP_FORCE_NEW_BLOCK, 0, 0},
322 {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0},
323 {GROUP_FORCE_NEW_BLOCK, 0, 0},
324 {R_028850_SQ_PGM_RESOURCES_PS, 0, 0},
325 {R_028854_SQ_PGM_EXPORTS_PS, 0, 0},
326 };
327
328 /* initialize */
329 void r600_context_fini(struct r600_context *ctx)
330 {
331 struct r600_block *block;
332 struct r600_range *range;
333
334 if (ctx->range) {
335 for (int i = 0; i < NUM_RANGES; i++) {
336 if (!ctx->range[i].blocks)
337 continue;
338 for (int j = 0; j < (1 << HASH_SHIFT); j++) {
339 block = ctx->range[i].blocks[j];
340 if (block) {
341 for (int k = 0, offset = block->start_offset; k < block->nreg; k++, offset += 4) {
342 range = &ctx->range[CTX_RANGE_ID(offset)];
343 range->blocks[CTX_BLOCK_ID(offset)] = NULL;
344 }
345 for (int k = 1; k <= block->nbo; k++) {
346 pipe_resource_reference((struct pipe_resource**)&block->reloc[k].bo, NULL);
347 }
348 free(block);
349 }
350 }
351 free(ctx->range[i].blocks);
352 }
353 }
354 free(ctx->blocks);
355 }
356
357 int r600_setup_block_table(struct r600_context *ctx)
358 {
359 /* setup block table */
360 int c = 0;
361 ctx->blocks = calloc(ctx->nblocks, sizeof(void*));
362 if (!ctx->blocks)
363 return -ENOMEM;
364 for (int i = 0; i < NUM_RANGES; i++) {
365 if (!ctx->range[i].blocks)
366 continue;
367 for (int j = 0, add; j < (1 << HASH_SHIFT); j++) {
368 if (!ctx->range[i].blocks[j])
369 continue;
370
371 add = 1;
372 for (int k = 0; k < c; k++) {
373 if (ctx->blocks[k] == ctx->range[i].blocks[j]) {
374 add = 0;
375 break;
376 }
377 }
378 if (add) {
379 assert(c < ctx->nblocks);
380 ctx->blocks[c++] = ctx->range[i].blocks[j];
381 j += (ctx->range[i].blocks[j]->nreg) - 1;
382 }
383 }
384 }
385 return 0;
386 }
387
388 int r600_context_init(struct r600_context *ctx)
389 {
390 int r;
391
392 /* add blocks */
393 r = r600_context_add_block(ctx, r600_config_reg_list,
394 Elements(r600_config_reg_list), PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET);
395 if (r)
396 goto out_err;
397 r = r600_context_add_block(ctx, r600_context_reg_list,
398 Elements(r600_context_reg_list), PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET);
399 if (r)
400 goto out_err;
401
402 r = r600_setup_block_table(ctx);
403 if (r)
404 goto out_err;
405
406 ctx->max_db = 4;
407 return 0;
408 out_err:
409 r600_context_fini(ctx);
410 return r;
411 }
412
413 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
414 boolean count_draw_in)
415 {
416 /* The number of dwords we already used in the CS so far. */
417 num_dw += ctx->cs->cdw;
418
419 if (count_draw_in) {
420 unsigned i;
421
422 /* The number of dwords all the dirty states would take. */
423 for (i = 0; i < R600_NUM_ATOMS; i++) {
424 if (ctx->atoms[i] && ctx->atoms[i]->dirty) {
425 num_dw += ctx->atoms[i]->num_dw;
426 }
427 }
428
429 num_dw += ctx->pm4_dirty_cdwords;
430
431 /* The upper-bound of how much space a draw command would take. */
432 num_dw += R600_MAX_FLUSH_CS_DWORDS + R600_MAX_DRAW_CS_DWORDS;
433 }
434
435 /* Count in queries_suspend. */
436 num_dw += ctx->num_cs_dw_nontimer_queries_suspend;
437 num_dw += ctx->num_cs_dw_timer_queries_suspend;
438
439 /* Count in streamout_end at the end of CS. */
440 num_dw += ctx->num_cs_dw_streamout_end;
441
442 /* Count in render_condition(NULL) at the end of CS. */
443 if (ctx->predicate_drawing) {
444 num_dw += 3;
445 }
446
447 /* SX_MISC */
448 if (ctx->chip_class <= R700) {
449 num_dw += 3;
450 }
451
452 /* Count in framebuffer cache flushes at the end of CS. */
453 num_dw += R600_MAX_FLUSH_CS_DWORDS;
454
455 /* The fence at the end of CS. */
456 num_dw += 10;
457
458 /* Flush if there's not enough space. */
459 if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
460 r600_flush(&ctx->context, NULL, RADEON_FLUSH_ASYNC);
461 }
462 }
463
464 void r600_context_dirty_block(struct r600_context *ctx,
465 struct r600_block *block,
466 int dirty, int index)
467 {
468 if ((index + 1) > block->nreg_dirty)
469 block->nreg_dirty = index + 1;
470
471 if ((dirty != (block->status & R600_BLOCK_STATUS_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) {
472 block->status |= R600_BLOCK_STATUS_DIRTY;
473 ctx->pm4_dirty_cdwords += block->pm4_ndwords;
474 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
475 block->status |= R600_BLOCK_STATUS_ENABLED;
476 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
477 }
478 LIST_ADDTAIL(&block->list,&ctx->dirty);
479
480 if (block->flags & REG_FLAG_FLUSH_CHANGE) {
481 ctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
482 }
483 }
484 }
485
486 /**
487 * If reg needs a reloc, this function will add it to its block's reloc list.
488 * @return true if reg needs a reloc, false otherwise
489 */
490 static bool r600_reg_set_block_reloc(struct r600_pipe_reg *reg)
491 {
492 unsigned reloc_id;
493
494 if (!reg->block->pm4_bo_index[reg->id]) {
495 return false;
496 }
497 /* find relocation */
498 reloc_id = reg->block->pm4_bo_index[reg->id];
499 pipe_resource_reference(
500 (struct pipe_resource**)&reg->block->reloc[reloc_id].bo,
501 &reg->bo->b.b);
502 reg->block->reloc[reloc_id].bo_usage = reg->bo_usage;
503 return true;
504 }
505
506 /**
507 * This function will emit all the registers in state directly to the command
508 * stream allowing you to bypass the r600_context dirty list.
509 *
510 * This is used for dispatching compute shaders to avoid mixing compute and
511 * 3D states in the context's dirty list.
512 *
513 * @param pkt_flags Should be either 0 or RADEON_CP_PACKET3_COMPUTE_MODE. This
514 * value will be passed on to r600_context_block_emit_dirty an or'd against
515 * the PKT3 headers.
516 */
517 void r600_context_pipe_state_emit(struct r600_context *ctx,
518 struct r600_pipe_state *state,
519 unsigned pkt_flags)
520 {
521 unsigned i;
522
523 /* Mark all blocks as dirty:
524 * Since two registers can be in the same block, we need to make sure
525 * we mark all the blocks dirty before we emit any of them. If we were
526 * to mark blocks dirty and emit them in the same loop, like this:
527 *
528 * foreach (reg in state->regs) {
529 * mark_dirty(reg->block)
530 * emit_block(reg->block)
531 * }
532 *
533 * Then if we have two registers in this state that are in the same
534 * block, we would end up emitting that block twice.
535 */
536 for (i = 0; i < state->nregs; i++) {
537 struct r600_pipe_reg *reg = &state->regs[i];
538 /* Mark all the registers in the block as dirty */
539 reg->block->nreg_dirty = reg->block->nreg;
540 reg->block->status |= R600_BLOCK_STATUS_DIRTY;
541 /* Update the reloc for this register if necessary. */
542 r600_reg_set_block_reloc(reg);
543 }
544
545 /* Emit the registers writes */
546 for (i = 0; i < state->nregs; i++) {
547 struct r600_pipe_reg *reg = &state->regs[i];
548 if (reg->block->status & R600_BLOCK_STATUS_DIRTY) {
549 r600_context_block_emit_dirty(ctx, reg->block, pkt_flags);
550 }
551 }
552 }
553
554 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state)
555 {
556 struct r600_block *block;
557 int dirty;
558 for (int i = 0; i < state->nregs; i++) {
559 unsigned id;
560 struct r600_pipe_reg *reg = &state->regs[i];
561
562 block = reg->block;
563 id = reg->id;
564
565 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
566
567 if (reg->value != block->reg[id]) {
568 block->reg[id] = reg->value;
569 dirty |= R600_BLOCK_STATUS_DIRTY;
570 }
571 if (block->flags & REG_FLAG_DIRTY_ALWAYS)
572 dirty |= R600_BLOCK_STATUS_DIRTY;
573 if (r600_reg_set_block_reloc(reg)) {
574 /* always force dirty for relocs for now */
575 dirty |= R600_BLOCK_STATUS_DIRTY;
576 }
577
578 if (dirty)
579 r600_context_dirty_block(ctx, block, dirty, id);
580 }
581 }
582
583 /**
584 * @param pkt_flags should be set to RADEON_CP_PACKET3_COMPUTE_MODE if this
585 * block will be used for compute shaders.
586 */
587 void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block,
588 unsigned pkt_flags)
589 {
590 struct radeon_winsys_cs *cs = ctx->cs;
591 int optional = block->nbo == 0 && !(block->flags & REG_FLAG_DIRTY_ALWAYS);
592 int cp_dwords = block->pm4_ndwords, start_dword = 0;
593 int new_dwords = 0;
594 int nbo = block->nbo;
595
596 if (block->nreg_dirty == 0 && optional) {
597 goto out;
598 }
599
600 if (nbo) {
601 for (int j = 0; j < block->nreg; j++) {
602 if (block->pm4_bo_index[j]) {
603 /* find relocation */
604 struct r600_block_reloc *reloc = &block->reloc[block->pm4_bo_index[j]];
605 if (reloc->bo) {
606 block->pm4[reloc->bo_pm4_index] =
607 r600_context_bo_reloc(ctx, reloc->bo, reloc->bo_usage);
608 } else {
609 block->pm4[reloc->bo_pm4_index] = 0;
610 }
611 nbo--;
612 if (nbo == 0)
613 break;
614
615 }
616 }
617 }
618
619 optional &= (block->nreg_dirty != block->nreg);
620 if (optional) {
621 new_dwords = block->nreg_dirty;
622 start_dword = cs->cdw;
623 cp_dwords = new_dwords + 2;
624 }
625 memcpy(&cs->buf[cs->cdw], block->pm4, cp_dwords * 4);
626
627 /* We are applying the pkt_flags after copying the register block to
628 * the the command stream, because it is possible this block will be
629 * emitted with a different pkt_flags, and we don't want to store the
630 * pkt_flags in the block.
631 */
632 cs->buf[cs->cdw] |= pkt_flags;
633 cs->cdw += cp_dwords;
634
635 if (optional) {
636 uint32_t newword;
637
638 newword = cs->buf[start_dword];
639 newword &= PKT_COUNT_C;
640 newword |= PKT_COUNT_S(new_dwords);
641 cs->buf[start_dword] = newword;
642 }
643 out:
644 block->status ^= R600_BLOCK_STATUS_DIRTY;
645 block->nreg_dirty = 0;
646 LIST_DELINIT(&block->list);
647 }
648
649 void r600_flush_emit(struct r600_context *rctx)
650 {
651 struct radeon_winsys_cs *cs = rctx->cs;
652
653 if (!rctx->flags) {
654 return;
655 }
656
657 if (rctx->flags & R600_CONTEXT_PS_PARTIAL_FLUSH) {
658 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
659 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
660 }
661
662 if (rctx->chip_class >= R700 &&
663 (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB_META)) {
664 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
665 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0);
666 }
667
668 if (rctx->flags & R600_CONTEXT_FLUSH_AND_INV) {
669 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
670 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
671
672 /* DB flushes are special due to errata with hyperz, we need to
673 * insert a no-op, so that the cache has time to really flush.
674 */
675 if (rctx->chip_class <= R700 &&
676 rctx->flags & R600_CONTEXT_HTILE_ERRATA) {
677 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 31, 0);
678 cs->buf[cs->cdw++] = 0xdeadcafe;
679 cs->buf[cs->cdw++] = 0xdeadcafe;
680 cs->buf[cs->cdw++] = 0xdeadcafe;
681 cs->buf[cs->cdw++] = 0xdeadcafe;
682 cs->buf[cs->cdw++] = 0xdeadcafe;
683 cs->buf[cs->cdw++] = 0xdeadcafe;
684 cs->buf[cs->cdw++] = 0xdeadcafe;
685 cs->buf[cs->cdw++] = 0xdeadcafe;
686 cs->buf[cs->cdw++] = 0xdeadcafe;
687 cs->buf[cs->cdw++] = 0xdeadcafe;
688 cs->buf[cs->cdw++] = 0xdeadcafe;
689 cs->buf[cs->cdw++] = 0xdeadcafe;
690 cs->buf[cs->cdw++] = 0xdeadcafe;
691 cs->buf[cs->cdw++] = 0xdeadcafe;
692 cs->buf[cs->cdw++] = 0xdeadcafe;
693 cs->buf[cs->cdw++] = 0xdeadcafe;
694 cs->buf[cs->cdw++] = 0xdeadcafe;
695 cs->buf[cs->cdw++] = 0xdeadcafe;
696 cs->buf[cs->cdw++] = 0xdeadcafe;
697 cs->buf[cs->cdw++] = 0xdeadcafe;
698 cs->buf[cs->cdw++] = 0xdeadcafe;
699 cs->buf[cs->cdw++] = 0xdeadcafe;
700 cs->buf[cs->cdw++] = 0xdeadcafe;
701 cs->buf[cs->cdw++] = 0xdeadcafe;
702 cs->buf[cs->cdw++] = 0xdeadcafe;
703 cs->buf[cs->cdw++] = 0xdeadcafe;
704 cs->buf[cs->cdw++] = 0xdeadcafe;
705 cs->buf[cs->cdw++] = 0xdeadcafe;
706 cs->buf[cs->cdw++] = 0xdeadcafe;
707 cs->buf[cs->cdw++] = 0xdeadcafe;
708 cs->buf[cs->cdw++] = 0xdeadcafe;
709 cs->buf[cs->cdw++] = 0xdeadcafe;
710 }
711 }
712
713 if (rctx->flags & (R600_CONTEXT_CB_FLUSH |
714 R600_CONTEXT_DB_FLUSH |
715 R600_CONTEXT_SHADERCONST_FLUSH |
716 R600_CONTEXT_TEX_FLUSH |
717 R600_CONTEXT_VTX_FLUSH |
718 R600_CONTEXT_STREAMOUT_FLUSH)) {
719 /* anything left (cb, vtx, shader, streamout) can be flushed
720 * using the surface sync packet
721 */
722 unsigned flags = 0;
723
724 if (rctx->flags & R600_CONTEXT_CB_FLUSH) {
725 flags |= S_0085F0_CB_ACTION_ENA(1) |
726 S_0085F0_CB0_DEST_BASE_ENA(1) |
727 S_0085F0_CB1_DEST_BASE_ENA(1) |
728 S_0085F0_CB2_DEST_BASE_ENA(1) |
729 S_0085F0_CB3_DEST_BASE_ENA(1) |
730 S_0085F0_CB4_DEST_BASE_ENA(1) |
731 S_0085F0_CB5_DEST_BASE_ENA(1) |
732 S_0085F0_CB6_DEST_BASE_ENA(1) |
733 S_0085F0_CB7_DEST_BASE_ENA(1);
734
735 if (rctx->chip_class >= EVERGREEN) {
736 flags |= S_0085F0_CB8_DEST_BASE_ENA(1) |
737 S_0085F0_CB9_DEST_BASE_ENA(1) |
738 S_0085F0_CB10_DEST_BASE_ENA(1) |
739 S_0085F0_CB11_DEST_BASE_ENA(1);
740 }
741
742 /* RV670 errata
743 * (CB1_DEST_BASE_ENA is also required, which is
744 * included unconditionally above). */
745 if (rctx->family == CHIP_RV670 ||
746 rctx->family == CHIP_RS780 ||
747 rctx->family == CHIP_RS880) {
748 flags |= S_0085F0_DEST_BASE_0_ENA(1);
749 }
750 }
751
752 if (rctx->flags & R600_CONTEXT_STREAMOUT_FLUSH) {
753 flags |= S_0085F0_SO0_DEST_BASE_ENA(1) |
754 S_0085F0_SO1_DEST_BASE_ENA(1) |
755 S_0085F0_SO2_DEST_BASE_ENA(1) |
756 S_0085F0_SO3_DEST_BASE_ENA(1) |
757 S_0085F0_SMX_ACTION_ENA(1);
758
759 /* RV670 errata */
760 if (rctx->family == CHIP_RV670 ||
761 rctx->family == CHIP_RS780 ||
762 rctx->family == CHIP_RS880) {
763 flags |= S_0085F0_DEST_BASE_0_ENA(1);
764 }
765 }
766
767 flags |= (rctx->flags & R600_CONTEXT_DB_FLUSH) ? S_0085F0_DB_ACTION_ENA(1) |
768 S_0085F0_DB_DEST_BASE_ENA(1): 0;
769 flags |= (rctx->flags & R600_CONTEXT_SHADERCONST_FLUSH) ? S_0085F0_SH_ACTION_ENA(1) : 0;
770 flags |= (rctx->flags & R600_CONTEXT_TEX_FLUSH) ? S_0085F0_TC_ACTION_ENA(1) : 0;
771 flags |= (rctx->flags & R600_CONTEXT_VTX_FLUSH) ? S_0085F0_VC_ACTION_ENA(1) : 0;
772
773 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
774 cs->buf[cs->cdw++] = flags; /* CP_COHER_CNTL */
775 cs->buf[cs->cdw++] = 0xffffffff; /* CP_COHER_SIZE */
776 cs->buf[cs->cdw++] = 0; /* CP_COHER_BASE */
777 cs->buf[cs->cdw++] = 0x0000000A; /* POLL_INTERVAL */
778 }
779
780 if (rctx->flags & R600_CONTEXT_WAIT_IDLE) {
781 /* wait for things to settle */
782 r600_write_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
783 }
784
785 /* everything is properly flushed */
786 rctx->flags = 0;
787 }
788
789 void r600_context_flush(struct r600_context *ctx, unsigned flags)
790 {
791 struct radeon_winsys_cs *cs = ctx->cs;
792
793 if (cs->cdw == ctx->start_cs_cmd.num_dw)
794 return;
795
796 ctx->timer_queries_suspended = false;
797 ctx->nontimer_queries_suspended = false;
798 ctx->streamout_suspended = false;
799
800 /* suspend queries */
801 if (ctx->num_cs_dw_timer_queries_suspend) {
802 r600_suspend_timer_queries(ctx);
803 ctx->timer_queries_suspended = true;
804 }
805 if (ctx->num_cs_dw_nontimer_queries_suspend) {
806 r600_suspend_nontimer_queries(ctx);
807 ctx->nontimer_queries_suspended = true;
808 }
809
810 if (ctx->num_cs_dw_streamout_end) {
811 r600_context_streamout_end(ctx);
812 ctx->streamout_suspended = true;
813 }
814
815 /* partial flush is needed to avoid lockups on some chips with user fences */
816 ctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
817
818 /* flush the framebuffer */
819 ctx->flags |= R600_CONTEXT_CB_FLUSH | R600_CONTEXT_DB_FLUSH;
820
821 /* R6xx errata */
822 if (ctx->chip_class == R600) {
823 ctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
824 }
825
826 r600_flush_emit(ctx);
827
828 /* old kernels and userspace don't set SX_MISC, so we must reset it to 0 here */
829 if (ctx->chip_class <= R700) {
830 r600_write_context_reg(cs, R_028350_SX_MISC, 0);
831 }
832
833 /* force to keep tiling flags */
834 if (ctx->keep_tiling_flags) {
835 flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
836 }
837
838 /* Flush the CS. */
839 ctx->ws->cs_flush(ctx->cs, flags);
840
841 r600_begin_new_cs(ctx);
842 }
843
844 void r600_begin_new_cs(struct r600_context *ctx)
845 {
846 struct r600_block *enable_block = NULL;
847 unsigned shader;
848
849 ctx->pm4_dirty_cdwords = 0;
850 ctx->flags = 0;
851
852 /* Begin a new CS. */
853 r600_emit_command_buffer(ctx->cs, &ctx->start_cs_cmd);
854
855 /* Re-emit states. */
856 ctx->alphatest_state.atom.dirty = true;
857 ctx->blend_color.atom.dirty = true;
858 ctx->cb_misc_state.atom.dirty = true;
859 ctx->clip_misc_state.atom.dirty = true;
860 ctx->clip_state.atom.dirty = true;
861 ctx->db_misc_state.atom.dirty = true;
862 ctx->framebuffer.atom.dirty = true;
863 ctx->poly_offset_state.atom.dirty = true;
864 ctx->vgt_state.atom.dirty = true;
865 ctx->vgt2_state.atom.dirty = true;
866 ctx->sample_mask.atom.dirty = true;
867 ctx->scissor.atom.dirty = true;
868 ctx->stencil_ref.atom.dirty = true;
869 ctx->vertex_fetch_shader.atom.dirty = true;
870 ctx->viewport.atom.dirty = true;
871
872 if (ctx->blend_state.cso)
873 ctx->blend_state.atom.dirty = true;
874
875 if (ctx->chip_class <= R700) {
876 ctx->seamless_cube_map.atom.dirty = true;
877 }
878
879 ctx->vertex_buffer_state.dirty_mask = ctx->vertex_buffer_state.enabled_mask;
880 r600_vertex_buffers_dirty(ctx);
881
882 /* Re-emit shader resources. */
883 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
884 struct r600_constbuf_state *constbuf = &ctx->constbuf_state[shader];
885 struct r600_textures_info *samplers = &ctx->samplers[shader];
886
887 constbuf->dirty_mask = constbuf->enabled_mask;
888 samplers->views.dirty_mask = samplers->views.enabled_mask;
889 samplers->states.dirty_mask = samplers->states.enabled_mask;
890
891 r600_constant_buffers_dirty(ctx, constbuf);
892 r600_sampler_views_dirty(ctx, &samplers->views);
893 r600_sampler_states_dirty(ctx, &samplers->states);
894 }
895
896 if (ctx->streamout_suspended) {
897 ctx->streamout_start = TRUE;
898 ctx->streamout_append_bitmask = ~0;
899 }
900
901 /* resume queries */
902 if (ctx->timer_queries_suspended) {
903 r600_resume_timer_queries(ctx);
904 }
905 if (ctx->nontimer_queries_suspended) {
906 r600_resume_nontimer_queries(ctx);
907 }
908
909 /* set all valid group as dirty so they get reemited on
910 * next draw command
911 */
912 LIST_FOR_EACH_ENTRY(enable_block, &ctx->enable_list, enable_list) {
913 if(!(enable_block->status & R600_BLOCK_STATUS_DIRTY)) {
914 LIST_ADDTAIL(&enable_block->list,&ctx->dirty);
915 enable_block->status |= R600_BLOCK_STATUS_DIRTY;
916 }
917 ctx->pm4_dirty_cdwords += enable_block->pm4_ndwords;
918 enable_block->nreg_dirty = enable_block->nreg;
919 }
920
921 /* Re-emit the draw state. */
922 ctx->last_primitive_type = -1;
923 ctx->last_start_instance = -1;
924 }
925
926 void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence_bo, unsigned offset, unsigned value)
927 {
928 struct radeon_winsys_cs *cs = ctx->cs;
929 uint64_t va;
930
931 r600_need_cs_space(ctx, 10, FALSE);
932
933 va = r600_resource_va(&ctx->screen->screen, (void*)fence_bo);
934 va = va + (offset << 2);
935
936 ctx->flags &= ~R600_CONTEXT_PS_PARTIAL_FLUSH;
937 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
938 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
939
940 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
941 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
942 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* ADDRESS_LO */
943 /* DATA_SEL | INT_EN | ADDRESS_HI */
944 cs->buf[cs->cdw++] = (1 << 29) | (0 << 24) | ((va >> 32UL) & 0xFF);
945 cs->buf[cs->cdw++] = value; /* DATA_LO */
946 cs->buf[cs->cdw++] = 0; /* DATA_HI */
947 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
948 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, fence_bo, RADEON_USAGE_WRITE);
949 }
950
951 static void r600_flush_vgt_streamout(struct r600_context *ctx)
952 {
953 struct radeon_winsys_cs *cs = ctx->cs;
954
955 r600_write_config_reg(cs, R_008490_CP_STRMOUT_CNTL, 0);
956
957 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
958 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0);
959
960 cs->buf[cs->cdw++] = PKT3(PKT3_WAIT_REG_MEM, 5, 0);
961 cs->buf[cs->cdw++] = WAIT_REG_MEM_EQUAL; /* wait until the register is equal to the reference value */
962 cs->buf[cs->cdw++] = R_008490_CP_STRMOUT_CNTL >> 2; /* register */
963 cs->buf[cs->cdw++] = 0;
964 cs->buf[cs->cdw++] = S_008490_OFFSET_UPDATE_DONE(1); /* reference value */
965 cs->buf[cs->cdw++] = S_008490_OFFSET_UPDATE_DONE(1); /* mask */
966 cs->buf[cs->cdw++] = 4; /* poll interval */
967 }
968
969 static void r600_set_streamout_enable(struct r600_context *ctx, unsigned buffer_enable_bit)
970 {
971 struct radeon_winsys_cs *cs = ctx->cs;
972
973 if (buffer_enable_bit) {
974 r600_write_context_reg(cs, R_028AB0_VGT_STRMOUT_EN, S_028AB0_STREAMOUT(1));
975 r600_write_context_reg(cs, R_028B20_VGT_STRMOUT_BUFFER_EN, buffer_enable_bit);
976 } else {
977 r600_write_context_reg(cs, R_028AB0_VGT_STRMOUT_EN, S_028AB0_STREAMOUT(0));
978 }
979 }
980
981 void r600_context_streamout_begin(struct r600_context *ctx)
982 {
983 struct radeon_winsys_cs *cs = ctx->cs;
984 struct r600_so_target **t = ctx->so_targets;
985 unsigned *stride_in_dw = ctx->vs_shader->so.stride;
986 unsigned buffer_en, i, update_flags = 0;
987 uint64_t va;
988
989 buffer_en = (ctx->num_so_targets >= 1 && t[0] ? 1 : 0) |
990 (ctx->num_so_targets >= 2 && t[1] ? 2 : 0) |
991 (ctx->num_so_targets >= 3 && t[2] ? 4 : 0) |
992 (ctx->num_so_targets >= 4 && t[3] ? 8 : 0);
993
994 ctx->num_cs_dw_streamout_end =
995 12 + /* flush_vgt_streamout */
996 util_bitcount(buffer_en) * 8 + /* STRMOUT_BUFFER_UPDATE */
997 3 /* set_streamout_enable(0) */;
998
999 r600_need_cs_space(ctx,
1000 12 + /* flush_vgt_streamout */
1001 6 + /* set_streamout_enable */
1002 util_bitcount(buffer_en) * 7 + /* SET_CONTEXT_REG */
1003 (ctx->family >= CHIP_RS780 &&
1004 ctx->family <= CHIP_RV740 ? util_bitcount(buffer_en) * 5 : 0) + /* STRMOUT_BASE_UPDATE */
1005 util_bitcount(buffer_en & ctx->streamout_append_bitmask) * 8 + /* STRMOUT_BUFFER_UPDATE */
1006 util_bitcount(buffer_en & ~ctx->streamout_append_bitmask) * 6 + /* STRMOUT_BUFFER_UPDATE */
1007 (ctx->family > CHIP_R600 && ctx->family < CHIP_RS780 ? 2 : 0) + /* SURFACE_BASE_UPDATE */
1008 ctx->num_cs_dw_streamout_end, TRUE);
1009
1010 if (ctx->chip_class >= EVERGREEN) {
1011 evergreen_flush_vgt_streamout(ctx);
1012 evergreen_set_streamout_enable(ctx, buffer_en);
1013 } else {
1014 r600_flush_vgt_streamout(ctx);
1015 r600_set_streamout_enable(ctx, buffer_en);
1016 }
1017
1018 for (i = 0; i < ctx->num_so_targets; i++) {
1019 if (t[i]) {
1020 t[i]->stride_in_dw = stride_in_dw[i];
1021 t[i]->so_index = i;
1022 va = r600_resource_va(&ctx->screen->screen,
1023 (void*)t[i]->b.buffer);
1024
1025 update_flags |= SURFACE_BASE_UPDATE_STRMOUT(i);
1026
1027 r600_write_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 3);
1028 r600_write_value(cs, (t[i]->b.buffer_offset +
1029 t[i]->b.buffer_size) >> 2); /* BUFFER_SIZE (in DW) */
1030 r600_write_value(cs, stride_in_dw[i]); /* VTX_STRIDE (in DW) */
1031 r600_write_value(cs, va >> 8); /* BUFFER_BASE */
1032
1033 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1034 cs->buf[cs->cdw++] =
1035 r600_context_bo_reloc(ctx, r600_resource(t[i]->b.buffer),
1036 RADEON_USAGE_WRITE);
1037
1038 /* R7xx requires this packet after updating BUFFER_BASE.
1039 * Without this, R7xx locks up. */
1040 if (ctx->family >= CHIP_RS780 && ctx->family <= CHIP_RV740) {
1041 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BASE_UPDATE, 1, 0);
1042 cs->buf[cs->cdw++] = i;
1043 cs->buf[cs->cdw++] = va >> 8;
1044
1045 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1046 cs->buf[cs->cdw++] =
1047 r600_context_bo_reloc(ctx, r600_resource(t[i]->b.buffer),
1048 RADEON_USAGE_WRITE);
1049 }
1050
1051 if (ctx->streamout_append_bitmask & (1 << i)) {
1052 va = r600_resource_va(&ctx->screen->screen,
1053 (void*)t[i]->filled_size);
1054 /* Append. */
1055 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
1056 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
1057 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM); /* control */
1058 cs->buf[cs->cdw++] = 0; /* unused */
1059 cs->buf[cs->cdw++] = 0; /* unused */
1060 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */
1061 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
1062
1063 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1064 cs->buf[cs->cdw++] =
1065 r600_context_bo_reloc(ctx, t[i]->filled_size,
1066 RADEON_USAGE_READ);
1067 } else {
1068 /* Start from the beginning. */
1069 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
1070 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
1071 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET); /* control */
1072 cs->buf[cs->cdw++] = 0; /* unused */
1073 cs->buf[cs->cdw++] = 0; /* unused */
1074 cs->buf[cs->cdw++] = t[i]->b.buffer_offset >> 2; /* buffer offset in DW */
1075 cs->buf[cs->cdw++] = 0; /* unused */
1076 }
1077 }
1078 }
1079
1080 if (ctx->family > CHIP_R600 && ctx->family < CHIP_RS780) {
1081 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0);
1082 cs->buf[cs->cdw++] = update_flags;
1083 }
1084 }
1085
1086 void r600_context_streamout_end(struct r600_context *ctx)
1087 {
1088 struct radeon_winsys_cs *cs = ctx->cs;
1089 struct r600_so_target **t = ctx->so_targets;
1090 unsigned i;
1091 uint64_t va;
1092
1093 if (ctx->chip_class >= EVERGREEN) {
1094 evergreen_flush_vgt_streamout(ctx);
1095 } else {
1096 r600_flush_vgt_streamout(ctx);
1097 }
1098
1099 for (i = 0; i < ctx->num_so_targets; i++) {
1100 if (t[i]) {
1101 va = r600_resource_va(&ctx->screen->screen,
1102 (void*)t[i]->filled_size);
1103 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
1104 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
1105 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
1106 STRMOUT_STORE_BUFFER_FILLED_SIZE; /* control */
1107 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* dst address lo */
1108 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* dst address hi */
1109 cs->buf[cs->cdw++] = 0; /* unused */
1110 cs->buf[cs->cdw++] = 0; /* unused */
1111
1112 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1113 cs->buf[cs->cdw++] =
1114 r600_context_bo_reloc(ctx, t[i]->filled_size,
1115 RADEON_USAGE_WRITE);
1116
1117 }
1118 }
1119
1120 if (ctx->chip_class >= EVERGREEN) {
1121 evergreen_set_streamout_enable(ctx, 0);
1122 } else {
1123 r600_set_streamout_enable(ctx, 0);
1124 }
1125 ctx->flags |= R600_CONTEXT_STREAMOUT_FLUSH;
1126
1127 /* R6xx errata */
1128 if (ctx->chip_class == R600) {
1129 ctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
1130 }
1131 ctx->num_cs_dw_streamout_end = 0;
1132 }