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[mesa.git] / src / gallium / drivers / r600 / r600_hw_context.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include "r600_hw_context_priv.h"
27 #include "r600d.h"
28 #include "util/u_memory.h"
29 #include <errno.h>
30 #include <unistd.h>
31
32 /* Get backends mask */
33 void r600_get_backend_mask(struct r600_context *ctx)
34 {
35 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
36 struct r600_resource *buffer;
37 uint32_t *results;
38 unsigned num_backends = ctx->screen->info.r600_num_backends;
39 unsigned i, mask = 0;
40 uint64_t va;
41
42 /* if backend_map query is supported by the kernel */
43 if (ctx->screen->info.r600_backend_map_valid) {
44 unsigned num_tile_pipes = ctx->screen->info.r600_num_tile_pipes;
45 unsigned backend_map = ctx->screen->info.r600_backend_map;
46 unsigned item_width, item_mask;
47
48 if (ctx->chip_class >= EVERGREEN) {
49 item_width = 4;
50 item_mask = 0x7;
51 } else {
52 item_width = 2;
53 item_mask = 0x3;
54 }
55
56 while(num_tile_pipes--) {
57 i = backend_map & item_mask;
58 mask |= (1<<i);
59 backend_map >>= item_width;
60 }
61 if (mask != 0) {
62 ctx->backend_mask = mask;
63 return;
64 }
65 }
66
67 /* otherwise backup path for older kernels */
68
69 /* create buffer for event data */
70 buffer = (struct r600_resource*)
71 pipe_buffer_create(&ctx->screen->screen, PIPE_BIND_CUSTOM,
72 PIPE_USAGE_STAGING, ctx->max_db*16);
73 if (!buffer)
74 goto err;
75 va = r600_resource_va(&ctx->screen->screen, (void*)buffer);
76
77 /* initialize buffer with zeroes */
78 results = r600_buffer_mmap_sync_with_rings(ctx, buffer, PIPE_TRANSFER_WRITE);
79 if (results) {
80 memset(results, 0, ctx->max_db * 4 * 4);
81 ctx->ws->buffer_unmap(buffer->cs_buf);
82
83 /* emit EVENT_WRITE for ZPASS_DONE */
84 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
85 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
86 cs->buf[cs->cdw++] = va;
87 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
88
89 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
90 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, &ctx->rings.gfx, buffer, RADEON_USAGE_WRITE);
91
92 /* analyze results */
93 results = r600_buffer_mmap_sync_with_rings(ctx, buffer, PIPE_TRANSFER_READ);
94 if (results) {
95 for(i = 0; i < ctx->max_db; i++) {
96 /* at least highest bit will be set if backend is used */
97 if (results[i*4 + 1])
98 mask |= (1<<i);
99 }
100 ctx->ws->buffer_unmap(buffer->cs_buf);
101 }
102 }
103
104 pipe_resource_reference((struct pipe_resource**)&buffer, NULL);
105
106 if (mask != 0) {
107 ctx->backend_mask = mask;
108 return;
109 }
110
111 err:
112 /* fallback to old method - set num_backends lower bits to 1 */
113 ctx->backend_mask = (~((uint32_t)0))>>(32-num_backends);
114 return;
115 }
116
117 static void r600_init_block(struct r600_context *ctx,
118 struct r600_block *block,
119 const struct r600_reg *reg, int index, int nreg,
120 unsigned opcode, unsigned offset_base)
121 {
122 int i = index;
123 int j, n = nreg;
124
125 /* initialize block */
126 block->flags = 0;
127 block->status |= R600_BLOCK_STATUS_DIRTY; /* dirty all blocks at start */
128 block->start_offset = reg[i].offset;
129 block->pm4[block->pm4_ndwords++] = PKT3(opcode, n, 0);
130 block->pm4[block->pm4_ndwords++] = (block->start_offset - offset_base) >> 2;
131 block->reg = &block->pm4[block->pm4_ndwords];
132 block->pm4_ndwords += n;
133 block->nreg = n;
134 block->nreg_dirty = n;
135 LIST_INITHEAD(&block->list);
136 LIST_INITHEAD(&block->enable_list);
137
138 for (j = 0; j < n; j++) {
139 if (reg[i+j].flags & REG_FLAG_DIRTY_ALWAYS) {
140 block->flags |= REG_FLAG_DIRTY_ALWAYS;
141 }
142 if (reg[i+j].flags & REG_FLAG_ENABLE_ALWAYS) {
143 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
144 block->status |= R600_BLOCK_STATUS_ENABLED;
145 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
146 LIST_ADDTAIL(&block->list,&ctx->dirty);
147 }
148 }
149 if (reg[i+j].flags & REG_FLAG_FLUSH_CHANGE) {
150 block->flags |= REG_FLAG_FLUSH_CHANGE;
151 }
152
153 if (reg[i+j].flags & REG_FLAG_NEED_BO) {
154 block->nbo++;
155 assert(block->nbo < R600_BLOCK_MAX_BO);
156 block->pm4_bo_index[j] = block->nbo;
157 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0, 0);
158 block->pm4[block->pm4_ndwords++] = 0x00000000;
159 block->reloc[block->nbo].bo_pm4_index = block->pm4_ndwords - 1;
160 }
161 }
162 /* check that we stay in limit */
163 assert(block->pm4_ndwords < R600_BLOCK_MAX_REG);
164 }
165
166 int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg,
167 unsigned opcode, unsigned offset_base)
168 {
169 struct r600_block *block;
170 struct r600_range *range;
171 int offset;
172
173 for (unsigned i = 0, n = 0; i < nreg; i += n) {
174 /* ignore new block balise */
175 if (reg[i].offset == GROUP_FORCE_NEW_BLOCK) {
176 n = 1;
177 continue;
178 }
179
180 /* register that need relocation are in their own group */
181 /* find number of consecutive registers */
182 n = 0;
183 offset = reg[i].offset;
184 while (reg[i + n].offset == offset) {
185 n++;
186 offset += 4;
187 if ((n + i) >= nreg)
188 break;
189 if (n >= (R600_BLOCK_MAX_REG - 2))
190 break;
191 }
192
193 /* allocate new block */
194 block = calloc(1, sizeof(struct r600_block));
195 if (block == NULL) {
196 return -ENOMEM;
197 }
198 ctx->nblocks++;
199 for (int j = 0; j < n; j++) {
200 range = &ctx->range[CTX_RANGE_ID(reg[i + j].offset)];
201 /* create block table if it doesn't exist */
202 if (!range->blocks)
203 range->blocks = calloc(1 << HASH_SHIFT, sizeof(void *));
204 if (!range->blocks) {
205 free(block);
206 return -1;
207 }
208
209 range->blocks[CTX_BLOCK_ID(reg[i + j].offset)] = block;
210 }
211
212 r600_init_block(ctx, block, reg, i, n, opcode, offset_base);
213
214 }
215 return 0;
216 }
217
218 /* initialize */
219 void r600_context_fini(struct r600_context *ctx)
220 {
221 struct r600_block *block;
222 struct r600_range *range;
223
224 if (ctx->range) {
225 for (int i = 0; i < NUM_RANGES; i++) {
226 if (!ctx->range[i].blocks)
227 continue;
228 for (int j = 0; j < (1 << HASH_SHIFT); j++) {
229 block = ctx->range[i].blocks[j];
230 if (block) {
231 for (int k = 0, offset = block->start_offset; k < block->nreg; k++, offset += 4) {
232 range = &ctx->range[CTX_RANGE_ID(offset)];
233 range->blocks[CTX_BLOCK_ID(offset)] = NULL;
234 }
235 for (int k = 1; k <= block->nbo; k++) {
236 pipe_resource_reference((struct pipe_resource**)&block->reloc[k].bo, NULL);
237 }
238 free(block);
239 }
240 }
241 free(ctx->range[i].blocks);
242 }
243 }
244 free(ctx->blocks);
245 }
246
247 int r600_setup_block_table(struct r600_context *ctx)
248 {
249 /* setup block table */
250 int c = 0;
251 ctx->blocks = calloc(ctx->nblocks, sizeof(void*));
252 if (!ctx->blocks)
253 return -ENOMEM;
254 for (int i = 0; i < NUM_RANGES; i++) {
255 if (!ctx->range[i].blocks)
256 continue;
257 for (int j = 0, add; j < (1 << HASH_SHIFT); j++) {
258 if (!ctx->range[i].blocks[j])
259 continue;
260
261 add = 1;
262 for (int k = 0; k < c; k++) {
263 if (ctx->blocks[k] == ctx->range[i].blocks[j]) {
264 add = 0;
265 break;
266 }
267 }
268 if (add) {
269 assert(c < ctx->nblocks);
270 ctx->blocks[c++] = ctx->range[i].blocks[j];
271 j += (ctx->range[i].blocks[j]->nreg) - 1;
272 }
273 }
274 }
275 return 0;
276 }
277
278 int r600_context_init(struct r600_context *ctx)
279 {
280 int r;
281
282 r = r600_setup_block_table(ctx);
283 if (r)
284 goto out_err;
285
286 ctx->max_db = 4;
287 return 0;
288 out_err:
289 r600_context_fini(ctx);
290 return r;
291 }
292
293 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
294 boolean count_draw_in)
295 {
296 if (!ctx->ws->cs_memory_below_limit(ctx->rings.gfx.cs, ctx->vram, ctx->gtt)) {
297 ctx->gtt = 0;
298 ctx->vram = 0;
299 ctx->rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC);
300 return;
301 }
302 /* all will be accounted once relocation are emited */
303 ctx->gtt = 0;
304 ctx->vram = 0;
305
306 /* The number of dwords we already used in the CS so far. */
307 num_dw += ctx->rings.gfx.cs->cdw;
308
309 if (count_draw_in) {
310 unsigned i;
311
312 /* The number of dwords all the dirty states would take. */
313 for (i = 0; i < R600_NUM_ATOMS; i++) {
314 if (ctx->atoms[i] && ctx->atoms[i]->dirty) {
315 num_dw += ctx->atoms[i]->num_dw;
316 #if R600_TRACE_CS
317 if (ctx->screen->trace_bo) {
318 num_dw += R600_TRACE_CS_DWORDS;
319 }
320 #endif
321 }
322 }
323
324 num_dw += ctx->pm4_dirty_cdwords;
325
326 /* The upper-bound of how much space a draw command would take. */
327 num_dw += R600_MAX_FLUSH_CS_DWORDS + R600_MAX_DRAW_CS_DWORDS;
328 #if R600_TRACE_CS
329 if (ctx->screen->trace_bo) {
330 num_dw += R600_TRACE_CS_DWORDS;
331 }
332 #endif
333 }
334
335 /* Count in queries_suspend. */
336 num_dw += ctx->num_cs_dw_nontimer_queries_suspend;
337
338 /* Count in streamout_end at the end of CS. */
339 if (ctx->streamout.begin_emitted) {
340 num_dw += ctx->streamout.num_dw_for_end;
341 }
342
343 /* Count in render_condition(NULL) at the end of CS. */
344 if (ctx->predicate_drawing) {
345 num_dw += 3;
346 }
347
348 /* SX_MISC */
349 if (ctx->chip_class <= R700) {
350 num_dw += 3;
351 }
352
353 /* Count in framebuffer cache flushes at the end of CS. */
354 num_dw += R600_MAX_FLUSH_CS_DWORDS;
355
356 /* The fence at the end of CS. */
357 num_dw += 10;
358
359 /* Flush if there's not enough space. */
360 if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
361 ctx->rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC);
362 }
363 }
364
365 void r600_context_dirty_block(struct r600_context *ctx,
366 struct r600_block *block,
367 int dirty, int index)
368 {
369 if ((index + 1) > block->nreg_dirty)
370 block->nreg_dirty = index + 1;
371
372 if ((dirty != (block->status & R600_BLOCK_STATUS_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) {
373 block->status |= R600_BLOCK_STATUS_DIRTY;
374 ctx->pm4_dirty_cdwords += block->pm4_ndwords;
375 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
376 block->status |= R600_BLOCK_STATUS_ENABLED;
377 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
378 }
379 LIST_ADDTAIL(&block->list,&ctx->dirty);
380
381 if (block->flags & REG_FLAG_FLUSH_CHANGE) {
382 ctx->flags |= R600_CONTEXT_WAIT_3D_IDLE;
383 }
384 }
385 }
386
387 /**
388 * If reg needs a reloc, this function will add it to its block's reloc list.
389 * @return true if reg needs a reloc, false otherwise
390 */
391 static bool r600_reg_set_block_reloc(struct r600_pipe_reg *reg)
392 {
393 unsigned reloc_id;
394
395 if (!reg->block->pm4_bo_index[reg->id]) {
396 return false;
397 }
398 /* find relocation */
399 reloc_id = reg->block->pm4_bo_index[reg->id];
400 pipe_resource_reference(
401 (struct pipe_resource**)&reg->block->reloc[reloc_id].bo,
402 &reg->bo->b.b);
403 reg->block->reloc[reloc_id].bo_usage = reg->bo_usage;
404 return true;
405 }
406
407 /**
408 * This function will emit all the registers in state directly to the command
409 * stream allowing you to bypass the r600_context dirty list.
410 *
411 * This is used for dispatching compute shaders to avoid mixing compute and
412 * 3D states in the context's dirty list.
413 *
414 * @param pkt_flags Should be either 0 or RADEON_CP_PACKET3_COMPUTE_MODE. This
415 * value will be passed on to r600_context_block_emit_dirty an or'd against
416 * the PKT3 headers.
417 */
418 void r600_context_pipe_state_emit(struct r600_context *ctx,
419 struct r600_pipe_state *state,
420 unsigned pkt_flags)
421 {
422 unsigned i;
423
424 /* Mark all blocks as dirty:
425 * Since two registers can be in the same block, we need to make sure
426 * we mark all the blocks dirty before we emit any of them. If we were
427 * to mark blocks dirty and emit them in the same loop, like this:
428 *
429 * foreach (reg in state->regs) {
430 * mark_dirty(reg->block)
431 * emit_block(reg->block)
432 * }
433 *
434 * Then if we have two registers in this state that are in the same
435 * block, we would end up emitting that block twice.
436 */
437 for (i = 0; i < state->nregs; i++) {
438 struct r600_pipe_reg *reg = &state->regs[i];
439 /* Mark all the registers in the block as dirty */
440 reg->block->nreg_dirty = reg->block->nreg;
441 reg->block->status |= R600_BLOCK_STATUS_DIRTY;
442 /* Update the reloc for this register if necessary. */
443 r600_reg_set_block_reloc(reg);
444 }
445
446 /* Emit the registers writes */
447 for (i = 0; i < state->nregs; i++) {
448 struct r600_pipe_reg *reg = &state->regs[i];
449 if (reg->block->status & R600_BLOCK_STATUS_DIRTY) {
450 r600_context_block_emit_dirty(ctx, reg->block, pkt_flags);
451 }
452 }
453 }
454
455 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state)
456 {
457 struct r600_block *block;
458 int dirty;
459 for (int i = 0; i < state->nregs; i++) {
460 unsigned id;
461 struct r600_pipe_reg *reg = &state->regs[i];
462
463 block = reg->block;
464 id = reg->id;
465
466 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
467
468 if (reg->value != block->reg[id]) {
469 block->reg[id] = reg->value;
470 dirty |= R600_BLOCK_STATUS_DIRTY;
471 }
472 if (block->flags & REG_FLAG_DIRTY_ALWAYS)
473 dirty |= R600_BLOCK_STATUS_DIRTY;
474 if (r600_reg_set_block_reloc(reg)) {
475 /* always force dirty for relocs for now */
476 dirty |= R600_BLOCK_STATUS_DIRTY;
477 }
478
479 if (dirty)
480 r600_context_dirty_block(ctx, block, dirty, id);
481 }
482 }
483
484 /**
485 * @param pkt_flags should be set to RADEON_CP_PACKET3_COMPUTE_MODE if this
486 * block will be used for compute shaders.
487 */
488 void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block,
489 unsigned pkt_flags)
490 {
491 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
492 int optional = block->nbo == 0 && !(block->flags & REG_FLAG_DIRTY_ALWAYS);
493 int cp_dwords = block->pm4_ndwords, start_dword = 0;
494 int new_dwords = 0;
495 int nbo = block->nbo;
496
497 if (block->nreg_dirty == 0 && optional) {
498 goto out;
499 }
500
501 if (nbo) {
502 for (int j = 0; j < block->nreg; j++) {
503 if (block->pm4_bo_index[j]) {
504 /* find relocation */
505 struct r600_block_reloc *reloc = &block->reloc[block->pm4_bo_index[j]];
506 if (reloc->bo) {
507 block->pm4[reloc->bo_pm4_index] =
508 r600_context_bo_reloc(ctx, &ctx->rings.gfx, reloc->bo, reloc->bo_usage);
509 } else {
510 block->pm4[reloc->bo_pm4_index] = 0;
511 }
512 nbo--;
513 if (nbo == 0)
514 break;
515
516 }
517 }
518 }
519
520 optional &= (block->nreg_dirty != block->nreg);
521 if (optional) {
522 new_dwords = block->nreg_dirty;
523 start_dword = cs->cdw;
524 cp_dwords = new_dwords + 2;
525 }
526 memcpy(&cs->buf[cs->cdw], block->pm4, cp_dwords * 4);
527
528 /* We are applying the pkt_flags after copying the register block to
529 * the the command stream, because it is possible this block will be
530 * emitted with a different pkt_flags, and we don't want to store the
531 * pkt_flags in the block.
532 */
533 cs->buf[cs->cdw] |= pkt_flags;
534 cs->cdw += cp_dwords;
535
536 if (optional) {
537 uint32_t newword;
538
539 newword = cs->buf[start_dword];
540 newword &= PKT_COUNT_C;
541 newword |= PKT_COUNT_S(new_dwords);
542 cs->buf[start_dword] = newword;
543 }
544 out:
545 block->status ^= R600_BLOCK_STATUS_DIRTY;
546 block->nreg_dirty = 0;
547 LIST_DELINIT(&block->list);
548 }
549
550 void r600_flush_emit(struct r600_context *rctx)
551 {
552 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
553 unsigned cp_coher_cntl = 0;
554 unsigned wait_until = 0;
555 unsigned emit_flush = 0;
556
557 if (!rctx->flags) {
558 return;
559 }
560
561 if (rctx->flags & R600_CONTEXT_WAIT_3D_IDLE) {
562 wait_until |= S_008040_WAIT_3D_IDLE(1);
563 }
564 if (rctx->flags & R600_CONTEXT_WAIT_CP_DMA_IDLE) {
565 wait_until |= S_008040_WAIT_CP_DMA_IDLE(1);
566 }
567
568 if (wait_until) {
569 /* Use of WAIT_UNTIL is deprecated on Cayman+ */
570 if (rctx->family >= CHIP_CAYMAN) {
571 /* emit a PS partial flush on Cayman/TN */
572 rctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
573 }
574 }
575
576 if (rctx->flags & R600_CONTEXT_PS_PARTIAL_FLUSH) {
577 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
578 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
579 }
580
581 if (rctx->chip_class >= R700 &&
582 (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB_META)) {
583 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
584 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0);
585 }
586
587 if (rctx->chip_class >= R700 &&
588 (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_DB_META)) {
589 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
590 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0);
591 }
592
593 if (rctx->flags & R600_CONTEXT_FLUSH_AND_INV) {
594 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
595 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
596 if (rctx->chip_class >= EVERGREEN) {
597 cp_coher_cntl = S_0085F0_CB0_DEST_BASE_ENA(1) |
598 S_0085F0_CB1_DEST_BASE_ENA(1) |
599 S_0085F0_CB2_DEST_BASE_ENA(1) |
600 S_0085F0_CB3_DEST_BASE_ENA(1) |
601 S_0085F0_CB4_DEST_BASE_ENA(1) |
602 S_0085F0_CB5_DEST_BASE_ENA(1) |
603 S_0085F0_CB6_DEST_BASE_ENA(1) |
604 S_0085F0_CB7_DEST_BASE_ENA(1) |
605 S_0085F0_CB8_DEST_BASE_ENA(1) |
606 S_0085F0_CB9_DEST_BASE_ENA(1) |
607 S_0085F0_CB10_DEST_BASE_ENA(1) |
608 S_0085F0_CB11_DEST_BASE_ENA(1) |
609 S_0085F0_DB_DEST_BASE_ENA(1) |
610 S_0085F0_TC_ACTION_ENA(1) |
611 S_0085F0_CB_ACTION_ENA(1) |
612 S_0085F0_DB_ACTION_ENA(1) |
613 S_0085F0_SH_ACTION_ENA(1) |
614 S_0085F0_SMX_ACTION_ENA(1) |
615 S_0085F0_FULL_CACHE_ENA(1);
616 } else {
617 cp_coher_cntl = S_0085F0_SMX_ACTION_ENA(1) |
618 S_0085F0_SH_ACTION_ENA(1) |
619 S_0085F0_VC_ACTION_ENA(1) |
620 S_0085F0_TC_ACTION_ENA(1) |
621 S_0085F0_FULL_CACHE_ENA(1);
622 }
623 emit_flush = 1;
624 }
625
626 if (rctx->flags & R600_CONTEXT_INVAL_READ_CACHES) {
627 cp_coher_cntl |= S_0085F0_VC_ACTION_ENA(1) |
628 S_0085F0_TC_ACTION_ENA(1) |
629 S_0085F0_FULL_CACHE_ENA(1);
630 emit_flush = 1;
631 }
632
633 if (rctx->flags & R600_CONTEXT_STREAMOUT_FLUSH) {
634 cp_coher_cntl |= S_0085F0_SO0_DEST_BASE_ENA(1) |
635 S_0085F0_SO1_DEST_BASE_ENA(1) |
636 S_0085F0_SO2_DEST_BASE_ENA(1) |
637 S_0085F0_SO3_DEST_BASE_ENA(1) |
638 S_0085F0_SMX_ACTION_ENA(1);
639 emit_flush = 1;
640 }
641
642 if (emit_flush) {
643 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
644 cs->buf[cs->cdw++] = cp_coher_cntl; /* CP_COHER_CNTL */
645 cs->buf[cs->cdw++] = 0xffffffff; /* CP_COHER_SIZE */
646 cs->buf[cs->cdw++] = 0; /* CP_COHER_BASE */
647 cs->buf[cs->cdw++] = 0x0000000A; /* POLL_INTERVAL */
648 }
649
650 if (wait_until) {
651 /* Use of WAIT_UNTIL is deprecated on Cayman+ */
652 if (rctx->family < CHIP_CAYMAN) {
653 /* wait for things to settle */
654 r600_write_config_reg(cs, R_008040_WAIT_UNTIL, wait_until);
655 }
656 }
657
658 /* everything is properly flushed */
659 rctx->flags = 0;
660 }
661
662 void r600_context_flush(struct r600_context *ctx, unsigned flags)
663 {
664 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
665
666 if (cs->cdw == ctx->start_cs_cmd.num_dw)
667 return;
668
669 ctx->nontimer_queries_suspended = false;
670 ctx->streamout.suspended = false;
671
672 /* suspend queries */
673 if (ctx->num_cs_dw_nontimer_queries_suspend) {
674 r600_suspend_nontimer_queries(ctx);
675 ctx->nontimer_queries_suspended = true;
676 }
677
678 if (ctx->streamout.begin_emitted) {
679 r600_emit_streamout_end(ctx);
680 ctx->streamout.suspended = true;
681 }
682
683 /* flush is needed to avoid lockups on some chips with user fences
684 * this will also flush the framebuffer cache
685 */
686 ctx->flags |= R600_CONTEXT_FLUSH_AND_INV |
687 R600_CONTEXT_FLUSH_AND_INV_CB_META |
688 R600_CONTEXT_FLUSH_AND_INV_DB_META |
689 R600_CONTEXT_WAIT_3D_IDLE |
690 R600_CONTEXT_WAIT_CP_DMA_IDLE;
691
692 r600_flush_emit(ctx);
693
694 /* old kernels and userspace don't set SX_MISC, so we must reset it to 0 here */
695 if (ctx->chip_class <= R700) {
696 r600_write_context_reg(cs, R_028350_SX_MISC, 0);
697 }
698
699 /* force to keep tiling flags */
700 if (ctx->keep_tiling_flags) {
701 flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
702 }
703
704 /* Flush the CS. */
705 #if R600_TRACE_CS
706 if (ctx->screen->trace_bo) {
707 struct r600_screen *rscreen = ctx->screen;
708 unsigned i;
709
710 for (i = 0; i < cs->cdw; i++) {
711 fprintf(stderr, "[%4d] [%5d] 0x%08x\n", rscreen->cs_count, i, cs->buf[i]);
712 }
713 rscreen->cs_count++;
714 }
715 #endif
716 ctx->ws->cs_flush(ctx->rings.gfx.cs, flags);
717 #if R600_TRACE_CS
718 if (ctx->screen->trace_bo) {
719 struct r600_screen *rscreen = ctx->screen;
720 unsigned i;
721
722 for (i = 0; i < 10; i++) {
723 usleep(5);
724 if (!ctx->ws->buffer_is_busy(rscreen->trace_bo->buf, RADEON_USAGE_READWRITE)) {
725 break;
726 }
727 }
728 if (i == 10) {
729 fprintf(stderr, "timeout on cs lockup likely happen at cs %d dw %d\n",
730 rscreen->trace_ptr[1], rscreen->trace_ptr[0]);
731 } else {
732 fprintf(stderr, "cs %d executed in %dms\n", rscreen->trace_ptr[1], i * 5);
733 }
734 }
735 #endif
736 }
737
738 void r600_begin_new_cs(struct r600_context *ctx)
739 {
740 struct r600_block *enable_block = NULL;
741 unsigned shader;
742
743 ctx->pm4_dirty_cdwords = 0;
744 ctx->flags = 0;
745 ctx->gtt = 0;
746 ctx->vram = 0;
747
748 /* Begin a new CS. */
749 r600_emit_command_buffer(ctx->rings.gfx.cs, &ctx->start_cs_cmd);
750
751 /* Re-emit states. */
752 ctx->alphatest_state.atom.dirty = true;
753 ctx->blend_color.atom.dirty = true;
754 ctx->cb_misc_state.atom.dirty = true;
755 ctx->clip_misc_state.atom.dirty = true;
756 ctx->clip_state.atom.dirty = true;
757 ctx->db_misc_state.atom.dirty = true;
758 ctx->db_state.atom.dirty = true;
759 ctx->framebuffer.atom.dirty = true;
760 ctx->pixel_shader.atom.dirty = true;
761 ctx->poly_offset_state.atom.dirty = true;
762 ctx->vgt_state.atom.dirty = true;
763 ctx->sample_mask.atom.dirty = true;
764 ctx->scissor.atom.dirty = true;
765 ctx->config_state.atom.dirty = true;
766 ctx->stencil_ref.atom.dirty = true;
767 ctx->vertex_fetch_shader.atom.dirty = true;
768 ctx->vertex_shader.atom.dirty = true;
769 ctx->viewport.atom.dirty = true;
770
771 if (ctx->blend_state.cso)
772 ctx->blend_state.atom.dirty = true;
773 if (ctx->dsa_state.cso)
774 ctx->dsa_state.atom.dirty = true;
775 if (ctx->rasterizer_state.cso)
776 ctx->rasterizer_state.atom.dirty = true;
777
778 if (ctx->chip_class <= R700) {
779 ctx->seamless_cube_map.atom.dirty = true;
780 }
781
782 ctx->vertex_buffer_state.dirty_mask = ctx->vertex_buffer_state.enabled_mask;
783 r600_vertex_buffers_dirty(ctx);
784
785 /* Re-emit shader resources. */
786 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
787 struct r600_constbuf_state *constbuf = &ctx->constbuf_state[shader];
788 struct r600_textures_info *samplers = &ctx->samplers[shader];
789
790 constbuf->dirty_mask = constbuf->enabled_mask;
791 samplers->views.dirty_mask = samplers->views.enabled_mask;
792 samplers->states.dirty_mask = samplers->states.enabled_mask;
793
794 r600_constant_buffers_dirty(ctx, constbuf);
795 r600_sampler_views_dirty(ctx, &samplers->views);
796 r600_sampler_states_dirty(ctx, &samplers->states);
797 }
798
799 if (ctx->streamout.suspended) {
800 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
801 r600_streamout_buffers_dirty(ctx);
802 }
803
804 /* resume queries */
805 if (ctx->nontimer_queries_suspended) {
806 r600_resume_nontimer_queries(ctx);
807 }
808
809 /* set all valid group as dirty so they get reemited on
810 * next draw command
811 */
812 LIST_FOR_EACH_ENTRY(enable_block, &ctx->enable_list, enable_list) {
813 if(!(enable_block->status & R600_BLOCK_STATUS_DIRTY)) {
814 LIST_ADDTAIL(&enable_block->list,&ctx->dirty);
815 enable_block->status |= R600_BLOCK_STATUS_DIRTY;
816 }
817 ctx->pm4_dirty_cdwords += enable_block->pm4_ndwords;
818 enable_block->nreg_dirty = enable_block->nreg;
819 }
820
821 /* Re-emit the draw state. */
822 ctx->last_primitive_type = -1;
823 ctx->last_start_instance = -1;
824 }
825
826 void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence_bo, unsigned offset, unsigned value)
827 {
828 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
829 uint64_t va;
830
831 r600_need_cs_space(ctx, 10, FALSE);
832
833 va = r600_resource_va(&ctx->screen->screen, (void*)fence_bo);
834 va = va + (offset << 2);
835
836 /* Use of WAIT_UNTIL is deprecated on Cayman+ */
837 if (ctx->family >= CHIP_CAYMAN) {
838 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
839 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
840 } else {
841 r600_write_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
842 }
843
844 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
845 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
846 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* ADDRESS_LO */
847 /* DATA_SEL | INT_EN | ADDRESS_HI */
848 cs->buf[cs->cdw++] = (1 << 29) | (0 << 24) | ((va >> 32UL) & 0xFF);
849 cs->buf[cs->cdw++] = value; /* DATA_LO */
850 cs->buf[cs->cdw++] = 0; /* DATA_HI */
851 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
852 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, &ctx->rings.gfx, fence_bo, RADEON_USAGE_WRITE);
853 }
854
855 static void r600_flush_vgt_streamout(struct r600_context *ctx)
856 {
857 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
858
859 r600_write_config_reg(cs, R_008490_CP_STRMOUT_CNTL, 0);
860
861 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
862 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0);
863
864 cs->buf[cs->cdw++] = PKT3(PKT3_WAIT_REG_MEM, 5, 0);
865 cs->buf[cs->cdw++] = WAIT_REG_MEM_EQUAL; /* wait until the register is equal to the reference value */
866 cs->buf[cs->cdw++] = R_008490_CP_STRMOUT_CNTL >> 2; /* register */
867 cs->buf[cs->cdw++] = 0;
868 cs->buf[cs->cdw++] = S_008490_OFFSET_UPDATE_DONE(1); /* reference value */
869 cs->buf[cs->cdw++] = S_008490_OFFSET_UPDATE_DONE(1); /* mask */
870 cs->buf[cs->cdw++] = 4; /* poll interval */
871 }
872
873 static void r600_set_streamout_enable(struct r600_context *ctx, unsigned buffer_enable_bit)
874 {
875 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
876
877 if (buffer_enable_bit) {
878 r600_write_context_reg(cs, R_028AB0_VGT_STRMOUT_EN, S_028AB0_STREAMOUT(1));
879 r600_write_context_reg(cs, R_028B20_VGT_STRMOUT_BUFFER_EN, buffer_enable_bit);
880 } else {
881 r600_write_context_reg(cs, R_028AB0_VGT_STRMOUT_EN, S_028AB0_STREAMOUT(0));
882 }
883 }
884
885 void r600_emit_streamout_begin(struct r600_context *ctx, struct r600_atom *atom)
886 {
887 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
888 struct r600_so_target **t = ctx->streamout.targets;
889 unsigned *stride_in_dw = ctx->vs_shader->so.stride;
890 unsigned i, update_flags = 0;
891 uint64_t va;
892
893 if (ctx->chip_class >= EVERGREEN) {
894 evergreen_flush_vgt_streamout(ctx);
895 evergreen_set_streamout_enable(ctx, ctx->streamout.enabled_mask);
896 } else {
897 r600_flush_vgt_streamout(ctx);
898 r600_set_streamout_enable(ctx, ctx->streamout.enabled_mask);
899 }
900
901 for (i = 0; i < ctx->streamout.num_targets; i++) {
902 if (t[i]) {
903 t[i]->stride_in_dw = stride_in_dw[i];
904 t[i]->so_index = i;
905 va = r600_resource_va(&ctx->screen->screen,
906 (void*)t[i]->b.buffer);
907
908 update_flags |= SURFACE_BASE_UPDATE_STRMOUT(i);
909
910 r600_write_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 3);
911 r600_write_value(cs, (t[i]->b.buffer_offset +
912 t[i]->b.buffer_size) >> 2); /* BUFFER_SIZE (in DW) */
913 r600_write_value(cs, stride_in_dw[i]); /* VTX_STRIDE (in DW) */
914 r600_write_value(cs, va >> 8); /* BUFFER_BASE */
915
916 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
917 cs->buf[cs->cdw++] =
918 r600_context_bo_reloc(ctx, &ctx->rings.gfx, r600_resource(t[i]->b.buffer),
919 RADEON_USAGE_WRITE);
920
921 /* R7xx requires this packet after updating BUFFER_BASE.
922 * Without this, R7xx locks up. */
923 if (ctx->family >= CHIP_RS780 && ctx->family <= CHIP_RV740) {
924 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BASE_UPDATE, 1, 0);
925 cs->buf[cs->cdw++] = i;
926 cs->buf[cs->cdw++] = va >> 8;
927
928 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
929 cs->buf[cs->cdw++] =
930 r600_context_bo_reloc(ctx, &ctx->rings.gfx, r600_resource(t[i]->b.buffer),
931 RADEON_USAGE_WRITE);
932 }
933
934 if (ctx->streamout.append_bitmask & (1 << i)) {
935 va = r600_resource_va(&ctx->screen->screen,
936 (void*)t[i]->buf_filled_size) + t[i]->buf_filled_size_offset;
937 /* Append. */
938 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
939 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
940 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM); /* control */
941 cs->buf[cs->cdw++] = 0; /* unused */
942 cs->buf[cs->cdw++] = 0; /* unused */
943 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */
944 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
945
946 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
947 cs->buf[cs->cdw++] =
948 r600_context_bo_reloc(ctx, &ctx->rings.gfx, t[i]->buf_filled_size,
949 RADEON_USAGE_READ);
950 } else {
951 /* Start from the beginning. */
952 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
953 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
954 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET); /* control */
955 cs->buf[cs->cdw++] = 0; /* unused */
956 cs->buf[cs->cdw++] = 0; /* unused */
957 cs->buf[cs->cdw++] = t[i]->b.buffer_offset >> 2; /* buffer offset in DW */
958 cs->buf[cs->cdw++] = 0; /* unused */
959 }
960 }
961 }
962
963 if (ctx->family > CHIP_R600 && ctx->family < CHIP_RV770) {
964 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0);
965 cs->buf[cs->cdw++] = update_flags;
966 }
967 ctx->streamout.begin_emitted = true;
968 }
969
970 void r600_emit_streamout_end(struct r600_context *ctx)
971 {
972 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
973 struct r600_so_target **t = ctx->streamout.targets;
974 unsigned i;
975 uint64_t va;
976
977 if (ctx->chip_class >= EVERGREEN) {
978 evergreen_flush_vgt_streamout(ctx);
979 } else {
980 r600_flush_vgt_streamout(ctx);
981 }
982
983 for (i = 0; i < ctx->streamout.num_targets; i++) {
984 if (t[i]) {
985 va = r600_resource_va(&ctx->screen->screen,
986 (void*)t[i]->buf_filled_size) + t[i]->buf_filled_size_offset;
987 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
988 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
989 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
990 STRMOUT_STORE_BUFFER_FILLED_SIZE; /* control */
991 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* dst address lo */
992 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* dst address hi */
993 cs->buf[cs->cdw++] = 0; /* unused */
994 cs->buf[cs->cdw++] = 0; /* unused */
995
996 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
997 cs->buf[cs->cdw++] =
998 r600_context_bo_reloc(ctx, &ctx->rings.gfx, t[i]->buf_filled_size,
999 RADEON_USAGE_WRITE);
1000 }
1001 }
1002
1003 if (ctx->chip_class >= EVERGREEN) {
1004 ctx->flags |= R600_CONTEXT_STREAMOUT_FLUSH;
1005 evergreen_set_streamout_enable(ctx, 0);
1006 } else {
1007 if (ctx->chip_class >= R700) {
1008 ctx->flags |= R600_CONTEXT_STREAMOUT_FLUSH;
1009 }
1010 r600_set_streamout_enable(ctx, 0);
1011 }
1012 ctx->flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1013 ctx->streamout.begin_emitted = false;
1014 }
1015
1016 /* The max number of bytes to copy per packet. */
1017 #define CP_DMA_MAX_BYTE_COUNT ((1 << 21) - 8)
1018
1019 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
1020 struct pipe_resource *dst, uint64_t dst_offset,
1021 struct pipe_resource *src, uint64_t src_offset,
1022 unsigned size)
1023 {
1024 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
1025
1026 assert(size);
1027 assert(rctx->screen->has_cp_dma);
1028
1029 dst_offset += r600_resource_va(&rctx->screen->screen, dst);
1030 src_offset += r600_resource_va(&rctx->screen->screen, src);
1031
1032 /* We flush the caches, because we might read from or write
1033 * to resources which are bound right now. */
1034 rctx->flags |= R600_CONTEXT_INVAL_READ_CACHES |
1035 R600_CONTEXT_FLUSH_AND_INV |
1036 R600_CONTEXT_FLUSH_AND_INV_CB_META |
1037 R600_CONTEXT_FLUSH_AND_INV_DB_META |
1038 R600_CONTEXT_STREAMOUT_FLUSH |
1039 R600_CONTEXT_WAIT_3D_IDLE;
1040
1041 /* There are differences between R700 and EG in CP DMA,
1042 * but we only use the common bits here. */
1043 while (size) {
1044 unsigned sync = 0;
1045 unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
1046 unsigned src_reloc, dst_reloc;
1047
1048 r600_need_cs_space(rctx, 10 + (rctx->flags ? R600_MAX_FLUSH_CS_DWORDS : 0), FALSE);
1049
1050 /* Flush the caches for the first copy only. */
1051 if (rctx->flags) {
1052 r600_flush_emit(rctx);
1053 }
1054
1055 /* Do the synchronization after the last copy, so that all data is written to memory. */
1056 if (size == byte_count) {
1057 sync = PKT3_CP_DMA_CP_SYNC;
1058 }
1059
1060 /* This must be done after r600_need_cs_space. */
1061 src_reloc = r600_context_bo_reloc(rctx, &rctx->rings.gfx, (struct r600_resource*)src, RADEON_USAGE_READ);
1062 dst_reloc = r600_context_bo_reloc(rctx, &rctx->rings.gfx, (struct r600_resource*)dst, RADEON_USAGE_WRITE);
1063
1064 r600_write_value(cs, PKT3(PKT3_CP_DMA, 4, 0));
1065 r600_write_value(cs, src_offset); /* SRC_ADDR_LO [31:0] */
1066 r600_write_value(cs, sync | ((src_offset >> 32) & 0xff)); /* CP_SYNC [31] | SRC_ADDR_HI [7:0] */
1067 r600_write_value(cs, dst_offset); /* DST_ADDR_LO [31:0] */
1068 r600_write_value(cs, (dst_offset >> 32) & 0xff); /* DST_ADDR_HI [7:0] */
1069 r600_write_value(cs, byte_count); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
1070
1071 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1072 r600_write_value(cs, src_reloc);
1073 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1074 r600_write_value(cs, dst_reloc);
1075
1076 size -= byte_count;
1077 src_offset += byte_count;
1078 dst_offset += byte_count;
1079 }
1080
1081 /* Invalidate the read caches. */
1082 rctx->flags |= R600_CONTEXT_INVAL_READ_CACHES;
1083
1084 util_range_add(&r600_resource(dst)->valid_buffer_range, dst_offset,
1085 dst_offset + size);
1086 }
1087
1088 void r600_need_dma_space(struct r600_context *ctx, unsigned num_dw)
1089 {
1090 /* The number of dwords we already used in the DMA so far. */
1091 num_dw += ctx->rings.dma.cs->cdw;
1092 /* Flush if there's not enough space. */
1093 if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
1094 ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC);
1095 }
1096 }
1097
1098 void r600_dma_copy(struct r600_context *rctx,
1099 struct pipe_resource *dst,
1100 struct pipe_resource *src,
1101 uint64_t dst_offset,
1102 uint64_t src_offset,
1103 uint64_t size)
1104 {
1105 struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
1106 unsigned i, ncopy, csize, shift;
1107 struct r600_resource *rdst = (struct r600_resource*)dst;
1108 struct r600_resource *rsrc = (struct r600_resource*)src;
1109
1110 /* make sure that the dma ring is only one active */
1111 rctx->rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC);
1112
1113 size >>= 2;
1114 shift = 2;
1115 ncopy = (size / 0xffff) + !!(size % 0xffff);
1116
1117 r600_need_dma_space(rctx, ncopy * 5);
1118 for (i = 0; i < ncopy; i++) {
1119 csize = size < 0xffff ? size : 0xffff;
1120 /* emit reloc before writting cs so that cs is always in consistent state */
1121 r600_context_bo_reloc(rctx, &rctx->rings.dma, rsrc, RADEON_USAGE_READ);
1122 r600_context_bo_reloc(rctx, &rctx->rings.dma, rdst, RADEON_USAGE_WRITE);
1123 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, 0, 0, csize);
1124 cs->buf[cs->cdw++] = dst_offset & 0xfffffffc;
1125 cs->buf[cs->cdw++] = src_offset & 0xfffffffc;
1126 cs->buf[cs->cdw++] = (dst_offset >> 32UL) & 0xff;
1127 cs->buf[cs->cdw++] = (src_offset >> 32UL) & 0xff;
1128 dst_offset += csize << shift;
1129 src_offset += csize << shift;
1130 size -= csize;
1131 }
1132
1133 util_range_add(&rdst->valid_buffer_range, dst_offset,
1134 dst_offset + size);
1135 }