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[mesa.git] / src / gallium / drivers / r600 / r600_hw_context.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include "r600_hw_context_priv.h"
27 #include "r600_pipe.h"
28 #include "r600d.h"
29 #include "util/u_memory.h"
30 #include <errno.h>
31
32 #define GROUP_FORCE_NEW_BLOCK 0
33
34 /* Get backends mask */
35 void r600_get_backend_mask(struct r600_context *ctx)
36 {
37 struct r600_resource *buffer;
38 u32 *results;
39 unsigned num_backends = ctx->screen->info.r600_num_backends;
40 unsigned i, mask = 0;
41
42 /* if backend_map query is supported by the kernel */
43 if (ctx->screen->info.r600_backend_map_valid) {
44 unsigned num_tile_pipes = ctx->screen->info.r600_num_tile_pipes;
45 unsigned backend_map = ctx->screen->info.r600_backend_map;
46 unsigned item_width, item_mask;
47
48 if (ctx->screen->chip_class >= EVERGREEN) {
49 item_width = 4;
50 item_mask = 0x7;
51 } else {
52 item_width = 2;
53 item_mask = 0x3;
54 }
55
56 while(num_tile_pipes--) {
57 i = backend_map & item_mask;
58 mask |= (1<<i);
59 backend_map >>= item_width;
60 }
61 if (mask != 0) {
62 ctx->backend_mask = mask;
63 return;
64 }
65 }
66
67 /* otherwise backup path for older kernels */
68
69 /* create buffer for event data */
70 buffer = (struct r600_resource*)
71 pipe_buffer_create(&ctx->screen->screen, PIPE_BIND_CUSTOM,
72 PIPE_USAGE_STAGING, ctx->max_db*16);
73 if (!buffer)
74 goto err;
75
76 /* initialize buffer with zeroes */
77 results = ctx->ws->buffer_map(buffer->buf, ctx->cs, PIPE_TRANSFER_WRITE);
78 if (results) {
79 memset(results, 0, ctx->max_db * 4 * 4);
80 ctx->ws->buffer_unmap(buffer->buf);
81
82 /* emit EVENT_WRITE for ZPASS_DONE */
83 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
84 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
85 ctx->pm4[ctx->pm4_cdwords++] = 0;
86 ctx->pm4[ctx->pm4_cdwords++] = 0;
87
88 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
89 ctx->pm4[ctx->pm4_cdwords++] = r600_context_bo_reloc(ctx, buffer, RADEON_USAGE_WRITE);
90
91 /* analyze results */
92 results = ctx->ws->buffer_map(buffer->buf, ctx->cs, PIPE_TRANSFER_READ);
93 if (results) {
94 for(i = 0; i < ctx->max_db; i++) {
95 /* at least highest bit will be set if backend is used */
96 if (results[i*4 + 1])
97 mask |= (1<<i);
98 }
99 ctx->ws->buffer_unmap(buffer->buf);
100 }
101 }
102
103 pipe_resource_reference((struct pipe_resource**)&buffer, NULL);
104
105 if (mask != 0) {
106 ctx->backend_mask = mask;
107 return;
108 }
109
110 err:
111 /* fallback to old method - set num_backends lower bits to 1 */
112 ctx->backend_mask = (~((u32)0))>>(32-num_backends);
113 return;
114 }
115
116 static inline void r600_context_ps_partial_flush(struct r600_context *ctx)
117 {
118 if (!(ctx->flags & R600_CONTEXT_DRAW_PENDING))
119 return;
120
121 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
122 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
123
124 ctx->flags &= ~R600_CONTEXT_DRAW_PENDING;
125 }
126
127 void r600_init_cs(struct r600_context *ctx)
128 {
129 /* R6xx requires this packet at the start of each command buffer */
130 if (ctx->screen->family < CHIP_RV770) {
131 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_START_3D_CMDBUF, 0, 0);
132 ctx->pm4[ctx->pm4_cdwords++] = 0x00000000;
133 }
134 /* All asics require this one */
135 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_CONTEXT_CONTROL, 1, 0);
136 ctx->pm4[ctx->pm4_cdwords++] = 0x80000000;
137 ctx->pm4[ctx->pm4_cdwords++] = 0x80000000;
138
139 ctx->init_dwords = ctx->pm4_cdwords;
140 }
141
142 static void r600_init_block(struct r600_context *ctx,
143 struct r600_block *block,
144 const struct r600_reg *reg, int index, int nreg,
145 unsigned opcode, unsigned offset_base)
146 {
147 int i = index;
148 int j, n = nreg;
149
150 /* initialize block */
151 if (opcode == PKT3_SET_RESOURCE) {
152 block->flags = BLOCK_FLAG_RESOURCE;
153 block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY; /* dirty all blocks at start */
154 } else {
155 block->flags = 0;
156 block->status |= R600_BLOCK_STATUS_DIRTY; /* dirty all blocks at start */
157 }
158 block->start_offset = reg[i].offset;
159 block->pm4[block->pm4_ndwords++] = PKT3(opcode, n, 0);
160 block->pm4[block->pm4_ndwords++] = (block->start_offset - offset_base) >> 2;
161 block->reg = &block->pm4[block->pm4_ndwords];
162 block->pm4_ndwords += n;
163 block->nreg = n;
164 block->nreg_dirty = n;
165 LIST_INITHEAD(&block->list);
166 LIST_INITHEAD(&block->enable_list);
167
168 for (j = 0; j < n; j++) {
169 if (reg[i+j].flags & REG_FLAG_DIRTY_ALWAYS) {
170 block->flags |= REG_FLAG_DIRTY_ALWAYS;
171 }
172 if (reg[i+j].flags & REG_FLAG_ENABLE_ALWAYS) {
173 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
174 block->status |= R600_BLOCK_STATUS_ENABLED;
175 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
176 LIST_ADDTAIL(&block->list,&ctx->dirty);
177 }
178 }
179 if (reg[i+j].flags & REG_FLAG_FLUSH_CHANGE) {
180 block->flags |= REG_FLAG_FLUSH_CHANGE;
181 }
182
183 if (reg[i+j].flags & REG_FLAG_NEED_BO) {
184 block->nbo++;
185 assert(block->nbo < R600_BLOCK_MAX_BO);
186 block->pm4_bo_index[j] = block->nbo;
187 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0, 0);
188 block->pm4[block->pm4_ndwords++] = 0x00000000;
189 if (reg[i+j].flags & REG_FLAG_RV6XX_SBU) {
190 block->reloc[block->nbo].flush_flags = 0;
191 block->reloc[block->nbo].flush_mask = 0;
192 } else {
193 block->reloc[block->nbo].flush_flags = reg[i+j].flush_flags;
194 block->reloc[block->nbo].flush_mask = reg[i+j].flush_mask;
195 }
196 block->reloc[block->nbo].bo_pm4_index = block->pm4_ndwords - 1;
197 }
198 if ((ctx->screen->family > CHIP_R600) &&
199 (ctx->screen->family < CHIP_RV770) && reg[i+j].flags & REG_FLAG_RV6XX_SBU) {
200 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0);
201 block->pm4[block->pm4_ndwords++] = reg[i+j].flush_flags;
202 }
203 }
204 for (j = 0; j < n; j++) {
205 if (reg[i+j].flush_flags) {
206 block->pm4_flush_ndwords += 7;
207 }
208 }
209 /* check that we stay in limit */
210 assert(block->pm4_ndwords < R600_BLOCK_MAX_REG);
211 }
212
213 int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg,
214 unsigned opcode, unsigned offset_base)
215 {
216 struct r600_block *block;
217 struct r600_range *range;
218 int offset;
219
220 for (unsigned i = 0, n = 0; i < nreg; i += n) {
221 /* ignore new block balise */
222 if (reg[i].offset == GROUP_FORCE_NEW_BLOCK) {
223 n = 1;
224 continue;
225 }
226
227 /* ignore regs not on R600 on R600 */
228 if ((reg[i].flags & REG_FLAG_NOT_R600) && ctx->screen->family == CHIP_R600) {
229 n = 1;
230 continue;
231 }
232
233 /* register that need relocation are in their own group */
234 /* find number of consecutive registers */
235 n = 0;
236 offset = reg[i].offset;
237 while (reg[i + n].offset == offset) {
238 n++;
239 offset += 4;
240 if ((n + i) >= nreg)
241 break;
242 if (n >= (R600_BLOCK_MAX_REG - 2))
243 break;
244 }
245
246 /* allocate new block */
247 block = calloc(1, sizeof(struct r600_block));
248 if (block == NULL) {
249 return -ENOMEM;
250 }
251 ctx->nblocks++;
252 for (int j = 0; j < n; j++) {
253 range = &ctx->range[CTX_RANGE_ID(reg[i + j].offset)];
254 /* create block table if it doesn't exist */
255 if (!range->blocks)
256 range->blocks = calloc(1 << HASH_SHIFT, sizeof(void *));
257 if (!range->blocks)
258 return -1;
259
260 range->blocks[CTX_BLOCK_ID(reg[i + j].offset)] = block;
261 }
262
263 r600_init_block(ctx, block, reg, i, n, opcode, offset_base);
264
265 }
266 return 0;
267 }
268
269 /* R600/R700 configuration */
270 static const struct r600_reg r600_config_reg_list[] = {
271 {R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0},
272 {R_008C00_SQ_CONFIG, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
273 {R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
274 {R_008C08_SQ_GPR_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
275 {R_008C0C_SQ_THREAD_RESOURCE_MGMT, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
276 {R_008C10_SQ_STACK_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
277 {R_008C14_SQ_STACK_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
278 {R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
279 {R_009508_TA_CNTL_AUX, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
280 {R_009714_VC_ENHANCE, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
281 {R_009830_DB_DEBUG, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
282 {R_009838_DB_WATERMARKS, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
283 };
284
285 static const struct r600_reg r600_ctl_const_list[] = {
286 {R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0, 0},
287 {R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0, 0},
288 };
289
290 static const struct r600_reg r600_context_reg_list[] = {
291 {R_028350_SX_MISC, 0, 0, 0},
292 {R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0},
293 {R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0, 0, 0},
294 {R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0, 0, 0},
295 {R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0, 0, 0},
296 {R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0, 0, 0},
297 {R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0, 0, 0},
298 {R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0, 0, 0},
299 {R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0, 0, 0},
300 {R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0, 0, 0},
301 {R_0288C8_SQ_GS_VERT_ITEMSIZE, 0, 0, 0},
302 {R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0, 0},
303 {R_028A14_VGT_HOS_CNTL, 0, 0, 0},
304 {R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0, 0},
305 {R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0, 0},
306 {R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0, 0},
307 {R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0, 0},
308 {R_028A28_VGT_GROUP_FIRST_DECR, 0, 0, 0},
309 {R_028A2C_VGT_GROUP_DECR, 0, 0, 0},
310 {R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0, 0},
311 {R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0, 0},
312 {R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0, 0},
313 {R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0, 0},
314 {R_028A40_VGT_GS_MODE, 0, 0, 0},
315 {R_028A4C_PA_SC_MODE_CNTL, 0, 0, 0},
316 {R_028AB0_VGT_STRMOUT_EN, 0, 0, 0},
317 {R_028AB4_VGT_REUSE_OFF, 0, 0, 0},
318 {R_028AB8_VGT_VTX_CNT_EN, 0, 0, 0},
319 {R_028B20_VGT_STRMOUT_BUFFER_EN, 0, 0, 0},
320 {R_028028_DB_STENCIL_CLEAR, 0, 0, 0},
321 {R_02802C_DB_DEPTH_CLEAR, 0, 0, 0},
322 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
323 {R_028040_CB_COLOR0_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(0), 0},
324 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
325 {R_0280A0_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
326 {R_028060_CB_COLOR0_SIZE, 0, 0, 0},
327 {R_028080_CB_COLOR0_VIEW, 0, 0, 0},
328 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
329 {R_0280E0_CB_COLOR0_FRAG, REG_FLAG_NEED_BO, 0, 0},
330 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
331 {R_0280C0_CB_COLOR0_TILE, REG_FLAG_NEED_BO, 0, 0},
332 {R_028100_CB_COLOR0_MASK, 0, 0, 0},
333 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
334 {R_028044_CB_COLOR1_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(1), 0},
335 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
336 {R_0280A4_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
337 {R_028064_CB_COLOR1_SIZE, 0, 0, 0},
338 {R_028084_CB_COLOR1_VIEW, 0, 0, 0},
339 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
340 {R_0280E4_CB_COLOR1_FRAG, REG_FLAG_NEED_BO, 0, 0},
341 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
342 {R_0280C4_CB_COLOR1_TILE, REG_FLAG_NEED_BO, 0, 0},
343 {R_028104_CB_COLOR1_MASK, 0, 0, 0},
344 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
345 {R_028048_CB_COLOR2_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(2), 0},
346 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
347 {R_0280A8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
348 {R_028068_CB_COLOR2_SIZE, 0, 0, 0},
349 {R_028088_CB_COLOR2_VIEW, 0, 0, 0},
350 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
351 {R_0280E8_CB_COLOR2_FRAG, REG_FLAG_NEED_BO, 0, 0},
352 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
353 {R_0280C8_CB_COLOR2_TILE, REG_FLAG_NEED_BO, 0, 0},
354 {R_028108_CB_COLOR2_MASK, 0, 0, 0},
355 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
356 {R_02804C_CB_COLOR3_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(3), 0},
357 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
358 {R_0280AC_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
359 {R_02806C_CB_COLOR3_SIZE, 0, 0, 0},
360 {R_02808C_CB_COLOR3_VIEW, 0, 0, 0},
361 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
362 {R_0280EC_CB_COLOR3_FRAG, REG_FLAG_NEED_BO, 0, 0},
363 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
364 {R_0280CC_CB_COLOR3_TILE, REG_FLAG_NEED_BO, 0, 0},
365 {R_02810C_CB_COLOR3_MASK, 0, 0, 0},
366 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
367 {R_028050_CB_COLOR4_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(4), 0},
368 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
369 {R_0280B0_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
370 {R_028070_CB_COLOR4_SIZE, 0, 0, 0},
371 {R_028090_CB_COLOR4_VIEW, 0, 0, 0},
372 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
373 {R_0280F0_CB_COLOR4_FRAG, REG_FLAG_NEED_BO, 0, 0},
374 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
375 {R_0280D0_CB_COLOR4_TILE, REG_FLAG_NEED_BO, 0, 0},
376 {R_028110_CB_COLOR4_MASK, 0, 0, 0},
377 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
378 {R_028054_CB_COLOR5_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(5), 0},
379 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
380 {R_0280B4_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
381 {R_028074_CB_COLOR5_SIZE, 0, 0, 0},
382 {R_028094_CB_COLOR5_VIEW, 0, 0, 0},
383 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
384 {R_0280F4_CB_COLOR5_FRAG, REG_FLAG_NEED_BO, 0, 0},
385 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
386 {R_0280D4_CB_COLOR5_TILE, REG_FLAG_NEED_BO, 0, 0},
387 {R_028114_CB_COLOR5_MASK, 0, 0, 0},
388 {R_028058_CB_COLOR6_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(6), 0},
389 {R_0280B8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
390 {R_028078_CB_COLOR6_SIZE, 0, 0, 0},
391 {R_028098_CB_COLOR6_VIEW, 0, 0, 0},
392 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
393 {R_0280F8_CB_COLOR6_FRAG, REG_FLAG_NEED_BO, 0, 0},
394 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
395 {R_0280D8_CB_COLOR6_TILE, REG_FLAG_NEED_BO, 0, 0},
396 {R_028118_CB_COLOR6_MASK, 0, 0, 0},
397 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
398 {R_02805C_CB_COLOR7_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(7), 0},
399 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
400 {R_0280BC_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
401 {R_02807C_CB_COLOR7_SIZE, 0, 0, 0},
402 {R_02809C_CB_COLOR7_VIEW, 0, 0, 0},
403 {R_0280FC_CB_COLOR7_FRAG, REG_FLAG_NEED_BO, 0, 0},
404 {R_0280DC_CB_COLOR7_TILE, REG_FLAG_NEED_BO, 0, 0},
405 {R_02811C_CB_COLOR7_MASK, 0, 0, 0},
406 {R_028120_CB_CLEAR_RED, 0, 0, 0},
407 {R_028124_CB_CLEAR_GREEN, 0, 0, 0},
408 {R_028128_CB_CLEAR_BLUE, 0, 0, 0},
409 {R_02812C_CB_CLEAR_ALPHA, 0, 0, 0},
410 {R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0},
411 {R_028144_ALU_CONST_BUFFER_SIZE_PS_1, REG_FLAG_DIRTY_ALWAYS, 0, 0},
412 {R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0},
413 {R_028184_ALU_CONST_BUFFER_SIZE_VS_1, REG_FLAG_DIRTY_ALWAYS, 0, 0},
414 {R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
415 {R_028944_ALU_CONST_CACHE_PS_1, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
416 {R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
417 {R_028984_ALU_CONST_CACHE_VS_1, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
418 {R_02823C_CB_SHADER_MASK, 0, 0, 0},
419 {R_028238_CB_TARGET_MASK, 0, 0, 0},
420 {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0},
421 {R_028414_CB_BLEND_RED, 0, 0, 0},
422 {R_028418_CB_BLEND_GREEN, 0, 0, 0},
423 {R_02841C_CB_BLEND_BLUE, 0, 0, 0},
424 {R_028420_CB_BLEND_ALPHA, 0, 0, 0},
425 {R_028424_CB_FOG_RED, 0, 0, 0},
426 {R_028428_CB_FOG_GREEN, 0, 0, 0},
427 {R_02842C_CB_FOG_BLUE, 0, 0, 0},
428 {R_028430_DB_STENCILREFMASK, 0, 0, 0},
429 {R_028434_DB_STENCILREFMASK_BF, 0, 0, 0},
430 {R_028438_SX_ALPHA_REF, 0, 0, 0},
431 {R_0286DC_SPI_FOG_CNTL, 0, 0, 0},
432 {R_0286E0_SPI_FOG_FUNC_SCALE, 0, 0, 0},
433 {R_0286E4_SPI_FOG_FUNC_BIAS, 0, 0, 0},
434 {R_028780_CB_BLEND0_CONTROL, REG_FLAG_NOT_R600, 0, 0},
435 {R_028784_CB_BLEND1_CONTROL, REG_FLAG_NOT_R600, 0, 0},
436 {R_028788_CB_BLEND2_CONTROL, REG_FLAG_NOT_R600, 0, 0},
437 {R_02878C_CB_BLEND3_CONTROL, REG_FLAG_NOT_R600, 0, 0},
438 {R_028790_CB_BLEND4_CONTROL, REG_FLAG_NOT_R600, 0, 0},
439 {R_028794_CB_BLEND5_CONTROL, REG_FLAG_NOT_R600, 0, 0},
440 {R_028798_CB_BLEND6_CONTROL, REG_FLAG_NOT_R600, 0, 0},
441 {R_02879C_CB_BLEND7_CONTROL, REG_FLAG_NOT_R600, 0, 0},
442 {R_0287A0_CB_SHADER_CONTROL, 0, 0, 0},
443 {R_028800_DB_DEPTH_CONTROL, 0, 0, 0},
444 {R_028804_CB_BLEND_CONTROL, 0, 0, 0},
445 {R_028808_CB_COLOR_CONTROL, 0, 0, 0},
446 {R_02880C_DB_SHADER_CONTROL, 0, 0, 0},
447 {R_028C04_PA_SC_AA_CONFIG, 0, 0, 0},
448 {R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0, 0},
449 {R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, 0, 0, 0},
450 {R_028C30_CB_CLRCMP_CONTROL, 0, 0, 0},
451 {R_028C34_CB_CLRCMP_SRC, 0, 0, 0},
452 {R_028C38_CB_CLRCMP_DST, 0, 0, 0},
453 {R_028C3C_CB_CLRCMP_MSK, 0, 0, 0},
454 {R_028C48_PA_SC_AA_MASK, 0, 0, 0},
455 {R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0, 0, 0},
456 {R_028D44_DB_ALPHA_TO_MASK, 0, 0, 0},
457 {R_02800C_DB_DEPTH_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_DEPTH, 0},
458 {R_028000_DB_DEPTH_SIZE, 0, 0, 0},
459 {R_028004_DB_DEPTH_VIEW, 0, 0, 0},
460 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
461 {R_028010_DB_DEPTH_INFO, REG_FLAG_NEED_BO, 0, 0},
462 {R_028D0C_DB_RENDER_CONTROL, 0, 0, 0},
463 {R_028D10_DB_RENDER_OVERRIDE, 0, 0, 0},
464 {R_028D24_DB_HTILE_SURFACE, 0, 0, 0},
465 {R_028D30_DB_PRELOAD_CONTROL, 0, 0, 0},
466 {R_028D34_DB_PREFETCH_LIMIT, 0, 0, 0},
467 {R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0, 0},
468 {R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0, 0},
469 {R_028200_PA_SC_WINDOW_OFFSET, 0, 0, 0},
470 {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0, 0},
471 {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0, 0},
472 {R_02820C_PA_SC_CLIPRECT_RULE, 0, 0, 0},
473 {R_028210_PA_SC_CLIPRECT_0_TL, 0, 0, 0},
474 {R_028214_PA_SC_CLIPRECT_0_BR, 0, 0, 0},
475 {R_028218_PA_SC_CLIPRECT_1_TL, 0, 0, 0},
476 {R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0, 0},
477 {R_028220_PA_SC_CLIPRECT_2_TL, 0, 0, 0},
478 {R_028224_PA_SC_CLIPRECT_2_BR, 0, 0, 0},
479 {R_028228_PA_SC_CLIPRECT_3_TL, 0, 0, 0},
480 {R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0, 0},
481 {R_028230_PA_SC_EDGERULE, 0, 0, 0},
482 {R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0, 0},
483 {R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0},
484 {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0},
485 {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0},
486 {R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0},
487 {R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0},
488 {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0},
489 {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0},
490 {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0},
491 {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0},
492 {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0},
493 {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0},
494 {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0, 0},
495 {R_028810_PA_CL_CLIP_CNTL, 0, 0, 0},
496 {R_028814_PA_SU_SC_MODE_CNTL, 0, 0, 0},
497 {R_028818_PA_CL_VTE_CNTL, 0, 0, 0},
498 {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0, 0},
499 {R_028820_PA_CL_NANINF_CNTL, 0, 0, 0},
500 {R_028A00_PA_SU_POINT_SIZE, 0, 0, 0},
501 {R_028A04_PA_SU_POINT_MINMAX, 0, 0, 0},
502 {R_028A08_PA_SU_LINE_CNTL, 0, 0, 0},
503 {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0, 0},
504 {R_028A48_PA_SC_MPASS_PS_CNTL, 0, 0, 0},
505 {R_028C00_PA_SC_LINE_CNTL, 0, 0, 0},
506 {R_028C08_PA_SU_VTX_CNTL, 0, 0, 0},
507 {R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0},
508 {R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0},
509 {R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0},
510 {R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0, 0},
511 {R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0, 0},
512 {R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0, 0},
513 {R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0, 0},
514 {R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0, 0},
515 {R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0, 0},
516 {R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0, 0},
517 {R_028E20_PA_CL_UCP0_X, 0, 0, 0},
518 {R_028E24_PA_CL_UCP0_Y, 0, 0, 0},
519 {R_028E28_PA_CL_UCP0_Z, 0, 0, 0},
520 {R_028E2C_PA_CL_UCP0_W, 0, 0, 0},
521 {R_028E30_PA_CL_UCP1_X, 0, 0, 0},
522 {R_028E34_PA_CL_UCP1_Y, 0, 0, 0},
523 {R_028E38_PA_CL_UCP1_Z, 0, 0, 0},
524 {R_028E3C_PA_CL_UCP1_W, 0, 0, 0},
525 {R_028E40_PA_CL_UCP2_X, 0, 0, 0},
526 {R_028E44_PA_CL_UCP2_Y, 0, 0, 0},
527 {R_028E48_PA_CL_UCP2_Z, 0, 0, 0},
528 {R_028E4C_PA_CL_UCP2_W, 0, 0, 0},
529 {R_028E50_PA_CL_UCP3_X, 0, 0, 0},
530 {R_028E54_PA_CL_UCP3_Y, 0, 0, 0},
531 {R_028E58_PA_CL_UCP3_Z, 0, 0, 0},
532 {R_028E5C_PA_CL_UCP3_W, 0, 0, 0},
533 {R_028E60_PA_CL_UCP4_X, 0, 0, 0},
534 {R_028E64_PA_CL_UCP4_Y, 0, 0, 0},
535 {R_028E68_PA_CL_UCP4_Z, 0, 0, 0},
536 {R_028E6C_PA_CL_UCP4_W, 0, 0, 0},
537 {R_028E70_PA_CL_UCP5_X, 0, 0, 0},
538 {R_028E74_PA_CL_UCP5_Y, 0, 0, 0},
539 {R_028E78_PA_CL_UCP5_Z, 0, 0, 0},
540 {R_028E7C_PA_CL_UCP5_W, 0, 0, 0},
541 {R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0},
542 {R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0},
543 {R_028388_SQ_VTX_SEMANTIC_2, 0, 0, 0},
544 {R_02838C_SQ_VTX_SEMANTIC_3, 0, 0, 0},
545 {R_028390_SQ_VTX_SEMANTIC_4, 0, 0, 0},
546 {R_028394_SQ_VTX_SEMANTIC_5, 0, 0, 0},
547 {R_028398_SQ_VTX_SEMANTIC_6, 0, 0, 0},
548 {R_02839C_SQ_VTX_SEMANTIC_7, 0, 0, 0},
549 {R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0, 0},
550 {R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0, 0},
551 {R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0, 0},
552 {R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0, 0},
553 {R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0, 0},
554 {R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0, 0},
555 {R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0, 0},
556 {R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0, 0},
557 {R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0, 0},
558 {R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0, 0},
559 {R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0, 0},
560 {R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0, 0},
561 {R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0, 0},
562 {R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0, 0},
563 {R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0, 0},
564 {R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0, 0},
565 {R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0, 0},
566 {R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0, 0},
567 {R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0, 0},
568 {R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0, 0},
569 {R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0, 0},
570 {R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0},
571 {R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0},
572 {R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0},
573 {R_028614_SPI_VS_OUT_ID_0, 0, 0, 0},
574 {R_028618_SPI_VS_OUT_ID_1, 0, 0, 0},
575 {R_02861C_SPI_VS_OUT_ID_2, 0, 0, 0},
576 {R_028620_SPI_VS_OUT_ID_3, 0, 0, 0},
577 {R_028624_SPI_VS_OUT_ID_4, 0, 0, 0},
578 {R_028628_SPI_VS_OUT_ID_5, 0, 0, 0},
579 {R_02862C_SPI_VS_OUT_ID_6, 0, 0, 0},
580 {R_028630_SPI_VS_OUT_ID_7, 0, 0, 0},
581 {R_028634_SPI_VS_OUT_ID_8, 0, 0, 0},
582 {R_028638_SPI_VS_OUT_ID_9, 0, 0, 0},
583 {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0, 0},
584 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
585 {R_028858_SQ_PGM_START_VS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
586 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
587 {R_028868_SQ_PGM_RESOURCES_VS, 0, 0, 0},
588 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
589 {R_028894_SQ_PGM_START_FS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
590 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
591 {R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0, 0},
592 {R_0288D0_SQ_PGM_CF_OFFSET_VS, 0, 0, 0},
593 {R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0, 0},
594 {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0, 0},
595 {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0, 0},
596 {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0},
597 {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0, 0},
598 {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0, 0},
599 {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0, 0},
600 {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0, 0},
601 {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0, 0},
602 {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0, 0},
603 {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0, 0},
604 {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0, 0},
605 {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0, 0},
606 {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0, 0},
607 {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0, 0},
608 {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0, 0},
609 {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0, 0},
610 {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0, 0},
611 {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0, 0},
612 {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0, 0},
613 {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0, 0},
614 {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0, 0},
615 {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0, 0},
616 {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0, 0},
617 {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0, 0},
618 {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0, 0},
619 {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0, 0},
620 {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0, 0},
621 {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0, 0},
622 {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0, 0},
623 {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0},
624 {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0},
625 {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0},
626 {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0, 0},
627 {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0, 0},
628 {R_0286D8_SPI_INPUT_Z, 0, 0, 0},
629 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
630 {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
631 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
632 {R_028850_SQ_PGM_RESOURCES_PS, 0, 0, 0},
633 {R_028854_SQ_PGM_EXPORTS_PS, 0, 0, 0},
634 {R_0288CC_SQ_PGM_CF_OFFSET_PS, 0, 0, 0},
635 {R_028400_VGT_MAX_VTX_INDX, 0, 0, 0},
636 {R_028404_VGT_MIN_VTX_INDX, 0, 0, 0},
637 {R_028408_VGT_INDX_OFFSET, 0, 0, 0},
638 {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0},
639 {R_028A84_VGT_PRIMITIVEID_EN, 0, 0, 0},
640 {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0, 0},
641 {R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0, 0, 0},
642 {R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0, 0, 0},
643 };
644
645 /* SHADER RESOURCE R600/R700 */
646 int r600_resource_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride, struct r600_reg *reg, int nreg, unsigned offset_base)
647 {
648 int i;
649 struct r600_block *block;
650 range->blocks = calloc(nblocks, sizeof(struct r600_block *));
651 if (range->blocks == NULL)
652 return -ENOMEM;
653
654 reg[0].offset += offset;
655 for (i = 0; i < nblocks; i++) {
656 block = calloc(1, sizeof(struct r600_block));
657 if (block == NULL) {
658 return -ENOMEM;
659 }
660 ctx->nblocks++;
661 range->blocks[i] = block;
662 r600_init_block(ctx, block, reg, 0, nreg, PKT3_SET_RESOURCE, offset_base);
663
664 reg[0].offset += stride;
665 }
666 return 0;
667 }
668
669
670 static int r600_resource_range_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride)
671 {
672 struct r600_reg r600_shader_resource[] = {
673 {R_038000_RESOURCE0_WORD0, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
674 {R_038004_RESOURCE0_WORD1, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
675 {R_038008_RESOURCE0_WORD2, 0, 0, 0},
676 {R_03800C_RESOURCE0_WORD3, 0, 0, 0},
677 {R_038010_RESOURCE0_WORD4, 0, 0, 0},
678 {R_038014_RESOURCE0_WORD5, 0, 0, 0},
679 {R_038018_RESOURCE0_WORD6, 0, 0, 0},
680 };
681 unsigned nreg = Elements(r600_shader_resource);
682
683 return r600_resource_init(ctx, range, offset, nblocks, stride, r600_shader_resource, nreg, R600_RESOURCE_OFFSET);
684 }
685
686 /* SHADER SAMPLER R600/R700 */
687 static int r600_state_sampler_init(struct r600_context *ctx, u32 offset)
688 {
689 struct r600_reg r600_shader_sampler[] = {
690 {R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0, 0},
691 {R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0, 0},
692 {R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0, 0},
693 };
694 unsigned nreg = Elements(r600_shader_sampler);
695
696 for (int i = 0; i < nreg; i++) {
697 r600_shader_sampler[i].offset += offset;
698 }
699 return r600_context_add_block(ctx, r600_shader_sampler, nreg, PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET);
700 }
701
702 /* SHADER SAMPLER BORDER R600/R700 */
703 static int r600_state_sampler_border_init(struct r600_context *ctx, u32 offset)
704 {
705 struct r600_reg r600_shader_sampler_border[] = {
706 {R_00A400_TD_PS_SAMPLER0_BORDER_RED, 0, 0, 0},
707 {R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0, 0},
708 {R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0, 0},
709 {R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0, 0},
710 };
711 unsigned nreg = Elements(r600_shader_sampler_border);
712
713 for (int i = 0; i < nreg; i++) {
714 r600_shader_sampler_border[i].offset += offset;
715 }
716 return r600_context_add_block(ctx, r600_shader_sampler_border, nreg, PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET);
717 }
718
719 static int r600_loop_const_init(struct r600_context *ctx, u32 offset)
720 {
721 unsigned nreg = 32;
722 struct r600_reg r600_loop_consts[32];
723 int i;
724
725 for (i = 0; i < nreg; i++) {
726 r600_loop_consts[i].offset = R600_LOOP_CONST_OFFSET + ((offset + i) * 4);
727 r600_loop_consts[i].flags = REG_FLAG_DIRTY_ALWAYS;
728 r600_loop_consts[i].flush_flags = 0;
729 r600_loop_consts[i].flush_mask = 0;
730 }
731 return r600_context_add_block(ctx, r600_loop_consts, nreg, PKT3_SET_LOOP_CONST, R600_LOOP_CONST_OFFSET);
732 }
733
734 static void r600_free_resource_range(struct r600_context *ctx, struct r600_range *range, int nblocks)
735 {
736 struct r600_block *block;
737 int i;
738 for (i = 0; i < nblocks; i++) {
739 block = range->blocks[i];
740 if (block) {
741 for (int k = 1; k <= block->nbo; k++)
742 pipe_resource_reference((struct pipe_resource**)&block->reloc[k].bo, NULL);
743 free(block);
744 }
745 }
746 free(range->blocks);
747
748 }
749
750 /* initialize */
751 void r600_context_fini(struct r600_context *ctx)
752 {
753 struct r600_block *block;
754 struct r600_range *range;
755
756 for (int i = 0; i < NUM_RANGES; i++) {
757 if (!ctx->range[i].blocks)
758 continue;
759 for (int j = 0; j < (1 << HASH_SHIFT); j++) {
760 block = ctx->range[i].blocks[j];
761 if (block) {
762 for (int k = 0, offset = block->start_offset; k < block->nreg; k++, offset += 4) {
763 range = &ctx->range[CTX_RANGE_ID(offset)];
764 range->blocks[CTX_BLOCK_ID(offset)] = NULL;
765 }
766 for (int k = 1; k <= block->nbo; k++) {
767 pipe_resource_reference((struct pipe_resource**)&block->reloc[k].bo, NULL);
768 }
769 free(block);
770 }
771 }
772 free(ctx->range[i].blocks);
773 }
774 r600_free_resource_range(ctx, &ctx->ps_resources, ctx->num_ps_resources);
775 r600_free_resource_range(ctx, &ctx->vs_resources, ctx->num_vs_resources);
776 r600_free_resource_range(ctx, &ctx->fs_resources, ctx->num_fs_resources);
777 free(ctx->range);
778 free(ctx->blocks);
779 free(ctx->bo);
780 ctx->ws->cs_destroy(ctx->cs);
781
782 memset(ctx, 0, sizeof(struct r600_context));
783 }
784
785 static void r600_add_resource_block(struct r600_context *ctx, struct r600_range *range, int num_blocks, int *index)
786 {
787 int c = *index;
788 for (int j = 0; j < num_blocks; j++) {
789 if (!range->blocks[j])
790 continue;
791
792 ctx->blocks[c++] = range->blocks[j];
793 }
794 *index = c;
795 }
796
797 int r600_setup_block_table(struct r600_context *ctx)
798 {
799 /* setup block table */
800 int c = 0;
801 ctx->blocks = calloc(ctx->nblocks, sizeof(void*));
802 if (!ctx->blocks)
803 return -ENOMEM;
804 for (int i = 0; i < NUM_RANGES; i++) {
805 if (!ctx->range[i].blocks)
806 continue;
807 for (int j = 0, add; j < (1 << HASH_SHIFT); j++) {
808 if (!ctx->range[i].blocks[j])
809 continue;
810
811 add = 1;
812 for (int k = 0; k < c; k++) {
813 if (ctx->blocks[k] == ctx->range[i].blocks[j]) {
814 add = 0;
815 break;
816 }
817 }
818 if (add) {
819 assert(c < ctx->nblocks);
820 ctx->blocks[c++] = ctx->range[i].blocks[j];
821 j += (ctx->range[i].blocks[j]->nreg) - 1;
822 }
823 }
824 }
825
826 r600_add_resource_block(ctx, &ctx->ps_resources, ctx->num_ps_resources, &c);
827 r600_add_resource_block(ctx, &ctx->vs_resources, ctx->num_vs_resources, &c);
828 r600_add_resource_block(ctx, &ctx->fs_resources, ctx->num_fs_resources, &c);
829 return 0;
830 }
831
832 int r600_context_init(struct r600_context *ctx, struct r600_screen *screen)
833 {
834 int r;
835
836 memset(ctx, 0, sizeof(struct r600_context));
837 ctx->screen = screen;
838 ctx->ws = screen->ws;
839
840 LIST_INITHEAD(&ctx->active_query_list);
841
842 /* init dirty list */
843 LIST_INITHEAD(&ctx->dirty);
844 LIST_INITHEAD(&ctx->resource_dirty);
845 LIST_INITHEAD(&ctx->enable_list);
846
847 ctx->range = calloc(NUM_RANGES, sizeof(struct r600_range));
848 if (!ctx->range) {
849 r = -ENOMEM;
850 goto out_err;
851 }
852
853 /* add blocks */
854 r = r600_context_add_block(ctx, r600_config_reg_list,
855 Elements(r600_config_reg_list), PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET);
856 if (r)
857 goto out_err;
858 r = r600_context_add_block(ctx, r600_context_reg_list,
859 Elements(r600_context_reg_list), PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET);
860 if (r)
861 goto out_err;
862 r = r600_context_add_block(ctx, r600_ctl_const_list,
863 Elements(r600_ctl_const_list), PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET);
864 if (r)
865 goto out_err;
866
867 /* PS SAMPLER BORDER */
868 for (int j = 0, offset = 0; j < 18; j++, offset += 0x10) {
869 r = r600_state_sampler_border_init(ctx, offset);
870 if (r)
871 goto out_err;
872 }
873
874 /* VS SAMPLER BORDER */
875 for (int j = 0, offset = 0x200; j < 18; j++, offset += 0x10) {
876 r = r600_state_sampler_border_init(ctx, offset);
877 if (r)
878 goto out_err;
879 }
880 /* PS SAMPLER */
881 for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) {
882 r = r600_state_sampler_init(ctx, offset);
883 if (r)
884 goto out_err;
885 }
886 /* VS SAMPLER */
887 for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) {
888 r = r600_state_sampler_init(ctx, offset);
889 if (r)
890 goto out_err;
891 }
892
893 ctx->num_ps_resources = 160;
894 ctx->num_vs_resources = 160;
895 ctx->num_fs_resources = 16;
896 r = r600_resource_range_init(ctx, &ctx->ps_resources, 0, 160, 0x1c);
897 if (r)
898 goto out_err;
899 r = r600_resource_range_init(ctx, &ctx->vs_resources, 0x1180, 160, 0x1c);
900 if (r)
901 goto out_err;
902 r = r600_resource_range_init(ctx, &ctx->fs_resources, 0x2300, 16, 0x1c);
903 if (r)
904 goto out_err;
905
906 /* PS loop const */
907 r600_loop_const_init(ctx, 0);
908 /* VS loop const */
909 r600_loop_const_init(ctx, 32);
910
911 r = r600_setup_block_table(ctx);
912 if (r)
913 goto out_err;
914
915 ctx->cs = screen->ws->cs_create(screen->ws);
916
917 /* allocate cs variables */
918 ctx->bo = calloc(RADEON_MAX_CMDBUF_DWORDS, sizeof(void *));
919 if (ctx->bo == NULL) {
920 r = -ENOMEM;
921 goto out_err;
922 }
923 ctx->pm4 = ctx->cs->buf;
924
925 r600_init_cs(ctx);
926 ctx->max_db = 4;
927 return 0;
928 out_err:
929 r600_context_fini(ctx);
930 return r;
931 }
932
933 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
934 boolean count_draw_in)
935 {
936 /* The number of dwords we already used in the CS so far. */
937 num_dw += ctx->pm4_cdwords;
938
939 if (count_draw_in) {
940 /* The number of dwords all the dirty states would take. */
941 num_dw += ctx->pm4_dirty_cdwords;
942
943 /* The upper-bound of how much a draw command would take. */
944 num_dw += R600_MAX_DRAW_CS_DWORDS;
945 }
946
947 /* Count in queries_suspend. */
948 num_dw += ctx->num_cs_dw_queries_suspend;
949
950 /* Count in streamout_end at the end of CS. */
951 num_dw += ctx->num_cs_dw_streamout_end;
952
953 /* Count in render_condition(NULL) at the end of CS. */
954 if (ctx->predicate_drawing) {
955 num_dw += 3;
956 }
957
958 /* Count in framebuffer cache flushes at the end of CS. */
959 num_dw += ctx->num_dest_buffers * 7;
960
961 /* Save 16 dwords for the fence mechanism. */
962 num_dw += 16;
963
964 /* Flush if there's not enough space. */
965 if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
966 ctx->flush(ctx->pipe, RADEON_FLUSH_ASYNC);
967 }
968 }
969
970 /* Flushes all surfaces */
971 void r600_context_flush_all(struct r600_context *ctx, unsigned flush_flags)
972 {
973 r600_need_cs_space(ctx, 5, FALSE);
974
975 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
976 ctx->pm4[ctx->pm4_cdwords++] = flush_flags; /* CP_COHER_CNTL */
977 ctx->pm4[ctx->pm4_cdwords++] = 0xffffffff; /* CP_COHER_SIZE */
978 ctx->pm4[ctx->pm4_cdwords++] = 0; /* CP_COHER_BASE */
979 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A; /* POLL_INTERVAL */
980 }
981
982 void r600_context_bo_flush(struct r600_context *ctx, unsigned flush_flags,
983 unsigned flush_mask, struct r600_resource *bo)
984 {
985 uint64_t va = 0;
986
987 /* if bo has already been flushed */
988 if (!(~bo->cs_buf->last_flush & flush_flags)) {
989 bo->cs_buf->last_flush &= flush_mask;
990 return;
991 }
992
993 if ((ctx->screen->family < CHIP_RV770) &&
994 (G_0085F0_CB_ACTION_ENA(flush_flags) ||
995 G_0085F0_DB_ACTION_ENA(flush_flags))) {
996 if (ctx->flags & R600_CONTEXT_CHECK_EVENT_FLUSH) {
997 /* the rv670 seems to fail fbo-generatemipmap unless we flush the CB1 dest base ena */
998 if ((bo->cs_buf->binding & BO_BOUND_TEXTURE) &&
999 (flush_flags & S_0085F0_CB_ACTION_ENA(1))) {
1000 if ((ctx->screen->family == CHIP_RV670) ||
1001 (ctx->screen->family == CHIP_RS780) ||
1002 (ctx->screen->family == CHIP_RS880)) {
1003 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
1004 ctx->pm4[ctx->pm4_cdwords++] = S_0085F0_CB1_DEST_BASE_ENA(1); /* CP_COHER_CNTL */
1005 ctx->pm4[ctx->pm4_cdwords++] = 0xffffffff; /* CP_COHER_SIZE */
1006 ctx->pm4[ctx->pm4_cdwords++] = 0; /* CP_COHER_BASE */
1007 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A; /* POLL_INTERVAL */
1008 }
1009 }
1010
1011 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
1012 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
1013 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
1014 }
1015 } else {
1016 va = r600_resource_va(&ctx->screen->screen, (void *)bo);
1017 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
1018 ctx->pm4[ctx->pm4_cdwords++] = flush_flags;
1019 ctx->pm4[ctx->pm4_cdwords++] = (bo->buf->size + 255) >> 8;
1020 ctx->pm4[ctx->pm4_cdwords++] = va >> 8;
1021 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A;
1022 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1023 ctx->pm4[ctx->pm4_cdwords++] = r600_context_bo_reloc(ctx, bo, RADEON_USAGE_WRITE);
1024 }
1025 bo->cs_buf->last_flush = (bo->cs_buf->last_flush | flush_flags) & flush_mask;
1026 }
1027
1028 void r600_context_reg(struct r600_context *ctx,
1029 unsigned offset, unsigned value,
1030 unsigned mask)
1031 {
1032 struct r600_range *range;
1033 struct r600_block *block;
1034 unsigned id;
1035 unsigned new_val;
1036 int dirty;
1037
1038 range = &ctx->range[CTX_RANGE_ID(offset)];
1039 block = range->blocks[CTX_BLOCK_ID(offset)];
1040 id = (offset - block->start_offset) >> 2;
1041
1042 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
1043
1044 new_val = block->reg[id];
1045 new_val &= ~mask;
1046 new_val |= value;
1047 if (new_val != block->reg[id]) {
1048 dirty |= R600_BLOCK_STATUS_DIRTY;
1049 block->reg[id] = new_val;
1050 }
1051 if (dirty)
1052 r600_context_dirty_block(ctx, block, dirty, id);
1053 }
1054
1055 void r600_context_dirty_block(struct r600_context *ctx,
1056 struct r600_block *block,
1057 int dirty, int index)
1058 {
1059 if ((index + 1) > block->nreg_dirty)
1060 block->nreg_dirty = index + 1;
1061
1062 if ((dirty != (block->status & R600_BLOCK_STATUS_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) {
1063 block->status |= R600_BLOCK_STATUS_DIRTY;
1064 ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords;
1065 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
1066 block->status |= R600_BLOCK_STATUS_ENABLED;
1067 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
1068 }
1069 LIST_ADDTAIL(&block->list,&ctx->dirty);
1070
1071 if (block->flags & REG_FLAG_FLUSH_CHANGE) {
1072 r600_context_ps_partial_flush(ctx);
1073 }
1074 }
1075 }
1076
1077 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state)
1078 {
1079 struct r600_block *block;
1080 unsigned new_val;
1081 int dirty;
1082 for (int i = 0; i < state->nregs; i++) {
1083 unsigned id, reloc_id;
1084 struct r600_pipe_reg *reg = &state->regs[i];
1085
1086 block = reg->block;
1087 id = reg->id;
1088
1089 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
1090
1091 new_val = block->reg[id];
1092 new_val &= ~reg->mask;
1093 new_val |= reg->value;
1094 if (new_val != block->reg[id]) {
1095 block->reg[id] = new_val;
1096 dirty |= R600_BLOCK_STATUS_DIRTY;
1097 }
1098 if (block->flags & REG_FLAG_DIRTY_ALWAYS)
1099 dirty |= R600_BLOCK_STATUS_DIRTY;
1100 if (block->pm4_bo_index[id]) {
1101 /* find relocation */
1102 reloc_id = block->pm4_bo_index[id];
1103 pipe_resource_reference((struct pipe_resource**)&block->reloc[reloc_id].bo, &reg->bo->b.b.b);
1104 block->reloc[reloc_id].bo_usage = reg->bo_usage;
1105 /* always force dirty for relocs for now */
1106 dirty |= R600_BLOCK_STATUS_DIRTY;
1107 }
1108
1109 if (dirty)
1110 r600_context_dirty_block(ctx, block, dirty, id);
1111 }
1112 }
1113
1114 static void r600_context_dirty_resource_block(struct r600_context *ctx,
1115 struct r600_block *block,
1116 int dirty, int index)
1117 {
1118 block->nreg_dirty = index + 1;
1119
1120 if ((dirty != (block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) {
1121 block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1122 ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords;
1123 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
1124 block->status |= R600_BLOCK_STATUS_ENABLED;
1125 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
1126 }
1127 LIST_ADDTAIL(&block->list,&ctx->resource_dirty);
1128 }
1129 }
1130
1131 void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, struct r600_block *block)
1132 {
1133 int dirty;
1134 int num_regs = ctx->screen->chip_class >= EVERGREEN ? 8 : 7;
1135 boolean is_vertex;
1136
1137 if (state == NULL) {
1138 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_RESOURCE_DIRTY);
1139 if (block->reloc[1].bo)
1140 block->reloc[1].bo->cs_buf->binding &= ~BO_BOUND_TEXTURE;
1141
1142 pipe_resource_reference((struct pipe_resource**)&block->reloc[1].bo, NULL);
1143 pipe_resource_reference((struct pipe_resource**)&block->reloc[2].bo, NULL);
1144 LIST_DELINIT(&block->list);
1145 LIST_DELINIT(&block->enable_list);
1146 return;
1147 }
1148
1149 is_vertex = ((state->val[num_regs-1] & 0xc0000000) == 0xc0000000);
1150 dirty = block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY;
1151
1152 if (memcmp(block->reg, state->val, num_regs*4)) {
1153 memcpy(block->reg, state->val, num_regs * 4);
1154 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1155 }
1156
1157 /* if no BOs on block, force dirty */
1158 if (!block->reloc[1].bo || !block->reloc[2].bo)
1159 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1160
1161 if (!dirty) {
1162 if (is_vertex) {
1163 if (block->reloc[1].bo->buf != state->bo[0]->buf)
1164 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1165 } else {
1166 if ((block->reloc[1].bo->buf != state->bo[0]->buf) ||
1167 (block->reloc[2].bo->buf != state->bo[1]->buf))
1168 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1169 }
1170 }
1171
1172 if (dirty) {
1173 if (is_vertex) {
1174 /* VERTEX RESOURCE, we preted there is 2 bo to relocate so
1175 * we have single case btw VERTEX & TEXTURE resource
1176 */
1177 pipe_resource_reference((struct pipe_resource**)&block->reloc[1].bo, &state->bo[0]->b.b.b);
1178 block->reloc[1].bo_usage = state->bo_usage[0];
1179 pipe_resource_reference((struct pipe_resource**)&block->reloc[2].bo, NULL);
1180 } else {
1181 /* TEXTURE RESOURCE */
1182 pipe_resource_reference((struct pipe_resource**)&block->reloc[1].bo, &state->bo[0]->b.b.b);
1183 block->reloc[1].bo_usage = state->bo_usage[0];
1184 pipe_resource_reference((struct pipe_resource**)&block->reloc[2].bo, &state->bo[1]->b.b.b);
1185 block->reloc[2].bo_usage = state->bo_usage[1];
1186 state->bo[0]->cs_buf->binding |= BO_BOUND_TEXTURE;
1187 }
1188
1189 if (is_vertex)
1190 block->status |= R600_BLOCK_STATUS_RESOURCE_VERTEX;
1191 else
1192 block->status &= ~R600_BLOCK_STATUS_RESOURCE_VERTEX;
1193
1194 r600_context_dirty_resource_block(ctx, block, dirty, num_regs - 1);
1195 }
1196 }
1197
1198 void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
1199 {
1200 struct r600_block *block = ctx->ps_resources.blocks[rid];
1201
1202 r600_context_pipe_state_set_resource(ctx, state, block);
1203 }
1204
1205 void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
1206 {
1207 struct r600_block *block = ctx->vs_resources.blocks[rid];
1208
1209 r600_context_pipe_state_set_resource(ctx, state, block);
1210 }
1211
1212 void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
1213 {
1214 struct r600_block *block = ctx->fs_resources.blocks[rid];
1215
1216 r600_context_pipe_state_set_resource(ctx, state, block);
1217 }
1218
1219 static inline void r600_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
1220 {
1221 struct r600_range *range;
1222 struct r600_block *block;
1223 int i;
1224 int dirty;
1225
1226 range = &ctx->range[CTX_RANGE_ID(offset)];
1227 block = range->blocks[CTX_BLOCK_ID(offset)];
1228 if (state == NULL) {
1229 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
1230 LIST_DELINIT(&block->list);
1231 LIST_DELINIT(&block->enable_list);
1232 return;
1233 }
1234 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
1235 for (i = 0; i < 3; i++) {
1236 if (block->reg[i] != state->regs[i].value) {
1237 block->reg[i] = state->regs[i].value;
1238 dirty |= R600_BLOCK_STATUS_DIRTY;
1239 }
1240 }
1241
1242 if (dirty)
1243 r600_context_dirty_block(ctx, block, dirty, 2);
1244 }
1245
1246
1247 static inline void r600_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
1248 {
1249 struct r600_range *range;
1250 struct r600_block *block;
1251 int i;
1252 int dirty;
1253
1254 range = &ctx->range[CTX_RANGE_ID(offset)];
1255 block = range->blocks[CTX_BLOCK_ID(offset)];
1256 if (state == NULL) {
1257 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
1258 LIST_DELINIT(&block->list);
1259 LIST_DELINIT(&block->enable_list);
1260 return;
1261 }
1262 if (state->nregs <= 3) {
1263 return;
1264 }
1265 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
1266 for (i = 0; i < 4; i++) {
1267 if (block->reg[i] != state->regs[i + 3].value) {
1268 block->reg[i] = state->regs[i + 3].value;
1269 dirty |= R600_BLOCK_STATUS_DIRTY;
1270 }
1271 }
1272
1273 /* We have to flush the shaders before we change the border color
1274 * registers, or previous draw commands that haven't completed yet
1275 * will end up using the new border color. */
1276 if (dirty & R600_BLOCK_STATUS_DIRTY)
1277 r600_context_ps_partial_flush(ctx);
1278 if (dirty)
1279 r600_context_dirty_block(ctx, block, dirty, 3);
1280 }
1281
1282 void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
1283 {
1284 unsigned offset;
1285
1286 offset = 0x0003C000 + id * 0xc;
1287 r600_context_pipe_state_set_sampler(ctx, state, offset);
1288 offset = 0x0000A400 + id * 0x10;
1289 r600_context_pipe_state_set_sampler_border(ctx, state, offset);
1290 }
1291
1292 void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
1293 {
1294 unsigned offset;
1295
1296 offset = 0x0003C0D8 + id * 0xc;
1297 r600_context_pipe_state_set_sampler(ctx, state, offset);
1298 offset = 0x0000A600 + id * 0x10;
1299 r600_context_pipe_state_set_sampler_border(ctx, state, offset);
1300 }
1301
1302 struct r600_resource *r600_context_reg_bo(struct r600_context *ctx, unsigned offset)
1303 {
1304 struct r600_range *range;
1305 struct r600_block *block;
1306 unsigned id;
1307
1308 range = &ctx->range[CTX_RANGE_ID(offset)];
1309 block = range->blocks[CTX_BLOCK_ID(offset)];
1310 offset -= block->start_offset;
1311 id = block->pm4_bo_index[offset >> 2];
1312 if (block->reloc[id].bo) {
1313 return block->reloc[id].bo;
1314 }
1315 return NULL;
1316 }
1317
1318 void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block)
1319 {
1320 int optional = block->nbo == 0 && !(block->flags & REG_FLAG_DIRTY_ALWAYS);
1321 int cp_dwords = block->pm4_ndwords, start_dword = 0;
1322 int new_dwords = 0;
1323 int nbo = block->nbo;
1324
1325 if (block->nreg_dirty == 0 && optional) {
1326 goto out;
1327 }
1328
1329 if (nbo) {
1330 ctx->flags |= R600_CONTEXT_CHECK_EVENT_FLUSH;
1331
1332 for (int j = 0; j < block->nreg; j++) {
1333 if (block->pm4_bo_index[j]) {
1334 /* find relocation */
1335 struct r600_block_reloc *reloc = &block->reloc[block->pm4_bo_index[j]];
1336 if (reloc->bo) {
1337 block->pm4[reloc->bo_pm4_index] =
1338 r600_context_bo_reloc(ctx, reloc->bo, reloc->bo_usage);
1339 r600_context_bo_flush(ctx,
1340 reloc->flush_flags,
1341 reloc->flush_mask,
1342 reloc->bo);
1343 } else {
1344 block->pm4[reloc->bo_pm4_index] = 0;
1345 }
1346 nbo--;
1347 if (nbo == 0)
1348 break;
1349
1350 }
1351 }
1352 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
1353 }
1354
1355 optional &= (block->nreg_dirty != block->nreg);
1356 if (optional) {
1357 new_dwords = block->nreg_dirty;
1358 start_dword = ctx->pm4_cdwords;
1359 cp_dwords = new_dwords + 2;
1360 }
1361 memcpy(&ctx->pm4[ctx->pm4_cdwords], block->pm4, cp_dwords * 4);
1362 ctx->pm4_cdwords += cp_dwords;
1363
1364 if (optional) {
1365 uint32_t newword;
1366
1367 newword = ctx->pm4[start_dword];
1368 newword &= PKT_COUNT_C;
1369 newword |= PKT_COUNT_S(new_dwords);
1370 ctx->pm4[start_dword] = newword;
1371 }
1372 out:
1373 block->status ^= R600_BLOCK_STATUS_DIRTY;
1374 block->nreg_dirty = 0;
1375 LIST_DELINIT(&block->list);
1376 }
1377
1378 void r600_context_block_resource_emit_dirty(struct r600_context *ctx, struct r600_block *block)
1379 {
1380 int cp_dwords = block->pm4_ndwords;
1381 int nbo = block->nbo;
1382
1383 ctx->flags |= R600_CONTEXT_CHECK_EVENT_FLUSH;
1384
1385 if (block->status & R600_BLOCK_STATUS_RESOURCE_VERTEX) {
1386 nbo = 1;
1387 cp_dwords -= 2; /* don't copy the second NOP */
1388 }
1389
1390 for (int j = 0; j < nbo; j++) {
1391 if (block->pm4_bo_index[j]) {
1392 /* find relocation */
1393 struct r600_block_reloc *reloc = &block->reloc[block->pm4_bo_index[j]];
1394 block->pm4[reloc->bo_pm4_index] =
1395 r600_context_bo_reloc(ctx, reloc->bo, reloc->bo_usage);
1396 r600_context_bo_flush(ctx,
1397 reloc->flush_flags,
1398 reloc->flush_mask,
1399 reloc->bo);
1400 }
1401 }
1402 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
1403
1404 memcpy(&ctx->pm4[ctx->pm4_cdwords], block->pm4, cp_dwords * 4);
1405 ctx->pm4_cdwords += cp_dwords;
1406
1407 block->status ^= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1408 block->nreg_dirty = 0;
1409 LIST_DELINIT(&block->list);
1410 }
1411
1412 void r600_context_flush_dest_caches(struct r600_context *ctx)
1413 {
1414 struct r600_resource *cb[8];
1415 struct r600_resource *db;
1416 int i;
1417
1418 if (!(ctx->flags & R600_CONTEXT_DST_CACHES_DIRTY))
1419 return;
1420
1421 db = r600_context_reg_bo(ctx, R_02800C_DB_DEPTH_BASE);
1422 cb[0] = r600_context_reg_bo(ctx, R_028040_CB_COLOR0_BASE);
1423 cb[1] = r600_context_reg_bo(ctx, R_028044_CB_COLOR1_BASE);
1424 cb[2] = r600_context_reg_bo(ctx, R_028048_CB_COLOR2_BASE);
1425 cb[3] = r600_context_reg_bo(ctx, R_02804C_CB_COLOR3_BASE);
1426 cb[4] = r600_context_reg_bo(ctx, R_028050_CB_COLOR4_BASE);
1427 cb[5] = r600_context_reg_bo(ctx, R_028054_CB_COLOR5_BASE);
1428 cb[6] = r600_context_reg_bo(ctx, R_028058_CB_COLOR6_BASE);
1429 cb[7] = r600_context_reg_bo(ctx, R_02805C_CB_COLOR7_BASE);
1430
1431 ctx->flags |= R600_CONTEXT_CHECK_EVENT_FLUSH;
1432 /* flush the color buffers */
1433 for (i = 0; i < 8; i++) {
1434 if (!cb[i])
1435 continue;
1436
1437 r600_context_bo_flush(ctx,
1438 (S_0085F0_CB0_DEST_BASE_ENA(1) << i) |
1439 S_0085F0_CB_ACTION_ENA(1),
1440 0, cb[i]);
1441 }
1442 if (db) {
1443 r600_context_bo_flush(ctx, S_0085F0_DB_ACTION_ENA(1) | S_0085F0_DB_DEST_BASE_ENA(1), 0, db);
1444 }
1445 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
1446 ctx->flags &= ~R600_CONTEXT_DST_CACHES_DIRTY;
1447 }
1448
1449 void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw)
1450 {
1451 unsigned ndwords = 7;
1452 struct r600_block *dirty_block = NULL;
1453 struct r600_block *next_block;
1454 uint32_t *pm4;
1455
1456 if (draw->indices) {
1457 ndwords = 11;
1458 }
1459 /* when increasing ndwords, bump the max limit too */
1460 assert(ndwords <= R600_MAX_DRAW_CS_DWORDS);
1461
1462 /* queries need some special values
1463 * (this is non-zero if any query is active) */
1464 if (ctx->num_cs_dw_queries_suspend) {
1465 if (ctx->screen->family >= CHIP_RV770) {
1466 r600_context_reg(ctx,
1467 R_028D0C_DB_RENDER_CONTROL,
1468 S_028D0C_R700_PERFECT_ZPASS_COUNTS(1),
1469 S_028D0C_R700_PERFECT_ZPASS_COUNTS(1));
1470 }
1471 r600_context_reg(ctx,
1472 R_028D10_DB_RENDER_OVERRIDE,
1473 S_028D10_NOOP_CULL_DISABLE(1),
1474 S_028D10_NOOP_CULL_DISABLE(1));
1475 }
1476
1477 r600_need_cs_space(ctx, 0, TRUE);
1478 assert(ctx->pm4_cdwords + ctx->pm4_dirty_cdwords + ndwords < RADEON_MAX_CMDBUF_DWORDS);
1479
1480 /* enough room to copy packet */
1481 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &ctx->dirty, list) {
1482 r600_context_block_emit_dirty(ctx, dirty_block);
1483 }
1484
1485 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &ctx->resource_dirty, list) {
1486 r600_context_block_resource_emit_dirty(ctx, dirty_block);
1487 }
1488
1489 /* Enable stream out if needed. */
1490 if (ctx->streamout_start) {
1491 r600_context_streamout_begin(ctx);
1492 ctx->streamout_start = FALSE;
1493 }
1494
1495 /* draw packet */
1496 pm4 = &ctx->pm4[ctx->pm4_cdwords];
1497
1498 pm4[0] = PKT3(PKT3_INDEX_TYPE, 0, ctx->predicate_drawing);
1499 pm4[1] = draw->vgt_index_type;
1500 pm4[2] = PKT3(PKT3_NUM_INSTANCES, 0, ctx->predicate_drawing);
1501 pm4[3] = draw->vgt_num_instances;
1502 if (draw->indices) {
1503 pm4[4] = PKT3(PKT3_DRAW_INDEX, 3, ctx->predicate_drawing);
1504 pm4[5] = draw->indices_bo_offset;
1505 pm4[6] = 0;
1506 pm4[7] = draw->vgt_num_indices;
1507 pm4[8] = draw->vgt_draw_initiator;
1508 pm4[9] = PKT3(PKT3_NOP, 0, ctx->predicate_drawing);
1509 pm4[10] = r600_context_bo_reloc(ctx, draw->indices, RADEON_USAGE_READ);
1510 } else {
1511 pm4[4] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, ctx->predicate_drawing);
1512 pm4[5] = draw->vgt_num_indices;
1513 pm4[6] = draw->vgt_draw_initiator;
1514 }
1515 ctx->pm4_cdwords += ndwords;
1516
1517 ctx->flags |= (R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING);
1518
1519 /* all dirty state have been scheduled in current cs */
1520 ctx->pm4_dirty_cdwords = 0;
1521 }
1522
1523 void r600_context_flush(struct r600_context *ctx, unsigned flags)
1524 {
1525 struct r600_block *enable_block = NULL;
1526 bool queries_suspended = false;
1527 bool streamout_suspended = false;
1528
1529 if (ctx->pm4_cdwords == ctx->init_dwords)
1530 return;
1531
1532 /* suspend queries */
1533 if (ctx->num_cs_dw_queries_suspend) {
1534 r600_context_queries_suspend(ctx);
1535 queries_suspended = true;
1536 }
1537
1538 if (ctx->num_cs_dw_streamout_end) {
1539 r600_context_streamout_end(ctx);
1540 streamout_suspended = true;
1541 }
1542
1543 if (ctx->screen->chip_class >= EVERGREEN)
1544 evergreen_context_flush_dest_caches(ctx);
1545 else
1546 r600_context_flush_dest_caches(ctx);
1547
1548 /* partial flush is needed to avoid lockups on some chips with user fences */
1549 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
1550 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
1551
1552 /* Flush the CS. */
1553 ctx->cs->cdw = ctx->pm4_cdwords;
1554 ctx->ws->cs_flush(ctx->cs, flags);
1555
1556 /* We need to get the pointer to the other CS,
1557 * the command streams are double-buffered. */
1558 ctx->pm4 = ctx->cs->buf;
1559
1560 /* restart */
1561 for (int i = 0; i < ctx->creloc; i++) {
1562 ctx->bo[i]->cs_buf->last_flush = 0;
1563 pipe_resource_reference((struct pipe_resource**)&ctx->bo[i], NULL);
1564 }
1565 ctx->creloc = 0;
1566 ctx->pm4_dirty_cdwords = 0;
1567 ctx->pm4_cdwords = 0;
1568 ctx->flags = 0;
1569
1570 r600_init_cs(ctx);
1571
1572 if (streamout_suspended) {
1573 ctx->streamout_start = TRUE;
1574 ctx->streamout_append_bitmask = ~0;
1575 }
1576
1577 /* resume queries */
1578 if (queries_suspended) {
1579 r600_context_queries_resume(ctx);
1580 }
1581
1582 /* set all valid group as dirty so they get reemited on
1583 * next draw command
1584 */
1585 LIST_FOR_EACH_ENTRY(enable_block, &ctx->enable_list, enable_list) {
1586 if (!(enable_block->flags & BLOCK_FLAG_RESOURCE)) {
1587 if(!(enable_block->status & R600_BLOCK_STATUS_DIRTY)) {
1588 LIST_ADDTAIL(&enable_block->list,&ctx->dirty);
1589 enable_block->status |= R600_BLOCK_STATUS_DIRTY;
1590 }
1591 } else {
1592 if(!(enable_block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY)) {
1593 LIST_ADDTAIL(&enable_block->list,&ctx->resource_dirty);
1594 enable_block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1595 }
1596 }
1597 ctx->pm4_dirty_cdwords += enable_block->pm4_ndwords +
1598 enable_block->pm4_flush_ndwords;
1599 enable_block->nreg_dirty = enable_block->nreg;
1600 }
1601 }
1602
1603 void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence_bo, unsigned offset, unsigned value)
1604 {
1605 uint64_t va;
1606
1607 r600_need_cs_space(ctx, 10, FALSE);
1608
1609 va = r600_resource_va(&ctx->screen->screen, (void*)fence_bo);
1610 va = va + (offset << 2);
1611
1612 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
1613 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
1614 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1615 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1616 ctx->pm4[ctx->pm4_cdwords++] = va & 0xFFFFFFFFUL; /* ADDRESS_LO */
1617 /* DATA_SEL | INT_EN | ADDRESS_HI */
1618 ctx->pm4[ctx->pm4_cdwords++] = (1 << 29) | (0 << 24) | ((va >> 32UL) & 0xFF);
1619 ctx->pm4[ctx->pm4_cdwords++] = value; /* DATA_LO */
1620 ctx->pm4[ctx->pm4_cdwords++] = 0; /* DATA_HI */
1621 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1622 ctx->pm4[ctx->pm4_cdwords++] = r600_context_bo_reloc(ctx, fence_bo, RADEON_USAGE_WRITE);
1623 }
1624
1625 static unsigned r600_query_read_result(char *map, unsigned start_index, unsigned end_index,
1626 bool test_status_bit)
1627 {
1628 uint32_t *current_result = (uint32_t*)map;
1629 uint64_t start, end;
1630
1631 start = (uint64_t)current_result[start_index] |
1632 (uint64_t)current_result[start_index+1] << 32;
1633 end = (uint64_t)current_result[end_index] |
1634 (uint64_t)current_result[end_index+1] << 32;
1635
1636 if (!test_status_bit ||
1637 ((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL))) {
1638 return end - start;
1639 }
1640 return 0;
1641 }
1642
1643 static boolean r600_query_result(struct r600_context *ctx, struct r600_query *query, boolean wait)
1644 {
1645 unsigned results_base = query->results_start;
1646 char *map;
1647
1648 map = ctx->ws->buffer_map(query->buffer->buf, ctx->cs,
1649 PIPE_TRANSFER_READ |
1650 (wait ? 0 : PIPE_TRANSFER_DONTBLOCK));
1651 if (!map)
1652 return FALSE;
1653
1654 /* count all results across all data blocks */
1655 switch (query->type) {
1656 case PIPE_QUERY_OCCLUSION_COUNTER:
1657 while (results_base != query->results_end) {
1658 query->result.u64 +=
1659 r600_query_read_result(map + results_base, 0, 2, true);
1660 results_base = (results_base + 16) % query->buffer->b.b.b.width0;
1661 }
1662 break;
1663 case PIPE_QUERY_OCCLUSION_PREDICATE:
1664 while (results_base != query->results_end) {
1665 query->result.b = query->result.b ||
1666 r600_query_read_result(map + results_base, 0, 2, true) != 0;
1667 results_base = (results_base + 16) % query->buffer->b.b.b.width0;
1668 }
1669 break;
1670 case PIPE_QUERY_TIME_ELAPSED:
1671 while (results_base != query->results_end) {
1672 query->result.u64 +=
1673 r600_query_read_result(map + results_base, 0, 2, false);
1674 results_base = (results_base + query->result_size) % query->buffer->b.b.b.width0;
1675 }
1676 break;
1677 case PIPE_QUERY_PRIMITIVES_EMITTED:
1678 /* SAMPLE_STREAMOUTSTATS stores this structure:
1679 * {
1680 * u64 NumPrimitivesWritten;
1681 * u64 PrimitiveStorageNeeded;
1682 * }
1683 * We only need NumPrimitivesWritten here. */
1684 while (results_base != query->results_end) {
1685 query->result.u64 +=
1686 r600_query_read_result(map + results_base, 2, 6, true);
1687 results_base = (results_base + query->result_size) % query->buffer->b.b.b.width0;
1688 }
1689 break;
1690 case PIPE_QUERY_PRIMITIVES_GENERATED:
1691 /* Here we read PrimitiveStorageNeeded. */
1692 while (results_base != query->results_end) {
1693 query->result.u64 +=
1694 r600_query_read_result(map + results_base, 0, 4, true);
1695 results_base = (results_base + query->result_size) % query->buffer->b.b.b.width0;
1696 }
1697 break;
1698 case PIPE_QUERY_SO_STATISTICS:
1699 while (results_base != query->results_end) {
1700 query->result.so.num_primitives_written +=
1701 r600_query_read_result(map + results_base, 2, 6, true);
1702 query->result.so.primitives_storage_needed +=
1703 r600_query_read_result(map + results_base, 0, 4, true);
1704 results_base = (results_base + query->result_size) % query->buffer->b.b.b.width0;
1705 }
1706 break;
1707 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
1708 while (results_base != query->results_end) {
1709 query->result.b = query->result.b ||
1710 r600_query_read_result(map + results_base, 2, 6, true) !=
1711 r600_query_read_result(map + results_base, 0, 4, true);
1712 results_base = (results_base + query->result_size) % query->buffer->b.b.b.width0;
1713 }
1714 break;
1715 default:
1716 assert(0);
1717 }
1718
1719 query->results_start = query->results_end;
1720 ctx->ws->buffer_unmap(query->buffer->buf);
1721 return TRUE;
1722 }
1723
1724 void r600_query_begin(struct r600_context *ctx, struct r600_query *query)
1725 {
1726 unsigned new_results_end, i;
1727 u32 *results;
1728 uint64_t va;
1729
1730 r600_need_cs_space(ctx, query->num_cs_dw * 2, TRUE);
1731
1732 new_results_end = (query->results_end + query->result_size) % query->buffer->b.b.b.width0;
1733
1734 /* collect current results if query buffer is full */
1735 if (new_results_end == query->results_start) {
1736 r600_query_result(ctx, query, TRUE);
1737 }
1738
1739 switch (query->type) {
1740 case PIPE_QUERY_OCCLUSION_COUNTER:
1741 case PIPE_QUERY_OCCLUSION_PREDICATE:
1742 results = ctx->ws->buffer_map(query->buffer->buf, ctx->cs, PIPE_TRANSFER_WRITE);
1743 if (results) {
1744 results = (u32*)((char*)results + query->results_end);
1745 memset(results, 0, query->result_size);
1746
1747 /* Set top bits for unused backends */
1748 for (i = 0; i < ctx->max_db; i++) {
1749 if (!(ctx->backend_mask & (1<<i))) {
1750 results[(i * 4)+1] = 0x80000000;
1751 results[(i * 4)+3] = 0x80000000;
1752 }
1753 }
1754 ctx->ws->buffer_unmap(query->buffer->buf);
1755 }
1756 break;
1757 case PIPE_QUERY_TIME_ELAPSED:
1758 break;
1759 case PIPE_QUERY_PRIMITIVES_EMITTED:
1760 case PIPE_QUERY_PRIMITIVES_GENERATED:
1761 case PIPE_QUERY_SO_STATISTICS:
1762 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
1763 results = ctx->ws->buffer_map(query->buffer->buf, ctx->cs, PIPE_TRANSFER_WRITE);
1764 results = (u32*)((char*)results + query->results_end);
1765 memset(results, 0, query->result_size);
1766 ctx->ws->buffer_unmap(query->buffer->buf);
1767 break;
1768 default:
1769 assert(0);
1770 }
1771
1772 /* emit begin query */
1773 va = r600_resource_va(&ctx->screen->screen, (void*)query->buffer);
1774 va += query->results_end;
1775
1776 switch (query->type) {
1777 case PIPE_QUERY_OCCLUSION_COUNTER:
1778 case PIPE_QUERY_OCCLUSION_PREDICATE:
1779 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
1780 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
1781 ctx->pm4[ctx->pm4_cdwords++] = va;
1782 ctx->pm4[ctx->pm4_cdwords++] = (va >> 32UL) & 0xFF;
1783 break;
1784 case PIPE_QUERY_PRIMITIVES_EMITTED:
1785 case PIPE_QUERY_PRIMITIVES_GENERATED:
1786 case PIPE_QUERY_SO_STATISTICS:
1787 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
1788 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
1789 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_SAMPLE_STREAMOUTSTATS) | EVENT_INDEX(3);
1790 ctx->pm4[ctx->pm4_cdwords++] = query->results_end;
1791 ctx->pm4[ctx->pm4_cdwords++] = 0;
1792 break;
1793 case PIPE_QUERY_TIME_ELAPSED:
1794 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1795 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1796 ctx->pm4[ctx->pm4_cdwords++] = va;
1797 ctx->pm4[ctx->pm4_cdwords++] = (3 << 29) | ((va >> 32UL) & 0xFF);
1798 ctx->pm4[ctx->pm4_cdwords++] = 0;
1799 ctx->pm4[ctx->pm4_cdwords++] = 0;
1800 break;
1801 default:
1802 assert(0);
1803 }
1804 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1805 ctx->pm4[ctx->pm4_cdwords++] = r600_context_bo_reloc(ctx, query->buffer, RADEON_USAGE_WRITE);
1806
1807 ctx->num_cs_dw_queries_suspend += query->num_cs_dw;
1808 }
1809
1810 void r600_query_end(struct r600_context *ctx, struct r600_query *query)
1811 {
1812 uint64_t va;
1813
1814 va = r600_resource_va(&ctx->screen->screen, (void*)query->buffer);
1815 /* emit end query */
1816 switch (query->type) {
1817 case PIPE_QUERY_OCCLUSION_COUNTER:
1818 case PIPE_QUERY_OCCLUSION_PREDICATE:
1819 va += query->results_end + 8;
1820 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
1821 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
1822 ctx->pm4[ctx->pm4_cdwords++] = va;
1823 ctx->pm4[ctx->pm4_cdwords++] = (va >> 32UL) & 0xFF;
1824 break;
1825 case PIPE_QUERY_PRIMITIVES_EMITTED:
1826 case PIPE_QUERY_PRIMITIVES_GENERATED:
1827 case PIPE_QUERY_SO_STATISTICS:
1828 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
1829 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
1830 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_SAMPLE_STREAMOUTSTATS) | EVENT_INDEX(3);
1831 ctx->pm4[ctx->pm4_cdwords++] = query->results_end + query->result_size/2;
1832 ctx->pm4[ctx->pm4_cdwords++] = 0;
1833 break;
1834 case PIPE_QUERY_TIME_ELAPSED:
1835 va += query->results_end + query->result_size/2;
1836 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1837 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1838 ctx->pm4[ctx->pm4_cdwords++] = va;
1839 ctx->pm4[ctx->pm4_cdwords++] = (3 << 29) | ((va >> 32UL) & 0xFF);
1840 ctx->pm4[ctx->pm4_cdwords++] = 0;
1841 ctx->pm4[ctx->pm4_cdwords++] = 0;
1842 break;
1843 default:
1844 assert(0);
1845 }
1846 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1847 ctx->pm4[ctx->pm4_cdwords++] = r600_context_bo_reloc(ctx, query->buffer, RADEON_USAGE_WRITE);
1848
1849 query->results_end = (query->results_end + query->result_size) % query->buffer->b.b.b.width0;
1850 ctx->num_cs_dw_queries_suspend -= query->num_cs_dw;
1851 }
1852
1853 void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation,
1854 int flag_wait)
1855 {
1856 uint64_t va;
1857
1858 if (operation == PREDICATION_OP_CLEAR) {
1859 r600_need_cs_space(ctx, 3, FALSE);
1860
1861 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SET_PREDICATION, 1, 0);
1862 ctx->pm4[ctx->pm4_cdwords++] = 0;
1863 ctx->pm4[ctx->pm4_cdwords++] = PRED_OP(PREDICATION_OP_CLEAR);
1864 } else {
1865 unsigned results_base = query->results_start;
1866 unsigned count;
1867 u32 op;
1868
1869 /* find count of the query data blocks */
1870 count = (query->buffer->b.b.b.width0 + query->results_end - query->results_start) % query->buffer->b.b.b.width0;
1871 count /= query->result_size;
1872
1873 r600_need_cs_space(ctx, 5 * count, TRUE);
1874
1875 op = PRED_OP(operation) | PREDICATION_DRAW_VISIBLE |
1876 (flag_wait ? PREDICATION_HINT_WAIT : PREDICATION_HINT_NOWAIT_DRAW);
1877 va = r600_resource_va(&ctx->screen->screen, (void*)query->buffer);
1878
1879 /* emit predicate packets for all data blocks */
1880 while (results_base != query->results_end) {
1881 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SET_PREDICATION, 1, 0);
1882 ctx->pm4[ctx->pm4_cdwords++] = (va + results_base) & 0xFFFFFFFFUL;
1883 ctx->pm4[ctx->pm4_cdwords++] = op | (((va + results_base) >> 32UL) & 0xFF);
1884 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
1885 ctx->pm4[ctx->pm4_cdwords++] = r600_context_bo_reloc(ctx, query->buffer,
1886 RADEON_USAGE_READ);
1887 results_base = (results_base + query->result_size) % query->buffer->b.b.b.width0;
1888
1889 /* set CONTINUE bit for all packets except the first */
1890 op |= PREDICATION_CONTINUE;
1891 }
1892 }
1893 }
1894
1895 struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type)
1896 {
1897 struct r600_query *query;
1898 unsigned buffer_size = 4096;
1899
1900 query = CALLOC_STRUCT(r600_query);
1901 if (query == NULL)
1902 return NULL;
1903
1904 query->type = query_type;
1905
1906 switch (query_type) {
1907 case PIPE_QUERY_OCCLUSION_COUNTER:
1908 case PIPE_QUERY_OCCLUSION_PREDICATE:
1909 query->result_size = 16 * ctx->max_db;
1910 query->num_cs_dw = 6;
1911 break;
1912 case PIPE_QUERY_TIME_ELAPSED:
1913 query->result_size = 16;
1914 query->num_cs_dw = 8;
1915 break;
1916 case PIPE_QUERY_PRIMITIVES_EMITTED:
1917 case PIPE_QUERY_PRIMITIVES_GENERATED:
1918 case PIPE_QUERY_SO_STATISTICS:
1919 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
1920 /* NumPrimitivesWritten, PrimitiveStorageNeeded. */
1921 query->result_size = 32;
1922 query->num_cs_dw = 6;
1923 break;
1924 default:
1925 assert(0);
1926 FREE(query);
1927 return NULL;
1928 }
1929
1930 /* adjust buffer size to simplify offsets wrapping math */
1931 buffer_size -= buffer_size % query->result_size;
1932
1933 /* Queries are normally read by the CPU after
1934 * being written by the gpu, hence staging is probably a good
1935 * usage pattern.
1936 */
1937 query->buffer = (struct r600_resource*)
1938 pipe_buffer_create(&ctx->screen->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STAGING, buffer_size);
1939 if (!query->buffer) {
1940 FREE(query);
1941 return NULL;
1942 }
1943 return query;
1944 }
1945
1946 void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query)
1947 {
1948 pipe_resource_reference((struct pipe_resource**)&query->buffer, NULL);
1949 free(query);
1950 }
1951
1952 boolean r600_context_query_result(struct r600_context *ctx,
1953 struct r600_query *query,
1954 boolean wait, void *vresult)
1955 {
1956 boolean *result_b = (boolean*)vresult;
1957 uint64_t *result_u64 = (uint64_t*)vresult;
1958 struct pipe_query_data_so_statistics *result_so =
1959 (struct pipe_query_data_so_statistics*)vresult;
1960
1961 if (!r600_query_result(ctx, query, wait))
1962 return FALSE;
1963
1964 switch (query->type) {
1965 case PIPE_QUERY_OCCLUSION_COUNTER:
1966 case PIPE_QUERY_PRIMITIVES_EMITTED:
1967 case PIPE_QUERY_PRIMITIVES_GENERATED:
1968 *result_u64 = query->result.u64;
1969 break;
1970 case PIPE_QUERY_OCCLUSION_PREDICATE:
1971 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
1972 *result_b = query->result.b;
1973 break;
1974 case PIPE_QUERY_TIME_ELAPSED:
1975 *result_u64 = (1000000 * query->result.u64) / ctx->screen->info.r600_clock_crystal_freq;
1976 break;
1977 case PIPE_QUERY_SO_STATISTICS:
1978 *result_so = query->result.so;
1979 break;
1980 default:
1981 assert(0);
1982 }
1983 return TRUE;
1984 }
1985
1986 void r600_context_queries_suspend(struct r600_context *ctx)
1987 {
1988 struct r600_query *query;
1989
1990 LIST_FOR_EACH_ENTRY(query, &ctx->active_query_list, list) {
1991 r600_query_end(ctx, query);
1992 }
1993 assert(ctx->num_cs_dw_queries_suspend == 0);
1994 }
1995
1996 void r600_context_queries_resume(struct r600_context *ctx)
1997 {
1998 struct r600_query *query;
1999
2000 assert(ctx->num_cs_dw_queries_suspend == 0);
2001
2002 LIST_FOR_EACH_ENTRY(query, &ctx->active_query_list, list) {
2003 r600_query_begin(ctx, query);
2004 }
2005 }
2006
2007 static void r600_flush_vgt_streamout(struct r600_context *ctx)
2008 {
2009 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SET_CONFIG_REG, 1, 0);
2010 ctx->pm4[ctx->pm4_cdwords++] = (R_008490_CP_STRMOUT_CNTL - R600_CONFIG_REG_OFFSET) >> 2;
2011 ctx->pm4[ctx->pm4_cdwords++] = 0;
2012
2013 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
2014 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0);
2015
2016 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_WAIT_REG_MEM, 5, 0);
2017 ctx->pm4[ctx->pm4_cdwords++] = WAIT_REG_MEM_EQUAL; /* wait until the register is equal to the reference value */
2018 ctx->pm4[ctx->pm4_cdwords++] = R_008490_CP_STRMOUT_CNTL >> 2; /* register */
2019 ctx->pm4[ctx->pm4_cdwords++] = 0;
2020 ctx->pm4[ctx->pm4_cdwords++] = S_008490_OFFSET_UPDATE_DONE(1); /* reference value */
2021 ctx->pm4[ctx->pm4_cdwords++] = S_008490_OFFSET_UPDATE_DONE(1); /* mask */
2022 ctx->pm4[ctx->pm4_cdwords++] = 4; /* poll interval */
2023 }
2024
2025 static void r600_set_streamout_enable(struct r600_context *ctx, unsigned buffer_enable_bit)
2026 {
2027 if (buffer_enable_bit) {
2028 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
2029 ctx->pm4[ctx->pm4_cdwords++] = (R_028AB0_VGT_STRMOUT_EN - R600_CONTEXT_REG_OFFSET) >> 2;
2030 ctx->pm4[ctx->pm4_cdwords++] = S_028AB0_STREAMOUT(1);
2031
2032 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
2033 ctx->pm4[ctx->pm4_cdwords++] = (R_028B20_VGT_STRMOUT_BUFFER_EN - R600_CONTEXT_REG_OFFSET) >> 2;
2034 ctx->pm4[ctx->pm4_cdwords++] = buffer_enable_bit;
2035 } else {
2036 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
2037 ctx->pm4[ctx->pm4_cdwords++] = (R_028AB0_VGT_STRMOUT_EN - R600_CONTEXT_REG_OFFSET) >> 2;
2038 ctx->pm4[ctx->pm4_cdwords++] = S_028AB0_STREAMOUT(0);
2039 }
2040 }
2041
2042 void r600_context_streamout_begin(struct r600_context *ctx)
2043 {
2044 struct r600_so_target **t = ctx->so_targets;
2045 unsigned *stride_in_dw = ctx->vs_so_stride_in_dw;
2046 unsigned buffer_en, i, update_flags = 0;
2047 uint64_t va;
2048
2049 buffer_en = (ctx->num_so_targets >= 1 && t[0] ? 1 : 0) |
2050 (ctx->num_so_targets >= 2 && t[1] ? 2 : 0) |
2051 (ctx->num_so_targets >= 3 && t[2] ? 4 : 0) |
2052 (ctx->num_so_targets >= 4 && t[3] ? 8 : 0);
2053
2054 ctx->num_cs_dw_streamout_end =
2055 12 + /* flush_vgt_streamout */
2056 util_bitcount(buffer_en) * 8 +
2057 8;
2058
2059 r600_need_cs_space(ctx,
2060 12 + /* flush_vgt_streamout */
2061 6 + /* enables */
2062 util_bitcount(buffer_en & ctx->streamout_append_bitmask) * 8 +
2063 util_bitcount(buffer_en & ~ctx->streamout_append_bitmask) * 6 +
2064 (ctx->screen->family > CHIP_R600 && ctx->screen->family < CHIP_RV770 ? 2 : 0) +
2065 ctx->num_cs_dw_streamout_end, TRUE);
2066
2067 if (ctx->screen->chip_class >= EVERGREEN) {
2068 evergreen_flush_vgt_streamout(ctx);
2069 evergreen_set_streamout_enable(ctx, buffer_en);
2070 } else {
2071 r600_flush_vgt_streamout(ctx);
2072 r600_set_streamout_enable(ctx, buffer_en);
2073 }
2074
2075 for (i = 0; i < ctx->num_so_targets; i++) {
2076 if (t[i]) {
2077 t[i]->stride_in_dw = stride_in_dw[i];
2078 t[i]->so_index = i;
2079 va = r600_resource_va(&ctx->screen->screen,
2080 (void*)t[i]->b.buffer);
2081
2082 update_flags |= SURFACE_BASE_UPDATE_STRMOUT(i);
2083
2084 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SET_CONTEXT_REG, 3, 0);
2085 ctx->pm4[ctx->pm4_cdwords++] = (R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 +
2086 16*i - R600_CONTEXT_REG_OFFSET) >> 2;
2087 ctx->pm4[ctx->pm4_cdwords++] = (t[i]->b.buffer_offset +
2088 t[i]->b.buffer_size) >> 2; /* BUFFER_SIZE (in DW) */
2089 ctx->pm4[ctx->pm4_cdwords++] = stride_in_dw[i]; /* VTX_STRIDE (in DW) */
2090 ctx->pm4[ctx->pm4_cdwords++] = va >> 8; /* BUFFER_BASE */
2091
2092 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
2093 ctx->pm4[ctx->pm4_cdwords++] =
2094 r600_context_bo_reloc(ctx, r600_resource(t[i]->b.buffer),
2095 RADEON_USAGE_WRITE);
2096
2097 if (ctx->streamout_append_bitmask & (1 << i)) {
2098 va = r600_resource_va(&ctx->screen->screen,
2099 (void*)t[i]->filled_size);
2100 /* Append. */
2101 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
2102 ctx->pm4[ctx->pm4_cdwords++] = STRMOUT_SELECT_BUFFER(i) |
2103 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM); /* control */
2104 ctx->pm4[ctx->pm4_cdwords++] = 0; /* unused */
2105 ctx->pm4[ctx->pm4_cdwords++] = 0; /* unused */
2106 ctx->pm4[ctx->pm4_cdwords++] = va & 0xFFFFFFFFUL; /* src address lo */
2107 ctx->pm4[ctx->pm4_cdwords++] = (va >> 32UL) & 0xFFUL; /* src address hi */
2108
2109 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
2110 ctx->pm4[ctx->pm4_cdwords++] =
2111 r600_context_bo_reloc(ctx, t[i]->filled_size,
2112 RADEON_USAGE_READ);
2113 } else {
2114 /* Start from the beginning. */
2115 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
2116 ctx->pm4[ctx->pm4_cdwords++] = STRMOUT_SELECT_BUFFER(i) |
2117 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET); /* control */
2118 ctx->pm4[ctx->pm4_cdwords++] = 0; /* unused */
2119 ctx->pm4[ctx->pm4_cdwords++] = 0; /* unused */
2120 ctx->pm4[ctx->pm4_cdwords++] = t[i]->b.buffer_offset >> 2; /* buffer offset in DW */
2121 ctx->pm4[ctx->pm4_cdwords++] = 0; /* unused */
2122 }
2123 }
2124 }
2125
2126 if (ctx->screen->family > CHIP_R600 && ctx->screen->family < CHIP_RV770) {
2127 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0);
2128 ctx->pm4[ctx->pm4_cdwords++] = update_flags;
2129 }
2130 }
2131
2132 void r600_context_streamout_end(struct r600_context *ctx)
2133 {
2134 struct r600_so_target **t = ctx->so_targets;
2135 unsigned i, flush_flags = 0;
2136 uint64_t va;
2137
2138 if (ctx->screen->chip_class >= EVERGREEN) {
2139 evergreen_flush_vgt_streamout(ctx);
2140 } else {
2141 r600_flush_vgt_streamout(ctx);
2142 }
2143
2144 for (i = 0; i < ctx->num_so_targets; i++) {
2145 if (t[i]) {
2146 va = r600_resource_va(&ctx->screen->screen,
2147 (void*)t[i]->filled_size);
2148 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
2149 ctx->pm4[ctx->pm4_cdwords++] = STRMOUT_SELECT_BUFFER(i) |
2150 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
2151 STRMOUT_STORE_BUFFER_FILLED_SIZE; /* control */
2152 ctx->pm4[ctx->pm4_cdwords++] = va & 0xFFFFFFFFUL; /* dst address lo */
2153 ctx->pm4[ctx->pm4_cdwords++] = (va >> 32UL) & 0xFFUL; /* dst address hi */
2154 ctx->pm4[ctx->pm4_cdwords++] = 0; /* unused */
2155 ctx->pm4[ctx->pm4_cdwords++] = 0; /* unused */
2156
2157 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
2158 ctx->pm4[ctx->pm4_cdwords++] =
2159 r600_context_bo_reloc(ctx, t[i]->filled_size,
2160 RADEON_USAGE_WRITE);
2161
2162 flush_flags |= S_0085F0_SO0_DEST_BASE_ENA(1) << i;
2163 }
2164 }
2165
2166 if (ctx->screen->chip_class >= EVERGREEN) {
2167 evergreen_set_streamout_enable(ctx, 0);
2168 } else {
2169 r600_set_streamout_enable(ctx, 0);
2170 }
2171
2172 if (ctx->screen->family < CHIP_RV770) {
2173 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
2174 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
2175 } else {
2176 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
2177 ctx->pm4[ctx->pm4_cdwords++] = flush_flags; /* CP_COHER_CNTL */
2178 ctx->pm4[ctx->pm4_cdwords++] = 0xffffffff; /* CP_COHER_SIZE */
2179 ctx->pm4[ctx->pm4_cdwords++] = 0; /* CP_COHER_BASE */
2180 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A; /* POLL_INTERVAL */
2181 }
2182
2183 ctx->num_cs_dw_streamout_end = 0;
2184
2185 #if 0
2186 for (i = 0; i < ctx->num_so_targets; i++) {
2187 if (!t[i])
2188 continue;
2189
2190 uint32_t *ptr = ctx->ws->buffer_map(t[i]->filled_size->buf, ctx->cs, RADEON_USAGE_READ);
2191 printf("FILLED_SIZE%i: %u\n", i, *ptr);
2192 ctx->ws->buffer_unmap(t[i]->filled_size->buf);
2193 }
2194 #endif
2195 }
2196
2197 void r600_context_draw_opaque_count(struct r600_context *ctx, struct r600_so_target *t)
2198 {
2199 uint64_t va = r600_resource_va(&ctx->screen->screen,
2200 (void*)t->filled_size);
2201
2202 r600_need_cs_space(ctx, 14 + 21, TRUE);
2203
2204 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
2205 ctx->pm4[ctx->pm4_cdwords++] = (R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET - R600_CONTEXT_REG_OFFSET) >> 2;
2206 ctx->pm4[ctx->pm4_cdwords++] = 0;
2207
2208 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
2209 ctx->pm4[ctx->pm4_cdwords++] = (R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE - R600_CONTEXT_REG_OFFSET) >> 2;
2210 ctx->pm4[ctx->pm4_cdwords++] = t->stride_in_dw;
2211
2212 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_COPY_DW, 4, 0);
2213 ctx->pm4[ctx->pm4_cdwords++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG;
2214 ctx->pm4[ctx->pm4_cdwords++] = va & 0xFFFFFFFFUL; /* src address lo */
2215 ctx->pm4[ctx->pm4_cdwords++] = (va >> 32UL) & 0xFFUL; /* src address hi */
2216 ctx->pm4[ctx->pm4_cdwords++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */
2217 ctx->pm4[ctx->pm4_cdwords++] = 0; /* unused */
2218
2219 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
2220 ctx->pm4[ctx->pm4_cdwords++] = r600_context_bo_reloc(ctx, t->filled_size,
2221 RADEON_USAGE_READ);
2222 }