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ee36a07e28ce12f6ba40d100a4400aab46c1cc17
[mesa.git] / src / gallium / drivers / r600 / r600_hw_context.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include "r600_hw_context_priv.h"
27 #include "r600d.h"
28 #include "util/u_memory.h"
29 #include <errno.h>
30
31 /* Get backends mask */
32 void r600_get_backend_mask(struct r600_context *ctx)
33 {
34 struct radeon_winsys_cs *cs = ctx->cs;
35 struct r600_resource *buffer;
36 uint32_t *results;
37 unsigned num_backends = ctx->screen->info.r600_num_backends;
38 unsigned i, mask = 0;
39
40 /* if backend_map query is supported by the kernel */
41 if (ctx->screen->info.r600_backend_map_valid) {
42 unsigned num_tile_pipes = ctx->screen->info.r600_num_tile_pipes;
43 unsigned backend_map = ctx->screen->info.r600_backend_map;
44 unsigned item_width, item_mask;
45
46 if (ctx->chip_class >= EVERGREEN) {
47 item_width = 4;
48 item_mask = 0x7;
49 } else {
50 item_width = 2;
51 item_mask = 0x3;
52 }
53
54 while(num_tile_pipes--) {
55 i = backend_map & item_mask;
56 mask |= (1<<i);
57 backend_map >>= item_width;
58 }
59 if (mask != 0) {
60 ctx->backend_mask = mask;
61 return;
62 }
63 }
64
65 /* otherwise backup path for older kernels */
66
67 /* create buffer for event data */
68 buffer = (struct r600_resource*)
69 pipe_buffer_create(&ctx->screen->screen, PIPE_BIND_CUSTOM,
70 PIPE_USAGE_STAGING, ctx->max_db*16);
71 if (!buffer)
72 goto err;
73
74 /* initialize buffer with zeroes */
75 results = ctx->ws->buffer_map(buffer->buf, ctx->cs, PIPE_TRANSFER_WRITE);
76 if (results) {
77 memset(results, 0, ctx->max_db * 4 * 4);
78 ctx->ws->buffer_unmap(buffer->buf);
79
80 /* emit EVENT_WRITE for ZPASS_DONE */
81 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
82 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
83 cs->buf[cs->cdw++] = 0;
84 cs->buf[cs->cdw++] = 0;
85
86 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
87 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, buffer, RADEON_USAGE_WRITE);
88
89 /* analyze results */
90 results = ctx->ws->buffer_map(buffer->buf, ctx->cs, PIPE_TRANSFER_READ);
91 if (results) {
92 for(i = 0; i < ctx->max_db; i++) {
93 /* at least highest bit will be set if backend is used */
94 if (results[i*4 + 1])
95 mask |= (1<<i);
96 }
97 ctx->ws->buffer_unmap(buffer->buf);
98 }
99 }
100
101 pipe_resource_reference((struct pipe_resource**)&buffer, NULL);
102
103 if (mask != 0) {
104 ctx->backend_mask = mask;
105 return;
106 }
107
108 err:
109 /* fallback to old method - set num_backends lower bits to 1 */
110 ctx->backend_mask = (~((uint32_t)0))>>(32-num_backends);
111 return;
112 }
113
114 void r600_context_ps_partial_flush(struct r600_context *ctx)
115 {
116 struct radeon_winsys_cs *cs = ctx->cs;
117
118 if (!(ctx->flags & R600_CONTEXT_DRAW_PENDING))
119 return;
120
121 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
122 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
123
124 ctx->flags &= ~R600_CONTEXT_DRAW_PENDING;
125 }
126
127 static void r600_init_block(struct r600_context *ctx,
128 struct r600_block *block,
129 const struct r600_reg *reg, int index, int nreg,
130 unsigned opcode, unsigned offset_base)
131 {
132 int i = index;
133 int j, n = nreg;
134
135 /* initialize block */
136 if (opcode == PKT3_SET_RESOURCE) {
137 block->flags = BLOCK_FLAG_RESOURCE;
138 block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY; /* dirty all blocks at start */
139 } else {
140 block->flags = 0;
141 block->status |= R600_BLOCK_STATUS_DIRTY; /* dirty all blocks at start */
142 }
143 block->start_offset = reg[i].offset;
144 block->pm4[block->pm4_ndwords++] = PKT3(opcode, n, 0);
145 block->pm4[block->pm4_ndwords++] = (block->start_offset - offset_base) >> 2;
146 block->reg = &block->pm4[block->pm4_ndwords];
147 block->pm4_ndwords += n;
148 block->nreg = n;
149 block->nreg_dirty = n;
150 LIST_INITHEAD(&block->list);
151 LIST_INITHEAD(&block->enable_list);
152
153 for (j = 0; j < n; j++) {
154 if (reg[i+j].flags & REG_FLAG_DIRTY_ALWAYS) {
155 block->flags |= REG_FLAG_DIRTY_ALWAYS;
156 }
157 if (reg[i+j].flags & REG_FLAG_ENABLE_ALWAYS) {
158 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
159 block->status |= R600_BLOCK_STATUS_ENABLED;
160 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
161 LIST_ADDTAIL(&block->list,&ctx->dirty);
162 }
163 }
164 if (reg[i+j].flags & REG_FLAG_FLUSH_CHANGE) {
165 block->flags |= REG_FLAG_FLUSH_CHANGE;
166 }
167
168 if (reg[i+j].flags & REG_FLAG_NEED_BO) {
169 block->nbo++;
170 assert(block->nbo < R600_BLOCK_MAX_BO);
171 block->pm4_bo_index[j] = block->nbo;
172 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0, 0);
173 block->pm4[block->pm4_ndwords++] = 0x00000000;
174 block->reloc[block->nbo].bo_pm4_index = block->pm4_ndwords - 1;
175 }
176 if ((ctx->family > CHIP_R600) &&
177 (ctx->family < CHIP_RV770) && reg[i+j].flags & REG_FLAG_RV6XX_SBU) {
178 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0);
179 block->pm4[block->pm4_ndwords++] = reg[i+j].sbu_flags;
180 }
181 }
182 /* check that we stay in limit */
183 assert(block->pm4_ndwords < R600_BLOCK_MAX_REG);
184 }
185
186 int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg,
187 unsigned opcode, unsigned offset_base)
188 {
189 struct r600_block *block;
190 struct r600_range *range;
191 int offset;
192
193 for (unsigned i = 0, n = 0; i < nreg; i += n) {
194 /* ignore new block balise */
195 if (reg[i].offset == GROUP_FORCE_NEW_BLOCK) {
196 n = 1;
197 continue;
198 }
199
200 /* ignore regs not on R600 on R600 */
201 if ((reg[i].flags & REG_FLAG_NOT_R600) && ctx->family == CHIP_R600) {
202 n = 1;
203 continue;
204 }
205
206 /* register that need relocation are in their own group */
207 /* find number of consecutive registers */
208 n = 0;
209 offset = reg[i].offset;
210 while (reg[i + n].offset == offset) {
211 n++;
212 offset += 4;
213 if ((n + i) >= nreg)
214 break;
215 if (n >= (R600_BLOCK_MAX_REG - 2))
216 break;
217 }
218
219 /* allocate new block */
220 block = calloc(1, sizeof(struct r600_block));
221 if (block == NULL) {
222 return -ENOMEM;
223 }
224 ctx->nblocks++;
225 for (int j = 0; j < n; j++) {
226 range = &ctx->range[CTX_RANGE_ID(reg[i + j].offset)];
227 /* create block table if it doesn't exist */
228 if (!range->blocks)
229 range->blocks = calloc(1 << HASH_SHIFT, sizeof(void *));
230 if (!range->blocks)
231 return -1;
232
233 range->blocks[CTX_BLOCK_ID(reg[i + j].offset)] = block;
234 }
235
236 r600_init_block(ctx, block, reg, i, n, opcode, offset_base);
237
238 }
239 return 0;
240 }
241
242 /* R600/R700 configuration */
243 static const struct r600_reg r600_config_reg_list[] = {
244 {R_008958_VGT_PRIMITIVE_TYPE, 0, 0},
245 {R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
246 {R_009508_TA_CNTL_AUX, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
247 };
248
249 static const struct r600_reg r600_ctl_const_list[] = {
250 {R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0},
251 };
252
253 static const struct r600_reg r600_context_reg_list[] = {
254 {R_028A4C_PA_SC_MODE_CNTL, 0, 0},
255 {GROUP_FORCE_NEW_BLOCK, 0, 0},
256 {R_028040_CB_COLOR0_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(0)},
257 {GROUP_FORCE_NEW_BLOCK, 0, 0},
258 {R_0280A0_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0},
259 {R_028060_CB_COLOR0_SIZE, 0, 0},
260 {R_028080_CB_COLOR0_VIEW, 0, 0},
261 {GROUP_FORCE_NEW_BLOCK, 0, 0},
262 {R_0280E0_CB_COLOR0_FRAG, REG_FLAG_NEED_BO, 0},
263 {GROUP_FORCE_NEW_BLOCK, 0, 0},
264 {R_0280C0_CB_COLOR0_TILE, REG_FLAG_NEED_BO, 0},
265 {GROUP_FORCE_NEW_BLOCK, 0, 0},
266 {R_028044_CB_COLOR1_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(1)},
267 {GROUP_FORCE_NEW_BLOCK, 0, 0},
268 {R_0280A4_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0},
269 {R_028064_CB_COLOR1_SIZE, 0, 0},
270 {R_028084_CB_COLOR1_VIEW, 0, 0},
271 {GROUP_FORCE_NEW_BLOCK, 0, 0},
272 {R_0280E4_CB_COLOR1_FRAG, REG_FLAG_NEED_BO, 0},
273 {GROUP_FORCE_NEW_BLOCK, 0, 0},
274 {R_0280C4_CB_COLOR1_TILE, REG_FLAG_NEED_BO, 0},
275 {GROUP_FORCE_NEW_BLOCK, 0, 0},
276 {R_028048_CB_COLOR2_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(2)},
277 {GROUP_FORCE_NEW_BLOCK, 0, 0},
278 {R_0280A8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0},
279 {R_028068_CB_COLOR2_SIZE, 0, 0},
280 {R_028088_CB_COLOR2_VIEW, 0, 0},
281 {GROUP_FORCE_NEW_BLOCK, 0, 0},
282 {R_0280E8_CB_COLOR2_FRAG, REG_FLAG_NEED_BO, 0},
283 {GROUP_FORCE_NEW_BLOCK, 0, 0},
284 {R_0280C8_CB_COLOR2_TILE, REG_FLAG_NEED_BO, 0},
285 {GROUP_FORCE_NEW_BLOCK, 0, 0},
286 {R_02804C_CB_COLOR3_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(3)},
287 {GROUP_FORCE_NEW_BLOCK, 0, 0},
288 {R_0280AC_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0},
289 {R_02806C_CB_COLOR3_SIZE, 0, 0},
290 {R_02808C_CB_COLOR3_VIEW, 0, 0},
291 {GROUP_FORCE_NEW_BLOCK, 0, 0},
292 {R_0280EC_CB_COLOR3_FRAG, REG_FLAG_NEED_BO, 0},
293 {GROUP_FORCE_NEW_BLOCK, 0, 0},
294 {R_0280CC_CB_COLOR3_TILE, REG_FLAG_NEED_BO, 0},
295 {GROUP_FORCE_NEW_BLOCK, 0, 0},
296 {R_028050_CB_COLOR4_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(4)},
297 {GROUP_FORCE_NEW_BLOCK, 0, 0},
298 {R_0280B0_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0},
299 {R_028070_CB_COLOR4_SIZE, 0, 0},
300 {R_028090_CB_COLOR4_VIEW, 0, 0},
301 {GROUP_FORCE_NEW_BLOCK, 0, 0},
302 {R_0280F0_CB_COLOR4_FRAG, REG_FLAG_NEED_BO, 0},
303 {GROUP_FORCE_NEW_BLOCK, 0, 0},
304 {R_0280D0_CB_COLOR4_TILE, REG_FLAG_NEED_BO, 0},
305 {GROUP_FORCE_NEW_BLOCK, 0, 0},
306 {R_028054_CB_COLOR5_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(5)},
307 {GROUP_FORCE_NEW_BLOCK, 0, 0},
308 {R_0280B4_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0},
309 {R_028074_CB_COLOR5_SIZE, 0, 0},
310 {R_028094_CB_COLOR5_VIEW, 0, 0},
311 {GROUP_FORCE_NEW_BLOCK, 0, 0},
312 {R_0280F4_CB_COLOR5_FRAG, REG_FLAG_NEED_BO, 0},
313 {GROUP_FORCE_NEW_BLOCK, 0, 0},
314 {R_0280D4_CB_COLOR5_TILE, REG_FLAG_NEED_BO, 0},
315 {R_028058_CB_COLOR6_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(6)},
316 {R_0280B8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0},
317 {R_028078_CB_COLOR6_SIZE, 0, 0},
318 {R_028098_CB_COLOR6_VIEW, 0, 0},
319 {GROUP_FORCE_NEW_BLOCK, 0, 0},
320 {R_0280F8_CB_COLOR6_FRAG, REG_FLAG_NEED_BO, 0},
321 {GROUP_FORCE_NEW_BLOCK, 0, 0},
322 {R_0280D8_CB_COLOR6_TILE, REG_FLAG_NEED_BO, 0},
323 {GROUP_FORCE_NEW_BLOCK, 0, 0},
324 {R_02805C_CB_COLOR7_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(7)},
325 {GROUP_FORCE_NEW_BLOCK, 0, 0},
326 {R_0280BC_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0},
327 {R_02807C_CB_COLOR7_SIZE, 0, 0},
328 {R_02809C_CB_COLOR7_VIEW, 0, 0},
329 {R_0280FC_CB_COLOR7_FRAG, REG_FLAG_NEED_BO, 0},
330 {R_0280DC_CB_COLOR7_TILE, REG_FLAG_NEED_BO, 0},
331 {R_028120_CB_CLEAR_RED, 0, 0},
332 {R_028124_CB_CLEAR_GREEN, 0, 0},
333 {R_028128_CB_CLEAR_BLUE, 0, 0},
334 {R_02812C_CB_CLEAR_ALPHA, 0, 0},
335 {R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0},
336 {R_028144_ALU_CONST_BUFFER_SIZE_PS_1, REG_FLAG_DIRTY_ALWAYS, 0},
337 {R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0},
338 {R_028184_ALU_CONST_BUFFER_SIZE_VS_1, REG_FLAG_DIRTY_ALWAYS, 0},
339 {R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, 0},
340 {R_028944_ALU_CONST_CACHE_PS_1, REG_FLAG_NEED_BO, 0},
341 {R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, 0},
342 {R_028984_ALU_CONST_CACHE_VS_1, REG_FLAG_NEED_BO, 0},
343 {R_02823C_CB_SHADER_MASK, 0, 0},
344 {R_028238_CB_TARGET_MASK, 0, 0},
345 {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0},
346 {R_028414_CB_BLEND_RED, 0, 0},
347 {R_028418_CB_BLEND_GREEN, 0, 0},
348 {R_02841C_CB_BLEND_BLUE, 0, 0},
349 {R_028420_CB_BLEND_ALPHA, 0, 0},
350 {R_028424_CB_FOG_RED, 0, 0},
351 {R_028428_CB_FOG_GREEN, 0, 0},
352 {R_02842C_CB_FOG_BLUE, 0, 0},
353 {R_028430_DB_STENCILREFMASK, 0, 0},
354 {R_028434_DB_STENCILREFMASK_BF, 0, 0},
355 {R_028438_SX_ALPHA_REF, 0, 0},
356 {R_028780_CB_BLEND0_CONTROL, REG_FLAG_NOT_R600, 0},
357 {R_028784_CB_BLEND1_CONTROL, REG_FLAG_NOT_R600, 0},
358 {R_028788_CB_BLEND2_CONTROL, REG_FLAG_NOT_R600, 0},
359 {R_02878C_CB_BLEND3_CONTROL, REG_FLAG_NOT_R600, 0},
360 {R_028790_CB_BLEND4_CONTROL, REG_FLAG_NOT_R600, 0},
361 {R_028794_CB_BLEND5_CONTROL, REG_FLAG_NOT_R600, 0},
362 {R_028798_CB_BLEND6_CONTROL, REG_FLAG_NOT_R600, 0},
363 {R_02879C_CB_BLEND7_CONTROL, REG_FLAG_NOT_R600, 0},
364 {R_0287A0_CB_SHADER_CONTROL, 0, 0},
365 {R_028800_DB_DEPTH_CONTROL, 0, 0},
366 {R_028804_CB_BLEND_CONTROL, 0, 0},
367 {R_028808_CB_COLOR_CONTROL, 0, 0},
368 {R_02880C_DB_SHADER_CONTROL, 0, 0},
369 {R_02800C_DB_DEPTH_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_DEPTH},
370 {R_028000_DB_DEPTH_SIZE, 0, 0},
371 {R_028004_DB_DEPTH_VIEW, 0, 0},
372 {GROUP_FORCE_NEW_BLOCK, 0, 0},
373 {R_028010_DB_DEPTH_INFO, REG_FLAG_NEED_BO, 0},
374 {R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0, 0},
375 {R_028D24_DB_HTILE_SURFACE, 0, 0},
376 {R_028D34_DB_PREFETCH_LIMIT, 0, 0},
377 {R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0},
378 {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
379 {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
380 {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0},
381 {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
382 {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0},
383 {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0},
384 {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0},
385 {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0},
386 {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0},
387 {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0},
388 {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0},
389 {R_028810_PA_CL_CLIP_CNTL, 0, 0},
390 {R_028814_PA_SU_SC_MODE_CNTL, 0, 0},
391 {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0},
392 {R_028A00_PA_SU_POINT_SIZE, 0, 0},
393 {R_028A04_PA_SU_POINT_MINMAX, 0, 0},
394 {R_028A08_PA_SU_LINE_CNTL, 0, 0},
395 {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0},
396 {R_028C08_PA_SU_VTX_CNTL, 0, 0},
397 {R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0},
398 {R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0},
399 {R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0},
400 {R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0},
401 {R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0},
402 {R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0},
403 {R_028E20_PA_CL_UCP0_X, 0, 0},
404 {R_028E24_PA_CL_UCP0_Y, 0, 0},
405 {R_028E28_PA_CL_UCP0_Z, 0, 0},
406 {R_028E2C_PA_CL_UCP0_W, 0, 0},
407 {R_028E30_PA_CL_UCP1_X, 0, 0},
408 {R_028E34_PA_CL_UCP1_Y, 0, 0},
409 {R_028E38_PA_CL_UCP1_Z, 0, 0},
410 {R_028E3C_PA_CL_UCP1_W, 0, 0},
411 {R_028E40_PA_CL_UCP2_X, 0, 0},
412 {R_028E44_PA_CL_UCP2_Y, 0, 0},
413 {R_028E48_PA_CL_UCP2_Z, 0, 0},
414 {R_028E4C_PA_CL_UCP2_W, 0, 0},
415 {R_028E50_PA_CL_UCP3_X, 0, 0},
416 {R_028E54_PA_CL_UCP3_Y, 0, 0},
417 {R_028E58_PA_CL_UCP3_Z, 0, 0},
418 {R_028E5C_PA_CL_UCP3_W, 0, 0},
419 {R_028E60_PA_CL_UCP4_X, 0, 0},
420 {R_028E64_PA_CL_UCP4_Y, 0, 0},
421 {R_028E68_PA_CL_UCP4_Z, 0, 0},
422 {R_028E6C_PA_CL_UCP4_W, 0, 0},
423 {R_028E70_PA_CL_UCP5_X, 0, 0},
424 {R_028E74_PA_CL_UCP5_Y, 0, 0},
425 {R_028E78_PA_CL_UCP5_Z, 0, 0},
426 {R_028E7C_PA_CL_UCP5_W, 0, 0},
427 {R_028380_SQ_VTX_SEMANTIC_0, 0, 0},
428 {R_028384_SQ_VTX_SEMANTIC_1, 0, 0},
429 {R_028388_SQ_VTX_SEMANTIC_2, 0, 0},
430 {R_02838C_SQ_VTX_SEMANTIC_3, 0, 0},
431 {R_028390_SQ_VTX_SEMANTIC_4, 0, 0},
432 {R_028394_SQ_VTX_SEMANTIC_5, 0, 0},
433 {R_028398_SQ_VTX_SEMANTIC_6, 0, 0},
434 {R_02839C_SQ_VTX_SEMANTIC_7, 0, 0},
435 {R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0},
436 {R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0},
437 {R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0},
438 {R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0},
439 {R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0},
440 {R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0},
441 {R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0},
442 {R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0},
443 {R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0},
444 {R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0},
445 {R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0},
446 {R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0},
447 {R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0},
448 {R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0},
449 {R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0},
450 {R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0},
451 {R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0},
452 {R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0},
453 {R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0},
454 {R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0},
455 {R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0},
456 {R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0},
457 {R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0},
458 {R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0},
459 {R_028614_SPI_VS_OUT_ID_0, 0, 0},
460 {R_028618_SPI_VS_OUT_ID_1, 0, 0},
461 {R_02861C_SPI_VS_OUT_ID_2, 0, 0},
462 {R_028620_SPI_VS_OUT_ID_3, 0, 0},
463 {R_028624_SPI_VS_OUT_ID_4, 0, 0},
464 {R_028628_SPI_VS_OUT_ID_5, 0, 0},
465 {R_02862C_SPI_VS_OUT_ID_6, 0, 0},
466 {R_028630_SPI_VS_OUT_ID_7, 0, 0},
467 {R_028634_SPI_VS_OUT_ID_8, 0, 0},
468 {R_028638_SPI_VS_OUT_ID_9, 0, 0},
469 {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0},
470 {GROUP_FORCE_NEW_BLOCK, 0, 0},
471 {R_028858_SQ_PGM_START_VS, REG_FLAG_NEED_BO, 0},
472 {GROUP_FORCE_NEW_BLOCK, 0, 0},
473 {R_028868_SQ_PGM_RESOURCES_VS, 0, 0},
474 {GROUP_FORCE_NEW_BLOCK, 0, 0},
475 {R_028894_SQ_PGM_START_FS, REG_FLAG_NEED_BO, 0},
476 {GROUP_FORCE_NEW_BLOCK, 0, 0},
477 {R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0},
478 {R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0},
479 {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0},
480 {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0},
481 {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0},
482 {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0},
483 {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0},
484 {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0},
485 {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0},
486 {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0},
487 {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0},
488 {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0},
489 {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0},
490 {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0},
491 {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0},
492 {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0},
493 {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0},
494 {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0},
495 {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0},
496 {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0},
497 {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0},
498 {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0},
499 {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0},
500 {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0},
501 {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0},
502 {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0},
503 {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0},
504 {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0},
505 {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0},
506 {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0},
507 {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0},
508 {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0},
509 {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0},
510 {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0},
511 {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0},
512 {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0},
513 {R_0286D8_SPI_INPUT_Z, 0, 0},
514 {GROUP_FORCE_NEW_BLOCK, 0, 0},
515 {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0},
516 {GROUP_FORCE_NEW_BLOCK, 0, 0},
517 {R_028850_SQ_PGM_RESOURCES_PS, 0, 0},
518 {R_028854_SQ_PGM_EXPORTS_PS, 0, 0},
519 {R_028408_VGT_INDX_OFFSET, 0, 0},
520 {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0},
521 {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0},
522 };
523
524 /* SHADER RESOURCE R600/R700 */
525 int r600_resource_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride, struct r600_reg *reg, int nreg, unsigned offset_base)
526 {
527 int i;
528 struct r600_block *block;
529 range->blocks = calloc(nblocks, sizeof(struct r600_block *));
530 if (range->blocks == NULL)
531 return -ENOMEM;
532
533 reg[0].offset += offset;
534 for (i = 0; i < nblocks; i++) {
535 block = calloc(1, sizeof(struct r600_block));
536 if (block == NULL) {
537 return -ENOMEM;
538 }
539 ctx->nblocks++;
540 range->blocks[i] = block;
541 r600_init_block(ctx, block, reg, 0, nreg, PKT3_SET_RESOURCE, offset_base);
542
543 reg[0].offset += stride;
544 }
545 return 0;
546 }
547
548
549 static int r600_resource_range_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride)
550 {
551 struct r600_reg r600_shader_resource[] = {
552 {R_038000_RESOURCE0_WORD0, REG_FLAG_NEED_BO, 0},
553 {R_038004_RESOURCE0_WORD1, REG_FLAG_NEED_BO, 0},
554 {R_038008_RESOURCE0_WORD2, 0, 0},
555 {R_03800C_RESOURCE0_WORD3, 0, 0},
556 {R_038010_RESOURCE0_WORD4, 0, 0},
557 {R_038014_RESOURCE0_WORD5, 0, 0},
558 {R_038018_RESOURCE0_WORD6, 0, 0},
559 };
560 unsigned nreg = Elements(r600_shader_resource);
561
562 return r600_resource_init(ctx, range, offset, nblocks, stride, r600_shader_resource, nreg, R600_RESOURCE_OFFSET);
563 }
564
565 /* SHADER SAMPLER R600/R700/EG/CM */
566 int r600_state_sampler_init(struct r600_context *ctx, uint32_t offset)
567 {
568 struct r600_reg r600_shader_sampler[] = {
569 {R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0},
570 {R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0},
571 {R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0},
572 };
573 unsigned nreg = Elements(r600_shader_sampler);
574
575 for (int i = 0; i < nreg; i++) {
576 r600_shader_sampler[i].offset += offset;
577 }
578 return r600_context_add_block(ctx, r600_shader_sampler, nreg, PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET);
579 }
580
581 /* SHADER SAMPLER BORDER R600/R700 */
582 static int r600_state_sampler_border_init(struct r600_context *ctx, uint32_t offset)
583 {
584 struct r600_reg r600_shader_sampler_border[] = {
585 {R_00A400_TD_PS_SAMPLER0_BORDER_RED, 0, 0},
586 {R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0},
587 {R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0},
588 {R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0},
589 };
590 unsigned nreg = Elements(r600_shader_sampler_border);
591
592 for (int i = 0; i < nreg; i++) {
593 r600_shader_sampler_border[i].offset += offset;
594 }
595 return r600_context_add_block(ctx, r600_shader_sampler_border, nreg, PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET);
596 }
597
598 static int r600_loop_const_init(struct r600_context *ctx, uint32_t offset)
599 {
600 unsigned nreg = 32;
601 struct r600_reg r600_loop_consts[32];
602 int i;
603
604 for (i = 0; i < nreg; i++) {
605 r600_loop_consts[i].offset = R600_LOOP_CONST_OFFSET + ((offset + i) * 4);
606 r600_loop_consts[i].flags = REG_FLAG_DIRTY_ALWAYS;
607 r600_loop_consts[i].sbu_flags = 0;
608 }
609 return r600_context_add_block(ctx, r600_loop_consts, nreg, PKT3_SET_LOOP_CONST, R600_LOOP_CONST_OFFSET);
610 }
611
612 static void r600_free_resource_range(struct r600_context *ctx, struct r600_range *range, int nblocks)
613 {
614 struct r600_block *block;
615 int i;
616
617 if (!range->blocks) {
618 return; /* nothing to do */
619 }
620
621 for (i = 0; i < nblocks; i++) {
622 block = range->blocks[i];
623 if (block) {
624 for (int k = 1; k <= block->nbo; k++)
625 pipe_resource_reference((struct pipe_resource**)&block->reloc[k].bo, NULL);
626 free(block);
627 }
628 }
629 free(range->blocks);
630 }
631
632 /* initialize */
633 void r600_context_fini(struct r600_context *ctx)
634 {
635 struct r600_block *block;
636 struct r600_range *range;
637
638 if (ctx->range) {
639 for (int i = 0; i < NUM_RANGES; i++) {
640 if (!ctx->range[i].blocks)
641 continue;
642 for (int j = 0; j < (1 << HASH_SHIFT); j++) {
643 block = ctx->range[i].blocks[j];
644 if (block) {
645 for (int k = 0, offset = block->start_offset; k < block->nreg; k++, offset += 4) {
646 range = &ctx->range[CTX_RANGE_ID(offset)];
647 range->blocks[CTX_BLOCK_ID(offset)] = NULL;
648 }
649 for (int k = 1; k <= block->nbo; k++) {
650 pipe_resource_reference((struct pipe_resource**)&block->reloc[k].bo, NULL);
651 }
652 free(block);
653 }
654 }
655 free(ctx->range[i].blocks);
656 }
657 }
658 r600_free_resource_range(ctx, &ctx->ps_resources, ctx->num_ps_resources);
659 r600_free_resource_range(ctx, &ctx->vs_resources, ctx->num_vs_resources);
660 r600_free_resource_range(ctx, &ctx->fs_resources, ctx->num_fs_resources);
661 free(ctx->blocks);
662 }
663
664 static void r600_add_resource_block(struct r600_context *ctx, struct r600_range *range, int num_blocks, int *index)
665 {
666 int c = *index;
667 for (int j = 0; j < num_blocks; j++) {
668 if (!range->blocks[j])
669 continue;
670
671 ctx->blocks[c++] = range->blocks[j];
672 }
673 *index = c;
674 }
675
676 int r600_setup_block_table(struct r600_context *ctx)
677 {
678 /* setup block table */
679 int c = 0;
680 ctx->blocks = calloc(ctx->nblocks, sizeof(void*));
681 if (!ctx->blocks)
682 return -ENOMEM;
683 for (int i = 0; i < NUM_RANGES; i++) {
684 if (!ctx->range[i].blocks)
685 continue;
686 for (int j = 0, add; j < (1 << HASH_SHIFT); j++) {
687 if (!ctx->range[i].blocks[j])
688 continue;
689
690 add = 1;
691 for (int k = 0; k < c; k++) {
692 if (ctx->blocks[k] == ctx->range[i].blocks[j]) {
693 add = 0;
694 break;
695 }
696 }
697 if (add) {
698 assert(c < ctx->nblocks);
699 ctx->blocks[c++] = ctx->range[i].blocks[j];
700 j += (ctx->range[i].blocks[j]->nreg) - 1;
701 }
702 }
703 }
704
705 r600_add_resource_block(ctx, &ctx->ps_resources, ctx->num_ps_resources, &c);
706 r600_add_resource_block(ctx, &ctx->vs_resources, ctx->num_vs_resources, &c);
707 r600_add_resource_block(ctx, &ctx->fs_resources, ctx->num_fs_resources, &c);
708 return 0;
709 }
710
711 int r600_context_init(struct r600_context *ctx)
712 {
713 int r;
714
715 /* add blocks */
716 r = r600_context_add_block(ctx, r600_config_reg_list,
717 Elements(r600_config_reg_list), PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET);
718 if (r)
719 goto out_err;
720 r = r600_context_add_block(ctx, r600_context_reg_list,
721 Elements(r600_context_reg_list), PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET);
722 if (r)
723 goto out_err;
724 r = r600_context_add_block(ctx, r600_ctl_const_list,
725 Elements(r600_ctl_const_list), PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET);
726 if (r)
727 goto out_err;
728
729 /* PS SAMPLER BORDER */
730 for (int j = 0, offset = 0; j < 18; j++, offset += 0x10) {
731 r = r600_state_sampler_border_init(ctx, offset);
732 if (r)
733 goto out_err;
734 }
735
736 /* VS SAMPLER BORDER */
737 for (int j = 0, offset = 0x200; j < 18; j++, offset += 0x10) {
738 r = r600_state_sampler_border_init(ctx, offset);
739 if (r)
740 goto out_err;
741 }
742 /* PS SAMPLER */
743 for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) {
744 r = r600_state_sampler_init(ctx, offset);
745 if (r)
746 goto out_err;
747 }
748 /* VS SAMPLER */
749 for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) {
750 r = r600_state_sampler_init(ctx, offset);
751 if (r)
752 goto out_err;
753 }
754
755 ctx->num_ps_resources = 160;
756 ctx->num_vs_resources = 160;
757 ctx->num_fs_resources = 16;
758 r = r600_resource_range_init(ctx, &ctx->ps_resources, 0, 160, 0x1c);
759 if (r)
760 goto out_err;
761 r = r600_resource_range_init(ctx, &ctx->vs_resources, 0x1180, 160, 0x1c);
762 if (r)
763 goto out_err;
764 r = r600_resource_range_init(ctx, &ctx->fs_resources, 0x2300, 16, 0x1c);
765 if (r)
766 goto out_err;
767
768 /* PS loop const */
769 r600_loop_const_init(ctx, 0);
770 /* VS loop const */
771 r600_loop_const_init(ctx, 32);
772
773 r = r600_setup_block_table(ctx);
774 if (r)
775 goto out_err;
776
777 ctx->max_db = 4;
778 return 0;
779 out_err:
780 r600_context_fini(ctx);
781 return r;
782 }
783
784 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
785 boolean count_draw_in)
786 {
787 struct r600_atom *state;
788
789 /* The number of dwords we already used in the CS so far. */
790 num_dw += ctx->cs->cdw;
791
792 if (count_draw_in) {
793 /* The number of dwords all the dirty states would take. */
794 LIST_FOR_EACH_ENTRY(state, &ctx->dirty_states, head) {
795 num_dw += state->num_dw;
796 }
797
798 num_dw += ctx->pm4_dirty_cdwords;
799
800 /* The upper-bound of how much a draw command would take. */
801 num_dw += R600_MAX_DRAW_CS_DWORDS;
802 }
803
804 /* Count in queries_suspend. */
805 num_dw += ctx->num_cs_dw_nontimer_queries_suspend;
806 num_dw += ctx->num_cs_dw_timer_queries_suspend;
807
808 /* Count in streamout_end at the end of CS. */
809 num_dw += ctx->num_cs_dw_streamout_end;
810
811 /* Count in render_condition(NULL) at the end of CS. */
812 if (ctx->predicate_drawing) {
813 num_dw += 3;
814 }
815
816 /* Count in framebuffer cache flushes at the end of CS. */
817 num_dw += 7; /* one SURFACE_SYNC and CACHE_FLUSH_AND_INV (r6xx-only) */
818
819 /* Save 16 dwords for the fence mechanism. */
820 num_dw += 16;
821
822 /* Flush if there's not enough space. */
823 if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
824 r600_flush(&ctx->context, NULL, RADEON_FLUSH_ASYNC);
825 }
826 }
827
828 void r600_context_dirty_block(struct r600_context *ctx,
829 struct r600_block *block,
830 int dirty, int index)
831 {
832 if ((index + 1) > block->nreg_dirty)
833 block->nreg_dirty = index + 1;
834
835 if ((dirty != (block->status & R600_BLOCK_STATUS_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) {
836 block->status |= R600_BLOCK_STATUS_DIRTY;
837 ctx->pm4_dirty_cdwords += block->pm4_ndwords;
838 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
839 block->status |= R600_BLOCK_STATUS_ENABLED;
840 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
841 }
842 LIST_ADDTAIL(&block->list,&ctx->dirty);
843
844 if (block->flags & REG_FLAG_FLUSH_CHANGE) {
845 r600_context_ps_partial_flush(ctx);
846 }
847 }
848 }
849
850 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state)
851 {
852 struct r600_block *block;
853 int dirty;
854 for (int i = 0; i < state->nregs; i++) {
855 unsigned id, reloc_id;
856 struct r600_pipe_reg *reg = &state->regs[i];
857
858 block = reg->block;
859 id = reg->id;
860
861 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
862
863 if (reg->value != block->reg[id]) {
864 block->reg[id] = reg->value;
865 dirty |= R600_BLOCK_STATUS_DIRTY;
866 }
867 if (block->flags & REG_FLAG_DIRTY_ALWAYS)
868 dirty |= R600_BLOCK_STATUS_DIRTY;
869 if (block->pm4_bo_index[id]) {
870 /* find relocation */
871 reloc_id = block->pm4_bo_index[id];
872 pipe_resource_reference((struct pipe_resource**)&block->reloc[reloc_id].bo, &reg->bo->b.b.b);
873 block->reloc[reloc_id].bo_usage = reg->bo_usage;
874 /* always force dirty for relocs for now */
875 dirty |= R600_BLOCK_STATUS_DIRTY;
876 }
877
878 if (dirty)
879 r600_context_dirty_block(ctx, block, dirty, id);
880 }
881 }
882
883 static void r600_context_dirty_resource_block(struct r600_context *ctx,
884 struct r600_block *block,
885 int dirty, int index)
886 {
887 block->nreg_dirty = index + 1;
888
889 if ((dirty != (block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) {
890 block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
891 ctx->pm4_dirty_cdwords += block->pm4_ndwords;
892 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
893 block->status |= R600_BLOCK_STATUS_ENABLED;
894 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
895 }
896 LIST_ADDTAIL(&block->list,&ctx->resource_dirty);
897 }
898 }
899
900 void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, struct r600_block *block)
901 {
902 int dirty;
903 int num_regs = ctx->chip_class >= EVERGREEN ? 8 : 7;
904 boolean is_vertex;
905
906 if (state == NULL) {
907 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_RESOURCE_DIRTY);
908 pipe_resource_reference((struct pipe_resource**)&block->reloc[1].bo, NULL);
909 pipe_resource_reference((struct pipe_resource**)&block->reloc[2].bo, NULL);
910 LIST_DELINIT(&block->list);
911 LIST_DELINIT(&block->enable_list);
912 return;
913 }
914
915 is_vertex = ((state->val[num_regs-1] & 0xc0000000) == 0xc0000000);
916 dirty = block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY;
917
918 if (memcmp(block->reg, state->val, num_regs*4)) {
919 memcpy(block->reg, state->val, num_regs * 4);
920 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
921 }
922
923 /* if no BOs on block, force dirty */
924 if (!block->reloc[1].bo || !block->reloc[2].bo)
925 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
926
927 if (!dirty) {
928 if (is_vertex) {
929 if (block->reloc[1].bo->buf != state->bo[0]->buf)
930 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
931 } else {
932 if ((block->reloc[1].bo->buf != state->bo[0]->buf) ||
933 (block->reloc[2].bo->buf != state->bo[1]->buf))
934 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
935 }
936 }
937
938 if (dirty) {
939 if (is_vertex) {
940 /* VERTEX RESOURCE, we preted there is 2 bo to relocate so
941 * we have single case btw VERTEX & TEXTURE resource
942 */
943 pipe_resource_reference((struct pipe_resource**)&block->reloc[1].bo, &state->bo[0]->b.b.b);
944 block->reloc[1].bo_usage = state->bo_usage[0];
945 pipe_resource_reference((struct pipe_resource**)&block->reloc[2].bo, NULL);
946 } else {
947 /* TEXTURE RESOURCE */
948 pipe_resource_reference((struct pipe_resource**)&block->reloc[1].bo, &state->bo[0]->b.b.b);
949 block->reloc[1].bo_usage = state->bo_usage[0];
950 pipe_resource_reference((struct pipe_resource**)&block->reloc[2].bo, &state->bo[1]->b.b.b);
951 block->reloc[2].bo_usage = state->bo_usage[1];
952 }
953
954 if (is_vertex)
955 block->status |= R600_BLOCK_STATUS_RESOURCE_VERTEX;
956 else
957 block->status &= ~R600_BLOCK_STATUS_RESOURCE_VERTEX;
958
959 r600_context_dirty_resource_block(ctx, block, dirty, num_regs - 1);
960 }
961 }
962
963 void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
964 {
965 struct r600_block *block = ctx->ps_resources.blocks[rid];
966
967 r600_context_pipe_state_set_resource(ctx, state, block);
968 }
969
970 void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
971 {
972 struct r600_block *block = ctx->vs_resources.blocks[rid];
973
974 r600_context_pipe_state_set_resource(ctx, state, block);
975 }
976
977 void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
978 {
979 struct r600_block *block = ctx->fs_resources.blocks[rid];
980
981 r600_context_pipe_state_set_resource(ctx, state, block);
982 }
983
984 void r600_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
985 {
986 struct r600_range *range;
987 struct r600_block *block;
988 int i;
989 int dirty;
990
991 range = &ctx->range[CTX_RANGE_ID(offset)];
992 block = range->blocks[CTX_BLOCK_ID(offset)];
993 if (state == NULL) {
994 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
995 LIST_DELINIT(&block->list);
996 LIST_DELINIT(&block->enable_list);
997 return;
998 }
999 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
1000
1001 for (i = 0; i < 3; i++) {
1002 if (block->reg[i] != state->regs[i].value) {
1003 block->reg[i] = state->regs[i].value;
1004 dirty |= R600_BLOCK_STATUS_DIRTY;
1005 }
1006 }
1007
1008 if (dirty)
1009 r600_context_dirty_block(ctx, block, dirty, 2);
1010 }
1011
1012 static inline void r600_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
1013 {
1014 struct r600_range *range;
1015 struct r600_block *block;
1016 int i;
1017 int dirty;
1018
1019 range = &ctx->range[CTX_RANGE_ID(offset)];
1020 block = range->blocks[CTX_BLOCK_ID(offset)];
1021 if (state == NULL) {
1022 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
1023 LIST_DELINIT(&block->list);
1024 LIST_DELINIT(&block->enable_list);
1025 return;
1026 }
1027 if (state->nregs <= 3) {
1028 return;
1029 }
1030 dirty = block->status & R600_BLOCK_STATUS_DIRTY;
1031 for (i = 0; i < 4; i++) {
1032 if (block->reg[i] != state->regs[i + 3].value) {
1033 block->reg[i] = state->regs[i + 3].value;
1034 dirty |= R600_BLOCK_STATUS_DIRTY;
1035 }
1036 }
1037
1038 /* We have to flush the shaders before we change the border color
1039 * registers, or previous draw commands that haven't completed yet
1040 * will end up using the new border color. */
1041 if (dirty & R600_BLOCK_STATUS_DIRTY)
1042 r600_context_ps_partial_flush(ctx);
1043 if (dirty)
1044 r600_context_dirty_block(ctx, block, dirty, 3);
1045 }
1046
1047 void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
1048 {
1049 unsigned offset;
1050
1051 offset = R_03C000_SQ_TEX_SAMPLER_WORD0_0 + 12*id;
1052 r600_context_pipe_state_set_sampler(ctx, state, offset);
1053 offset = R_00A400_TD_PS_SAMPLER0_BORDER_RED + 16*id;
1054 r600_context_pipe_state_set_sampler_border(ctx, state, offset);
1055 }
1056
1057 void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
1058 {
1059 unsigned offset;
1060
1061 offset = R_03C000_SQ_TEX_SAMPLER_WORD0_0 + 12*(id + 18);
1062 r600_context_pipe_state_set_sampler(ctx, state, offset);
1063 offset = R_00A600_TD_VS_SAMPLER0_BORDER_RED + 16*id;
1064 r600_context_pipe_state_set_sampler_border(ctx, state, offset);
1065 }
1066
1067 void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block)
1068 {
1069 struct radeon_winsys_cs *cs = ctx->cs;
1070 int optional = block->nbo == 0 && !(block->flags & REG_FLAG_DIRTY_ALWAYS);
1071 int cp_dwords = block->pm4_ndwords, start_dword = 0;
1072 int new_dwords = 0;
1073 int nbo = block->nbo;
1074
1075 if (block->nreg_dirty == 0 && optional) {
1076 goto out;
1077 }
1078
1079 if (nbo) {
1080 for (int j = 0; j < block->nreg; j++) {
1081 if (block->pm4_bo_index[j]) {
1082 /* find relocation */
1083 struct r600_block_reloc *reloc = &block->reloc[block->pm4_bo_index[j]];
1084 if (reloc->bo) {
1085 block->pm4[reloc->bo_pm4_index] =
1086 r600_context_bo_reloc(ctx, reloc->bo, reloc->bo_usage);
1087 } else {
1088 block->pm4[reloc->bo_pm4_index] = 0;
1089 }
1090 nbo--;
1091 if (nbo == 0)
1092 break;
1093
1094 }
1095 }
1096 }
1097
1098 optional &= (block->nreg_dirty != block->nreg);
1099 if (optional) {
1100 new_dwords = block->nreg_dirty;
1101 start_dword = cs->cdw;
1102 cp_dwords = new_dwords + 2;
1103 }
1104 memcpy(&cs->buf[cs->cdw], block->pm4, cp_dwords * 4);
1105 cs->cdw += cp_dwords;
1106
1107 if (optional) {
1108 uint32_t newword;
1109
1110 newword = cs->buf[start_dword];
1111 newword &= PKT_COUNT_C;
1112 newword |= PKT_COUNT_S(new_dwords);
1113 cs->buf[start_dword] = newword;
1114 }
1115 out:
1116 block->status ^= R600_BLOCK_STATUS_DIRTY;
1117 block->nreg_dirty = 0;
1118 LIST_DELINIT(&block->list);
1119 }
1120
1121 void r600_context_block_resource_emit_dirty(struct r600_context *ctx, struct r600_block *block)
1122 {
1123 struct radeon_winsys_cs *cs = ctx->cs;
1124 int cp_dwords = block->pm4_ndwords;
1125 int nbo = block->nbo;
1126
1127 if (block->status & R600_BLOCK_STATUS_RESOURCE_VERTEX) {
1128 nbo = 1;
1129 cp_dwords -= 2; /* don't copy the second NOP */
1130 }
1131
1132 for (int j = 0; j < nbo; j++) {
1133 if (block->pm4_bo_index[j]) {
1134 /* find relocation */
1135 struct r600_block_reloc *reloc = &block->reloc[block->pm4_bo_index[j]];
1136 block->pm4[reloc->bo_pm4_index] =
1137 r600_context_bo_reloc(ctx, reloc->bo, reloc->bo_usage);
1138 }
1139 }
1140
1141 memcpy(&cs->buf[cs->cdw], block->pm4, cp_dwords * 4);
1142 cs->cdw += cp_dwords;
1143
1144 block->status ^= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1145 block->nreg_dirty = 0;
1146 LIST_DELINIT(&block->list);
1147 }
1148
1149 void r600_inval_shader_cache(struct r600_context *ctx)
1150 {
1151 ctx->atom_surface_sync.flush_flags |= S_0085F0_SH_ACTION_ENA(1);
1152 r600_atom_dirty(ctx, &ctx->atom_surface_sync.atom);
1153 }
1154
1155 void r600_inval_texture_cache(struct r600_context *ctx)
1156 {
1157 ctx->atom_surface_sync.flush_flags |= S_0085F0_TC_ACTION_ENA(1);
1158 r600_atom_dirty(ctx, &ctx->atom_surface_sync.atom);
1159 }
1160
1161 void r600_inval_vertex_cache(struct r600_context *ctx)
1162 {
1163 if (ctx->family == CHIP_RV610 ||
1164 ctx->family == CHIP_RV620 ||
1165 ctx->family == CHIP_RS780 ||
1166 ctx->family == CHIP_RS880 ||
1167 ctx->family == CHIP_RV710 ||
1168 ctx->family == CHIP_CEDAR ||
1169 ctx->family == CHIP_PALM ||
1170 ctx->family == CHIP_SUMO ||
1171 ctx->family == CHIP_SUMO2 ||
1172 ctx->family == CHIP_CAICOS ||
1173 ctx->family == CHIP_CAYMAN) {
1174 /* Some GPUs don't have the vertex cache and must use the texture cache instead. */
1175 ctx->atom_surface_sync.flush_flags |= S_0085F0_TC_ACTION_ENA(1);
1176 } else {
1177 ctx->atom_surface_sync.flush_flags |= S_0085F0_VC_ACTION_ENA(1);
1178 }
1179 r600_atom_dirty(ctx, &ctx->atom_surface_sync.atom);
1180 }
1181
1182 void r600_flush_framebuffer(struct r600_context *ctx, bool flush_now)
1183 {
1184 if (!(ctx->flags & R600_CONTEXT_DST_CACHES_DIRTY))
1185 return;
1186
1187 ctx->atom_surface_sync.flush_flags |=
1188 r600_get_cb_flush_flags(ctx) |
1189 (ctx->framebuffer.zsbuf ? S_0085F0_DB_ACTION_ENA(1) | S_0085F0_DB_DEST_BASE_ENA(1) : 0);
1190
1191 if (flush_now) {
1192 r600_emit_atom(ctx, &ctx->atom_surface_sync.atom);
1193 } else {
1194 r600_atom_dirty(ctx, &ctx->atom_surface_sync.atom);
1195 }
1196
1197 /* Also add a complete cache flush to work around broken flushing on R6xx. */
1198 if (ctx->chip_class == R600) {
1199 if (flush_now) {
1200 r600_emit_atom(ctx, &ctx->atom_r6xx_flush_and_inv);
1201 } else {
1202 r600_atom_dirty(ctx, &ctx->atom_r6xx_flush_and_inv);
1203 }
1204 }
1205
1206 ctx->flags &= ~R600_CONTEXT_DST_CACHES_DIRTY;
1207 }
1208
1209 void r600_context_flush(struct r600_context *ctx, unsigned flags)
1210 {
1211 struct radeon_winsys_cs *cs = ctx->cs;
1212 struct r600_block *enable_block = NULL;
1213 bool timer_queries_suspended = false;
1214 bool nontimer_queries_suspended = false;
1215 bool streamout_suspended = false;
1216
1217 if (cs->cdw == ctx->atom_start_cs.atom.num_dw)
1218 return;
1219
1220 /* suspend queries */
1221 if (ctx->num_cs_dw_timer_queries_suspend) {
1222 r600_suspend_timer_queries(ctx);
1223 timer_queries_suspended = true;
1224 }
1225 if (ctx->num_cs_dw_nontimer_queries_suspend) {
1226 r600_suspend_nontimer_queries(ctx);
1227 nontimer_queries_suspended = true;
1228 }
1229
1230 if (ctx->num_cs_dw_streamout_end) {
1231 r600_context_streamout_end(ctx);
1232 streamout_suspended = true;
1233 }
1234
1235 r600_flush_framebuffer(ctx, true);
1236
1237 /* partial flush is needed to avoid lockups on some chips with user fences */
1238 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
1239 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
1240
1241 /* force to keep tiling flags */
1242 flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
1243
1244 /* Flush the CS. */
1245 ctx->ws->cs_flush(ctx->cs, flags);
1246
1247 ctx->pm4_dirty_cdwords = 0;
1248 ctx->flags = 0;
1249
1250 r600_emit_atom(ctx, &ctx->atom_start_cs.atom);
1251 r600_atom_dirty(ctx, &ctx->atom_db_misc_state.atom);
1252 if (ctx->chip_class >= EVERGREEN)
1253 r600_atom_dirty(ctx, &ctx->atom_eg_strmout_config.atom);
1254
1255 if (streamout_suspended) {
1256 ctx->streamout_start = TRUE;
1257 ctx->streamout_append_bitmask = ~0;
1258 }
1259
1260 /* resume queries */
1261 if (timer_queries_suspended) {
1262 r600_resume_timer_queries(ctx);
1263 }
1264 if (nontimer_queries_suspended) {
1265 r600_resume_nontimer_queries(ctx);
1266 }
1267
1268 /* set all valid group as dirty so they get reemited on
1269 * next draw command
1270 */
1271 LIST_FOR_EACH_ENTRY(enable_block, &ctx->enable_list, enable_list) {
1272 if (!(enable_block->flags & BLOCK_FLAG_RESOURCE)) {
1273 if(!(enable_block->status & R600_BLOCK_STATUS_DIRTY)) {
1274 LIST_ADDTAIL(&enable_block->list,&ctx->dirty);
1275 enable_block->status |= R600_BLOCK_STATUS_DIRTY;
1276 }
1277 } else {
1278 if(!(enable_block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY)) {
1279 LIST_ADDTAIL(&enable_block->list,&ctx->resource_dirty);
1280 enable_block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
1281 }
1282 }
1283 ctx->pm4_dirty_cdwords += enable_block->pm4_ndwords;
1284 enable_block->nreg_dirty = enable_block->nreg;
1285 }
1286 }
1287
1288 void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence_bo, unsigned offset, unsigned value)
1289 {
1290 struct radeon_winsys_cs *cs = ctx->cs;
1291 uint64_t va;
1292
1293 r600_need_cs_space(ctx, 10, FALSE);
1294
1295 va = r600_resource_va(&ctx->screen->screen, (void*)fence_bo);
1296 va = va + (offset << 2);
1297
1298 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
1299 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
1300 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
1301 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
1302 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* ADDRESS_LO */
1303 /* DATA_SEL | INT_EN | ADDRESS_HI */
1304 cs->buf[cs->cdw++] = (1 << 29) | (0 << 24) | ((va >> 32UL) & 0xFF);
1305 cs->buf[cs->cdw++] = value; /* DATA_LO */
1306 cs->buf[cs->cdw++] = 0; /* DATA_HI */
1307 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1308 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, fence_bo, RADEON_USAGE_WRITE);
1309 }
1310
1311 static void r600_flush_vgt_streamout(struct r600_context *ctx)
1312 {
1313 struct radeon_winsys_cs *cs = ctx->cs;
1314
1315 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, 1, 0);
1316 cs->buf[cs->cdw++] = (R_008490_CP_STRMOUT_CNTL - R600_CONFIG_REG_OFFSET) >> 2;
1317 cs->buf[cs->cdw++] = 0;
1318
1319 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
1320 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0);
1321
1322 cs->buf[cs->cdw++] = PKT3(PKT3_WAIT_REG_MEM, 5, 0);
1323 cs->buf[cs->cdw++] = WAIT_REG_MEM_EQUAL; /* wait until the register is equal to the reference value */
1324 cs->buf[cs->cdw++] = R_008490_CP_STRMOUT_CNTL >> 2; /* register */
1325 cs->buf[cs->cdw++] = 0;
1326 cs->buf[cs->cdw++] = S_008490_OFFSET_UPDATE_DONE(1); /* reference value */
1327 cs->buf[cs->cdw++] = S_008490_OFFSET_UPDATE_DONE(1); /* mask */
1328 cs->buf[cs->cdw++] = 4; /* poll interval */
1329 }
1330
1331 static void r600_set_streamout_enable(struct r600_context *ctx, unsigned buffer_enable_bit)
1332 {
1333 struct radeon_winsys_cs *cs = ctx->cs;
1334
1335 if (buffer_enable_bit) {
1336 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
1337 cs->buf[cs->cdw++] = (R_028AB0_VGT_STRMOUT_EN - R600_CONTEXT_REG_OFFSET) >> 2;
1338 cs->buf[cs->cdw++] = S_028AB0_STREAMOUT(1);
1339
1340 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
1341 cs->buf[cs->cdw++] = (R_028B20_VGT_STRMOUT_BUFFER_EN - R600_CONTEXT_REG_OFFSET) >> 2;
1342 cs->buf[cs->cdw++] = buffer_enable_bit;
1343 } else {
1344 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
1345 cs->buf[cs->cdw++] = (R_028AB0_VGT_STRMOUT_EN - R600_CONTEXT_REG_OFFSET) >> 2;
1346 cs->buf[cs->cdw++] = S_028AB0_STREAMOUT(0);
1347 }
1348 }
1349
1350 void r600_context_streamout_begin(struct r600_context *ctx)
1351 {
1352 struct radeon_winsys_cs *cs = ctx->cs;
1353 struct r600_so_target **t = ctx->so_targets;
1354 unsigned *stride_in_dw = ctx->vs_shader->so.stride;
1355 unsigned buffer_en, i, update_flags = 0;
1356 uint64_t va;
1357
1358 buffer_en = (ctx->num_so_targets >= 1 && t[0] ? 1 : 0) |
1359 (ctx->num_so_targets >= 2 && t[1] ? 2 : 0) |
1360 (ctx->num_so_targets >= 3 && t[2] ? 4 : 0) |
1361 (ctx->num_so_targets >= 4 && t[3] ? 8 : 0);
1362
1363 ctx->num_cs_dw_streamout_end =
1364 12 + /* flush_vgt_streamout */
1365 util_bitcount(buffer_en) * 8 +
1366 3;
1367
1368 r600_need_cs_space(ctx,
1369 12 + /* flush_vgt_streamout */
1370 6 + /* enables */
1371 util_bitcount(buffer_en & ctx->streamout_append_bitmask) * 8 +
1372 util_bitcount(buffer_en & ~ctx->streamout_append_bitmask) * 6 +
1373 (ctx->family > CHIP_R600 && ctx->family < CHIP_RV770 ? 2 : 0) +
1374 ctx->num_cs_dw_streamout_end, TRUE);
1375
1376 if (ctx->chip_class >= EVERGREEN) {
1377 evergreen_flush_vgt_streamout(ctx);
1378 evergreen_set_streamout_enable(ctx, buffer_en);
1379 } else {
1380 r600_flush_vgt_streamout(ctx);
1381 r600_set_streamout_enable(ctx, buffer_en);
1382 }
1383
1384 for (i = 0; i < ctx->num_so_targets; i++) {
1385 if (t[i]) {
1386 t[i]->stride_in_dw = stride_in_dw[i];
1387 t[i]->so_index = i;
1388 va = r600_resource_va(&ctx->screen->screen,
1389 (void*)t[i]->b.buffer);
1390
1391 update_flags |= SURFACE_BASE_UPDATE_STRMOUT(i);
1392
1393 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 3, 0);
1394 cs->buf[cs->cdw++] = (R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 +
1395 16*i - R600_CONTEXT_REG_OFFSET) >> 2;
1396 cs->buf[cs->cdw++] = (t[i]->b.buffer_offset +
1397 t[i]->b.buffer_size) >> 2; /* BUFFER_SIZE (in DW) */
1398 cs->buf[cs->cdw++] = stride_in_dw[i]; /* VTX_STRIDE (in DW) */
1399 cs->buf[cs->cdw++] = va >> 8; /* BUFFER_BASE */
1400
1401 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1402 cs->buf[cs->cdw++] =
1403 r600_context_bo_reloc(ctx, r600_resource(t[i]->b.buffer),
1404 RADEON_USAGE_WRITE);
1405
1406 if (ctx->streamout_append_bitmask & (1 << i)) {
1407 va = r600_resource_va(&ctx->screen->screen,
1408 (void*)t[i]->filled_size);
1409 /* Append. */
1410 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
1411 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
1412 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM); /* control */
1413 cs->buf[cs->cdw++] = 0; /* unused */
1414 cs->buf[cs->cdw++] = 0; /* unused */
1415 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */
1416 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
1417
1418 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1419 cs->buf[cs->cdw++] =
1420 r600_context_bo_reloc(ctx, t[i]->filled_size,
1421 RADEON_USAGE_READ);
1422 } else {
1423 /* Start from the beginning. */
1424 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
1425 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
1426 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET); /* control */
1427 cs->buf[cs->cdw++] = 0; /* unused */
1428 cs->buf[cs->cdw++] = 0; /* unused */
1429 cs->buf[cs->cdw++] = t[i]->b.buffer_offset >> 2; /* buffer offset in DW */
1430 cs->buf[cs->cdw++] = 0; /* unused */
1431 }
1432 }
1433 }
1434
1435 if (ctx->family > CHIP_R600 && ctx->family < CHIP_RV770) {
1436 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0);
1437 cs->buf[cs->cdw++] = update_flags;
1438 }
1439 }
1440
1441 void r600_context_streamout_end(struct r600_context *ctx)
1442 {
1443 struct radeon_winsys_cs *cs = ctx->cs;
1444 struct r600_so_target **t = ctx->so_targets;
1445 unsigned i, flush_flags = 0;
1446 uint64_t va;
1447
1448 if (ctx->chip_class >= EVERGREEN) {
1449 evergreen_flush_vgt_streamout(ctx);
1450 } else {
1451 r600_flush_vgt_streamout(ctx);
1452 }
1453
1454 for (i = 0; i < ctx->num_so_targets; i++) {
1455 if (t[i]) {
1456 va = r600_resource_va(&ctx->screen->screen,
1457 (void*)t[i]->filled_size);
1458 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
1459 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
1460 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
1461 STRMOUT_STORE_BUFFER_FILLED_SIZE; /* control */
1462 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* dst address lo */
1463 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* dst address hi */
1464 cs->buf[cs->cdw++] = 0; /* unused */
1465 cs->buf[cs->cdw++] = 0; /* unused */
1466
1467 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1468 cs->buf[cs->cdw++] =
1469 r600_context_bo_reloc(ctx, t[i]->filled_size,
1470 RADEON_USAGE_WRITE);
1471
1472 flush_flags |= S_0085F0_SO0_DEST_BASE_ENA(1) << i;
1473 }
1474 }
1475
1476 if (ctx->chip_class >= EVERGREEN) {
1477 evergreen_set_streamout_enable(ctx, 0);
1478 } else {
1479 r600_set_streamout_enable(ctx, 0);
1480 }
1481
1482 /* This is needed to fix cache flushes on r600. */
1483 if (ctx->chip_class == R600) {
1484 if (ctx->family == CHIP_RV670 ||
1485 ctx->family == CHIP_RS780 ||
1486 ctx->family == CHIP_RS880) {
1487 flush_flags |= S_0085F0_DEST_BASE_0_ENA(1);
1488 }
1489
1490 r600_atom_dirty(ctx, &ctx->atom_r6xx_flush_and_inv);
1491 }
1492
1493 /* Flush streamout caches. */
1494 ctx->atom_surface_sync.flush_flags |= flush_flags;
1495 r600_atom_dirty(ctx, &ctx->atom_surface_sync.atom);
1496
1497 ctx->num_cs_dw_streamout_end = 0;
1498
1499 #if 0
1500 for (i = 0; i < ctx->num_so_targets; i++) {
1501 if (!t[i])
1502 continue;
1503
1504 uint32_t *ptr = ctx->ws->buffer_map(t[i]->filled_size->buf, ctx->cs, RADEON_USAGE_READ);
1505 printf("FILLED_SIZE%i: %u\n", i, *ptr);
1506 ctx->ws->buffer_unmap(t[i]->filled_size->buf);
1507 }
1508 #endif
1509 }
1510
1511 void r600_context_draw_opaque_count(struct r600_context *ctx, struct r600_so_target *t)
1512 {
1513 struct radeon_winsys_cs *cs = ctx->cs;
1514 uint64_t va = r600_resource_va(&ctx->screen->screen,
1515 (void*)t->filled_size);
1516
1517 r600_need_cs_space(ctx, 14 + 21, TRUE);
1518
1519 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
1520 cs->buf[cs->cdw++] = (R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET - R600_CONTEXT_REG_OFFSET) >> 2;
1521 cs->buf[cs->cdw++] = 0;
1522
1523 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
1524 cs->buf[cs->cdw++] = (R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE - R600_CONTEXT_REG_OFFSET) >> 2;
1525 cs->buf[cs->cdw++] = t->stride_in_dw;
1526
1527 cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0);
1528 cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG;
1529 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */
1530 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
1531 cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */
1532 cs->buf[cs->cdw++] = 0; /* unused */
1533
1534 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1535 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, t->filled_size, RADEON_USAGE_READ);
1536 }