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r600g: split INVAL_READ_CACHES into vertex, tex, and const cache flags
[mesa.git] / src / gallium / drivers / r600 / r600_hw_context.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include "r600_pipe.h"
27 #include "r600d.h"
28 #include "util/u_memory.h"
29 #include <errno.h>
30 #include <unistd.h>
31
32 /* Get backends mask */
33 void r600_get_backend_mask(struct r600_context *ctx)
34 {
35 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
36 struct r600_resource *buffer;
37 uint32_t *results;
38 unsigned num_backends = ctx->screen->info.r600_num_backends;
39 unsigned i, mask = 0;
40 uint64_t va;
41
42 /* if backend_map query is supported by the kernel */
43 if (ctx->screen->info.r600_backend_map_valid) {
44 unsigned num_tile_pipes = ctx->screen->info.r600_num_tile_pipes;
45 unsigned backend_map = ctx->screen->info.r600_backend_map;
46 unsigned item_width, item_mask;
47
48 if (ctx->chip_class >= EVERGREEN) {
49 item_width = 4;
50 item_mask = 0x7;
51 } else {
52 item_width = 2;
53 item_mask = 0x3;
54 }
55
56 while(num_tile_pipes--) {
57 i = backend_map & item_mask;
58 mask |= (1<<i);
59 backend_map >>= item_width;
60 }
61 if (mask != 0) {
62 ctx->backend_mask = mask;
63 return;
64 }
65 }
66
67 /* otherwise backup path for older kernels */
68
69 /* create buffer for event data */
70 buffer = (struct r600_resource*)
71 pipe_buffer_create(&ctx->screen->screen, PIPE_BIND_CUSTOM,
72 PIPE_USAGE_STAGING, ctx->max_db*16);
73 if (!buffer)
74 goto err;
75 va = r600_resource_va(&ctx->screen->screen, (void*)buffer);
76
77 /* initialize buffer with zeroes */
78 results = r600_buffer_mmap_sync_with_rings(ctx, buffer, PIPE_TRANSFER_WRITE);
79 if (results) {
80 memset(results, 0, ctx->max_db * 4 * 4);
81 ctx->ws->buffer_unmap(buffer->cs_buf);
82
83 /* emit EVENT_WRITE for ZPASS_DONE */
84 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
85 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
86 cs->buf[cs->cdw++] = va;
87 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
88
89 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
90 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, &ctx->rings.gfx, buffer, RADEON_USAGE_WRITE);
91
92 /* analyze results */
93 results = r600_buffer_mmap_sync_with_rings(ctx, buffer, PIPE_TRANSFER_READ);
94 if (results) {
95 for(i = 0; i < ctx->max_db; i++) {
96 /* at least highest bit will be set if backend is used */
97 if (results[i*4 + 1])
98 mask |= (1<<i);
99 }
100 ctx->ws->buffer_unmap(buffer->cs_buf);
101 }
102 }
103
104 pipe_resource_reference((struct pipe_resource**)&buffer, NULL);
105
106 if (mask != 0) {
107 ctx->backend_mask = mask;
108 return;
109 }
110
111 err:
112 /* fallback to old method - set num_backends lower bits to 1 */
113 ctx->backend_mask = (~((uint32_t)0))>>(32-num_backends);
114 return;
115 }
116
117 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
118 boolean count_draw_in)
119 {
120 if (!ctx->ws->cs_memory_below_limit(ctx->rings.gfx.cs, ctx->vram, ctx->gtt)) {
121 ctx->gtt = 0;
122 ctx->vram = 0;
123 ctx->rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC);
124 return;
125 }
126 /* all will be accounted once relocation are emited */
127 ctx->gtt = 0;
128 ctx->vram = 0;
129
130 /* The number of dwords we already used in the CS so far. */
131 num_dw += ctx->rings.gfx.cs->cdw;
132
133 if (count_draw_in) {
134 unsigned i;
135
136 /* The number of dwords all the dirty states would take. */
137 for (i = 0; i < R600_NUM_ATOMS; i++) {
138 if (ctx->atoms[i] && ctx->atoms[i]->dirty) {
139 num_dw += ctx->atoms[i]->num_dw;
140 if (ctx->screen->trace_bo) {
141 num_dw += R600_TRACE_CS_DWORDS;
142 }
143 }
144 }
145
146 /* The upper-bound of how much space a draw command would take. */
147 num_dw += R600_MAX_FLUSH_CS_DWORDS + R600_MAX_DRAW_CS_DWORDS;
148 if (ctx->screen->trace_bo) {
149 num_dw += R600_TRACE_CS_DWORDS;
150 }
151 }
152
153 /* Count in queries_suspend. */
154 num_dw += ctx->num_cs_dw_nontimer_queries_suspend;
155
156 /* Count in streamout_end at the end of CS. */
157 if (ctx->streamout.begin_emitted) {
158 num_dw += ctx->streamout.num_dw_for_end;
159 }
160
161 /* Count in render_condition(NULL) at the end of CS. */
162 if (ctx->predicate_drawing) {
163 num_dw += 3;
164 }
165
166 /* SX_MISC */
167 if (ctx->chip_class <= R700) {
168 num_dw += 3;
169 }
170
171 /* Count in framebuffer cache flushes at the end of CS. */
172 num_dw += R600_MAX_FLUSH_CS_DWORDS;
173
174 /* The fence at the end of CS. */
175 num_dw += 10;
176
177 /* Flush if there's not enough space. */
178 if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
179 ctx->rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC);
180 }
181 }
182
183 void r600_flush_emit(struct r600_context *rctx)
184 {
185 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
186 unsigned cp_coher_cntl = 0;
187 unsigned wait_until = 0;
188
189 if (!rctx->flags) {
190 return;
191 }
192
193 if (rctx->flags & R600_CONTEXT_WAIT_3D_IDLE) {
194 wait_until |= S_008040_WAIT_3D_IDLE(1);
195 }
196 if (rctx->flags & R600_CONTEXT_WAIT_CP_DMA_IDLE) {
197 wait_until |= S_008040_WAIT_CP_DMA_IDLE(1);
198 }
199
200 if (wait_until) {
201 /* Use of WAIT_UNTIL is deprecated on Cayman+ */
202 if (rctx->family >= CHIP_CAYMAN) {
203 /* emit a PS partial flush on Cayman/TN */
204 rctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
205 }
206 }
207
208 if (rctx->flags & R600_CONTEXT_PS_PARTIAL_FLUSH) {
209 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
210 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
211 }
212
213 if (rctx->chip_class >= R700 &&
214 (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB_META)) {
215 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
216 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0);
217 }
218
219 if (rctx->chip_class >= R700 &&
220 (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_DB_META)) {
221 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
222 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0);
223
224 /* Set FULL_CACHE_ENA for DB META flushes on r7xx and later.
225 *
226 * This hack predates use of FLUSH_AND_INV_DB_META, so it's
227 * unclear whether it's still needed or even whether it has
228 * any effect.
229 */
230 cp_coher_cntl |= S_0085F0_FULL_CACHE_ENA(1);
231 }
232
233 if (rctx->flags & R600_CONTEXT_FLUSH_AND_INV) {
234 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
235 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
236 }
237
238 if (rctx->flags & R600_CONTEXT_INV_CONST_CACHE) {
239 cp_coher_cntl |= S_0085F0_SH_ACTION_ENA(1);
240 }
241 if (rctx->flags & R600_CONTEXT_INV_VERTEX_CACHE) {
242 cp_coher_cntl |= rctx->has_vertex_cache ? S_0085F0_VC_ACTION_ENA(1)
243 : S_0085F0_TC_ACTION_ENA(1);
244 }
245 if (rctx->flags & R600_CONTEXT_INV_TEX_CACHE) {
246 cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1);
247 }
248
249 if (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_DB) {
250 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
251 S_0085F0_DB_DEST_BASE_ENA(1) |
252 S_0085F0_SMX_ACTION_ENA(1);
253 }
254
255 if (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB) {
256 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
257 S_0085F0_CB0_DEST_BASE_ENA(1) |
258 S_0085F0_CB1_DEST_BASE_ENA(1) |
259 S_0085F0_CB2_DEST_BASE_ENA(1) |
260 S_0085F0_CB3_DEST_BASE_ENA(1) |
261 S_0085F0_CB4_DEST_BASE_ENA(1) |
262 S_0085F0_CB5_DEST_BASE_ENA(1) |
263 S_0085F0_CB6_DEST_BASE_ENA(1) |
264 S_0085F0_CB7_DEST_BASE_ENA(1) |
265 S_0085F0_SMX_ACTION_ENA(1);
266 if (rctx->chip_class >= EVERGREEN)
267 cp_coher_cntl |= S_0085F0_CB8_DEST_BASE_ENA(1) |
268 S_0085F0_CB9_DEST_BASE_ENA(1) |
269 S_0085F0_CB10_DEST_BASE_ENA(1) |
270 S_0085F0_CB11_DEST_BASE_ENA(1);
271 }
272
273 if (rctx->flags & R600_CONTEXT_STREAMOUT_FLUSH) {
274 cp_coher_cntl |= S_0085F0_SO0_DEST_BASE_ENA(1) |
275 S_0085F0_SO1_DEST_BASE_ENA(1) |
276 S_0085F0_SO2_DEST_BASE_ENA(1) |
277 S_0085F0_SO3_DEST_BASE_ENA(1) |
278 S_0085F0_SMX_ACTION_ENA(1);
279 }
280
281 if (cp_coher_cntl) {
282 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
283 cs->buf[cs->cdw++] = cp_coher_cntl; /* CP_COHER_CNTL */
284 cs->buf[cs->cdw++] = 0xffffffff; /* CP_COHER_SIZE */
285 cs->buf[cs->cdw++] = 0; /* CP_COHER_BASE */
286 cs->buf[cs->cdw++] = 0x0000000A; /* POLL_INTERVAL */
287 }
288
289 if (wait_until) {
290 /* Use of WAIT_UNTIL is deprecated on Cayman+ */
291 if (rctx->family < CHIP_CAYMAN) {
292 /* wait for things to settle */
293 r600_write_config_reg(cs, R_008040_WAIT_UNTIL, wait_until);
294 }
295 }
296
297 /* everything is properly flushed */
298 rctx->flags = 0;
299 }
300
301 void r600_context_flush(struct r600_context *ctx, unsigned flags)
302 {
303 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
304
305 if (cs->cdw == ctx->start_cs_cmd.num_dw)
306 return;
307
308 ctx->nontimer_queries_suspended = false;
309 ctx->streamout.suspended = false;
310
311 /* suspend queries */
312 if (ctx->num_cs_dw_nontimer_queries_suspend) {
313 r600_suspend_nontimer_queries(ctx);
314 ctx->nontimer_queries_suspended = true;
315 }
316
317 if (ctx->streamout.begin_emitted) {
318 r600_emit_streamout_end(ctx);
319 ctx->streamout.suspended = true;
320 }
321
322 /* flush is needed to avoid lockups on some chips with user fences
323 * this will also flush the framebuffer cache
324 */
325 ctx->flags |= R600_CONTEXT_FLUSH_AND_INV |
326 R600_CONTEXT_FLUSH_AND_INV_CB |
327 R600_CONTEXT_FLUSH_AND_INV_DB |
328 R600_CONTEXT_FLUSH_AND_INV_CB_META |
329 R600_CONTEXT_FLUSH_AND_INV_DB_META |
330 R600_CONTEXT_WAIT_3D_IDLE |
331 R600_CONTEXT_WAIT_CP_DMA_IDLE;
332
333 r600_flush_emit(ctx);
334
335 /* old kernels and userspace don't set SX_MISC, so we must reset it to 0 here */
336 if (ctx->chip_class <= R700) {
337 r600_write_context_reg(cs, R_028350_SX_MISC, 0);
338 }
339
340 /* force to keep tiling flags */
341 if (ctx->keep_tiling_flags) {
342 flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
343 }
344
345 /* Flush the CS. */
346 ctx->ws->cs_flush(ctx->rings.gfx.cs, flags, ctx->screen->cs_count++);
347 }
348
349 void r600_begin_new_cs(struct r600_context *ctx)
350 {
351 unsigned shader;
352
353 ctx->flags = 0;
354 ctx->gtt = 0;
355 ctx->vram = 0;
356
357 /* Begin a new CS. */
358 r600_emit_command_buffer(ctx->rings.gfx.cs, &ctx->start_cs_cmd);
359
360 /* Re-emit states. */
361 ctx->alphatest_state.atom.dirty = true;
362 ctx->blend_color.atom.dirty = true;
363 ctx->cb_misc_state.atom.dirty = true;
364 ctx->clip_misc_state.atom.dirty = true;
365 ctx->clip_state.atom.dirty = true;
366 ctx->db_misc_state.atom.dirty = true;
367 ctx->db_state.atom.dirty = true;
368 ctx->framebuffer.atom.dirty = true;
369 ctx->pixel_shader.atom.dirty = true;
370 ctx->poly_offset_state.atom.dirty = true;
371 ctx->vgt_state.atom.dirty = true;
372 ctx->sample_mask.atom.dirty = true;
373 ctx->scissor.atom.dirty = true;
374 ctx->config_state.atom.dirty = true;
375 ctx->stencil_ref.atom.dirty = true;
376 ctx->vertex_fetch_shader.atom.dirty = true;
377 ctx->vertex_shader.atom.dirty = true;
378 ctx->viewport.atom.dirty = true;
379
380 if (ctx->blend_state.cso)
381 ctx->blend_state.atom.dirty = true;
382 if (ctx->dsa_state.cso)
383 ctx->dsa_state.atom.dirty = true;
384 if (ctx->rasterizer_state.cso)
385 ctx->rasterizer_state.atom.dirty = true;
386
387 if (ctx->chip_class <= R700) {
388 ctx->seamless_cube_map.atom.dirty = true;
389 }
390
391 ctx->vertex_buffer_state.dirty_mask = ctx->vertex_buffer_state.enabled_mask;
392 r600_vertex_buffers_dirty(ctx);
393
394 /* Re-emit shader resources. */
395 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
396 struct r600_constbuf_state *constbuf = &ctx->constbuf_state[shader];
397 struct r600_textures_info *samplers = &ctx->samplers[shader];
398
399 constbuf->dirty_mask = constbuf->enabled_mask;
400 samplers->views.dirty_mask = samplers->views.enabled_mask;
401 samplers->states.dirty_mask = samplers->states.enabled_mask;
402
403 r600_constant_buffers_dirty(ctx, constbuf);
404 r600_sampler_views_dirty(ctx, &samplers->views);
405 r600_sampler_states_dirty(ctx, &samplers->states);
406 }
407
408 if (ctx->streamout.suspended) {
409 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
410 r600_streamout_buffers_dirty(ctx);
411 }
412
413 /* resume queries */
414 if (ctx->nontimer_queries_suspended) {
415 r600_resume_nontimer_queries(ctx);
416 }
417
418 /* Re-emit the draw state. */
419 ctx->last_primitive_type = -1;
420 ctx->last_start_instance = -1;
421 }
422
423 void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence_bo, unsigned offset, unsigned value)
424 {
425 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
426 uint64_t va;
427
428 r600_need_cs_space(ctx, 10, FALSE);
429
430 va = r600_resource_va(&ctx->screen->screen, (void*)fence_bo);
431 va = va + (offset << 2);
432
433 /* Use of WAIT_UNTIL is deprecated on Cayman+ */
434 if (ctx->family >= CHIP_CAYMAN) {
435 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
436 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
437 } else {
438 r600_write_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
439 }
440
441 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
442 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
443 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* ADDRESS_LO */
444 /* DATA_SEL | INT_EN | ADDRESS_HI */
445 cs->buf[cs->cdw++] = (1 << 29) | (0 << 24) | ((va >> 32UL) & 0xFF);
446 cs->buf[cs->cdw++] = value; /* DATA_LO */
447 cs->buf[cs->cdw++] = 0; /* DATA_HI */
448 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
449 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, &ctx->rings.gfx, fence_bo, RADEON_USAGE_WRITE);
450 }
451
452 static void r600_flush_vgt_streamout(struct r600_context *ctx)
453 {
454 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
455
456 r600_write_config_reg(cs, R_008490_CP_STRMOUT_CNTL, 0);
457
458 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
459 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0);
460
461 cs->buf[cs->cdw++] = PKT3(PKT3_WAIT_REG_MEM, 5, 0);
462 cs->buf[cs->cdw++] = WAIT_REG_MEM_EQUAL; /* wait until the register is equal to the reference value */
463 cs->buf[cs->cdw++] = R_008490_CP_STRMOUT_CNTL >> 2; /* register */
464 cs->buf[cs->cdw++] = 0;
465 cs->buf[cs->cdw++] = S_008490_OFFSET_UPDATE_DONE(1); /* reference value */
466 cs->buf[cs->cdw++] = S_008490_OFFSET_UPDATE_DONE(1); /* mask */
467 cs->buf[cs->cdw++] = 4; /* poll interval */
468 }
469
470 static void r600_set_streamout_enable(struct r600_context *ctx, unsigned buffer_enable_bit)
471 {
472 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
473
474 if (buffer_enable_bit) {
475 r600_write_context_reg(cs, R_028AB0_VGT_STRMOUT_EN, S_028AB0_STREAMOUT(1));
476 r600_write_context_reg(cs, R_028B20_VGT_STRMOUT_BUFFER_EN, buffer_enable_bit);
477 } else {
478 r600_write_context_reg(cs, R_028AB0_VGT_STRMOUT_EN, S_028AB0_STREAMOUT(0));
479 }
480 }
481
482 void r600_emit_streamout_begin(struct r600_context *ctx, struct r600_atom *atom)
483 {
484 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
485 struct r600_so_target **t = ctx->streamout.targets;
486 unsigned *stride_in_dw = ctx->vs_shader->so.stride;
487 unsigned i, update_flags = 0;
488 uint64_t va;
489
490 if (ctx->chip_class >= EVERGREEN) {
491 evergreen_flush_vgt_streamout(ctx);
492 evergreen_set_streamout_enable(ctx, ctx->streamout.enabled_mask);
493 } else {
494 r600_flush_vgt_streamout(ctx);
495 r600_set_streamout_enable(ctx, ctx->streamout.enabled_mask);
496 }
497
498 for (i = 0; i < ctx->streamout.num_targets; i++) {
499 if (t[i]) {
500 t[i]->stride_in_dw = stride_in_dw[i];
501 t[i]->so_index = i;
502 va = r600_resource_va(&ctx->screen->screen,
503 (void*)t[i]->b.buffer);
504
505 update_flags |= SURFACE_BASE_UPDATE_STRMOUT(i);
506
507 r600_write_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 3);
508 r600_write_value(cs, (t[i]->b.buffer_offset +
509 t[i]->b.buffer_size) >> 2); /* BUFFER_SIZE (in DW) */
510 r600_write_value(cs, stride_in_dw[i]); /* VTX_STRIDE (in DW) */
511 r600_write_value(cs, va >> 8); /* BUFFER_BASE */
512
513 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
514 cs->buf[cs->cdw++] =
515 r600_context_bo_reloc(ctx, &ctx->rings.gfx, r600_resource(t[i]->b.buffer),
516 RADEON_USAGE_WRITE);
517
518 /* R7xx requires this packet after updating BUFFER_BASE.
519 * Without this, R7xx locks up. */
520 if (ctx->family >= CHIP_RS780 && ctx->family <= CHIP_RV740) {
521 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BASE_UPDATE, 1, 0);
522 cs->buf[cs->cdw++] = i;
523 cs->buf[cs->cdw++] = va >> 8;
524
525 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
526 cs->buf[cs->cdw++] =
527 r600_context_bo_reloc(ctx, &ctx->rings.gfx, r600_resource(t[i]->b.buffer),
528 RADEON_USAGE_WRITE);
529 }
530
531 if (ctx->streamout.append_bitmask & (1 << i)) {
532 va = r600_resource_va(&ctx->screen->screen,
533 (void*)t[i]->buf_filled_size) + t[i]->buf_filled_size_offset;
534 /* Append. */
535 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
536 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
537 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM); /* control */
538 cs->buf[cs->cdw++] = 0; /* unused */
539 cs->buf[cs->cdw++] = 0; /* unused */
540 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */
541 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
542
543 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
544 cs->buf[cs->cdw++] =
545 r600_context_bo_reloc(ctx, &ctx->rings.gfx, t[i]->buf_filled_size,
546 RADEON_USAGE_READ);
547 } else {
548 /* Start from the beginning. */
549 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
550 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
551 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET); /* control */
552 cs->buf[cs->cdw++] = 0; /* unused */
553 cs->buf[cs->cdw++] = 0; /* unused */
554 cs->buf[cs->cdw++] = t[i]->b.buffer_offset >> 2; /* buffer offset in DW */
555 cs->buf[cs->cdw++] = 0; /* unused */
556 }
557 }
558 }
559
560 if (ctx->family > CHIP_R600 && ctx->family < CHIP_RV770) {
561 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0);
562 cs->buf[cs->cdw++] = update_flags;
563 }
564 ctx->streamout.begin_emitted = true;
565 }
566
567 void r600_emit_streamout_end(struct r600_context *ctx)
568 {
569 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
570 struct r600_so_target **t = ctx->streamout.targets;
571 unsigned i;
572 uint64_t va;
573
574 if (ctx->chip_class >= EVERGREEN) {
575 evergreen_flush_vgt_streamout(ctx);
576 } else {
577 r600_flush_vgt_streamout(ctx);
578 }
579
580 for (i = 0; i < ctx->streamout.num_targets; i++) {
581 if (t[i]) {
582 va = r600_resource_va(&ctx->screen->screen,
583 (void*)t[i]->buf_filled_size) + t[i]->buf_filled_size_offset;
584 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
585 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
586 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
587 STRMOUT_STORE_BUFFER_FILLED_SIZE; /* control */
588 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* dst address lo */
589 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* dst address hi */
590 cs->buf[cs->cdw++] = 0; /* unused */
591 cs->buf[cs->cdw++] = 0; /* unused */
592
593 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
594 cs->buf[cs->cdw++] =
595 r600_context_bo_reloc(ctx, &ctx->rings.gfx, t[i]->buf_filled_size,
596 RADEON_USAGE_WRITE);
597 }
598 }
599
600 if (ctx->chip_class >= EVERGREEN) {
601 ctx->flags |= R600_CONTEXT_STREAMOUT_FLUSH;
602 evergreen_set_streamout_enable(ctx, 0);
603 } else {
604 if (ctx->chip_class >= R700) {
605 ctx->flags |= R600_CONTEXT_STREAMOUT_FLUSH;
606 }
607 r600_set_streamout_enable(ctx, 0);
608 }
609 ctx->flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
610 ctx->streamout.begin_emitted = false;
611 }
612
613 /* The max number of bytes to copy per packet. */
614 #define CP_DMA_MAX_BYTE_COUNT ((1 << 21) - 8)
615
616 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
617 struct pipe_resource *dst, uint64_t dst_offset,
618 struct pipe_resource *src, uint64_t src_offset,
619 unsigned size)
620 {
621 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
622
623 assert(size);
624 assert(rctx->screen->has_cp_dma);
625
626 dst_offset += r600_resource_va(&rctx->screen->screen, dst);
627 src_offset += r600_resource_va(&rctx->screen->screen, src);
628
629 /* We flush the caches, because we might read from or write
630 * to resources which are bound right now. */
631 rctx->flags |= R600_CONTEXT_INV_CONST_CACHE |
632 R600_CONTEXT_INV_VERTEX_CACHE |
633 R600_CONTEXT_INV_TEX_CACHE |
634 R600_CONTEXT_FLUSH_AND_INV |
635 R600_CONTEXT_FLUSH_AND_INV_CB |
636 R600_CONTEXT_FLUSH_AND_INV_DB |
637 R600_CONTEXT_FLUSH_AND_INV_CB_META |
638 R600_CONTEXT_FLUSH_AND_INV_DB_META |
639 R600_CONTEXT_STREAMOUT_FLUSH |
640 R600_CONTEXT_WAIT_3D_IDLE;
641
642 /* There are differences between R700 and EG in CP DMA,
643 * but we only use the common bits here. */
644 while (size) {
645 unsigned sync = 0;
646 unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
647 unsigned src_reloc, dst_reloc;
648
649 r600_need_cs_space(rctx, 10 + (rctx->flags ? R600_MAX_FLUSH_CS_DWORDS : 0), FALSE);
650
651 /* Flush the caches for the first copy only. */
652 if (rctx->flags) {
653 r600_flush_emit(rctx);
654 }
655
656 /* Do the synchronization after the last copy, so that all data is written to memory. */
657 if (size == byte_count) {
658 sync = PKT3_CP_DMA_CP_SYNC;
659 }
660
661 /* This must be done after r600_need_cs_space. */
662 src_reloc = r600_context_bo_reloc(rctx, &rctx->rings.gfx, (struct r600_resource*)src, RADEON_USAGE_READ);
663 dst_reloc = r600_context_bo_reloc(rctx, &rctx->rings.gfx, (struct r600_resource*)dst, RADEON_USAGE_WRITE);
664
665 r600_write_value(cs, PKT3(PKT3_CP_DMA, 4, 0));
666 r600_write_value(cs, src_offset); /* SRC_ADDR_LO [31:0] */
667 r600_write_value(cs, sync | ((src_offset >> 32) & 0xff)); /* CP_SYNC [31] | SRC_ADDR_HI [7:0] */
668 r600_write_value(cs, dst_offset); /* DST_ADDR_LO [31:0] */
669 r600_write_value(cs, (dst_offset >> 32) & 0xff); /* DST_ADDR_HI [7:0] */
670 r600_write_value(cs, byte_count); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
671
672 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
673 r600_write_value(cs, src_reloc);
674 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
675 r600_write_value(cs, dst_reloc);
676
677 size -= byte_count;
678 src_offset += byte_count;
679 dst_offset += byte_count;
680 }
681
682 /* Invalidate the read caches. */
683 rctx->flags |= R600_CONTEXT_INV_CONST_CACHE |
684 R600_CONTEXT_INV_VERTEX_CACHE |
685 R600_CONTEXT_INV_TEX_CACHE;
686
687 util_range_add(&r600_resource(dst)->valid_buffer_range, dst_offset,
688 dst_offset + size);
689 }
690
691 void r600_need_dma_space(struct r600_context *ctx, unsigned num_dw)
692 {
693 /* The number of dwords we already used in the DMA so far. */
694 num_dw += ctx->rings.dma.cs->cdw;
695 /* Flush if there's not enough space. */
696 if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
697 ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC);
698 }
699 }
700
701 void r600_dma_copy(struct r600_context *rctx,
702 struct pipe_resource *dst,
703 struct pipe_resource *src,
704 uint64_t dst_offset,
705 uint64_t src_offset,
706 uint64_t size)
707 {
708 struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
709 unsigned i, ncopy, csize, shift;
710 struct r600_resource *rdst = (struct r600_resource*)dst;
711 struct r600_resource *rsrc = (struct r600_resource*)src;
712
713 /* make sure that the dma ring is only one active */
714 rctx->rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC);
715
716 size >>= 2;
717 shift = 2;
718 ncopy = (size / 0xffff) + !!(size % 0xffff);
719
720 r600_need_dma_space(rctx, ncopy * 5);
721 for (i = 0; i < ncopy; i++) {
722 csize = size < 0xffff ? size : 0xffff;
723 /* emit reloc before writting cs so that cs is always in consistent state */
724 r600_context_bo_reloc(rctx, &rctx->rings.dma, rsrc, RADEON_USAGE_READ);
725 r600_context_bo_reloc(rctx, &rctx->rings.dma, rdst, RADEON_USAGE_WRITE);
726 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, 0, 0, csize);
727 cs->buf[cs->cdw++] = dst_offset & 0xfffffffc;
728 cs->buf[cs->cdw++] = src_offset & 0xfffffffc;
729 cs->buf[cs->cdw++] = (dst_offset >> 32UL) & 0xff;
730 cs->buf[cs->cdw++] = (src_offset >> 32UL) & 0xff;
731 dst_offset += csize << shift;
732 src_offset += csize << shift;
733 size -= csize;
734 }
735
736 util_range_add(&rdst->valid_buffer_range, dst_offset,
737 dst_offset + size);
738 }