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r600g: improve the mechanism for recognizing an empty CS
[mesa.git] / src / gallium / drivers / r600 / r600_hw_context.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include "r600_pipe.h"
27 #include "r600d.h"
28 #include "util/u_memory.h"
29 #include <errno.h>
30 #include <unistd.h>
31
32 /* Get backends mask */
33 void r600_get_backend_mask(struct r600_context *ctx)
34 {
35 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
36 struct r600_resource *buffer;
37 uint32_t *results;
38 unsigned num_backends = ctx->screen->info.r600_num_backends;
39 unsigned i, mask = 0;
40 uint64_t va;
41
42 /* if backend_map query is supported by the kernel */
43 if (ctx->screen->info.r600_backend_map_valid) {
44 unsigned num_tile_pipes = ctx->screen->info.r600_num_tile_pipes;
45 unsigned backend_map = ctx->screen->info.r600_backend_map;
46 unsigned item_width, item_mask;
47
48 if (ctx->chip_class >= EVERGREEN) {
49 item_width = 4;
50 item_mask = 0x7;
51 } else {
52 item_width = 2;
53 item_mask = 0x3;
54 }
55
56 while(num_tile_pipes--) {
57 i = backend_map & item_mask;
58 mask |= (1<<i);
59 backend_map >>= item_width;
60 }
61 if (mask != 0) {
62 ctx->backend_mask = mask;
63 return;
64 }
65 }
66
67 /* otherwise backup path for older kernels */
68
69 /* create buffer for event data */
70 buffer = (struct r600_resource*)
71 pipe_buffer_create(&ctx->screen->screen, PIPE_BIND_CUSTOM,
72 PIPE_USAGE_STAGING, ctx->max_db*16);
73 if (!buffer)
74 goto err;
75 va = r600_resource_va(&ctx->screen->screen, (void*)buffer);
76
77 /* initialize buffer with zeroes */
78 results = r600_buffer_mmap_sync_with_rings(ctx, buffer, PIPE_TRANSFER_WRITE);
79 if (results) {
80 memset(results, 0, ctx->max_db * 4 * 4);
81 ctx->ws->buffer_unmap(buffer->cs_buf);
82
83 /* emit EVENT_WRITE for ZPASS_DONE */
84 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
85 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
86 cs->buf[cs->cdw++] = va;
87 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
88
89 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
90 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, &ctx->rings.gfx, buffer, RADEON_USAGE_WRITE);
91
92 /* analyze results */
93 results = r600_buffer_mmap_sync_with_rings(ctx, buffer, PIPE_TRANSFER_READ);
94 if (results) {
95 for(i = 0; i < ctx->max_db; i++) {
96 /* at least highest bit will be set if backend is used */
97 if (results[i*4 + 1])
98 mask |= (1<<i);
99 }
100 ctx->ws->buffer_unmap(buffer->cs_buf);
101 }
102 }
103
104 pipe_resource_reference((struct pipe_resource**)&buffer, NULL);
105
106 if (mask != 0) {
107 ctx->backend_mask = mask;
108 return;
109 }
110
111 err:
112 /* fallback to old method - set num_backends lower bits to 1 */
113 ctx->backend_mask = (~((uint32_t)0))>>(32-num_backends);
114 return;
115 }
116
117 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
118 boolean count_draw_in)
119 {
120 if (!ctx->ws->cs_memory_below_limit(ctx->rings.gfx.cs, ctx->vram, ctx->gtt)) {
121 ctx->gtt = 0;
122 ctx->vram = 0;
123 ctx->rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC);
124 return;
125 }
126 /* all will be accounted once relocation are emited */
127 ctx->gtt = 0;
128 ctx->vram = 0;
129
130 /* The number of dwords we already used in the CS so far. */
131 num_dw += ctx->rings.gfx.cs->cdw;
132
133 if (count_draw_in) {
134 unsigned i;
135
136 /* The number of dwords all the dirty states would take. */
137 for (i = 0; i < R600_NUM_ATOMS; i++) {
138 if (ctx->atoms[i] && ctx->atoms[i]->dirty) {
139 num_dw += ctx->atoms[i]->num_dw;
140 if (ctx->screen->trace_bo) {
141 num_dw += R600_TRACE_CS_DWORDS;
142 }
143 }
144 }
145
146 /* The upper-bound of how much space a draw command would take. */
147 num_dw += R600_MAX_FLUSH_CS_DWORDS + R600_MAX_DRAW_CS_DWORDS;
148 if (ctx->screen->trace_bo) {
149 num_dw += R600_TRACE_CS_DWORDS;
150 }
151 }
152
153 /* Count in queries_suspend. */
154 num_dw += ctx->num_cs_dw_nontimer_queries_suspend;
155
156 /* Count in streamout_end at the end of CS. */
157 if (ctx->streamout.begin_emitted) {
158 num_dw += ctx->streamout.num_dw_for_end;
159 }
160
161 /* Count in render_condition(NULL) at the end of CS. */
162 if (ctx->predicate_drawing) {
163 num_dw += 3;
164 }
165
166 /* SX_MISC */
167 if (ctx->chip_class <= R700) {
168 num_dw += 3;
169 }
170
171 /* Count in framebuffer cache flushes at the end of CS. */
172 num_dw += R600_MAX_FLUSH_CS_DWORDS;
173
174 /* The fence at the end of CS. */
175 num_dw += 10;
176
177 /* Flush if there's not enough space. */
178 if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
179 ctx->rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC);
180 }
181 }
182
183 void r600_flush_emit(struct r600_context *rctx)
184 {
185 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
186 unsigned cp_coher_cntl = 0;
187 unsigned wait_until = 0;
188
189 if (!rctx->flags) {
190 return;
191 }
192
193 if (rctx->flags & R600_CONTEXT_WAIT_3D_IDLE) {
194 wait_until |= S_008040_WAIT_3D_IDLE(1);
195 }
196 if (rctx->flags & R600_CONTEXT_WAIT_CP_DMA_IDLE) {
197 wait_until |= S_008040_WAIT_CP_DMA_IDLE(1);
198 }
199
200 if (wait_until) {
201 /* Use of WAIT_UNTIL is deprecated on Cayman+ */
202 if (rctx->family >= CHIP_CAYMAN) {
203 /* emit a PS partial flush on Cayman/TN */
204 rctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
205 }
206 }
207
208 if (rctx->flags & R600_CONTEXT_PS_PARTIAL_FLUSH) {
209 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
210 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
211 }
212
213 if (rctx->chip_class >= R700 &&
214 (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB_META)) {
215 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
216 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0);
217 }
218
219 if (rctx->chip_class >= R700 &&
220 (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_DB_META)) {
221 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
222 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0);
223
224 /* Set FULL_CACHE_ENA for DB META flushes on r7xx and later.
225 *
226 * This hack predates use of FLUSH_AND_INV_DB_META, so it's
227 * unclear whether it's still needed or even whether it has
228 * any effect.
229 */
230 cp_coher_cntl |= S_0085F0_FULL_CACHE_ENA(1);
231 }
232
233 if (rctx->flags & R600_CONTEXT_FLUSH_AND_INV) {
234 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
235 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
236 }
237
238 if (rctx->flags & R600_CONTEXT_INV_CONST_CACHE) {
239 cp_coher_cntl |= S_0085F0_SH_ACTION_ENA(1);
240 }
241 if (rctx->flags & R600_CONTEXT_INV_VERTEX_CACHE) {
242 cp_coher_cntl |= rctx->has_vertex_cache ? S_0085F0_VC_ACTION_ENA(1)
243 : S_0085F0_TC_ACTION_ENA(1);
244 }
245 if (rctx->flags & R600_CONTEXT_INV_TEX_CACHE) {
246 cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1);
247 }
248
249 if (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_DB) {
250 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
251 S_0085F0_DB_DEST_BASE_ENA(1) |
252 S_0085F0_SMX_ACTION_ENA(1);
253 }
254
255 if (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB) {
256 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
257 S_0085F0_CB0_DEST_BASE_ENA(1) |
258 S_0085F0_CB1_DEST_BASE_ENA(1) |
259 S_0085F0_CB2_DEST_BASE_ENA(1) |
260 S_0085F0_CB3_DEST_BASE_ENA(1) |
261 S_0085F0_CB4_DEST_BASE_ENA(1) |
262 S_0085F0_CB5_DEST_BASE_ENA(1) |
263 S_0085F0_CB6_DEST_BASE_ENA(1) |
264 S_0085F0_CB7_DEST_BASE_ENA(1) |
265 S_0085F0_SMX_ACTION_ENA(1);
266 if (rctx->chip_class >= EVERGREEN)
267 cp_coher_cntl |= S_0085F0_CB8_DEST_BASE_ENA(1) |
268 S_0085F0_CB9_DEST_BASE_ENA(1) |
269 S_0085F0_CB10_DEST_BASE_ENA(1) |
270 S_0085F0_CB11_DEST_BASE_ENA(1);
271 }
272
273 if (rctx->flags & R600_CONTEXT_STREAMOUT_FLUSH) {
274 cp_coher_cntl |= S_0085F0_SO0_DEST_BASE_ENA(1) |
275 S_0085F0_SO1_DEST_BASE_ENA(1) |
276 S_0085F0_SO2_DEST_BASE_ENA(1) |
277 S_0085F0_SO3_DEST_BASE_ENA(1) |
278 S_0085F0_SMX_ACTION_ENA(1);
279 }
280
281 if (cp_coher_cntl) {
282 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
283 cs->buf[cs->cdw++] = cp_coher_cntl; /* CP_COHER_CNTL */
284 cs->buf[cs->cdw++] = 0xffffffff; /* CP_COHER_SIZE */
285 cs->buf[cs->cdw++] = 0; /* CP_COHER_BASE */
286 cs->buf[cs->cdw++] = 0x0000000A; /* POLL_INTERVAL */
287 }
288
289 if (wait_until) {
290 /* Use of WAIT_UNTIL is deprecated on Cayman+ */
291 if (rctx->family < CHIP_CAYMAN) {
292 /* wait for things to settle */
293 r600_write_config_reg(cs, R_008040_WAIT_UNTIL, wait_until);
294 }
295 }
296
297 /* everything is properly flushed */
298 rctx->flags = 0;
299 }
300
301 void r600_context_flush(struct r600_context *ctx, unsigned flags)
302 {
303 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
304
305 ctx->nontimer_queries_suspended = false;
306 ctx->streamout.suspended = false;
307
308 /* suspend queries */
309 if (ctx->num_cs_dw_nontimer_queries_suspend) {
310 r600_suspend_nontimer_queries(ctx);
311 ctx->nontimer_queries_suspended = true;
312 }
313
314 if (ctx->streamout.begin_emitted) {
315 r600_emit_streamout_end(ctx);
316 ctx->streamout.suspended = true;
317 }
318
319 /* flush is needed to avoid lockups on some chips with user fences
320 * this will also flush the framebuffer cache
321 */
322 ctx->flags |= R600_CONTEXT_FLUSH_AND_INV |
323 R600_CONTEXT_FLUSH_AND_INV_CB |
324 R600_CONTEXT_FLUSH_AND_INV_DB |
325 R600_CONTEXT_FLUSH_AND_INV_CB_META |
326 R600_CONTEXT_FLUSH_AND_INV_DB_META |
327 R600_CONTEXT_WAIT_3D_IDLE |
328 R600_CONTEXT_WAIT_CP_DMA_IDLE;
329
330 r600_flush_emit(ctx);
331
332 /* old kernels and userspace don't set SX_MISC, so we must reset it to 0 here */
333 if (ctx->chip_class <= R700) {
334 r600_write_context_reg(cs, R_028350_SX_MISC, 0);
335 }
336
337 /* force to keep tiling flags */
338 if (ctx->keep_tiling_flags) {
339 flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
340 }
341
342 /* Flush the CS. */
343 ctx->ws->cs_flush(ctx->rings.gfx.cs, flags, ctx->screen->cs_count++);
344 }
345
346 void r600_begin_new_cs(struct r600_context *ctx)
347 {
348 unsigned shader;
349
350 ctx->flags = 0;
351 ctx->gtt = 0;
352 ctx->vram = 0;
353
354 /* Begin a new CS. */
355 r600_emit_command_buffer(ctx->rings.gfx.cs, &ctx->start_cs_cmd);
356
357 /* Re-emit states. */
358 ctx->alphatest_state.atom.dirty = true;
359 ctx->blend_color.atom.dirty = true;
360 ctx->cb_misc_state.atom.dirty = true;
361 ctx->clip_misc_state.atom.dirty = true;
362 ctx->clip_state.atom.dirty = true;
363 ctx->db_misc_state.atom.dirty = true;
364 ctx->db_state.atom.dirty = true;
365 ctx->framebuffer.atom.dirty = true;
366 ctx->pixel_shader.atom.dirty = true;
367 ctx->poly_offset_state.atom.dirty = true;
368 ctx->vgt_state.atom.dirty = true;
369 ctx->sample_mask.atom.dirty = true;
370 ctx->scissor.atom.dirty = true;
371 ctx->config_state.atom.dirty = true;
372 ctx->stencil_ref.atom.dirty = true;
373 ctx->vertex_fetch_shader.atom.dirty = true;
374 ctx->vertex_shader.atom.dirty = true;
375 ctx->viewport.atom.dirty = true;
376
377 if (ctx->blend_state.cso)
378 ctx->blend_state.atom.dirty = true;
379 if (ctx->dsa_state.cso)
380 ctx->dsa_state.atom.dirty = true;
381 if (ctx->rasterizer_state.cso)
382 ctx->rasterizer_state.atom.dirty = true;
383
384 if (ctx->chip_class <= R700) {
385 ctx->seamless_cube_map.atom.dirty = true;
386 }
387
388 ctx->vertex_buffer_state.dirty_mask = ctx->vertex_buffer_state.enabled_mask;
389 r600_vertex_buffers_dirty(ctx);
390
391 /* Re-emit shader resources. */
392 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
393 struct r600_constbuf_state *constbuf = &ctx->constbuf_state[shader];
394 struct r600_textures_info *samplers = &ctx->samplers[shader];
395
396 constbuf->dirty_mask = constbuf->enabled_mask;
397 samplers->views.dirty_mask = samplers->views.enabled_mask;
398 samplers->states.dirty_mask = samplers->states.enabled_mask;
399
400 r600_constant_buffers_dirty(ctx, constbuf);
401 r600_sampler_views_dirty(ctx, &samplers->views);
402 r600_sampler_states_dirty(ctx, &samplers->states);
403 }
404
405 if (ctx->streamout.suspended) {
406 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
407 r600_streamout_buffers_dirty(ctx);
408 }
409
410 /* resume queries */
411 if (ctx->nontimer_queries_suspended) {
412 r600_resume_nontimer_queries(ctx);
413 }
414
415 /* Re-emit the draw state. */
416 ctx->last_primitive_type = -1;
417 ctx->last_start_instance = -1;
418
419 ctx->initial_gfx_cs_size = ctx->rings.gfx.cs->cdw;
420 }
421
422 void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence_bo, unsigned offset, unsigned value)
423 {
424 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
425 uint64_t va;
426
427 r600_need_cs_space(ctx, 10, FALSE);
428
429 va = r600_resource_va(&ctx->screen->screen, (void*)fence_bo);
430 va = va + (offset << 2);
431
432 /* Use of WAIT_UNTIL is deprecated on Cayman+ */
433 if (ctx->family >= CHIP_CAYMAN) {
434 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
435 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
436 } else {
437 r600_write_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
438 }
439
440 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
441 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
442 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* ADDRESS_LO */
443 /* DATA_SEL | INT_EN | ADDRESS_HI */
444 cs->buf[cs->cdw++] = (1 << 29) | (0 << 24) | ((va >> 32UL) & 0xFF);
445 cs->buf[cs->cdw++] = value; /* DATA_LO */
446 cs->buf[cs->cdw++] = 0; /* DATA_HI */
447 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
448 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, &ctx->rings.gfx, fence_bo, RADEON_USAGE_WRITE);
449 }
450
451 static void r600_flush_vgt_streamout(struct r600_context *ctx)
452 {
453 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
454
455 r600_write_config_reg(cs, R_008490_CP_STRMOUT_CNTL, 0);
456
457 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
458 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0);
459
460 cs->buf[cs->cdw++] = PKT3(PKT3_WAIT_REG_MEM, 5, 0);
461 cs->buf[cs->cdw++] = WAIT_REG_MEM_EQUAL; /* wait until the register is equal to the reference value */
462 cs->buf[cs->cdw++] = R_008490_CP_STRMOUT_CNTL >> 2; /* register */
463 cs->buf[cs->cdw++] = 0;
464 cs->buf[cs->cdw++] = S_008490_OFFSET_UPDATE_DONE(1); /* reference value */
465 cs->buf[cs->cdw++] = S_008490_OFFSET_UPDATE_DONE(1); /* mask */
466 cs->buf[cs->cdw++] = 4; /* poll interval */
467 }
468
469 static void r600_set_streamout_enable(struct r600_context *ctx, unsigned buffer_enable_bit)
470 {
471 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
472
473 if (buffer_enable_bit) {
474 r600_write_context_reg(cs, R_028AB0_VGT_STRMOUT_EN, S_028AB0_STREAMOUT(1));
475 r600_write_context_reg(cs, R_028B20_VGT_STRMOUT_BUFFER_EN, buffer_enable_bit);
476 } else {
477 r600_write_context_reg(cs, R_028AB0_VGT_STRMOUT_EN, S_028AB0_STREAMOUT(0));
478 }
479 }
480
481 void r600_emit_streamout_begin(struct r600_context *ctx, struct r600_atom *atom)
482 {
483 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
484 struct r600_so_target **t = ctx->streamout.targets;
485 unsigned *stride_in_dw = ctx->vs_shader->so.stride;
486 unsigned i, update_flags = 0;
487 uint64_t va;
488
489 if (ctx->chip_class >= EVERGREEN) {
490 evergreen_flush_vgt_streamout(ctx);
491 evergreen_set_streamout_enable(ctx, ctx->streamout.enabled_mask);
492 } else {
493 r600_flush_vgt_streamout(ctx);
494 r600_set_streamout_enable(ctx, ctx->streamout.enabled_mask);
495 }
496
497 for (i = 0; i < ctx->streamout.num_targets; i++) {
498 if (t[i]) {
499 t[i]->stride_in_dw = stride_in_dw[i];
500 t[i]->so_index = i;
501 va = r600_resource_va(&ctx->screen->screen,
502 (void*)t[i]->b.buffer);
503
504 update_flags |= SURFACE_BASE_UPDATE_STRMOUT(i);
505
506 r600_write_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 3);
507 r600_write_value(cs, (t[i]->b.buffer_offset +
508 t[i]->b.buffer_size) >> 2); /* BUFFER_SIZE (in DW) */
509 r600_write_value(cs, stride_in_dw[i]); /* VTX_STRIDE (in DW) */
510 r600_write_value(cs, va >> 8); /* BUFFER_BASE */
511
512 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
513 cs->buf[cs->cdw++] =
514 r600_context_bo_reloc(ctx, &ctx->rings.gfx, r600_resource(t[i]->b.buffer),
515 RADEON_USAGE_WRITE);
516
517 /* R7xx requires this packet after updating BUFFER_BASE.
518 * Without this, R7xx locks up. */
519 if (ctx->family >= CHIP_RS780 && ctx->family <= CHIP_RV740) {
520 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BASE_UPDATE, 1, 0);
521 cs->buf[cs->cdw++] = i;
522 cs->buf[cs->cdw++] = va >> 8;
523
524 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
525 cs->buf[cs->cdw++] =
526 r600_context_bo_reloc(ctx, &ctx->rings.gfx, r600_resource(t[i]->b.buffer),
527 RADEON_USAGE_WRITE);
528 }
529
530 if (ctx->streamout.append_bitmask & (1 << i)) {
531 va = r600_resource_va(&ctx->screen->screen,
532 (void*)t[i]->buf_filled_size) + t[i]->buf_filled_size_offset;
533 /* Append. */
534 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
535 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
536 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM); /* control */
537 cs->buf[cs->cdw++] = 0; /* unused */
538 cs->buf[cs->cdw++] = 0; /* unused */
539 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */
540 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
541
542 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
543 cs->buf[cs->cdw++] =
544 r600_context_bo_reloc(ctx, &ctx->rings.gfx, t[i]->buf_filled_size,
545 RADEON_USAGE_READ);
546 } else {
547 /* Start from the beginning. */
548 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
549 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
550 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET); /* control */
551 cs->buf[cs->cdw++] = 0; /* unused */
552 cs->buf[cs->cdw++] = 0; /* unused */
553 cs->buf[cs->cdw++] = t[i]->b.buffer_offset >> 2; /* buffer offset in DW */
554 cs->buf[cs->cdw++] = 0; /* unused */
555 }
556 }
557 }
558
559 if (ctx->family > CHIP_R600 && ctx->family < CHIP_RV770) {
560 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0);
561 cs->buf[cs->cdw++] = update_flags;
562 }
563 ctx->streamout.begin_emitted = true;
564 }
565
566 void r600_emit_streamout_end(struct r600_context *ctx)
567 {
568 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
569 struct r600_so_target **t = ctx->streamout.targets;
570 unsigned i;
571 uint64_t va;
572
573 if (ctx->chip_class >= EVERGREEN) {
574 evergreen_flush_vgt_streamout(ctx);
575 } else {
576 r600_flush_vgt_streamout(ctx);
577 }
578
579 for (i = 0; i < ctx->streamout.num_targets; i++) {
580 if (t[i]) {
581 va = r600_resource_va(&ctx->screen->screen,
582 (void*)t[i]->buf_filled_size) + t[i]->buf_filled_size_offset;
583 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
584 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
585 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
586 STRMOUT_STORE_BUFFER_FILLED_SIZE; /* control */
587 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* dst address lo */
588 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* dst address hi */
589 cs->buf[cs->cdw++] = 0; /* unused */
590 cs->buf[cs->cdw++] = 0; /* unused */
591
592 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
593 cs->buf[cs->cdw++] =
594 r600_context_bo_reloc(ctx, &ctx->rings.gfx, t[i]->buf_filled_size,
595 RADEON_USAGE_WRITE);
596 }
597 }
598
599 if (ctx->chip_class >= EVERGREEN) {
600 ctx->flags |= R600_CONTEXT_STREAMOUT_FLUSH;
601 evergreen_set_streamout_enable(ctx, 0);
602 } else {
603 if (ctx->chip_class >= R700) {
604 ctx->flags |= R600_CONTEXT_STREAMOUT_FLUSH;
605 }
606 r600_set_streamout_enable(ctx, 0);
607 }
608 ctx->flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
609 ctx->streamout.begin_emitted = false;
610 }
611
612 /* The max number of bytes to copy per packet. */
613 #define CP_DMA_MAX_BYTE_COUNT ((1 << 21) - 8)
614
615 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
616 struct pipe_resource *dst, uint64_t dst_offset,
617 struct pipe_resource *src, uint64_t src_offset,
618 unsigned size)
619 {
620 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
621
622 assert(size);
623 assert(rctx->screen->has_cp_dma);
624
625 dst_offset += r600_resource_va(&rctx->screen->screen, dst);
626 src_offset += r600_resource_va(&rctx->screen->screen, src);
627
628 /* Flush the caches where the resources are bound. */
629 r600_flag_resource_cache_flush(rctx, src);
630 r600_flag_resource_cache_flush(rctx, dst);
631
632 /* There are differences between R700 and EG in CP DMA,
633 * but we only use the common bits here. */
634 while (size) {
635 unsigned sync = 0;
636 unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
637 unsigned src_reloc, dst_reloc;
638
639 r600_need_cs_space(rctx, 10 + (rctx->flags ? R600_MAX_FLUSH_CS_DWORDS : 0), FALSE);
640
641 /* Flush the caches for the first copy only. */
642 if (rctx->flags) {
643 r600_flush_emit(rctx);
644 }
645
646 /* Do the synchronization after the last copy, so that all data is written to memory. */
647 if (size == byte_count) {
648 sync = PKT3_CP_DMA_CP_SYNC;
649 }
650
651 /* This must be done after r600_need_cs_space. */
652 src_reloc = r600_context_bo_reloc(rctx, &rctx->rings.gfx, (struct r600_resource*)src, RADEON_USAGE_READ);
653 dst_reloc = r600_context_bo_reloc(rctx, &rctx->rings.gfx, (struct r600_resource*)dst, RADEON_USAGE_WRITE);
654
655 r600_write_value(cs, PKT3(PKT3_CP_DMA, 4, 0));
656 r600_write_value(cs, src_offset); /* SRC_ADDR_LO [31:0] */
657 r600_write_value(cs, sync | ((src_offset >> 32) & 0xff)); /* CP_SYNC [31] | SRC_ADDR_HI [7:0] */
658 r600_write_value(cs, dst_offset); /* DST_ADDR_LO [31:0] */
659 r600_write_value(cs, (dst_offset >> 32) & 0xff); /* DST_ADDR_HI [7:0] */
660 r600_write_value(cs, byte_count); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
661
662 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
663 r600_write_value(cs, src_reloc);
664 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
665 r600_write_value(cs, dst_reloc);
666
667 size -= byte_count;
668 src_offset += byte_count;
669 dst_offset += byte_count;
670 }
671
672 /* Flush the cache of the dst resource again in case the 3D engine
673 * has been prefetching it. */
674 r600_flag_resource_cache_flush(rctx, dst);
675
676 util_range_add(&r600_resource(dst)->valid_buffer_range, dst_offset,
677 dst_offset + size);
678 }
679
680 void r600_need_dma_space(struct r600_context *ctx, unsigned num_dw)
681 {
682 /* The number of dwords we already used in the DMA so far. */
683 num_dw += ctx->rings.dma.cs->cdw;
684 /* Flush if there's not enough space. */
685 if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
686 ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC);
687 }
688 }
689
690 void r600_dma_copy(struct r600_context *rctx,
691 struct pipe_resource *dst,
692 struct pipe_resource *src,
693 uint64_t dst_offset,
694 uint64_t src_offset,
695 uint64_t size)
696 {
697 struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
698 unsigned i, ncopy, csize, shift;
699 struct r600_resource *rdst = (struct r600_resource*)dst;
700 struct r600_resource *rsrc = (struct r600_resource*)src;
701
702 /* make sure that the dma ring is only one active */
703 rctx->rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC);
704
705 size >>= 2;
706 shift = 2;
707 ncopy = (size / 0xffff) + !!(size % 0xffff);
708
709 r600_need_dma_space(rctx, ncopy * 5);
710 for (i = 0; i < ncopy; i++) {
711 csize = size < 0xffff ? size : 0xffff;
712 /* emit reloc before writting cs so that cs is always in consistent state */
713 r600_context_bo_reloc(rctx, &rctx->rings.dma, rsrc, RADEON_USAGE_READ);
714 r600_context_bo_reloc(rctx, &rctx->rings.dma, rdst, RADEON_USAGE_WRITE);
715 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, 0, 0, csize);
716 cs->buf[cs->cdw++] = dst_offset & 0xfffffffc;
717 cs->buf[cs->cdw++] = src_offset & 0xfffffffc;
718 cs->buf[cs->cdw++] = (dst_offset >> 32UL) & 0xff;
719 cs->buf[cs->cdw++] = (src_offset >> 32UL) & 0xff;
720 dst_offset += csize << shift;
721 src_offset += csize << shift;
722 size -= csize;
723 }
724
725 util_range_add(&rdst->valid_buffer_range, dst_offset,
726 dst_offset + size);
727 }
728
729 /* Flag the cache of the resource for it to be flushed later if the resource
730 * is bound. Otherwise do nothing. Used for synchronization between engines.
731 */
732 void r600_flag_resource_cache_flush(struct r600_context *rctx,
733 struct pipe_resource *res)
734 {
735 /* Check vertex buffers. */
736 uint32_t mask = rctx->vertex_buffer_state.enabled_mask;
737 while (mask) {
738 uint32_t i = u_bit_scan(&mask);
739 if (rctx->vertex_buffer_state.vb[i].buffer == res) {
740 rctx->flags |= R600_CONTEXT_INV_VERTEX_CACHE;
741 }
742 }
743
744 /* Check vertex buffers for compute. */
745 mask = rctx->cs_vertex_buffer_state.enabled_mask;
746 while (mask) {
747 uint32_t i = u_bit_scan(&mask);
748 if (rctx->cs_vertex_buffer_state.vb[i].buffer == res) {
749 rctx->flags |= R600_CONTEXT_INV_VERTEX_CACHE;
750 }
751 }
752
753 /* Check constant buffers. */
754 unsigned shader;
755 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
756 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
757 uint32_t mask = state->enabled_mask;
758
759 while (mask) {
760 unsigned i = u_bit_scan(&mask);
761 if (state->cb[i].buffer == res) {
762 rctx->flags |= R600_CONTEXT_INV_CONST_CACHE;
763
764 shader = PIPE_SHADER_TYPES; /* break the outer loop */
765 break;
766 }
767 }
768 }
769
770 /* Check textures. */
771 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
772 struct r600_samplerview_state *state = &rctx->samplers[shader].views;
773 uint32_t mask = state->enabled_mask;
774
775 while (mask) {
776 uint32_t i = u_bit_scan(&mask);
777 if (&state->views[i]->tex_resource->b.b == res) {
778 rctx->flags |= R600_CONTEXT_INV_TEX_CACHE;
779
780 shader = PIPE_SHADER_TYPES; /* break the outer loop */
781 break;
782 }
783 }
784 }
785
786 /* Check streamout buffers. */
787 int i;
788 for (i = 0; i < rctx->streamout.num_targets; i++) {
789 if (rctx->streamout.targets[i]->b.buffer == res) {
790 rctx->flags |= R600_CONTEXT_STREAMOUT_FLUSH |
791 R600_CONTEXT_FLUSH_AND_INV |
792 R600_CONTEXT_WAIT_3D_IDLE;
793 break;
794 }
795 }
796
797 /* Check colorbuffers. */
798 for (i = 0; i < rctx->framebuffer.state.nr_cbufs; i++) {
799 if (rctx->framebuffer.state.cbufs[i] &&
800 rctx->framebuffer.state.cbufs[i]->texture == res) {
801 struct r600_texture *tex =
802 (struct r600_texture*)rctx->framebuffer.state.cbufs[i]->texture;
803
804 rctx->flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
805 R600_CONTEXT_FLUSH_AND_INV |
806 R600_CONTEXT_WAIT_3D_IDLE;
807
808 if (tex->cmask_size || tex->fmask_size) {
809 rctx->flags |= R600_CONTEXT_FLUSH_AND_INV_CB_META;
810 }
811 break;
812 }
813 }
814
815 /* Check a depth buffer. */
816 if (rctx->framebuffer.state.zsbuf) {
817 if (rctx->framebuffer.state.zsbuf->texture == res) {
818 rctx->flags |= R600_CONTEXT_FLUSH_AND_INV_DB |
819 R600_CONTEXT_FLUSH_AND_INV |
820 R600_CONTEXT_WAIT_3D_IDLE;
821 }
822
823 struct r600_texture *tex =
824 (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
825 if (tex && tex->htile && &tex->htile->b.b == res) {
826 rctx->flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META |
827 R600_CONTEXT_FLUSH_AND_INV |
828 R600_CONTEXT_WAIT_3D_IDLE;
829 }
830 }
831 }